1 /* 2 * Copyright 2015 Amazon.com, Inc. or its affiliates. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef ENA_H 34 #define ENA_H 35 36 #include <linux/bitops.h> 37 #include <linux/dim.h> 38 #include <linux/etherdevice.h> 39 #include <linux/inetdevice.h> 40 #include <linux/interrupt.h> 41 #include <linux/netdevice.h> 42 #include <linux/skbuff.h> 43 44 #include "ena_com.h" 45 #include "ena_eth_com.h" 46 47 #define DRV_MODULE_VER_MAJOR 2 48 #define DRV_MODULE_VER_MINOR 1 49 #define DRV_MODULE_VER_SUBMINOR 0 50 51 #define DRV_MODULE_NAME "ena" 52 #ifndef DRV_MODULE_VERSION 53 #define DRV_MODULE_VERSION \ 54 __stringify(DRV_MODULE_VER_MAJOR) "." \ 55 __stringify(DRV_MODULE_VER_MINOR) "." \ 56 __stringify(DRV_MODULE_VER_SUBMINOR) "K" 57 #endif 58 59 #define DEVICE_NAME "Elastic Network Adapter (ENA)" 60 61 /* 1 for AENQ + ADMIN */ 62 #define ENA_ADMIN_MSIX_VEC 1 63 #define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues)) 64 65 /* The ENA buffer length fields is 16 bit long. So when PAGE_SIZE == 64kB the 66 * driver passes 0. 67 * Since the max packet size the ENA handles is ~9kB limit the buffer length to 68 * 16kB. 69 */ 70 #if PAGE_SIZE > SZ_16K 71 #define ENA_PAGE_SIZE SZ_16K 72 #else 73 #define ENA_PAGE_SIZE PAGE_SIZE 74 #endif 75 76 #define ENA_MIN_MSIX_VEC 2 77 78 #define ENA_REG_BAR 0 79 #define ENA_MEM_BAR 2 80 #define ENA_BAR_MASK (BIT(ENA_REG_BAR) | BIT(ENA_MEM_BAR)) 81 82 #define ENA_DEFAULT_RING_SIZE (1024) 83 #define ENA_MIN_RING_SIZE (256) 84 85 #define ENA_TX_WAKEUP_THRESH (MAX_SKB_FRAGS + 2) 86 #define ENA_DEFAULT_RX_COPYBREAK (256 - NET_IP_ALIGN) 87 88 /* limit the buffer size to 600 bytes to handle MTU changes from very 89 * small to very large, in which case the number of buffers per packet 90 * could exceed ENA_PKT_MAX_BUFS 91 */ 92 #define ENA_DEFAULT_MIN_RX_BUFF_ALLOC_SIZE 600 93 94 #define ENA_MIN_MTU 128 95 96 #define ENA_NAME_MAX_LEN 20 97 #define ENA_IRQNAME_SIZE 40 98 99 #define ENA_PKT_MAX_BUFS 19 100 101 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 102 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 103 104 #define ENA_HASH_KEY_SIZE 40 105 106 /* The number of tx packet completions that will be handled each NAPI poll 107 * cycle is ring_size / ENA_TX_POLL_BUDGET_DIVIDER. 108 */ 109 #define ENA_TX_POLL_BUDGET_DIVIDER 4 110 111 /* Refill Rx queue when number of required descriptors is above 112 * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER or ENA_RX_REFILL_THRESH_PACKET 113 */ 114 #define ENA_RX_REFILL_THRESH_DIVIDER 8 115 #define ENA_RX_REFILL_THRESH_PACKET 256 116 117 /* Number of queues to check for missing queues per timer service */ 118 #define ENA_MONITORED_TX_QUEUES 4 119 /* Max timeout packets before device reset */ 120 #define MAX_NUM_OF_TIMEOUTED_PACKETS 128 121 122 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 123 124 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 125 #define ENA_RX_RING_IDX_ADD(idx, n, ring_size) \ 126 (((idx) + (n)) & ((ring_size) - 1)) 127 128 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 129 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 130 131 #define ENA_MGMNT_IRQ_IDX 0 132 #define ENA_IO_IRQ_FIRST_IDX 1 133 #define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q)) 134 135 /* ENA device should send keep alive msg every 1 sec. 136 * We wait for 6 sec just to be on the safe side. 137 */ 138 #define ENA_DEVICE_KALIVE_TIMEOUT (6 * HZ) 139 #define ENA_MAX_NO_INTERRUPT_ITERATIONS 3 140 141 #define ENA_MMIO_DISABLE_REG_READ BIT(0) 142 143 struct ena_irq { 144 irq_handler_t handler; 145 void *data; 146 int cpu; 147 u32 vector; 148 cpumask_t affinity_hint_mask; 149 char name[ENA_IRQNAME_SIZE]; 150 }; 151 152 struct ena_napi { 153 struct napi_struct napi ____cacheline_aligned; 154 struct ena_ring *tx_ring; 155 struct ena_ring *rx_ring; 156 u32 qid; 157 struct dim dim; 158 }; 159 160 struct ena_calc_queue_size_ctx { 161 struct ena_com_dev_get_features_ctx *get_feat_ctx; 162 struct ena_com_dev *ena_dev; 163 struct pci_dev *pdev; 164 u16 tx_queue_size; 165 u16 rx_queue_size; 166 u16 max_tx_queue_size; 167 u16 max_rx_queue_size; 168 u16 max_tx_sgl_size; 169 u16 max_rx_sgl_size; 170 }; 171 172 struct ena_tx_buffer { 173 struct sk_buff *skb; 174 /* num of ena desc for this specific skb 175 * (includes data desc and metadata desc) 176 */ 177 u32 tx_descs; 178 /* num of buffers used by this skb */ 179 u32 num_of_bufs; 180 181 /* Indicate if bufs[0] map the linear data of the skb. */ 182 u8 map_linear_data; 183 184 /* Used for detect missing tx packets to limit the number of prints */ 185 u32 print_once; 186 /* Save the last jiffies to detect missing tx packets 187 * 188 * sets to non zero value on ena_start_xmit and set to zero on 189 * napi and timer_Service_routine. 190 * 191 * while this value is not protected by lock, 192 * a given packet is not expected to be handled by ena_start_xmit 193 * and by napi/timer_service at the same time. 194 */ 195 unsigned long last_jiffies; 196 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS]; 197 } ____cacheline_aligned; 198 199 struct ena_rx_buffer { 200 struct sk_buff *skb; 201 struct page *page; 202 u32 page_offset; 203 struct ena_com_buf ena_buf; 204 } ____cacheline_aligned; 205 206 struct ena_stats_tx { 207 u64 cnt; 208 u64 bytes; 209 u64 queue_stop; 210 u64 prepare_ctx_err; 211 u64 queue_wakeup; 212 u64 dma_mapping_err; 213 u64 linearize; 214 u64 linearize_failed; 215 u64 napi_comp; 216 u64 tx_poll; 217 u64 doorbells; 218 u64 bad_req_id; 219 u64 llq_buffer_copy; 220 u64 missed_tx; 221 }; 222 223 struct ena_stats_rx { 224 u64 cnt; 225 u64 bytes; 226 u64 rx_copybreak_pkt; 227 u64 csum_good; 228 u64 refil_partial; 229 u64 bad_csum; 230 u64 page_alloc_fail; 231 u64 skb_alloc_fail; 232 u64 dma_mapping_err; 233 u64 bad_desc_num; 234 u64 bad_req_id; 235 u64 empty_rx_ring; 236 u64 csum_unchecked; 237 }; 238 239 struct ena_ring { 240 /* Holds the empty requests for TX/RX 241 * out of order completions 242 */ 243 u16 *free_ids; 244 245 union { 246 struct ena_tx_buffer *tx_buffer_info; 247 struct ena_rx_buffer *rx_buffer_info; 248 }; 249 250 /* cache ptr to avoid using the adapter */ 251 struct device *dev; 252 struct pci_dev *pdev; 253 struct napi_struct *napi; 254 struct net_device *netdev; 255 struct ena_com_dev *ena_dev; 256 struct ena_adapter *adapter; 257 struct ena_com_io_cq *ena_com_io_cq; 258 struct ena_com_io_sq *ena_com_io_sq; 259 260 u16 next_to_use; 261 u16 next_to_clean; 262 u16 rx_copybreak; 263 u16 qid; 264 u16 mtu; 265 u16 sgl_size; 266 267 /* The maximum header length the device can handle */ 268 u8 tx_max_header_size; 269 270 bool first_interrupt; 271 u16 no_interrupt_event_cnt; 272 273 /* cpu for TPH */ 274 int cpu; 275 /* number of tx/rx_buffer_info's entries */ 276 int ring_size; 277 278 enum ena_admin_placement_policy_type tx_mem_queue_type; 279 280 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]; 281 u32 smoothed_interval; 282 u32 per_napi_packets; 283 u16 non_empty_napi_events; 284 struct u64_stats_sync syncp; 285 union { 286 struct ena_stats_tx tx_stats; 287 struct ena_stats_rx rx_stats; 288 }; 289 290 u8 *push_buf_intermediate_buf; 291 int empty_rx_queue; 292 } ____cacheline_aligned; 293 294 struct ena_stats_dev { 295 u64 tx_timeout; 296 u64 suspend; 297 u64 resume; 298 u64 wd_expired; 299 u64 interface_up; 300 u64 interface_down; 301 u64 admin_q_pause; 302 u64 rx_drops; 303 }; 304 305 enum ena_flags_t { 306 ENA_FLAG_DEVICE_RUNNING, 307 ENA_FLAG_DEV_UP, 308 ENA_FLAG_LINK_UP, 309 ENA_FLAG_MSIX_ENABLED, 310 ENA_FLAG_TRIGGER_RESET, 311 ENA_FLAG_ONGOING_RESET 312 }; 313 314 /* adapter specific private data structure */ 315 struct ena_adapter { 316 struct ena_com_dev *ena_dev; 317 /* OS defined structs */ 318 struct net_device *netdev; 319 struct pci_dev *pdev; 320 321 /* rx packets that shorter that this len will be copied to the skb 322 * header 323 */ 324 u32 rx_copybreak; 325 u32 max_mtu; 326 327 int num_queues; 328 329 int msix_vecs; 330 331 u32 missing_tx_completion_threshold; 332 333 u32 requested_tx_ring_size; 334 u32 requested_rx_ring_size; 335 336 u32 max_tx_ring_size; 337 u32 max_rx_ring_size; 338 339 u32 msg_enable; 340 341 u16 max_tx_sgl_size; 342 u16 max_rx_sgl_size; 343 344 u8 mac_addr[ETH_ALEN]; 345 346 unsigned long keep_alive_timeout; 347 unsigned long missing_tx_completion_to; 348 349 char name[ENA_NAME_MAX_LEN]; 350 351 unsigned long flags; 352 /* TX */ 353 struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES] 354 ____cacheline_aligned_in_smp; 355 356 /* RX */ 357 struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES] 358 ____cacheline_aligned_in_smp; 359 360 struct ena_napi ena_napi[ENA_MAX_NUM_IO_QUEUES]; 361 362 struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)]; 363 364 /* timer service */ 365 struct work_struct reset_task; 366 struct timer_list timer_service; 367 368 bool wd_state; 369 bool dev_up_before_reset; 370 unsigned long last_keep_alive_jiffies; 371 372 struct u64_stats_sync syncp; 373 struct ena_stats_dev dev_stats; 374 375 /* last queue index that was checked for uncompleted tx packets */ 376 u32 last_monitored_tx_qid; 377 378 enum ena_regs_reset_reason_types reset_reason; 379 }; 380 381 void ena_set_ethtool_ops(struct net_device *netdev); 382 383 void ena_dump_stats_to_dmesg(struct ena_adapter *adapter); 384 385 void ena_dump_stats_to_buf(struct ena_adapter *adapter, u8 *buf); 386 387 int ena_update_queue_sizes(struct ena_adapter *adapter, 388 u32 new_tx_size, 389 u32 new_rx_size); 390 391 int ena_get_sset_count(struct net_device *netdev, int sset); 392 393 #endif /* !(ENA_H) */ 394