1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* 3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved. 4 */ 5 6 #ifndef ENA_H 7 #define ENA_H 8 9 #include <linux/bitops.h> 10 #include <linux/dim.h> 11 #include <linux/etherdevice.h> 12 #include <linux/if_vlan.h> 13 #include <linux/inetdevice.h> 14 #include <linux/interrupt.h> 15 #include <linux/netdevice.h> 16 #include <linux/skbuff.h> 17 #include <net/xdp.h> 18 #include <uapi/linux/bpf.h> 19 #include <net/devlink.h> 20 21 #include "ena_com.h" 22 #include "ena_eth_com.h" 23 24 #define DRV_MODULE_GEN_MAJOR 2 25 #define DRV_MODULE_GEN_MINOR 1 26 #define DRV_MODULE_GEN_SUBMINOR 0 27 28 #define DRV_MODULE_NAME "ena" 29 30 #define DEVICE_NAME "Elastic Network Adapter (ENA)" 31 32 /* 1 for AENQ + ADMIN */ 33 #define ENA_ADMIN_MSIX_VEC 1 34 #define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues)) 35 36 /* The ENA buffer length fields is 16 bit long. So when PAGE_SIZE == 64kB the 37 * driver passes 0. 38 * Since the max packet size the ENA handles is ~9kB limit the buffer length to 39 * 16kB. 40 */ 41 #if PAGE_SIZE > SZ_16K 42 #define ENA_PAGE_SIZE (_AC(SZ_16K, UL)) 43 #else 44 #define ENA_PAGE_SIZE PAGE_SIZE 45 #endif 46 47 #define ENA_MIN_MSIX_VEC 2 48 49 #define ENA_REG_BAR 0 50 #define ENA_MEM_BAR 2 51 #define ENA_BAR_MASK (BIT(ENA_REG_BAR) | BIT(ENA_MEM_BAR)) 52 53 #define ENA_DEFAULT_RING_SIZE (1024) 54 #define ENA_MIN_RING_SIZE (256) 55 56 #define ENA_MIN_RX_BUF_SIZE (2048) 57 58 #define ENA_MIN_NUM_IO_QUEUES (1) 59 60 #define ENA_TX_WAKEUP_THRESH (MAX_SKB_FRAGS + 2) 61 #define ENA_DEFAULT_RX_COPYBREAK (256 - NET_IP_ALIGN) 62 63 #define ENA_MIN_MTU 128 64 65 #define ENA_NAME_MAX_LEN 20 66 #define ENA_IRQNAME_SIZE 40 67 68 #define ENA_PKT_MAX_BUFS 19 69 70 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 71 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 72 73 /* The number of tx packet completions that will be handled each NAPI poll 74 * cycle is ring_size / ENA_TX_POLL_BUDGET_DIVIDER. 75 */ 76 #define ENA_TX_POLL_BUDGET_DIVIDER 4 77 78 /* Refill Rx queue when number of required descriptors is above 79 * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER or ENA_RX_REFILL_THRESH_PACKET 80 */ 81 #define ENA_RX_REFILL_THRESH_DIVIDER 8 82 #define ENA_RX_REFILL_THRESH_PACKET 256 83 84 /* Number of queues to check for missing queues per timer service */ 85 #define ENA_MONITORED_TX_QUEUES 4 86 /* Max timeout packets before device reset */ 87 #define MAX_NUM_OF_TIMEOUTED_PACKETS 128 88 89 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 90 91 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 92 #define ENA_RX_RING_IDX_ADD(idx, n, ring_size) \ 93 (((idx) + (n)) & ((ring_size) - 1)) 94 95 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 96 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 97 #define ENA_IO_TXQ_IDX_TO_COMBINED_IDX(q) ((q) / 2) 98 #define ENA_IO_RXQ_IDX_TO_COMBINED_IDX(q) (((q) - 1) / 2) 99 100 #define ENA_MGMNT_IRQ_IDX 0 101 #define ENA_IO_IRQ_FIRST_IDX 1 102 #define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q)) 103 104 #define ENA_ADMIN_POLL_DELAY_US 100 105 106 /* ENA device should send keep alive msg every 1 sec. 107 * We wait for 6 sec just to be on the safe side. 108 */ 109 #define ENA_DEVICE_KALIVE_TIMEOUT (6 * HZ) 110 #define ENA_MAX_NO_INTERRUPT_ITERATIONS 3 111 112 #define ENA_MMIO_DISABLE_REG_READ BIT(0) 113 114 struct ena_phc_info; 115 116 struct ena_irq { 117 irq_handler_t handler; 118 void *data; 119 int cpu; 120 u32 vector; 121 cpumask_t affinity_hint_mask; 122 char name[ENA_IRQNAME_SIZE]; 123 }; 124 125 struct ena_napi { 126 u8 first_interrupt ____cacheline_aligned; 127 u8 interrupts_masked; 128 struct napi_struct napi; 129 struct ena_ring *tx_ring; 130 struct ena_ring *rx_ring; 131 u32 qid; 132 struct dim dim; 133 }; 134 135 struct ena_tx_buffer { 136 union { 137 struct sk_buff *skb; 138 /* XDP buffer structure which is used for sending packets in 139 * the xdp queues 140 */ 141 struct xdp_frame *xdpf; 142 }; 143 /* num of ena desc for this specific skb 144 * (includes data desc and metadata desc) 145 */ 146 u32 tx_descs; 147 /* num of buffers used by this skb */ 148 u32 num_of_bufs; 149 150 /* Total size of all buffers in bytes */ 151 u32 total_tx_size; 152 153 /* Indicate if bufs[0] map the linear data of the skb. */ 154 u8 map_linear_data; 155 156 /* Used for detect missing tx packets to limit the number of prints */ 157 u8 print_once; 158 /* Save the last jiffies to detect missing tx packets 159 * 160 * sets to non zero value on ena_start_xmit and set to zero on 161 * napi and timer_Service_routine. 162 * 163 * while this value is not protected by lock, 164 * a given packet is not expected to be handled by ena_start_xmit 165 * and by napi/timer_service at the same time. 166 */ 167 unsigned long last_jiffies; 168 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS]; 169 } ____cacheline_aligned; 170 171 struct ena_rx_buffer { 172 struct sk_buff *skb; 173 struct page *page; 174 dma_addr_t dma_addr; 175 u32 page_offset; 176 u32 buf_offset; 177 struct ena_com_buf ena_buf; 178 } ____cacheline_aligned; 179 180 struct ena_stats_tx { 181 u64 cnt; 182 u64 bytes; 183 u64 queue_stop; 184 u64 prepare_ctx_err; 185 u64 queue_wakeup; 186 u64 dma_mapping_err; 187 u64 linearize; 188 u64 linearize_failed; 189 u64 napi_comp; 190 u64 tx_poll; 191 u64 doorbells; 192 u64 bad_req_id; 193 u64 llq_buffer_copy; 194 u64 missed_tx; 195 u64 unmask_interrupt; 196 u64 last_napi_jiffies; 197 }; 198 199 struct ena_stats_rx { 200 u64 cnt; 201 u64 bytes; 202 u64 rx_copybreak_pkt; 203 u64 csum_good; 204 u64 refil_partial; 205 u64 csum_bad; 206 u64 page_alloc_fail; 207 u64 skb_alloc_fail; 208 u64 dma_mapping_err; 209 u64 bad_desc_num; 210 u64 bad_req_id; 211 u64 empty_rx_ring; 212 u64 csum_unchecked; 213 u64 xdp_aborted; 214 u64 xdp_drop; 215 u64 xdp_pass; 216 u64 xdp_tx; 217 u64 xdp_invalid; 218 u64 xdp_redirect; 219 }; 220 221 struct ena_ring { 222 /* Holds the empty requests for TX/RX 223 * out of order completions 224 */ 225 u16 *free_ids; 226 227 union { 228 struct ena_tx_buffer *tx_buffer_info; 229 struct ena_rx_buffer *rx_buffer_info; 230 }; 231 232 /* cache ptr to avoid using the adapter */ 233 struct device *dev; 234 struct pci_dev *pdev; 235 struct napi_struct *napi; 236 struct net_device *netdev; 237 struct ena_com_dev *ena_dev; 238 struct ena_adapter *adapter; 239 struct ena_com_io_cq *ena_com_io_cq; 240 struct ena_com_io_sq *ena_com_io_sq; 241 struct bpf_prog *xdp_bpf_prog; 242 struct xdp_rxq_info xdp_rxq; 243 spinlock_t xdp_tx_lock; /* synchronize XDP TX/Redirect traffic */ 244 /* Used for rx queues only to point to the xdp tx ring, to 245 * which traffic should be redirected from this rx ring. 246 */ 247 struct ena_ring *xdp_ring; 248 249 u16 next_to_use; 250 u16 next_to_clean; 251 u16 rx_copybreak; 252 u16 rx_headroom; 253 u16 qid; 254 u16 mtu; 255 u16 sgl_size; 256 257 /* The maximum header length the device can handle */ 258 u8 tx_max_header_size; 259 260 bool disable_meta_caching; 261 u16 no_interrupt_event_cnt; 262 263 /* cpu and NUMA for TPH */ 264 int cpu; 265 int numa_node; 266 267 /* number of tx/rx_buffer_info's entries */ 268 int ring_size; 269 270 enum ena_admin_placement_policy_type tx_mem_queue_type; 271 272 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]; 273 u32 smoothed_interval; 274 u32 per_napi_packets; 275 u16 non_empty_napi_events; 276 struct u64_stats_sync syncp; 277 union { 278 struct ena_stats_tx tx_stats; 279 struct ena_stats_rx rx_stats; 280 }; 281 282 u8 *push_buf_intermediate_buf; 283 int empty_rx_queue; 284 } ____cacheline_aligned; 285 286 struct ena_stats_dev { 287 u64 tx_timeout; 288 u64 suspend; 289 u64 resume; 290 u64 wd_expired; 291 u64 interface_up; 292 u64 interface_down; 293 u64 admin_q_pause; 294 u64 rx_drops; 295 u64 tx_drops; 296 u64 reset_fail; 297 }; 298 299 enum ena_flags_t { 300 ENA_FLAG_DEVICE_RUNNING, 301 ENA_FLAG_DEV_UP, 302 ENA_FLAG_LINK_UP, 303 ENA_FLAG_MSIX_ENABLED, 304 ENA_FLAG_TRIGGER_RESET, 305 ENA_FLAG_ONGOING_RESET 306 }; 307 308 /* adapter specific private data structure */ 309 struct ena_adapter { 310 struct ena_com_dev *ena_dev; 311 /* OS defined structs */ 312 struct net_device *netdev; 313 struct pci_dev *pdev; 314 315 /* rx packets that shorter that this len will be copied to the skb 316 * header 317 */ 318 u32 rx_copybreak; 319 u32 max_mtu; 320 321 u32 num_io_queues; 322 u32 max_num_io_queues; 323 324 int msix_vecs; 325 326 u32 missing_tx_completion_threshold; 327 328 u32 requested_tx_ring_size; 329 u32 requested_rx_ring_size; 330 331 u32 max_tx_ring_size; 332 u32 max_rx_ring_size; 333 334 u32 msg_enable; 335 336 /* large_llq_header_enabled is used for two purposes: 337 * 1. Indicates that large LLQ has been requested. 338 * 2. Indicates whether large LLQ is set or not after device 339 * initialization / configuration. 340 */ 341 bool large_llq_header_enabled; 342 bool large_llq_header_supported; 343 344 u16 max_tx_sgl_size; 345 u16 max_rx_sgl_size; 346 347 u8 mac_addr[ETH_ALEN]; 348 349 unsigned long keep_alive_timeout; 350 unsigned long missing_tx_completion_to; 351 352 char name[ENA_NAME_MAX_LEN]; 353 354 struct ena_phc_info *phc_info; 355 356 unsigned long flags; 357 /* TX */ 358 struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES] 359 ____cacheline_aligned_in_smp; 360 361 /* RX */ 362 struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES] 363 ____cacheline_aligned_in_smp; 364 365 struct ena_napi ena_napi[ENA_MAX_NUM_IO_QUEUES]; 366 367 struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)]; 368 369 /* timer service */ 370 struct work_struct reset_task; 371 struct timer_list timer_service; 372 373 bool wd_state; 374 bool dev_up_before_reset; 375 bool disable_meta_caching; 376 unsigned long last_keep_alive_jiffies; 377 378 struct u64_stats_sync syncp; 379 struct ena_stats_dev dev_stats; 380 struct ena_admin_eni_stats eni_stats; 381 struct ena_admin_ena_srd_info ena_srd_info; 382 383 /* last queue index that was checked for uncompleted tx packets */ 384 u32 last_monitored_tx_qid; 385 386 enum ena_regs_reset_reason_types reset_reason; 387 388 struct bpf_prog *xdp_bpf_prog; 389 u32 xdp_first_ring; 390 u32 xdp_num_queues; 391 392 struct devlink *devlink; 393 struct devlink_port devlink_port; 394 #ifdef CONFIG_DEBUG_FS 395 396 struct dentry *debugfs_base; 397 #endif /* CONFIG_DEBUG_FS */ 398 }; 399 400 void ena_set_ethtool_ops(struct net_device *netdev); 401 402 void ena_dump_stats_to_dmesg(struct ena_adapter *adapter); 403 404 void ena_dump_stats_to_buf(struct ena_adapter *adapter, u8 *buf); 405 406 407 int ena_update_queue_params(struct ena_adapter *adapter, 408 u32 new_tx_size, 409 u32 new_rx_size, 410 u32 new_llq_header_len); 411 412 int ena_update_queue_count(struct ena_adapter *adapter, u32 new_channel_count); 413 414 int ena_set_rx_copybreak(struct ena_adapter *adapter, u32 rx_copybreak); 415 416 int ena_get_sset_count(struct net_device *netdev, int sset); 417 418 static inline void ena_reset_device(struct ena_adapter *adapter, 419 enum ena_regs_reset_reason_types reset_reason) 420 { 421 adapter->reset_reason = reset_reason; 422 /* Make sure reset reason is set before triggering the reset */ 423 smp_mb__before_atomic(); 424 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags); 425 } 426 427 int ena_destroy_device(struct ena_adapter *adapter, bool graceful); 428 int ena_restore_device(struct ena_adapter *adapter); 429 int handle_invalid_req_id(struct ena_ring *ring, u16 req_id, 430 struct ena_tx_buffer *tx_info, bool is_xdp); 431 432 /* Increase a stat by cnt while holding syncp seqlock on 32bit machines */ 433 static inline void ena_increase_stat(u64 *statp, u64 cnt, 434 struct u64_stats_sync *syncp) 435 { 436 u64_stats_update_begin(syncp); 437 (*statp) += cnt; 438 u64_stats_update_end(syncp); 439 } 440 441 static inline void ena_ring_tx_doorbell(struct ena_ring *tx_ring) 442 { 443 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 444 ena_increase_stat(&tx_ring->tx_stats.doorbells, 1, &tx_ring->syncp); 445 } 446 447 int ena_xmit_common(struct ena_adapter *adapter, 448 struct ena_ring *ring, 449 struct ena_tx_buffer *tx_info, 450 struct ena_com_tx_ctx *ena_tx_ctx, 451 u16 next_to_use, 452 u32 bytes); 453 void ena_unmap_tx_buff(struct ena_ring *tx_ring, 454 struct ena_tx_buffer *tx_info); 455 void ena_init_io_rings(struct ena_adapter *adapter, 456 int first_index, int count); 457 int ena_create_io_tx_queues_in_range(struct ena_adapter *adapter, 458 int first_index, int count); 459 int ena_setup_tx_resources_in_range(struct ena_adapter *adapter, 460 int first_index, int count); 461 void ena_free_all_io_tx_resources_in_range(struct ena_adapter *adapter, 462 int first_index, int count); 463 void ena_free_all_io_tx_resources(struct ena_adapter *adapter); 464 void ena_down(struct ena_adapter *adapter); 465 int ena_up(struct ena_adapter *adapter); 466 void ena_unmask_interrupt(struct ena_ring *tx_ring, struct ena_ring *rx_ring); 467 void ena_update_ring_numa_node(struct ena_ring *tx_ring, 468 struct ena_ring *rx_ring); 469 #endif /* !(ENA_H) */ 470