1 /* 2 * Copyright 2015 Amazon.com, Inc. or its affiliates. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 34 35 #ifdef CONFIG_RFS_ACCEL 36 #include <linux/cpu_rmap.h> 37 #endif /* CONFIG_RFS_ACCEL */ 38 #include <linux/ethtool.h> 39 #include <linux/if_vlan.h> 40 #include <linux/kernel.h> 41 #include <linux/module.h> 42 #include <linux/moduleparam.h> 43 #include <linux/numa.h> 44 #include <linux/pci.h> 45 #include <linux/utsname.h> 46 #include <linux/version.h> 47 #include <linux/vmalloc.h> 48 #include <net/ip.h> 49 50 #include "ena_netdev.h" 51 #include "ena_pci_id_tbl.h" 52 53 static char version[] = DEVICE_NAME " v" DRV_MODULE_VERSION "\n"; 54 55 MODULE_AUTHOR("Amazon.com, Inc. or its affiliates"); 56 MODULE_DESCRIPTION(DEVICE_NAME); 57 MODULE_LICENSE("GPL"); 58 MODULE_VERSION(DRV_MODULE_VERSION); 59 60 /* Time in jiffies before concluding the transmitter is hung. */ 61 #define TX_TIMEOUT (5 * HZ) 62 63 #define ENA_NAPI_BUDGET 64 64 65 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | \ 66 NETIF_MSG_TX_DONE | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR) 67 static int debug = -1; 68 module_param(debug, int, 0); 69 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 70 71 static struct ena_aenq_handlers aenq_handlers; 72 73 static struct workqueue_struct *ena_wq; 74 75 MODULE_DEVICE_TABLE(pci, ena_pci_tbl); 76 77 static int ena_rss_init_default(struct ena_adapter *adapter); 78 79 static void ena_tx_timeout(struct net_device *dev) 80 { 81 struct ena_adapter *adapter = netdev_priv(dev); 82 83 /* Change the state of the device to trigger reset 84 * Check that we are not in the middle or a trigger already 85 */ 86 87 if (test_and_set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags)) 88 return; 89 90 u64_stats_update_begin(&adapter->syncp); 91 adapter->dev_stats.tx_timeout++; 92 u64_stats_update_end(&adapter->syncp); 93 94 netif_err(adapter, tx_err, dev, "Transmit time out\n"); 95 } 96 97 static void update_rx_ring_mtu(struct ena_adapter *adapter, int mtu) 98 { 99 int i; 100 101 for (i = 0; i < adapter->num_queues; i++) 102 adapter->rx_ring[i].mtu = mtu; 103 } 104 105 static int ena_change_mtu(struct net_device *dev, int new_mtu) 106 { 107 struct ena_adapter *adapter = netdev_priv(dev); 108 int ret; 109 110 ret = ena_com_set_dev_mtu(adapter->ena_dev, new_mtu); 111 if (!ret) { 112 netif_dbg(adapter, drv, dev, "set MTU to %d\n", new_mtu); 113 update_rx_ring_mtu(adapter, new_mtu); 114 dev->mtu = new_mtu; 115 } else { 116 netif_err(adapter, drv, dev, "Failed to set MTU to %d\n", 117 new_mtu); 118 } 119 120 return ret; 121 } 122 123 static int ena_init_rx_cpu_rmap(struct ena_adapter *adapter) 124 { 125 #ifdef CONFIG_RFS_ACCEL 126 u32 i; 127 int rc; 128 129 adapter->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(adapter->num_queues); 130 if (!adapter->netdev->rx_cpu_rmap) 131 return -ENOMEM; 132 for (i = 0; i < adapter->num_queues; i++) { 133 int irq_idx = ENA_IO_IRQ_IDX(i); 134 135 rc = irq_cpu_rmap_add(adapter->netdev->rx_cpu_rmap, 136 pci_irq_vector(adapter->pdev, irq_idx)); 137 if (rc) { 138 free_irq_cpu_rmap(adapter->netdev->rx_cpu_rmap); 139 adapter->netdev->rx_cpu_rmap = NULL; 140 return rc; 141 } 142 } 143 #endif /* CONFIG_RFS_ACCEL */ 144 return 0; 145 } 146 147 static void ena_init_io_rings_common(struct ena_adapter *adapter, 148 struct ena_ring *ring, u16 qid) 149 { 150 ring->qid = qid; 151 ring->pdev = adapter->pdev; 152 ring->dev = &adapter->pdev->dev; 153 ring->netdev = adapter->netdev; 154 ring->napi = &adapter->ena_napi[qid].napi; 155 ring->adapter = adapter; 156 ring->ena_dev = adapter->ena_dev; 157 ring->per_napi_packets = 0; 158 ring->per_napi_bytes = 0; 159 ring->cpu = 0; 160 u64_stats_init(&ring->syncp); 161 } 162 163 static void ena_init_io_rings(struct ena_adapter *adapter) 164 { 165 struct ena_com_dev *ena_dev; 166 struct ena_ring *txr, *rxr; 167 int i; 168 169 ena_dev = adapter->ena_dev; 170 171 for (i = 0; i < adapter->num_queues; i++) { 172 txr = &adapter->tx_ring[i]; 173 rxr = &adapter->rx_ring[i]; 174 175 /* TX/RX common ring state */ 176 ena_init_io_rings_common(adapter, txr, i); 177 ena_init_io_rings_common(adapter, rxr, i); 178 179 /* TX specific ring state */ 180 txr->ring_size = adapter->tx_ring_size; 181 txr->tx_max_header_size = ena_dev->tx_max_header_size; 182 txr->tx_mem_queue_type = ena_dev->tx_mem_queue_type; 183 txr->sgl_size = adapter->max_tx_sgl_size; 184 txr->smoothed_interval = 185 ena_com_get_nonadaptive_moderation_interval_tx(ena_dev); 186 187 /* RX specific ring state */ 188 rxr->ring_size = adapter->rx_ring_size; 189 rxr->rx_copybreak = adapter->rx_copybreak; 190 rxr->sgl_size = adapter->max_rx_sgl_size; 191 rxr->smoothed_interval = 192 ena_com_get_nonadaptive_moderation_interval_rx(ena_dev); 193 } 194 } 195 196 /* ena_setup_tx_resources - allocate I/O Tx resources (Descriptors) 197 * @adapter: network interface device structure 198 * @qid: queue index 199 * 200 * Return 0 on success, negative on failure 201 */ 202 static int ena_setup_tx_resources(struct ena_adapter *adapter, int qid) 203 { 204 struct ena_ring *tx_ring = &adapter->tx_ring[qid]; 205 struct ena_irq *ena_irq = &adapter->irq_tbl[ENA_IO_IRQ_IDX(qid)]; 206 int size, i, node; 207 208 if (tx_ring->tx_buffer_info) { 209 netif_err(adapter, ifup, 210 adapter->netdev, "tx_buffer_info info is not NULL"); 211 return -EEXIST; 212 } 213 214 size = sizeof(struct ena_tx_buffer) * tx_ring->ring_size; 215 node = cpu_to_node(ena_irq->cpu); 216 217 tx_ring->tx_buffer_info = vzalloc_node(size, node); 218 if (!tx_ring->tx_buffer_info) { 219 tx_ring->tx_buffer_info = vzalloc(size); 220 if (!tx_ring->tx_buffer_info) 221 return -ENOMEM; 222 } 223 224 size = sizeof(u16) * tx_ring->ring_size; 225 tx_ring->free_tx_ids = vzalloc_node(size, node); 226 if (!tx_ring->free_tx_ids) { 227 tx_ring->free_tx_ids = vzalloc(size); 228 if (!tx_ring->free_tx_ids) { 229 vfree(tx_ring->tx_buffer_info); 230 return -ENOMEM; 231 } 232 } 233 234 /* Req id ring for TX out of order completions */ 235 for (i = 0; i < tx_ring->ring_size; i++) 236 tx_ring->free_tx_ids[i] = i; 237 238 /* Reset tx statistics */ 239 memset(&tx_ring->tx_stats, 0x0, sizeof(tx_ring->tx_stats)); 240 241 tx_ring->next_to_use = 0; 242 tx_ring->next_to_clean = 0; 243 tx_ring->cpu = ena_irq->cpu; 244 return 0; 245 } 246 247 /* ena_free_tx_resources - Free I/O Tx Resources per Queue 248 * @adapter: network interface device structure 249 * @qid: queue index 250 * 251 * Free all transmit software resources 252 */ 253 static void ena_free_tx_resources(struct ena_adapter *adapter, int qid) 254 { 255 struct ena_ring *tx_ring = &adapter->tx_ring[qid]; 256 257 vfree(tx_ring->tx_buffer_info); 258 tx_ring->tx_buffer_info = NULL; 259 260 vfree(tx_ring->free_tx_ids); 261 tx_ring->free_tx_ids = NULL; 262 } 263 264 /* ena_setup_all_tx_resources - allocate I/O Tx queues resources for All queues 265 * @adapter: private structure 266 * 267 * Return 0 on success, negative on failure 268 */ 269 static int ena_setup_all_tx_resources(struct ena_adapter *adapter) 270 { 271 int i, rc = 0; 272 273 for (i = 0; i < adapter->num_queues; i++) { 274 rc = ena_setup_tx_resources(adapter, i); 275 if (rc) 276 goto err_setup_tx; 277 } 278 279 return 0; 280 281 err_setup_tx: 282 283 netif_err(adapter, ifup, adapter->netdev, 284 "Tx queue %d: allocation failed\n", i); 285 286 /* rewind the index freeing the rings as we go */ 287 while (i--) 288 ena_free_tx_resources(adapter, i); 289 return rc; 290 } 291 292 /* ena_free_all_io_tx_resources - Free I/O Tx Resources for All Queues 293 * @adapter: board private structure 294 * 295 * Free all transmit software resources 296 */ 297 static void ena_free_all_io_tx_resources(struct ena_adapter *adapter) 298 { 299 int i; 300 301 for (i = 0; i < adapter->num_queues; i++) 302 ena_free_tx_resources(adapter, i); 303 } 304 305 /* ena_setup_rx_resources - allocate I/O Rx resources (Descriptors) 306 * @adapter: network interface device structure 307 * @qid: queue index 308 * 309 * Returns 0 on success, negative on failure 310 */ 311 static int ena_setup_rx_resources(struct ena_adapter *adapter, 312 u32 qid) 313 { 314 struct ena_ring *rx_ring = &adapter->rx_ring[qid]; 315 struct ena_irq *ena_irq = &adapter->irq_tbl[ENA_IO_IRQ_IDX(qid)]; 316 int size, node; 317 318 if (rx_ring->rx_buffer_info) { 319 netif_err(adapter, ifup, adapter->netdev, 320 "rx_buffer_info is not NULL"); 321 return -EEXIST; 322 } 323 324 /* alloc extra element so in rx path 325 * we can always prefetch rx_info + 1 326 */ 327 size = sizeof(struct ena_rx_buffer) * (rx_ring->ring_size + 1); 328 node = cpu_to_node(ena_irq->cpu); 329 330 rx_ring->rx_buffer_info = vzalloc_node(size, node); 331 if (!rx_ring->rx_buffer_info) { 332 rx_ring->rx_buffer_info = vzalloc(size); 333 if (!rx_ring->rx_buffer_info) 334 return -ENOMEM; 335 } 336 337 /* Reset rx statistics */ 338 memset(&rx_ring->rx_stats, 0x0, sizeof(rx_ring->rx_stats)); 339 340 rx_ring->next_to_clean = 0; 341 rx_ring->next_to_use = 0; 342 rx_ring->cpu = ena_irq->cpu; 343 344 return 0; 345 } 346 347 /* ena_free_rx_resources - Free I/O Rx Resources 348 * @adapter: network interface device structure 349 * @qid: queue index 350 * 351 * Free all receive software resources 352 */ 353 static void ena_free_rx_resources(struct ena_adapter *adapter, 354 u32 qid) 355 { 356 struct ena_ring *rx_ring = &adapter->rx_ring[qid]; 357 358 vfree(rx_ring->rx_buffer_info); 359 rx_ring->rx_buffer_info = NULL; 360 } 361 362 /* ena_setup_all_rx_resources - allocate I/O Rx queues resources for all queues 363 * @adapter: board private structure 364 * 365 * Return 0 on success, negative on failure 366 */ 367 static int ena_setup_all_rx_resources(struct ena_adapter *adapter) 368 { 369 int i, rc = 0; 370 371 for (i = 0; i < adapter->num_queues; i++) { 372 rc = ena_setup_rx_resources(adapter, i); 373 if (rc) 374 goto err_setup_rx; 375 } 376 377 return 0; 378 379 err_setup_rx: 380 381 netif_err(adapter, ifup, adapter->netdev, 382 "Rx queue %d: allocation failed\n", i); 383 384 /* rewind the index freeing the rings as we go */ 385 while (i--) 386 ena_free_rx_resources(adapter, i); 387 return rc; 388 } 389 390 /* ena_free_all_io_rx_resources - Free I/O Rx Resources for All Queues 391 * @adapter: board private structure 392 * 393 * Free all receive software resources 394 */ 395 static void ena_free_all_io_rx_resources(struct ena_adapter *adapter) 396 { 397 int i; 398 399 for (i = 0; i < adapter->num_queues; i++) 400 ena_free_rx_resources(adapter, i); 401 } 402 403 static inline int ena_alloc_rx_page(struct ena_ring *rx_ring, 404 struct ena_rx_buffer *rx_info, gfp_t gfp) 405 { 406 struct ena_com_buf *ena_buf; 407 struct page *page; 408 dma_addr_t dma; 409 410 /* if previous allocated page is not used */ 411 if (unlikely(rx_info->page)) 412 return 0; 413 414 page = alloc_page(gfp); 415 if (unlikely(!page)) { 416 u64_stats_update_begin(&rx_ring->syncp); 417 rx_ring->rx_stats.page_alloc_fail++; 418 u64_stats_update_end(&rx_ring->syncp); 419 return -ENOMEM; 420 } 421 422 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, 423 DMA_FROM_DEVICE); 424 if (unlikely(dma_mapping_error(rx_ring->dev, dma))) { 425 u64_stats_update_begin(&rx_ring->syncp); 426 rx_ring->rx_stats.dma_mapping_err++; 427 u64_stats_update_end(&rx_ring->syncp); 428 429 __free_page(page); 430 return -EIO; 431 } 432 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev, 433 "alloc page %p, rx_info %p\n", page, rx_info); 434 435 rx_info->page = page; 436 rx_info->page_offset = 0; 437 ena_buf = &rx_info->ena_buf; 438 ena_buf->paddr = dma; 439 ena_buf->len = PAGE_SIZE; 440 441 return 0; 442 } 443 444 static void ena_free_rx_page(struct ena_ring *rx_ring, 445 struct ena_rx_buffer *rx_info) 446 { 447 struct page *page = rx_info->page; 448 struct ena_com_buf *ena_buf = &rx_info->ena_buf; 449 450 if (unlikely(!page)) { 451 netif_warn(rx_ring->adapter, rx_err, rx_ring->netdev, 452 "Trying to free unallocated buffer\n"); 453 return; 454 } 455 456 dma_unmap_page(rx_ring->dev, ena_buf->paddr, PAGE_SIZE, 457 DMA_FROM_DEVICE); 458 459 __free_page(page); 460 rx_info->page = NULL; 461 } 462 463 static int ena_refill_rx_bufs(struct ena_ring *rx_ring, u32 num) 464 { 465 u16 next_to_use; 466 u32 i; 467 int rc; 468 469 next_to_use = rx_ring->next_to_use; 470 471 for (i = 0; i < num; i++) { 472 struct ena_rx_buffer *rx_info = 473 &rx_ring->rx_buffer_info[next_to_use]; 474 475 rc = ena_alloc_rx_page(rx_ring, rx_info, 476 __GFP_COLD | GFP_ATOMIC | __GFP_COMP); 477 if (unlikely(rc < 0)) { 478 netif_warn(rx_ring->adapter, rx_err, rx_ring->netdev, 479 "failed to alloc buffer for rx queue %d\n", 480 rx_ring->qid); 481 break; 482 } 483 rc = ena_com_add_single_rx_desc(rx_ring->ena_com_io_sq, 484 &rx_info->ena_buf, 485 next_to_use); 486 if (unlikely(rc)) { 487 netif_warn(rx_ring->adapter, rx_status, rx_ring->netdev, 488 "failed to add buffer for rx queue %d\n", 489 rx_ring->qid); 490 break; 491 } 492 next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use, 493 rx_ring->ring_size); 494 } 495 496 if (unlikely(i < num)) { 497 u64_stats_update_begin(&rx_ring->syncp); 498 rx_ring->rx_stats.refil_partial++; 499 u64_stats_update_end(&rx_ring->syncp); 500 netdev_warn(rx_ring->netdev, 501 "refilled rx qid %d with only %d buffers (from %d)\n", 502 rx_ring->qid, i, num); 503 } 504 505 if (likely(i)) { 506 /* Add memory barrier to make sure the desc were written before 507 * issue a doorbell 508 */ 509 wmb(); 510 ena_com_write_sq_doorbell(rx_ring->ena_com_io_sq); 511 } 512 513 rx_ring->next_to_use = next_to_use; 514 515 return i; 516 } 517 518 static void ena_free_rx_bufs(struct ena_adapter *adapter, 519 u32 qid) 520 { 521 struct ena_ring *rx_ring = &adapter->rx_ring[qid]; 522 u32 i; 523 524 for (i = 0; i < rx_ring->ring_size; i++) { 525 struct ena_rx_buffer *rx_info = &rx_ring->rx_buffer_info[i]; 526 527 if (rx_info->page) 528 ena_free_rx_page(rx_ring, rx_info); 529 } 530 } 531 532 /* ena_refill_all_rx_bufs - allocate all queues Rx buffers 533 * @adapter: board private structure 534 * 535 */ 536 static void ena_refill_all_rx_bufs(struct ena_adapter *adapter) 537 { 538 struct ena_ring *rx_ring; 539 int i, rc, bufs_num; 540 541 for (i = 0; i < adapter->num_queues; i++) { 542 rx_ring = &adapter->rx_ring[i]; 543 bufs_num = rx_ring->ring_size - 1; 544 rc = ena_refill_rx_bufs(rx_ring, bufs_num); 545 546 if (unlikely(rc != bufs_num)) 547 netif_warn(rx_ring->adapter, rx_status, rx_ring->netdev, 548 "refilling Queue %d failed. allocated %d buffers from: %d\n", 549 i, rc, bufs_num); 550 } 551 } 552 553 static void ena_free_all_rx_bufs(struct ena_adapter *adapter) 554 { 555 int i; 556 557 for (i = 0; i < adapter->num_queues; i++) 558 ena_free_rx_bufs(adapter, i); 559 } 560 561 /* ena_free_tx_bufs - Free Tx Buffers per Queue 562 * @tx_ring: TX ring for which buffers be freed 563 */ 564 static void ena_free_tx_bufs(struct ena_ring *tx_ring) 565 { 566 bool print_once = true; 567 u32 i; 568 569 for (i = 0; i < tx_ring->ring_size; i++) { 570 struct ena_tx_buffer *tx_info = &tx_ring->tx_buffer_info[i]; 571 struct ena_com_buf *ena_buf; 572 int nr_frags; 573 int j; 574 575 if (!tx_info->skb) 576 continue; 577 578 if (print_once) { 579 netdev_notice(tx_ring->netdev, 580 "free uncompleted tx skb qid %d idx 0x%x\n", 581 tx_ring->qid, i); 582 print_once = false; 583 } else { 584 netdev_dbg(tx_ring->netdev, 585 "free uncompleted tx skb qid %d idx 0x%x\n", 586 tx_ring->qid, i); 587 } 588 589 ena_buf = tx_info->bufs; 590 dma_unmap_single(tx_ring->dev, 591 ena_buf->paddr, 592 ena_buf->len, 593 DMA_TO_DEVICE); 594 595 /* unmap remaining mapped pages */ 596 nr_frags = tx_info->num_of_bufs - 1; 597 for (j = 0; j < nr_frags; j++) { 598 ena_buf++; 599 dma_unmap_page(tx_ring->dev, 600 ena_buf->paddr, 601 ena_buf->len, 602 DMA_TO_DEVICE); 603 } 604 605 dev_kfree_skb_any(tx_info->skb); 606 } 607 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev, 608 tx_ring->qid)); 609 } 610 611 static void ena_free_all_tx_bufs(struct ena_adapter *adapter) 612 { 613 struct ena_ring *tx_ring; 614 int i; 615 616 for (i = 0; i < adapter->num_queues; i++) { 617 tx_ring = &adapter->tx_ring[i]; 618 ena_free_tx_bufs(tx_ring); 619 } 620 } 621 622 static void ena_destroy_all_tx_queues(struct ena_adapter *adapter) 623 { 624 u16 ena_qid; 625 int i; 626 627 for (i = 0; i < adapter->num_queues; i++) { 628 ena_qid = ENA_IO_TXQ_IDX(i); 629 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid); 630 } 631 } 632 633 static void ena_destroy_all_rx_queues(struct ena_adapter *adapter) 634 { 635 u16 ena_qid; 636 int i; 637 638 for (i = 0; i < adapter->num_queues; i++) { 639 ena_qid = ENA_IO_RXQ_IDX(i); 640 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid); 641 } 642 } 643 644 static void ena_destroy_all_io_queues(struct ena_adapter *adapter) 645 { 646 ena_destroy_all_tx_queues(adapter); 647 ena_destroy_all_rx_queues(adapter); 648 } 649 650 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id) 651 { 652 struct ena_tx_buffer *tx_info = NULL; 653 654 if (likely(req_id < tx_ring->ring_size)) { 655 tx_info = &tx_ring->tx_buffer_info[req_id]; 656 if (likely(tx_info->skb)) 657 return 0; 658 } 659 660 if (tx_info) 661 netif_err(tx_ring->adapter, tx_done, tx_ring->netdev, 662 "tx_info doesn't have valid skb\n"); 663 else 664 netif_err(tx_ring->adapter, tx_done, tx_ring->netdev, 665 "Invalid req_id: %hu\n", req_id); 666 667 u64_stats_update_begin(&tx_ring->syncp); 668 tx_ring->tx_stats.bad_req_id++; 669 u64_stats_update_end(&tx_ring->syncp); 670 671 /* Trigger device reset */ 672 set_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags); 673 return -EFAULT; 674 } 675 676 static int ena_clean_tx_irq(struct ena_ring *tx_ring, u32 budget) 677 { 678 struct netdev_queue *txq; 679 bool above_thresh; 680 u32 tx_bytes = 0; 681 u32 total_done = 0; 682 u16 next_to_clean; 683 u16 req_id; 684 int tx_pkts = 0; 685 int rc; 686 687 next_to_clean = tx_ring->next_to_clean; 688 txq = netdev_get_tx_queue(tx_ring->netdev, tx_ring->qid); 689 690 while (tx_pkts < budget) { 691 struct ena_tx_buffer *tx_info; 692 struct sk_buff *skb; 693 struct ena_com_buf *ena_buf; 694 int i, nr_frags; 695 696 rc = ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, 697 &req_id); 698 if (rc) 699 break; 700 701 rc = validate_tx_req_id(tx_ring, req_id); 702 if (rc) 703 break; 704 705 tx_info = &tx_ring->tx_buffer_info[req_id]; 706 skb = tx_info->skb; 707 708 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */ 709 prefetch(&skb->end); 710 711 tx_info->skb = NULL; 712 tx_info->last_jiffies = 0; 713 714 if (likely(tx_info->num_of_bufs != 0)) { 715 ena_buf = tx_info->bufs; 716 717 dma_unmap_single(tx_ring->dev, 718 dma_unmap_addr(ena_buf, paddr), 719 dma_unmap_len(ena_buf, len), 720 DMA_TO_DEVICE); 721 722 /* unmap remaining mapped pages */ 723 nr_frags = tx_info->num_of_bufs - 1; 724 for (i = 0; i < nr_frags; i++) { 725 ena_buf++; 726 dma_unmap_page(tx_ring->dev, 727 dma_unmap_addr(ena_buf, paddr), 728 dma_unmap_len(ena_buf, len), 729 DMA_TO_DEVICE); 730 } 731 } 732 733 netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev, 734 "tx_poll: q %d skb %p completed\n", tx_ring->qid, 735 skb); 736 737 tx_bytes += skb->len; 738 dev_kfree_skb(skb); 739 tx_pkts++; 740 total_done += tx_info->tx_descs; 741 742 tx_ring->free_tx_ids[next_to_clean] = req_id; 743 next_to_clean = ENA_TX_RING_IDX_NEXT(next_to_clean, 744 tx_ring->ring_size); 745 } 746 747 tx_ring->next_to_clean = next_to_clean; 748 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_done); 749 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq); 750 751 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes); 752 753 netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev, 754 "tx_poll: q %d done. total pkts: %d\n", 755 tx_ring->qid, tx_pkts); 756 757 /* need to make the rings circular update visible to 758 * ena_start_xmit() before checking for netif_queue_stopped(). 759 */ 760 smp_mb(); 761 762 above_thresh = ena_com_sq_empty_space(tx_ring->ena_com_io_sq) > 763 ENA_TX_WAKEUP_THRESH; 764 if (unlikely(netif_tx_queue_stopped(txq) && above_thresh)) { 765 __netif_tx_lock(txq, smp_processor_id()); 766 above_thresh = ena_com_sq_empty_space(tx_ring->ena_com_io_sq) > 767 ENA_TX_WAKEUP_THRESH; 768 if (netif_tx_queue_stopped(txq) && above_thresh) { 769 netif_tx_wake_queue(txq); 770 u64_stats_update_begin(&tx_ring->syncp); 771 tx_ring->tx_stats.queue_wakeup++; 772 u64_stats_update_end(&tx_ring->syncp); 773 } 774 __netif_tx_unlock(txq); 775 } 776 777 tx_ring->per_napi_bytes += tx_bytes; 778 tx_ring->per_napi_packets += tx_pkts; 779 780 return tx_pkts; 781 } 782 783 static struct sk_buff *ena_rx_skb(struct ena_ring *rx_ring, 784 struct ena_com_rx_buf_info *ena_bufs, 785 u32 descs, 786 u16 *next_to_clean) 787 { 788 struct sk_buff *skb; 789 struct ena_rx_buffer *rx_info = 790 &rx_ring->rx_buffer_info[*next_to_clean]; 791 u32 len; 792 u32 buf = 0; 793 void *va; 794 795 len = ena_bufs[0].len; 796 if (unlikely(!rx_info->page)) { 797 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev, 798 "Page is NULL\n"); 799 return NULL; 800 } 801 802 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev, 803 "rx_info %p page %p\n", 804 rx_info, rx_info->page); 805 806 /* save virt address of first buffer */ 807 va = page_address(rx_info->page) + rx_info->page_offset; 808 prefetch(va + NET_IP_ALIGN); 809 810 if (len <= rx_ring->rx_copybreak) { 811 skb = netdev_alloc_skb_ip_align(rx_ring->netdev, 812 rx_ring->rx_copybreak); 813 if (unlikely(!skb)) { 814 u64_stats_update_begin(&rx_ring->syncp); 815 rx_ring->rx_stats.skb_alloc_fail++; 816 u64_stats_update_end(&rx_ring->syncp); 817 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev, 818 "Failed to allocate skb\n"); 819 return NULL; 820 } 821 822 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev, 823 "rx allocated small packet. len %d. data_len %d\n", 824 skb->len, skb->data_len); 825 826 /* sync this buffer for CPU use */ 827 dma_sync_single_for_cpu(rx_ring->dev, 828 dma_unmap_addr(&rx_info->ena_buf, paddr), 829 len, 830 DMA_FROM_DEVICE); 831 skb_copy_to_linear_data(skb, va, len); 832 dma_sync_single_for_device(rx_ring->dev, 833 dma_unmap_addr(&rx_info->ena_buf, paddr), 834 len, 835 DMA_FROM_DEVICE); 836 837 skb_put(skb, len); 838 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 839 *next_to_clean = ENA_RX_RING_IDX_ADD(*next_to_clean, descs, 840 rx_ring->ring_size); 841 return skb; 842 } 843 844 skb = napi_get_frags(rx_ring->napi); 845 if (unlikely(!skb)) { 846 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev, 847 "Failed allocating skb\n"); 848 u64_stats_update_begin(&rx_ring->syncp); 849 rx_ring->rx_stats.skb_alloc_fail++; 850 u64_stats_update_end(&rx_ring->syncp); 851 return NULL; 852 } 853 854 do { 855 dma_unmap_page(rx_ring->dev, 856 dma_unmap_addr(&rx_info->ena_buf, paddr), 857 PAGE_SIZE, DMA_FROM_DEVICE); 858 859 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_info->page, 860 rx_info->page_offset, len, PAGE_SIZE); 861 862 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev, 863 "rx skb updated. len %d. data_len %d\n", 864 skb->len, skb->data_len); 865 866 rx_info->page = NULL; 867 *next_to_clean = 868 ENA_RX_RING_IDX_NEXT(*next_to_clean, 869 rx_ring->ring_size); 870 if (likely(--descs == 0)) 871 break; 872 rx_info = &rx_ring->rx_buffer_info[*next_to_clean]; 873 len = ena_bufs[++buf].len; 874 } while (1); 875 876 return skb; 877 } 878 879 /* ena_rx_checksum - indicate in skb if hw indicated a good cksum 880 * @adapter: structure containing adapter specific data 881 * @ena_rx_ctx: received packet context/metadata 882 * @skb: skb currently being received and modified 883 */ 884 static inline void ena_rx_checksum(struct ena_ring *rx_ring, 885 struct ena_com_rx_ctx *ena_rx_ctx, 886 struct sk_buff *skb) 887 { 888 /* Rx csum disabled */ 889 if (unlikely(!(rx_ring->netdev->features & NETIF_F_RXCSUM))) { 890 skb->ip_summed = CHECKSUM_NONE; 891 return; 892 } 893 894 /* For fragmented packets the checksum isn't valid */ 895 if (ena_rx_ctx->frag) { 896 skb->ip_summed = CHECKSUM_NONE; 897 return; 898 } 899 900 /* if IP and error */ 901 if (unlikely((ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) && 902 (ena_rx_ctx->l3_csum_err))) { 903 /* ipv4 checksum error */ 904 skb->ip_summed = CHECKSUM_NONE; 905 u64_stats_update_begin(&rx_ring->syncp); 906 rx_ring->rx_stats.bad_csum++; 907 u64_stats_update_end(&rx_ring->syncp); 908 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev, 909 "RX IPv4 header checksum error\n"); 910 return; 911 } 912 913 /* if TCP/UDP */ 914 if (likely((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) || 915 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP))) { 916 if (unlikely(ena_rx_ctx->l4_csum_err)) { 917 /* TCP/UDP checksum error */ 918 u64_stats_update_begin(&rx_ring->syncp); 919 rx_ring->rx_stats.bad_csum++; 920 u64_stats_update_end(&rx_ring->syncp); 921 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev, 922 "RX L4 checksum error\n"); 923 skb->ip_summed = CHECKSUM_NONE; 924 return; 925 } 926 927 skb->ip_summed = CHECKSUM_UNNECESSARY; 928 } 929 } 930 931 static void ena_set_rx_hash(struct ena_ring *rx_ring, 932 struct ena_com_rx_ctx *ena_rx_ctx, 933 struct sk_buff *skb) 934 { 935 enum pkt_hash_types hash_type; 936 937 if (likely(rx_ring->netdev->features & NETIF_F_RXHASH)) { 938 if (likely((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) || 939 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP))) 940 941 hash_type = PKT_HASH_TYPE_L4; 942 else 943 hash_type = PKT_HASH_TYPE_NONE; 944 945 /* Override hash type if the packet is fragmented */ 946 if (ena_rx_ctx->frag) 947 hash_type = PKT_HASH_TYPE_NONE; 948 949 skb_set_hash(skb, ena_rx_ctx->hash, hash_type); 950 } 951 } 952 953 /* ena_clean_rx_irq - Cleanup RX irq 954 * @rx_ring: RX ring to clean 955 * @napi: napi handler 956 * @budget: how many packets driver is allowed to clean 957 * 958 * Returns the number of cleaned buffers. 959 */ 960 static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi, 961 u32 budget) 962 { 963 u16 next_to_clean = rx_ring->next_to_clean; 964 u32 res_budget, work_done; 965 966 struct ena_com_rx_ctx ena_rx_ctx; 967 struct ena_adapter *adapter; 968 struct sk_buff *skb; 969 int refill_required; 970 int refill_threshold; 971 int rc = 0; 972 int total_len = 0; 973 int rx_copybreak_pkt = 0; 974 975 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev, 976 "%s qid %d\n", __func__, rx_ring->qid); 977 res_budget = budget; 978 979 do { 980 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 981 ena_rx_ctx.max_bufs = rx_ring->sgl_size; 982 ena_rx_ctx.descs = 0; 983 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq, 984 rx_ring->ena_com_io_sq, 985 &ena_rx_ctx); 986 if (unlikely(rc)) 987 goto error; 988 989 if (unlikely(ena_rx_ctx.descs == 0)) 990 break; 991 992 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev, 993 "rx_poll: q %d got packet from ena. descs #: %d l3 proto %d l4 proto %d hash: %x\n", 994 rx_ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto, 995 ena_rx_ctx.l4_proto, ena_rx_ctx.hash); 996 997 /* allocate skb and fill it */ 998 skb = ena_rx_skb(rx_ring, rx_ring->ena_bufs, ena_rx_ctx.descs, 999 &next_to_clean); 1000 1001 /* exit if we failed to retrieve a buffer */ 1002 if (unlikely(!skb)) { 1003 next_to_clean = ENA_RX_RING_IDX_ADD(next_to_clean, 1004 ena_rx_ctx.descs, 1005 rx_ring->ring_size); 1006 break; 1007 } 1008 1009 ena_rx_checksum(rx_ring, &ena_rx_ctx, skb); 1010 1011 ena_set_rx_hash(rx_ring, &ena_rx_ctx, skb); 1012 1013 skb_record_rx_queue(skb, rx_ring->qid); 1014 1015 if (rx_ring->ena_bufs[0].len <= rx_ring->rx_copybreak) { 1016 total_len += rx_ring->ena_bufs[0].len; 1017 rx_copybreak_pkt++; 1018 napi_gro_receive(napi, skb); 1019 } else { 1020 total_len += skb->len; 1021 napi_gro_frags(napi); 1022 } 1023 1024 res_budget--; 1025 } while (likely(res_budget)); 1026 1027 work_done = budget - res_budget; 1028 rx_ring->per_napi_bytes += total_len; 1029 rx_ring->per_napi_packets += work_done; 1030 u64_stats_update_begin(&rx_ring->syncp); 1031 rx_ring->rx_stats.bytes += total_len; 1032 rx_ring->rx_stats.cnt += work_done; 1033 rx_ring->rx_stats.rx_copybreak_pkt += rx_copybreak_pkt; 1034 u64_stats_update_end(&rx_ring->syncp); 1035 1036 rx_ring->next_to_clean = next_to_clean; 1037 1038 refill_required = ena_com_sq_empty_space(rx_ring->ena_com_io_sq); 1039 refill_threshold = rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER; 1040 1041 /* Optimization, try to batch new rx buffers */ 1042 if (refill_required > refill_threshold) { 1043 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 1044 ena_refill_rx_bufs(rx_ring, refill_required); 1045 } 1046 1047 return work_done; 1048 1049 error: 1050 adapter = netdev_priv(rx_ring->netdev); 1051 1052 u64_stats_update_begin(&rx_ring->syncp); 1053 rx_ring->rx_stats.bad_desc_num++; 1054 u64_stats_update_end(&rx_ring->syncp); 1055 1056 /* Too many desc from the device. Trigger reset */ 1057 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags); 1058 1059 return 0; 1060 } 1061 1062 inline void ena_adjust_intr_moderation(struct ena_ring *rx_ring, 1063 struct ena_ring *tx_ring) 1064 { 1065 /* We apply adaptive moderation on Rx path only. 1066 * Tx uses static interrupt moderation. 1067 */ 1068 ena_com_calculate_interrupt_delay(rx_ring->ena_dev, 1069 rx_ring->per_napi_packets, 1070 rx_ring->per_napi_bytes, 1071 &rx_ring->smoothed_interval, 1072 &rx_ring->moder_tbl_idx); 1073 1074 /* Reset per napi packets/bytes */ 1075 tx_ring->per_napi_packets = 0; 1076 tx_ring->per_napi_bytes = 0; 1077 rx_ring->per_napi_packets = 0; 1078 rx_ring->per_napi_bytes = 0; 1079 } 1080 1081 static inline void ena_update_ring_numa_node(struct ena_ring *tx_ring, 1082 struct ena_ring *rx_ring) 1083 { 1084 int cpu = get_cpu(); 1085 int numa_node; 1086 1087 /* Check only one ring since the 2 rings are running on the same cpu */ 1088 if (likely(tx_ring->cpu == cpu)) 1089 goto out; 1090 1091 numa_node = cpu_to_node(cpu); 1092 put_cpu(); 1093 1094 if (numa_node != NUMA_NO_NODE) { 1095 ena_com_update_numa_node(tx_ring->ena_com_io_cq, numa_node); 1096 ena_com_update_numa_node(rx_ring->ena_com_io_cq, numa_node); 1097 } 1098 1099 tx_ring->cpu = cpu; 1100 rx_ring->cpu = cpu; 1101 1102 return; 1103 out: 1104 put_cpu(); 1105 } 1106 1107 static int ena_io_poll(struct napi_struct *napi, int budget) 1108 { 1109 struct ena_napi *ena_napi = container_of(napi, struct ena_napi, napi); 1110 struct ena_ring *tx_ring, *rx_ring; 1111 struct ena_eth_io_intr_reg intr_reg; 1112 1113 u32 tx_work_done; 1114 u32 rx_work_done; 1115 int tx_budget; 1116 int napi_comp_call = 0; 1117 int ret; 1118 1119 tx_ring = ena_napi->tx_ring; 1120 rx_ring = ena_napi->rx_ring; 1121 1122 tx_budget = tx_ring->ring_size / ENA_TX_POLL_BUDGET_DIVIDER; 1123 1124 if (!test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags) || 1125 test_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags)) { 1126 napi_complete_done(napi, 0); 1127 return 0; 1128 } 1129 1130 tx_work_done = ena_clean_tx_irq(tx_ring, tx_budget); 1131 rx_work_done = ena_clean_rx_irq(rx_ring, napi, budget); 1132 1133 /* If the device is about to reset or down, avoid unmask 1134 * the interrupt and return 0 so NAPI won't reschedule 1135 */ 1136 if (unlikely(!test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags) || 1137 test_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags))) { 1138 napi_complete_done(napi, 0); 1139 ret = 0; 1140 1141 } else if ((budget > rx_work_done) && (tx_budget > tx_work_done)) { 1142 napi_comp_call = 1; 1143 1144 /* Update numa and unmask the interrupt only when schedule 1145 * from the interrupt context (vs from sk_busy_loop) 1146 */ 1147 if (napi_complete_done(napi, rx_work_done)) { 1148 /* Tx and Rx share the same interrupt vector */ 1149 if (ena_com_get_adaptive_moderation_enabled(rx_ring->ena_dev)) 1150 ena_adjust_intr_moderation(rx_ring, tx_ring); 1151 1152 /* Update intr register: rx intr delay, 1153 * tx intr delay and interrupt unmask 1154 */ 1155 ena_com_update_intr_reg(&intr_reg, 1156 rx_ring->smoothed_interval, 1157 tx_ring->smoothed_interval, 1158 true); 1159 1160 /* It is a shared MSI-X. 1161 * Tx and Rx CQ have pointer to it. 1162 * So we use one of them to reach the intr reg 1163 */ 1164 ena_com_unmask_intr(rx_ring->ena_com_io_cq, &intr_reg); 1165 } 1166 1167 1168 ena_update_ring_numa_node(tx_ring, rx_ring); 1169 1170 ret = rx_work_done; 1171 } else { 1172 ret = budget; 1173 } 1174 1175 u64_stats_update_begin(&tx_ring->syncp); 1176 tx_ring->tx_stats.napi_comp += napi_comp_call; 1177 tx_ring->tx_stats.tx_poll++; 1178 u64_stats_update_end(&tx_ring->syncp); 1179 1180 return ret; 1181 } 1182 1183 static irqreturn_t ena_intr_msix_mgmnt(int irq, void *data) 1184 { 1185 struct ena_adapter *adapter = (struct ena_adapter *)data; 1186 1187 ena_com_admin_q_comp_intr_handler(adapter->ena_dev); 1188 1189 /* Don't call the aenq handler before probe is done */ 1190 if (likely(test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags))) 1191 ena_com_aenq_intr_handler(adapter->ena_dev, data); 1192 1193 return IRQ_HANDLED; 1194 } 1195 1196 /* ena_intr_msix_io - MSI-X Interrupt Handler for Tx/Rx 1197 * @irq: interrupt number 1198 * @data: pointer to a network interface private napi device structure 1199 */ 1200 static irqreturn_t ena_intr_msix_io(int irq, void *data) 1201 { 1202 struct ena_napi *ena_napi = data; 1203 1204 napi_schedule(&ena_napi->napi); 1205 1206 return IRQ_HANDLED; 1207 } 1208 1209 static int ena_enable_msix(struct ena_adapter *adapter, int num_queues) 1210 { 1211 int msix_vecs, rc; 1212 1213 /* Reserved the max msix vectors we might need */ 1214 msix_vecs = ENA_MAX_MSIX_VEC(num_queues); 1215 1216 netif_dbg(adapter, probe, adapter->netdev, 1217 "trying to enable MSI-X, vectors %d\n", msix_vecs); 1218 1219 rc = pci_alloc_irq_vectors(adapter->pdev, msix_vecs, msix_vecs, 1220 PCI_IRQ_MSIX); 1221 if (rc < 0) { 1222 netif_err(adapter, probe, adapter->netdev, 1223 "Failed to enable MSI-X, vectors %d rc %d\n", 1224 msix_vecs, rc); 1225 return -ENOSPC; 1226 } 1227 1228 netif_dbg(adapter, probe, adapter->netdev, "enable MSI-X, vectors %d\n", 1229 msix_vecs); 1230 1231 if (msix_vecs >= 1) { 1232 if (ena_init_rx_cpu_rmap(adapter)) 1233 netif_warn(adapter, probe, adapter->netdev, 1234 "Failed to map IRQs to CPUs\n"); 1235 } 1236 1237 adapter->msix_vecs = msix_vecs; 1238 1239 return 0; 1240 } 1241 1242 static void ena_setup_mgmnt_intr(struct ena_adapter *adapter) 1243 { 1244 u32 cpu; 1245 1246 snprintf(adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].name, 1247 ENA_IRQNAME_SIZE, "ena-mgmnt@pci:%s", 1248 pci_name(adapter->pdev)); 1249 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].handler = 1250 ena_intr_msix_mgmnt; 1251 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].data = adapter; 1252 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].vector = 1253 pci_irq_vector(adapter->pdev, ENA_MGMNT_IRQ_IDX); 1254 cpu = cpumask_first(cpu_online_mask); 1255 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].cpu = cpu; 1256 cpumask_set_cpu(cpu, 1257 &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].affinity_hint_mask); 1258 } 1259 1260 static void ena_setup_io_intr(struct ena_adapter *adapter) 1261 { 1262 struct net_device *netdev; 1263 int irq_idx, i, cpu; 1264 1265 netdev = adapter->netdev; 1266 1267 for (i = 0; i < adapter->num_queues; i++) { 1268 irq_idx = ENA_IO_IRQ_IDX(i); 1269 cpu = i % num_online_cpus(); 1270 1271 snprintf(adapter->irq_tbl[irq_idx].name, ENA_IRQNAME_SIZE, 1272 "%s-Tx-Rx-%d", netdev->name, i); 1273 adapter->irq_tbl[irq_idx].handler = ena_intr_msix_io; 1274 adapter->irq_tbl[irq_idx].data = &adapter->ena_napi[i]; 1275 adapter->irq_tbl[irq_idx].vector = 1276 pci_irq_vector(adapter->pdev, irq_idx); 1277 adapter->irq_tbl[irq_idx].cpu = cpu; 1278 1279 cpumask_set_cpu(cpu, 1280 &adapter->irq_tbl[irq_idx].affinity_hint_mask); 1281 } 1282 } 1283 1284 static int ena_request_mgmnt_irq(struct ena_adapter *adapter) 1285 { 1286 unsigned long flags = 0; 1287 struct ena_irq *irq; 1288 int rc; 1289 1290 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX]; 1291 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 1292 irq->data); 1293 if (rc) { 1294 netif_err(adapter, probe, adapter->netdev, 1295 "failed to request admin irq\n"); 1296 return rc; 1297 } 1298 1299 netif_dbg(adapter, probe, adapter->netdev, 1300 "set affinity hint of mgmnt irq.to 0x%lx (irq vector: %d)\n", 1301 irq->affinity_hint_mask.bits[0], irq->vector); 1302 1303 irq_set_affinity_hint(irq->vector, &irq->affinity_hint_mask); 1304 1305 return rc; 1306 } 1307 1308 static int ena_request_io_irq(struct ena_adapter *adapter) 1309 { 1310 unsigned long flags = 0; 1311 struct ena_irq *irq; 1312 int rc = 0, i, k; 1313 1314 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) { 1315 irq = &adapter->irq_tbl[i]; 1316 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 1317 irq->data); 1318 if (rc) { 1319 netif_err(adapter, ifup, adapter->netdev, 1320 "Failed to request I/O IRQ. index %d rc %d\n", 1321 i, rc); 1322 goto err; 1323 } 1324 1325 netif_dbg(adapter, ifup, adapter->netdev, 1326 "set affinity hint of irq. index %d to 0x%lx (irq vector: %d)\n", 1327 i, irq->affinity_hint_mask.bits[0], irq->vector); 1328 1329 irq_set_affinity_hint(irq->vector, &irq->affinity_hint_mask); 1330 } 1331 1332 return rc; 1333 1334 err: 1335 for (k = ENA_IO_IRQ_FIRST_IDX; k < i; k++) { 1336 irq = &adapter->irq_tbl[k]; 1337 free_irq(irq->vector, irq->data); 1338 } 1339 1340 return rc; 1341 } 1342 1343 static void ena_free_mgmnt_irq(struct ena_adapter *adapter) 1344 { 1345 struct ena_irq *irq; 1346 1347 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX]; 1348 synchronize_irq(irq->vector); 1349 irq_set_affinity_hint(irq->vector, NULL); 1350 free_irq(irq->vector, irq->data); 1351 } 1352 1353 static void ena_free_io_irq(struct ena_adapter *adapter) 1354 { 1355 struct ena_irq *irq; 1356 int i; 1357 1358 #ifdef CONFIG_RFS_ACCEL 1359 if (adapter->msix_vecs >= 1) { 1360 free_irq_cpu_rmap(adapter->netdev->rx_cpu_rmap); 1361 adapter->netdev->rx_cpu_rmap = NULL; 1362 } 1363 #endif /* CONFIG_RFS_ACCEL */ 1364 1365 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) { 1366 irq = &adapter->irq_tbl[i]; 1367 irq_set_affinity_hint(irq->vector, NULL); 1368 free_irq(irq->vector, irq->data); 1369 } 1370 } 1371 1372 static void ena_disable_io_intr_sync(struct ena_adapter *adapter) 1373 { 1374 int i; 1375 1376 if (!netif_running(adapter->netdev)) 1377 return; 1378 1379 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) 1380 synchronize_irq(adapter->irq_tbl[i].vector); 1381 } 1382 1383 static void ena_del_napi(struct ena_adapter *adapter) 1384 { 1385 int i; 1386 1387 for (i = 0; i < adapter->num_queues; i++) 1388 netif_napi_del(&adapter->ena_napi[i].napi); 1389 } 1390 1391 static void ena_init_napi(struct ena_adapter *adapter) 1392 { 1393 struct ena_napi *napi; 1394 int i; 1395 1396 for (i = 0; i < adapter->num_queues; i++) { 1397 napi = &adapter->ena_napi[i]; 1398 1399 netif_napi_add(adapter->netdev, 1400 &adapter->ena_napi[i].napi, 1401 ena_io_poll, 1402 ENA_NAPI_BUDGET); 1403 napi->rx_ring = &adapter->rx_ring[i]; 1404 napi->tx_ring = &adapter->tx_ring[i]; 1405 napi->qid = i; 1406 } 1407 } 1408 1409 static void ena_napi_disable_all(struct ena_adapter *adapter) 1410 { 1411 int i; 1412 1413 for (i = 0; i < adapter->num_queues; i++) 1414 napi_disable(&adapter->ena_napi[i].napi); 1415 } 1416 1417 static void ena_napi_enable_all(struct ena_adapter *adapter) 1418 { 1419 int i; 1420 1421 for (i = 0; i < adapter->num_queues; i++) 1422 napi_enable(&adapter->ena_napi[i].napi); 1423 } 1424 1425 static void ena_restore_ethtool_params(struct ena_adapter *adapter) 1426 { 1427 adapter->tx_usecs = 0; 1428 adapter->rx_usecs = 0; 1429 adapter->tx_frames = 1; 1430 adapter->rx_frames = 1; 1431 } 1432 1433 /* Configure the Rx forwarding */ 1434 static int ena_rss_configure(struct ena_adapter *adapter) 1435 { 1436 struct ena_com_dev *ena_dev = adapter->ena_dev; 1437 int rc; 1438 1439 /* In case the RSS table wasn't initialized by probe */ 1440 if (!ena_dev->rss.tbl_log_size) { 1441 rc = ena_rss_init_default(adapter); 1442 if (rc && (rc != -EPERM)) { 1443 netif_err(adapter, ifup, adapter->netdev, 1444 "Failed to init RSS rc: %d\n", rc); 1445 return rc; 1446 } 1447 } 1448 1449 /* Set indirect table */ 1450 rc = ena_com_indirect_table_set(ena_dev); 1451 if (unlikely(rc && rc != -EPERM)) 1452 return rc; 1453 1454 /* Configure hash function (if supported) */ 1455 rc = ena_com_set_hash_function(ena_dev); 1456 if (unlikely(rc && (rc != -EPERM))) 1457 return rc; 1458 1459 /* Configure hash inputs (if supported) */ 1460 rc = ena_com_set_hash_ctrl(ena_dev); 1461 if (unlikely(rc && (rc != -EPERM))) 1462 return rc; 1463 1464 return 0; 1465 } 1466 1467 static int ena_up_complete(struct ena_adapter *adapter) 1468 { 1469 int rc, i; 1470 1471 rc = ena_rss_configure(adapter); 1472 if (rc) 1473 return rc; 1474 1475 ena_init_napi(adapter); 1476 1477 ena_change_mtu(adapter->netdev, adapter->netdev->mtu); 1478 1479 ena_refill_all_rx_bufs(adapter); 1480 1481 /* enable transmits */ 1482 netif_tx_start_all_queues(adapter->netdev); 1483 1484 ena_restore_ethtool_params(adapter); 1485 1486 ena_napi_enable_all(adapter); 1487 1488 /* schedule napi in case we had pending packets 1489 * from the last time we disable napi 1490 */ 1491 for (i = 0; i < adapter->num_queues; i++) 1492 napi_schedule(&adapter->ena_napi[i].napi); 1493 1494 return 0; 1495 } 1496 1497 static int ena_create_io_tx_queue(struct ena_adapter *adapter, int qid) 1498 { 1499 struct ena_com_create_io_ctx ctx = { 0 }; 1500 struct ena_com_dev *ena_dev; 1501 struct ena_ring *tx_ring; 1502 u32 msix_vector; 1503 u16 ena_qid; 1504 int rc; 1505 1506 ena_dev = adapter->ena_dev; 1507 1508 tx_ring = &adapter->tx_ring[qid]; 1509 msix_vector = ENA_IO_IRQ_IDX(qid); 1510 ena_qid = ENA_IO_TXQ_IDX(qid); 1511 1512 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1513 ctx.qid = ena_qid; 1514 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1515 ctx.msix_vector = msix_vector; 1516 ctx.queue_size = adapter->tx_ring_size; 1517 ctx.numa_node = cpu_to_node(tx_ring->cpu); 1518 1519 rc = ena_com_create_io_queue(ena_dev, &ctx); 1520 if (rc) { 1521 netif_err(adapter, ifup, adapter->netdev, 1522 "Failed to create I/O TX queue num %d rc: %d\n", 1523 qid, rc); 1524 return rc; 1525 } 1526 1527 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1528 &tx_ring->ena_com_io_sq, 1529 &tx_ring->ena_com_io_cq); 1530 if (rc) { 1531 netif_err(adapter, ifup, adapter->netdev, 1532 "Failed to get TX queue handlers. TX queue num %d rc: %d\n", 1533 qid, rc); 1534 ena_com_destroy_io_queue(ena_dev, ena_qid); 1535 } 1536 1537 ena_com_update_numa_node(tx_ring->ena_com_io_cq, ctx.numa_node); 1538 return rc; 1539 } 1540 1541 static int ena_create_all_io_tx_queues(struct ena_adapter *adapter) 1542 { 1543 struct ena_com_dev *ena_dev = adapter->ena_dev; 1544 int rc, i; 1545 1546 for (i = 0; i < adapter->num_queues; i++) { 1547 rc = ena_create_io_tx_queue(adapter, i); 1548 if (rc) 1549 goto create_err; 1550 } 1551 1552 return 0; 1553 1554 create_err: 1555 while (i--) 1556 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(i)); 1557 1558 return rc; 1559 } 1560 1561 static int ena_create_io_rx_queue(struct ena_adapter *adapter, int qid) 1562 { 1563 struct ena_com_dev *ena_dev; 1564 struct ena_com_create_io_ctx ctx = { 0 }; 1565 struct ena_ring *rx_ring; 1566 u32 msix_vector; 1567 u16 ena_qid; 1568 int rc; 1569 1570 ena_dev = adapter->ena_dev; 1571 1572 rx_ring = &adapter->rx_ring[qid]; 1573 msix_vector = ENA_IO_IRQ_IDX(qid); 1574 ena_qid = ENA_IO_RXQ_IDX(qid); 1575 1576 ctx.qid = ena_qid; 1577 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1578 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1579 ctx.msix_vector = msix_vector; 1580 ctx.queue_size = adapter->rx_ring_size; 1581 ctx.numa_node = cpu_to_node(rx_ring->cpu); 1582 1583 rc = ena_com_create_io_queue(ena_dev, &ctx); 1584 if (rc) { 1585 netif_err(adapter, ifup, adapter->netdev, 1586 "Failed to create I/O RX queue num %d rc: %d\n", 1587 qid, rc); 1588 return rc; 1589 } 1590 1591 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1592 &rx_ring->ena_com_io_sq, 1593 &rx_ring->ena_com_io_cq); 1594 if (rc) { 1595 netif_err(adapter, ifup, adapter->netdev, 1596 "Failed to get RX queue handlers. RX queue num %d rc: %d\n", 1597 qid, rc); 1598 ena_com_destroy_io_queue(ena_dev, ena_qid); 1599 } 1600 1601 ena_com_update_numa_node(rx_ring->ena_com_io_cq, ctx.numa_node); 1602 1603 return rc; 1604 } 1605 1606 static int ena_create_all_io_rx_queues(struct ena_adapter *adapter) 1607 { 1608 struct ena_com_dev *ena_dev = adapter->ena_dev; 1609 int rc, i; 1610 1611 for (i = 0; i < adapter->num_queues; i++) { 1612 rc = ena_create_io_rx_queue(adapter, i); 1613 if (rc) 1614 goto create_err; 1615 } 1616 1617 return 0; 1618 1619 create_err: 1620 while (i--) 1621 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(i)); 1622 1623 return rc; 1624 } 1625 1626 static int ena_up(struct ena_adapter *adapter) 1627 { 1628 int rc; 1629 1630 netdev_dbg(adapter->netdev, "%s\n", __func__); 1631 1632 ena_setup_io_intr(adapter); 1633 1634 rc = ena_request_io_irq(adapter); 1635 if (rc) 1636 goto err_req_irq; 1637 1638 /* allocate transmit descriptors */ 1639 rc = ena_setup_all_tx_resources(adapter); 1640 if (rc) 1641 goto err_setup_tx; 1642 1643 /* allocate receive descriptors */ 1644 rc = ena_setup_all_rx_resources(adapter); 1645 if (rc) 1646 goto err_setup_rx; 1647 1648 /* Create TX queues */ 1649 rc = ena_create_all_io_tx_queues(adapter); 1650 if (rc) 1651 goto err_create_tx_queues; 1652 1653 /* Create RX queues */ 1654 rc = ena_create_all_io_rx_queues(adapter); 1655 if (rc) 1656 goto err_create_rx_queues; 1657 1658 rc = ena_up_complete(adapter); 1659 if (rc) 1660 goto err_up; 1661 1662 if (test_bit(ENA_FLAG_LINK_UP, &adapter->flags)) 1663 netif_carrier_on(adapter->netdev); 1664 1665 u64_stats_update_begin(&adapter->syncp); 1666 adapter->dev_stats.interface_up++; 1667 u64_stats_update_end(&adapter->syncp); 1668 1669 set_bit(ENA_FLAG_DEV_UP, &adapter->flags); 1670 1671 return rc; 1672 1673 err_up: 1674 ena_destroy_all_rx_queues(adapter); 1675 err_create_rx_queues: 1676 ena_destroy_all_tx_queues(adapter); 1677 err_create_tx_queues: 1678 ena_free_all_io_rx_resources(adapter); 1679 err_setup_rx: 1680 ena_free_all_io_tx_resources(adapter); 1681 err_setup_tx: 1682 ena_free_io_irq(adapter); 1683 err_req_irq: 1684 1685 return rc; 1686 } 1687 1688 static void ena_down(struct ena_adapter *adapter) 1689 { 1690 netif_info(adapter, ifdown, adapter->netdev, "%s\n", __func__); 1691 1692 clear_bit(ENA_FLAG_DEV_UP, &adapter->flags); 1693 1694 u64_stats_update_begin(&adapter->syncp); 1695 adapter->dev_stats.interface_down++; 1696 u64_stats_update_end(&adapter->syncp); 1697 1698 netif_carrier_off(adapter->netdev); 1699 netif_tx_disable(adapter->netdev); 1700 1701 /* After this point the napi handler won't enable the tx queue */ 1702 ena_napi_disable_all(adapter); 1703 1704 /* After destroy the queue there won't be any new interrupts */ 1705 1706 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags)) { 1707 int rc; 1708 1709 rc = ena_com_dev_reset(adapter->ena_dev); 1710 if (rc) 1711 dev_err(&adapter->pdev->dev, "Device reset failed\n"); 1712 } 1713 1714 ena_destroy_all_io_queues(adapter); 1715 1716 ena_disable_io_intr_sync(adapter); 1717 ena_free_io_irq(adapter); 1718 ena_del_napi(adapter); 1719 1720 ena_free_all_tx_bufs(adapter); 1721 ena_free_all_rx_bufs(adapter); 1722 ena_free_all_io_tx_resources(adapter); 1723 ena_free_all_io_rx_resources(adapter); 1724 } 1725 1726 /* ena_open - Called when a network interface is made active 1727 * @netdev: network interface device structure 1728 * 1729 * Returns 0 on success, negative value on failure 1730 * 1731 * The open entry point is called when a network interface is made 1732 * active by the system (IFF_UP). At this point all resources needed 1733 * for transmit and receive operations are allocated, the interrupt 1734 * handler is registered with the OS, the watchdog timer is started, 1735 * and the stack is notified that the interface is ready. 1736 */ 1737 static int ena_open(struct net_device *netdev) 1738 { 1739 struct ena_adapter *adapter = netdev_priv(netdev); 1740 int rc; 1741 1742 /* Notify the stack of the actual queue counts. */ 1743 rc = netif_set_real_num_tx_queues(netdev, adapter->num_queues); 1744 if (rc) { 1745 netif_err(adapter, ifup, netdev, "Can't set num tx queues\n"); 1746 return rc; 1747 } 1748 1749 rc = netif_set_real_num_rx_queues(netdev, adapter->num_queues); 1750 if (rc) { 1751 netif_err(adapter, ifup, netdev, "Can't set num rx queues\n"); 1752 return rc; 1753 } 1754 1755 rc = ena_up(adapter); 1756 if (rc) 1757 return rc; 1758 1759 return rc; 1760 } 1761 1762 /* ena_close - Disables a network interface 1763 * @netdev: network interface device structure 1764 * 1765 * Returns 0, this is not allowed to fail 1766 * 1767 * The close entry point is called when an interface is de-activated 1768 * by the OS. The hardware is still under the drivers control, but 1769 * needs to be disabled. A global MAC reset is issued to stop the 1770 * hardware, and all transmit and receive resources are freed. 1771 */ 1772 static int ena_close(struct net_device *netdev) 1773 { 1774 struct ena_adapter *adapter = netdev_priv(netdev); 1775 1776 netif_dbg(adapter, ifdown, netdev, "%s\n", __func__); 1777 1778 if (test_bit(ENA_FLAG_DEV_UP, &adapter->flags)) 1779 ena_down(adapter); 1780 1781 return 0; 1782 } 1783 1784 static void ena_tx_csum(struct ena_com_tx_ctx *ena_tx_ctx, struct sk_buff *skb) 1785 { 1786 u32 mss = skb_shinfo(skb)->gso_size; 1787 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta; 1788 u8 l4_protocol = 0; 1789 1790 if ((skb->ip_summed == CHECKSUM_PARTIAL) || mss) { 1791 ena_tx_ctx->l4_csum_enable = 1; 1792 if (mss) { 1793 ena_tx_ctx->tso_enable = 1; 1794 ena_meta->l4_hdr_len = tcp_hdr(skb)->doff; 1795 ena_tx_ctx->l4_csum_partial = 0; 1796 } else { 1797 ena_tx_ctx->tso_enable = 0; 1798 ena_meta->l4_hdr_len = 0; 1799 ena_tx_ctx->l4_csum_partial = 1; 1800 } 1801 1802 switch (ip_hdr(skb)->version) { 1803 case IPVERSION: 1804 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 1805 if (ip_hdr(skb)->frag_off & htons(IP_DF)) 1806 ena_tx_ctx->df = 1; 1807 if (mss) 1808 ena_tx_ctx->l3_csum_enable = 1; 1809 l4_protocol = ip_hdr(skb)->protocol; 1810 break; 1811 case 6: 1812 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 1813 l4_protocol = ipv6_hdr(skb)->nexthdr; 1814 break; 1815 default: 1816 break; 1817 } 1818 1819 if (l4_protocol == IPPROTO_TCP) 1820 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 1821 else 1822 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 1823 1824 ena_meta->mss = mss; 1825 ena_meta->l3_hdr_len = skb_network_header_len(skb); 1826 ena_meta->l3_hdr_offset = skb_network_offset(skb); 1827 ena_tx_ctx->meta_valid = 1; 1828 1829 } else { 1830 ena_tx_ctx->meta_valid = 0; 1831 } 1832 } 1833 1834 static int ena_check_and_linearize_skb(struct ena_ring *tx_ring, 1835 struct sk_buff *skb) 1836 { 1837 int num_frags, header_len, rc; 1838 1839 num_frags = skb_shinfo(skb)->nr_frags; 1840 header_len = skb_headlen(skb); 1841 1842 if (num_frags < tx_ring->sgl_size) 1843 return 0; 1844 1845 if ((num_frags == tx_ring->sgl_size) && 1846 (header_len < tx_ring->tx_max_header_size)) 1847 return 0; 1848 1849 u64_stats_update_begin(&tx_ring->syncp); 1850 tx_ring->tx_stats.linearize++; 1851 u64_stats_update_end(&tx_ring->syncp); 1852 1853 rc = skb_linearize(skb); 1854 if (unlikely(rc)) { 1855 u64_stats_update_begin(&tx_ring->syncp); 1856 tx_ring->tx_stats.linearize_failed++; 1857 u64_stats_update_end(&tx_ring->syncp); 1858 } 1859 1860 return rc; 1861 } 1862 1863 /* Called with netif_tx_lock. */ 1864 static netdev_tx_t ena_start_xmit(struct sk_buff *skb, struct net_device *dev) 1865 { 1866 struct ena_adapter *adapter = netdev_priv(dev); 1867 struct ena_tx_buffer *tx_info; 1868 struct ena_com_tx_ctx ena_tx_ctx; 1869 struct ena_ring *tx_ring; 1870 struct netdev_queue *txq; 1871 struct ena_com_buf *ena_buf; 1872 void *push_hdr; 1873 u32 len, last_frag; 1874 u16 next_to_use; 1875 u16 req_id; 1876 u16 push_len; 1877 u16 header_len; 1878 dma_addr_t dma; 1879 int qid, rc, nb_hw_desc; 1880 int i = -1; 1881 1882 netif_dbg(adapter, tx_queued, dev, "%s skb %p\n", __func__, skb); 1883 /* Determine which tx ring we will be placed on */ 1884 qid = skb_get_queue_mapping(skb); 1885 tx_ring = &adapter->tx_ring[qid]; 1886 txq = netdev_get_tx_queue(dev, qid); 1887 1888 rc = ena_check_and_linearize_skb(tx_ring, skb); 1889 if (unlikely(rc)) 1890 goto error_drop_packet; 1891 1892 skb_tx_timestamp(skb); 1893 len = skb_headlen(skb); 1894 1895 next_to_use = tx_ring->next_to_use; 1896 req_id = tx_ring->free_tx_ids[next_to_use]; 1897 tx_info = &tx_ring->tx_buffer_info[req_id]; 1898 tx_info->num_of_bufs = 0; 1899 1900 WARN(tx_info->skb, "SKB isn't NULL req_id %d\n", req_id); 1901 ena_buf = tx_info->bufs; 1902 tx_info->skb = skb; 1903 1904 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 1905 /* prepared the push buffer */ 1906 push_len = min_t(u32, len, tx_ring->tx_max_header_size); 1907 header_len = push_len; 1908 push_hdr = skb->data; 1909 } else { 1910 push_len = 0; 1911 header_len = min_t(u32, len, tx_ring->tx_max_header_size); 1912 push_hdr = NULL; 1913 } 1914 1915 netif_dbg(adapter, tx_queued, dev, 1916 "skb: %p header_buf->vaddr: %p push_len: %d\n", skb, 1917 push_hdr, push_len); 1918 1919 if (len > push_len) { 1920 dma = dma_map_single(tx_ring->dev, skb->data + push_len, 1921 len - push_len, DMA_TO_DEVICE); 1922 if (dma_mapping_error(tx_ring->dev, dma)) 1923 goto error_report_dma_error; 1924 1925 ena_buf->paddr = dma; 1926 ena_buf->len = len - push_len; 1927 1928 ena_buf++; 1929 tx_info->num_of_bufs++; 1930 } 1931 1932 last_frag = skb_shinfo(skb)->nr_frags; 1933 1934 for (i = 0; i < last_frag; i++) { 1935 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1936 1937 len = skb_frag_size(frag); 1938 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, len, 1939 DMA_TO_DEVICE); 1940 if (dma_mapping_error(tx_ring->dev, dma)) 1941 goto error_report_dma_error; 1942 1943 ena_buf->paddr = dma; 1944 ena_buf->len = len; 1945 ena_buf++; 1946 } 1947 1948 tx_info->num_of_bufs += last_frag; 1949 1950 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx)); 1951 ena_tx_ctx.ena_bufs = tx_info->bufs; 1952 ena_tx_ctx.push_header = push_hdr; 1953 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 1954 ena_tx_ctx.req_id = req_id; 1955 ena_tx_ctx.header_len = header_len; 1956 1957 /* set flags and meta data */ 1958 ena_tx_csum(&ena_tx_ctx, skb); 1959 1960 /* prepare the packet's descriptors to dma engine */ 1961 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx, 1962 &nb_hw_desc); 1963 1964 if (unlikely(rc)) { 1965 netif_err(adapter, tx_queued, dev, 1966 "failed to prepare tx bufs\n"); 1967 u64_stats_update_begin(&tx_ring->syncp); 1968 tx_ring->tx_stats.queue_stop++; 1969 tx_ring->tx_stats.prepare_ctx_err++; 1970 u64_stats_update_end(&tx_ring->syncp); 1971 netif_tx_stop_queue(txq); 1972 goto error_unmap_dma; 1973 } 1974 1975 netdev_tx_sent_queue(txq, skb->len); 1976 1977 u64_stats_update_begin(&tx_ring->syncp); 1978 tx_ring->tx_stats.cnt++; 1979 tx_ring->tx_stats.bytes += skb->len; 1980 u64_stats_update_end(&tx_ring->syncp); 1981 1982 tx_info->tx_descs = nb_hw_desc; 1983 tx_info->last_jiffies = jiffies; 1984 1985 tx_ring->next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use, 1986 tx_ring->ring_size); 1987 1988 /* This WMB is aimed to: 1989 * 1 - perform smp barrier before reading next_to_completion 1990 * 2 - make sure the desc were written before trigger DB 1991 */ 1992 wmb(); 1993 1994 /* stop the queue when no more space available, the packet can have up 1995 * to sgl_size + 2. one for the meta descriptor and one for header 1996 * (if the header is larger than tx_max_header_size). 1997 */ 1998 if (unlikely(ena_com_sq_empty_space(tx_ring->ena_com_io_sq) < 1999 (tx_ring->sgl_size + 2))) { 2000 netif_dbg(adapter, tx_queued, dev, "%s stop queue %d\n", 2001 __func__, qid); 2002 2003 netif_tx_stop_queue(txq); 2004 u64_stats_update_begin(&tx_ring->syncp); 2005 tx_ring->tx_stats.queue_stop++; 2006 u64_stats_update_end(&tx_ring->syncp); 2007 2008 /* There is a rare condition where this function decide to 2009 * stop the queue but meanwhile clean_tx_irq updates 2010 * next_to_completion and terminates. 2011 * The queue will remain stopped forever. 2012 * To solve this issue this function perform rmb, check 2013 * the wakeup condition and wake up the queue if needed. 2014 */ 2015 smp_rmb(); 2016 2017 if (ena_com_sq_empty_space(tx_ring->ena_com_io_sq) 2018 > ENA_TX_WAKEUP_THRESH) { 2019 netif_tx_wake_queue(txq); 2020 u64_stats_update_begin(&tx_ring->syncp); 2021 tx_ring->tx_stats.queue_wakeup++; 2022 u64_stats_update_end(&tx_ring->syncp); 2023 } 2024 } 2025 2026 if (netif_xmit_stopped(txq) || !skb->xmit_more) { 2027 /* trigger the dma engine */ 2028 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2029 u64_stats_update_begin(&tx_ring->syncp); 2030 tx_ring->tx_stats.doorbells++; 2031 u64_stats_update_end(&tx_ring->syncp); 2032 } 2033 2034 return NETDEV_TX_OK; 2035 2036 error_report_dma_error: 2037 u64_stats_update_begin(&tx_ring->syncp); 2038 tx_ring->tx_stats.dma_mapping_err++; 2039 u64_stats_update_end(&tx_ring->syncp); 2040 netdev_warn(adapter->netdev, "failed to map skb\n"); 2041 2042 tx_info->skb = NULL; 2043 2044 error_unmap_dma: 2045 if (i >= 0) { 2046 /* save value of frag that failed */ 2047 last_frag = i; 2048 2049 /* start back at beginning and unmap skb */ 2050 tx_info->skb = NULL; 2051 ena_buf = tx_info->bufs; 2052 dma_unmap_single(tx_ring->dev, dma_unmap_addr(ena_buf, paddr), 2053 dma_unmap_len(ena_buf, len), DMA_TO_DEVICE); 2054 2055 /* unmap remaining mapped pages */ 2056 for (i = 0; i < last_frag; i++) { 2057 ena_buf++; 2058 dma_unmap_page(tx_ring->dev, dma_unmap_addr(ena_buf, paddr), 2059 dma_unmap_len(ena_buf, len), DMA_TO_DEVICE); 2060 } 2061 } 2062 2063 error_drop_packet: 2064 2065 dev_kfree_skb(skb); 2066 return NETDEV_TX_OK; 2067 } 2068 2069 #ifdef CONFIG_NET_POLL_CONTROLLER 2070 static void ena_netpoll(struct net_device *netdev) 2071 { 2072 struct ena_adapter *adapter = netdev_priv(netdev); 2073 int i; 2074 2075 /* Dont schedule NAPI if the driver is in the middle of reset 2076 * or netdev is down. 2077 */ 2078 2079 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags) || 2080 test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags)) 2081 return; 2082 2083 for (i = 0; i < adapter->num_queues; i++) 2084 napi_schedule(&adapter->ena_napi[i].napi); 2085 } 2086 #endif /* CONFIG_NET_POLL_CONTROLLER */ 2087 2088 static u16 ena_select_queue(struct net_device *dev, struct sk_buff *skb, 2089 void *accel_priv, select_queue_fallback_t fallback) 2090 { 2091 u16 qid; 2092 /* we suspect that this is good for in--kernel network services that 2093 * want to loop incoming skb rx to tx in normal user generated traffic, 2094 * most probably we will not get to this 2095 */ 2096 if (skb_rx_queue_recorded(skb)) 2097 qid = skb_get_rx_queue(skb); 2098 else 2099 qid = fallback(dev, skb); 2100 2101 return qid; 2102 } 2103 2104 static void ena_config_host_info(struct ena_com_dev *ena_dev) 2105 { 2106 struct ena_admin_host_info *host_info; 2107 int rc; 2108 2109 /* Allocate only the host info */ 2110 rc = ena_com_allocate_host_info(ena_dev); 2111 if (rc) { 2112 pr_err("Cannot allocate host info\n"); 2113 return; 2114 } 2115 2116 host_info = ena_dev->host_attr.host_info; 2117 2118 host_info->os_type = ENA_ADMIN_OS_LINUX; 2119 host_info->kernel_ver = LINUX_VERSION_CODE; 2120 strncpy(host_info->kernel_ver_str, utsname()->version, 2121 sizeof(host_info->kernel_ver_str) - 1); 2122 host_info->os_dist = 0; 2123 strncpy(host_info->os_dist_str, utsname()->release, 2124 sizeof(host_info->os_dist_str) - 1); 2125 host_info->driver_version = 2126 (DRV_MODULE_VER_MAJOR) | 2127 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 2128 (DRV_MODULE_VER_SUBMINOR << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 2129 2130 rc = ena_com_set_host_attributes(ena_dev); 2131 if (rc) { 2132 if (rc == -EPERM) 2133 pr_warn("Cannot set host attributes\n"); 2134 else 2135 pr_err("Cannot set host attributes\n"); 2136 2137 goto err; 2138 } 2139 2140 return; 2141 2142 err: 2143 ena_com_delete_host_info(ena_dev); 2144 } 2145 2146 static void ena_config_debug_area(struct ena_adapter *adapter) 2147 { 2148 u32 debug_area_size; 2149 int rc, ss_count; 2150 2151 ss_count = ena_get_sset_count(adapter->netdev, ETH_SS_STATS); 2152 if (ss_count <= 0) { 2153 netif_err(adapter, drv, adapter->netdev, 2154 "SS count is negative\n"); 2155 return; 2156 } 2157 2158 /* allocate 32 bytes for each string and 64bit for the value */ 2159 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count; 2160 2161 rc = ena_com_allocate_debug_area(adapter->ena_dev, debug_area_size); 2162 if (rc) { 2163 pr_err("Cannot allocate debug area\n"); 2164 return; 2165 } 2166 2167 rc = ena_com_set_host_attributes(adapter->ena_dev); 2168 if (rc) { 2169 if (rc == -EPERM) 2170 netif_warn(adapter, drv, adapter->netdev, 2171 "Cannot set host attributes\n"); 2172 else 2173 netif_err(adapter, drv, adapter->netdev, 2174 "Cannot set host attributes\n"); 2175 goto err; 2176 } 2177 2178 return; 2179 err: 2180 ena_com_delete_debug_area(adapter->ena_dev); 2181 } 2182 2183 static void ena_get_stats64(struct net_device *netdev, 2184 struct rtnl_link_stats64 *stats) 2185 { 2186 struct ena_adapter *adapter = netdev_priv(netdev); 2187 struct ena_ring *rx_ring, *tx_ring; 2188 unsigned int start; 2189 u64 rx_drops; 2190 int i; 2191 2192 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags)) 2193 return; 2194 2195 for (i = 0; i < adapter->num_queues; i++) { 2196 u64 bytes, packets; 2197 2198 tx_ring = &adapter->tx_ring[i]; 2199 2200 do { 2201 start = u64_stats_fetch_begin_irq(&tx_ring->syncp); 2202 packets = tx_ring->tx_stats.cnt; 2203 bytes = tx_ring->tx_stats.bytes; 2204 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start)); 2205 2206 stats->tx_packets += packets; 2207 stats->tx_bytes += bytes; 2208 2209 rx_ring = &adapter->rx_ring[i]; 2210 2211 do { 2212 start = u64_stats_fetch_begin_irq(&rx_ring->syncp); 2213 packets = rx_ring->rx_stats.cnt; 2214 bytes = rx_ring->rx_stats.bytes; 2215 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start)); 2216 2217 stats->rx_packets += packets; 2218 stats->rx_bytes += bytes; 2219 } 2220 2221 do { 2222 start = u64_stats_fetch_begin_irq(&adapter->syncp); 2223 rx_drops = adapter->dev_stats.rx_drops; 2224 } while (u64_stats_fetch_retry_irq(&adapter->syncp, start)); 2225 2226 stats->rx_dropped = rx_drops; 2227 2228 stats->multicast = 0; 2229 stats->collisions = 0; 2230 2231 stats->rx_length_errors = 0; 2232 stats->rx_crc_errors = 0; 2233 stats->rx_frame_errors = 0; 2234 stats->rx_fifo_errors = 0; 2235 stats->rx_missed_errors = 0; 2236 stats->tx_window_errors = 0; 2237 2238 stats->rx_errors = 0; 2239 stats->tx_errors = 0; 2240 } 2241 2242 static const struct net_device_ops ena_netdev_ops = { 2243 .ndo_open = ena_open, 2244 .ndo_stop = ena_close, 2245 .ndo_start_xmit = ena_start_xmit, 2246 .ndo_select_queue = ena_select_queue, 2247 .ndo_get_stats64 = ena_get_stats64, 2248 .ndo_tx_timeout = ena_tx_timeout, 2249 .ndo_change_mtu = ena_change_mtu, 2250 .ndo_set_mac_address = NULL, 2251 .ndo_validate_addr = eth_validate_addr, 2252 #ifdef CONFIG_NET_POLL_CONTROLLER 2253 .ndo_poll_controller = ena_netpoll, 2254 #endif /* CONFIG_NET_POLL_CONTROLLER */ 2255 }; 2256 2257 static void ena_device_io_suspend(struct work_struct *work) 2258 { 2259 struct ena_adapter *adapter = 2260 container_of(work, struct ena_adapter, suspend_io_task); 2261 struct net_device *netdev = adapter->netdev; 2262 2263 /* ena_napi_disable_all disables only the IO handling. 2264 * We are still subject to AENQ keep alive watchdog. 2265 */ 2266 u64_stats_update_begin(&adapter->syncp); 2267 adapter->dev_stats.io_suspend++; 2268 u64_stats_update_begin(&adapter->syncp); 2269 ena_napi_disable_all(adapter); 2270 netif_tx_lock(netdev); 2271 netif_device_detach(netdev); 2272 netif_tx_unlock(netdev); 2273 } 2274 2275 static void ena_device_io_resume(struct work_struct *work) 2276 { 2277 struct ena_adapter *adapter = 2278 container_of(work, struct ena_adapter, resume_io_task); 2279 struct net_device *netdev = adapter->netdev; 2280 2281 u64_stats_update_begin(&adapter->syncp); 2282 adapter->dev_stats.io_resume++; 2283 u64_stats_update_end(&adapter->syncp); 2284 2285 netif_device_attach(netdev); 2286 ena_napi_enable_all(adapter); 2287 } 2288 2289 static int ena_device_validate_params(struct ena_adapter *adapter, 2290 struct ena_com_dev_get_features_ctx *get_feat_ctx) 2291 { 2292 struct net_device *netdev = adapter->netdev; 2293 int rc; 2294 2295 rc = ether_addr_equal(get_feat_ctx->dev_attr.mac_addr, 2296 adapter->mac_addr); 2297 if (!rc) { 2298 netif_err(adapter, drv, netdev, 2299 "Error, mac address are different\n"); 2300 return -EINVAL; 2301 } 2302 2303 if ((get_feat_ctx->max_queues.max_cq_num < adapter->num_queues) || 2304 (get_feat_ctx->max_queues.max_sq_num < adapter->num_queues)) { 2305 netif_err(adapter, drv, netdev, 2306 "Error, device doesn't support enough queues\n"); 2307 return -EINVAL; 2308 } 2309 2310 if (get_feat_ctx->dev_attr.max_mtu < netdev->mtu) { 2311 netif_err(adapter, drv, netdev, 2312 "Error, device max mtu is smaller than netdev MTU\n"); 2313 return -EINVAL; 2314 } 2315 2316 return 0; 2317 } 2318 2319 static int ena_device_init(struct ena_com_dev *ena_dev, struct pci_dev *pdev, 2320 struct ena_com_dev_get_features_ctx *get_feat_ctx, 2321 bool *wd_state) 2322 { 2323 struct device *dev = &pdev->dev; 2324 bool readless_supported; 2325 u32 aenq_groups; 2326 int dma_width; 2327 int rc; 2328 2329 rc = ena_com_mmio_reg_read_request_init(ena_dev); 2330 if (rc) { 2331 dev_err(dev, "failed to init mmio read less\n"); 2332 return rc; 2333 } 2334 2335 /* The PCIe configuration space revision id indicate if mmio reg 2336 * read is disabled 2337 */ 2338 readless_supported = !(pdev->revision & ENA_MMIO_DISABLE_REG_READ); 2339 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 2340 2341 rc = ena_com_dev_reset(ena_dev); 2342 if (rc) { 2343 dev_err(dev, "Can not reset device\n"); 2344 goto err_mmio_read_less; 2345 } 2346 2347 rc = ena_com_validate_version(ena_dev); 2348 if (rc) { 2349 dev_err(dev, "device version is too low\n"); 2350 goto err_mmio_read_less; 2351 } 2352 2353 dma_width = ena_com_get_dma_width(ena_dev); 2354 if (dma_width < 0) { 2355 dev_err(dev, "Invalid dma width value %d", dma_width); 2356 rc = dma_width; 2357 goto err_mmio_read_less; 2358 } 2359 2360 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(dma_width)); 2361 if (rc) { 2362 dev_err(dev, "pci_set_dma_mask failed 0x%x\n", rc); 2363 goto err_mmio_read_less; 2364 } 2365 2366 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(dma_width)); 2367 if (rc) { 2368 dev_err(dev, "err_pci_set_consistent_dma_mask failed 0x%x\n", 2369 rc); 2370 goto err_mmio_read_less; 2371 } 2372 2373 /* ENA admin level init */ 2374 rc = ena_com_admin_init(ena_dev, &aenq_handlers, true); 2375 if (rc) { 2376 dev_err(dev, 2377 "Can not initialize ena admin queue with device\n"); 2378 goto err_mmio_read_less; 2379 } 2380 2381 /* To enable the msix interrupts the driver needs to know the number 2382 * of queues. So the driver uses polling mode to retrieve this 2383 * information 2384 */ 2385 ena_com_set_admin_polling_mode(ena_dev, true); 2386 2387 ena_config_host_info(ena_dev); 2388 2389 /* Get Device Attributes*/ 2390 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 2391 if (rc) { 2392 dev_err(dev, "Cannot get attribute for ena device rc=%d\n", rc); 2393 goto err_admin_init; 2394 } 2395 2396 /* Try to turn all the available aenq groups */ 2397 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | 2398 BIT(ENA_ADMIN_FATAL_ERROR) | 2399 BIT(ENA_ADMIN_WARNING) | 2400 BIT(ENA_ADMIN_NOTIFICATION) | 2401 BIT(ENA_ADMIN_KEEP_ALIVE); 2402 2403 aenq_groups &= get_feat_ctx->aenq.supported_groups; 2404 2405 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 2406 if (rc) { 2407 dev_err(dev, "Cannot configure aenq groups rc= %d\n", rc); 2408 goto err_admin_init; 2409 } 2410 2411 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 2412 2413 return 0; 2414 2415 err_admin_init: 2416 ena_com_delete_host_info(ena_dev); 2417 ena_com_admin_destroy(ena_dev); 2418 err_mmio_read_less: 2419 ena_com_mmio_reg_read_request_destroy(ena_dev); 2420 2421 return rc; 2422 } 2423 2424 static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *adapter, 2425 int io_vectors) 2426 { 2427 struct ena_com_dev *ena_dev = adapter->ena_dev; 2428 struct device *dev = &adapter->pdev->dev; 2429 int rc; 2430 2431 rc = ena_enable_msix(adapter, io_vectors); 2432 if (rc) { 2433 dev_err(dev, "Can not reserve msix vectors\n"); 2434 return rc; 2435 } 2436 2437 ena_setup_mgmnt_intr(adapter); 2438 2439 rc = ena_request_mgmnt_irq(adapter); 2440 if (rc) { 2441 dev_err(dev, "Can not setup management interrupts\n"); 2442 goto err_disable_msix; 2443 } 2444 2445 ena_com_set_admin_polling_mode(ena_dev, false); 2446 2447 ena_com_admin_aenq_enable(ena_dev); 2448 2449 return 0; 2450 2451 err_disable_msix: 2452 pci_free_irq_vectors(adapter->pdev); 2453 return rc; 2454 } 2455 2456 static void ena_fw_reset_device(struct work_struct *work) 2457 { 2458 struct ena_com_dev_get_features_ctx get_feat_ctx; 2459 struct ena_adapter *adapter = 2460 container_of(work, struct ena_adapter, reset_task); 2461 struct net_device *netdev = adapter->netdev; 2462 struct ena_com_dev *ena_dev = adapter->ena_dev; 2463 struct pci_dev *pdev = adapter->pdev; 2464 bool dev_up, wd_state; 2465 int rc; 2466 2467 if (unlikely(!test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) { 2468 dev_err(&pdev->dev, 2469 "device reset schedule while reset bit is off\n"); 2470 return; 2471 } 2472 2473 netif_carrier_off(netdev); 2474 2475 del_timer_sync(&adapter->timer_service); 2476 2477 rtnl_lock(); 2478 2479 dev_up = test_bit(ENA_FLAG_DEV_UP, &adapter->flags); 2480 ena_com_set_admin_running_state(ena_dev, false); 2481 2482 /* After calling ena_close the tx queues and the napi 2483 * are disabled so no one can interfere or touch the 2484 * data structures 2485 */ 2486 ena_close(netdev); 2487 2488 ena_free_mgmnt_irq(adapter); 2489 2490 pci_free_irq_vectors(adapter->pdev); 2491 2492 ena_com_abort_admin_commands(ena_dev); 2493 2494 ena_com_wait_for_abort_completion(ena_dev); 2495 2496 ena_com_admin_destroy(ena_dev); 2497 2498 ena_com_mmio_reg_read_request_destroy(ena_dev); 2499 2500 clear_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags); 2501 2502 /* Finish with the destroy part. Start the init part */ 2503 2504 rc = ena_device_init(ena_dev, adapter->pdev, &get_feat_ctx, &wd_state); 2505 if (rc) { 2506 dev_err(&pdev->dev, "Can not initialize device\n"); 2507 goto err; 2508 } 2509 adapter->wd_state = wd_state; 2510 2511 rc = ena_device_validate_params(adapter, &get_feat_ctx); 2512 if (rc) { 2513 dev_err(&pdev->dev, "Validation of device parameters failed\n"); 2514 goto err_device_destroy; 2515 } 2516 2517 rc = ena_enable_msix_and_set_admin_interrupts(adapter, 2518 adapter->num_queues); 2519 if (rc) { 2520 dev_err(&pdev->dev, "Enable MSI-X failed\n"); 2521 goto err_device_destroy; 2522 } 2523 /* If the interface was up before the reset bring it up */ 2524 if (dev_up) { 2525 rc = ena_up(adapter); 2526 if (rc) { 2527 dev_err(&pdev->dev, "Failed to create I/O queues\n"); 2528 goto err_disable_msix; 2529 } 2530 } 2531 2532 mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ)); 2533 2534 rtnl_unlock(); 2535 2536 dev_err(&pdev->dev, "Device reset completed successfully\n"); 2537 2538 return; 2539 err_disable_msix: 2540 ena_free_mgmnt_irq(adapter); 2541 pci_free_irq_vectors(adapter->pdev); 2542 err_device_destroy: 2543 ena_com_admin_destroy(ena_dev); 2544 err: 2545 rtnl_unlock(); 2546 2547 clear_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags); 2548 2549 dev_err(&pdev->dev, 2550 "Reset attempt failed. Can not reset the device\n"); 2551 } 2552 2553 static void check_for_missing_tx_completions(struct ena_adapter *adapter) 2554 { 2555 struct ena_tx_buffer *tx_buf; 2556 unsigned long last_jiffies; 2557 struct ena_ring *tx_ring; 2558 int i, j, budget; 2559 u32 missed_tx; 2560 2561 /* Make sure the driver doesn't turn the device in other process */ 2562 smp_rmb(); 2563 2564 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags)) 2565 return; 2566 2567 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags)) 2568 return; 2569 2570 budget = ENA_MONITORED_TX_QUEUES; 2571 2572 for (i = adapter->last_monitored_tx_qid; i < adapter->num_queues; i++) { 2573 tx_ring = &adapter->tx_ring[i]; 2574 2575 for (j = 0; j < tx_ring->ring_size; j++) { 2576 tx_buf = &tx_ring->tx_buffer_info[j]; 2577 last_jiffies = tx_buf->last_jiffies; 2578 if (unlikely(last_jiffies && time_is_before_jiffies(last_jiffies + TX_TIMEOUT))) { 2579 netif_notice(adapter, tx_err, adapter->netdev, 2580 "Found a Tx that wasn't completed on time, qid %d, index %d.\n", 2581 tx_ring->qid, j); 2582 2583 u64_stats_update_begin(&tx_ring->syncp); 2584 missed_tx = tx_ring->tx_stats.missing_tx_comp++; 2585 u64_stats_update_end(&tx_ring->syncp); 2586 2587 /* Clear last jiffies so the lost buffer won't 2588 * be counted twice. 2589 */ 2590 tx_buf->last_jiffies = 0; 2591 2592 if (unlikely(missed_tx > MAX_NUM_OF_TIMEOUTED_PACKETS)) { 2593 netif_err(adapter, tx_err, adapter->netdev, 2594 "The number of lost tx completion is above the threshold (%d > %d). Reset the device\n", 2595 missed_tx, MAX_NUM_OF_TIMEOUTED_PACKETS); 2596 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags); 2597 } 2598 } 2599 } 2600 2601 budget--; 2602 if (!budget) 2603 break; 2604 } 2605 2606 adapter->last_monitored_tx_qid = i % adapter->num_queues; 2607 } 2608 2609 /* Check for keep alive expiration */ 2610 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 2611 { 2612 unsigned long keep_alive_expired; 2613 2614 if (!adapter->wd_state) 2615 return; 2616 2617 keep_alive_expired = round_jiffies(adapter->last_keep_alive_jiffies 2618 + ENA_DEVICE_KALIVE_TIMEOUT); 2619 if (unlikely(time_is_before_jiffies(keep_alive_expired))) { 2620 netif_err(adapter, drv, adapter->netdev, 2621 "Keep alive watchdog timeout.\n"); 2622 u64_stats_update_begin(&adapter->syncp); 2623 adapter->dev_stats.wd_expired++; 2624 u64_stats_update_end(&adapter->syncp); 2625 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags); 2626 } 2627 } 2628 2629 static void check_for_admin_com_state(struct ena_adapter *adapter) 2630 { 2631 if (unlikely(!ena_com_get_admin_running_state(adapter->ena_dev))) { 2632 netif_err(adapter, drv, adapter->netdev, 2633 "ENA admin queue is not in running state!\n"); 2634 u64_stats_update_begin(&adapter->syncp); 2635 adapter->dev_stats.admin_q_pause++; 2636 u64_stats_update_end(&adapter->syncp); 2637 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags); 2638 } 2639 } 2640 2641 static void ena_update_host_info(struct ena_admin_host_info *host_info, 2642 struct net_device *netdev) 2643 { 2644 host_info->supported_network_features[0] = 2645 netdev->features & GENMASK_ULL(31, 0); 2646 host_info->supported_network_features[1] = 2647 (netdev->features & GENMASK_ULL(63, 32)) >> 32; 2648 } 2649 2650 static void ena_timer_service(unsigned long data) 2651 { 2652 struct ena_adapter *adapter = (struct ena_adapter *)data; 2653 u8 *debug_area = adapter->ena_dev->host_attr.debug_area_virt_addr; 2654 struct ena_admin_host_info *host_info = 2655 adapter->ena_dev->host_attr.host_info; 2656 2657 check_for_missing_keep_alive(adapter); 2658 2659 check_for_admin_com_state(adapter); 2660 2661 check_for_missing_tx_completions(adapter); 2662 2663 if (debug_area) 2664 ena_dump_stats_to_buf(adapter, debug_area); 2665 2666 if (host_info) 2667 ena_update_host_info(host_info, adapter->netdev); 2668 2669 if (unlikely(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) { 2670 netif_err(adapter, drv, adapter->netdev, 2671 "Trigger reset is on\n"); 2672 ena_dump_stats_to_dmesg(adapter); 2673 queue_work(ena_wq, &adapter->reset_task); 2674 return; 2675 } 2676 2677 /* Reset the timer */ 2678 mod_timer(&adapter->timer_service, jiffies + HZ); 2679 } 2680 2681 static int ena_calc_io_queue_num(struct pci_dev *pdev, 2682 struct ena_com_dev *ena_dev, 2683 struct ena_com_dev_get_features_ctx *get_feat_ctx) 2684 { 2685 int io_sq_num, io_queue_num; 2686 2687 /* In case of LLQ use the llq number in the get feature cmd */ 2688 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 2689 io_sq_num = get_feat_ctx->max_queues.max_llq_num; 2690 2691 if (io_sq_num == 0) { 2692 dev_err(&pdev->dev, 2693 "Trying to use LLQ but llq_num is 0. Fall back into regular queues\n"); 2694 2695 ena_dev->tx_mem_queue_type = 2696 ENA_ADMIN_PLACEMENT_POLICY_HOST; 2697 io_sq_num = get_feat_ctx->max_queues.max_sq_num; 2698 } 2699 } else { 2700 io_sq_num = get_feat_ctx->max_queues.max_sq_num; 2701 } 2702 2703 io_queue_num = min_t(int, num_online_cpus(), ENA_MAX_NUM_IO_QUEUES); 2704 io_queue_num = min_t(int, io_queue_num, io_sq_num); 2705 io_queue_num = min_t(int, io_queue_num, 2706 get_feat_ctx->max_queues.max_cq_num); 2707 /* 1 IRQ for for mgmnt and 1 IRQs for each IO direction */ 2708 io_queue_num = min_t(int, io_queue_num, pci_msix_vec_count(pdev) - 1); 2709 if (unlikely(!io_queue_num)) { 2710 dev_err(&pdev->dev, "The device doesn't have io queues\n"); 2711 return -EFAULT; 2712 } 2713 2714 return io_queue_num; 2715 } 2716 2717 static void ena_set_push_mode(struct pci_dev *pdev, struct ena_com_dev *ena_dev, 2718 struct ena_com_dev_get_features_ctx *get_feat_ctx) 2719 { 2720 bool has_mem_bar; 2721 2722 has_mem_bar = pci_select_bars(pdev, IORESOURCE_MEM) & BIT(ENA_MEM_BAR); 2723 2724 /* Enable push mode if device supports LLQ */ 2725 if (has_mem_bar && (get_feat_ctx->max_queues.max_llq_num > 0)) 2726 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV; 2727 else 2728 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 2729 } 2730 2731 static void ena_set_dev_offloads(struct ena_com_dev_get_features_ctx *feat, 2732 struct net_device *netdev) 2733 { 2734 netdev_features_t dev_features = 0; 2735 2736 /* Set offload features */ 2737 if (feat->offload.tx & 2738 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) 2739 dev_features |= NETIF_F_IP_CSUM; 2740 2741 if (feat->offload.tx & 2742 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) 2743 dev_features |= NETIF_F_IPV6_CSUM; 2744 2745 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) 2746 dev_features |= NETIF_F_TSO; 2747 2748 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) 2749 dev_features |= NETIF_F_TSO6; 2750 2751 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK) 2752 dev_features |= NETIF_F_TSO_ECN; 2753 2754 if (feat->offload.rx_supported & 2755 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) 2756 dev_features |= NETIF_F_RXCSUM; 2757 2758 if (feat->offload.rx_supported & 2759 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) 2760 dev_features |= NETIF_F_RXCSUM; 2761 2762 netdev->features = 2763 dev_features | 2764 NETIF_F_SG | 2765 NETIF_F_RXHASH | 2766 NETIF_F_HIGHDMA; 2767 2768 netdev->hw_features |= netdev->features; 2769 netdev->vlan_features |= netdev->features; 2770 } 2771 2772 static void ena_set_conf_feat_params(struct ena_adapter *adapter, 2773 struct ena_com_dev_get_features_ctx *feat) 2774 { 2775 struct net_device *netdev = adapter->netdev; 2776 2777 /* Copy mac address */ 2778 if (!is_valid_ether_addr(feat->dev_attr.mac_addr)) { 2779 eth_hw_addr_random(netdev); 2780 ether_addr_copy(adapter->mac_addr, netdev->dev_addr); 2781 } else { 2782 ether_addr_copy(adapter->mac_addr, feat->dev_attr.mac_addr); 2783 ether_addr_copy(netdev->dev_addr, adapter->mac_addr); 2784 } 2785 2786 /* Set offload features */ 2787 ena_set_dev_offloads(feat, netdev); 2788 2789 adapter->max_mtu = feat->dev_attr.max_mtu; 2790 netdev->max_mtu = adapter->max_mtu; 2791 netdev->min_mtu = ENA_MIN_MTU; 2792 } 2793 2794 static int ena_rss_init_default(struct ena_adapter *adapter) 2795 { 2796 struct ena_com_dev *ena_dev = adapter->ena_dev; 2797 struct device *dev = &adapter->pdev->dev; 2798 int rc, i; 2799 u32 val; 2800 2801 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 2802 if (unlikely(rc)) { 2803 dev_err(dev, "Cannot init indirect table\n"); 2804 goto err_rss_init; 2805 } 2806 2807 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 2808 val = ethtool_rxfh_indir_default(i, adapter->num_queues); 2809 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 2810 ENA_IO_RXQ_IDX(val)); 2811 if (unlikely(rc && (rc != -EPERM))) { 2812 dev_err(dev, "Cannot fill indirect table\n"); 2813 goto err_fill_indir; 2814 } 2815 } 2816 2817 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 2818 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 2819 if (unlikely(rc && (rc != -EPERM))) { 2820 dev_err(dev, "Cannot fill hash function\n"); 2821 goto err_fill_indir; 2822 } 2823 2824 rc = ena_com_set_default_hash_ctrl(ena_dev); 2825 if (unlikely(rc && (rc != -EPERM))) { 2826 dev_err(dev, "Cannot fill hash control\n"); 2827 goto err_fill_indir; 2828 } 2829 2830 return 0; 2831 2832 err_fill_indir: 2833 ena_com_rss_destroy(ena_dev); 2834 err_rss_init: 2835 2836 return rc; 2837 } 2838 2839 static void ena_release_bars(struct ena_com_dev *ena_dev, struct pci_dev *pdev) 2840 { 2841 int release_bars; 2842 2843 release_bars = pci_select_bars(pdev, IORESOURCE_MEM) & ENA_BAR_MASK; 2844 pci_release_selected_regions(pdev, release_bars); 2845 } 2846 2847 static int ena_calc_queue_size(struct pci_dev *pdev, 2848 struct ena_com_dev *ena_dev, 2849 u16 *max_tx_sgl_size, 2850 u16 *max_rx_sgl_size, 2851 struct ena_com_dev_get_features_ctx *get_feat_ctx) 2852 { 2853 u32 queue_size = ENA_DEFAULT_RING_SIZE; 2854 2855 queue_size = min_t(u32, queue_size, 2856 get_feat_ctx->max_queues.max_cq_depth); 2857 queue_size = min_t(u32, queue_size, 2858 get_feat_ctx->max_queues.max_sq_depth); 2859 2860 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) 2861 queue_size = min_t(u32, queue_size, 2862 get_feat_ctx->max_queues.max_llq_depth); 2863 2864 queue_size = rounddown_pow_of_two(queue_size); 2865 2866 if (unlikely(!queue_size)) { 2867 dev_err(&pdev->dev, "Invalid queue size\n"); 2868 return -EFAULT; 2869 } 2870 2871 *max_tx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS, 2872 get_feat_ctx->max_queues.max_packet_tx_descs); 2873 *max_rx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS, 2874 get_feat_ctx->max_queues.max_packet_rx_descs); 2875 2876 return queue_size; 2877 } 2878 2879 /* ena_probe - Device Initialization Routine 2880 * @pdev: PCI device information struct 2881 * @ent: entry in ena_pci_tbl 2882 * 2883 * Returns 0 on success, negative on failure 2884 * 2885 * ena_probe initializes an adapter identified by a pci_dev structure. 2886 * The OS initialization, configuring of the adapter private structure, 2887 * and a hardware reset occur. 2888 */ 2889 static int ena_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2890 { 2891 struct ena_com_dev_get_features_ctx get_feat_ctx; 2892 static int version_printed; 2893 struct net_device *netdev; 2894 struct ena_adapter *adapter; 2895 struct ena_com_dev *ena_dev = NULL; 2896 static int adapters_found; 2897 int io_queue_num, bars, rc; 2898 int queue_size; 2899 u16 tx_sgl_size = 0; 2900 u16 rx_sgl_size = 0; 2901 bool wd_state; 2902 2903 dev_dbg(&pdev->dev, "%s\n", __func__); 2904 2905 if (version_printed++ == 0) 2906 dev_info(&pdev->dev, "%s", version); 2907 2908 rc = pci_enable_device_mem(pdev); 2909 if (rc) { 2910 dev_err(&pdev->dev, "pci_enable_device_mem() failed!\n"); 2911 return rc; 2912 } 2913 2914 pci_set_master(pdev); 2915 2916 ena_dev = vzalloc(sizeof(*ena_dev)); 2917 if (!ena_dev) { 2918 rc = -ENOMEM; 2919 goto err_disable_device; 2920 } 2921 2922 bars = pci_select_bars(pdev, IORESOURCE_MEM) & ENA_BAR_MASK; 2923 rc = pci_request_selected_regions(pdev, bars, DRV_MODULE_NAME); 2924 if (rc) { 2925 dev_err(&pdev->dev, "pci_request_selected_regions failed %d\n", 2926 rc); 2927 goto err_free_ena_dev; 2928 } 2929 2930 ena_dev->reg_bar = ioremap(pci_resource_start(pdev, ENA_REG_BAR), 2931 pci_resource_len(pdev, ENA_REG_BAR)); 2932 if (!ena_dev->reg_bar) { 2933 dev_err(&pdev->dev, "failed to remap regs bar\n"); 2934 rc = -EFAULT; 2935 goto err_free_region; 2936 } 2937 2938 ena_dev->dmadev = &pdev->dev; 2939 2940 rc = ena_device_init(ena_dev, pdev, &get_feat_ctx, &wd_state); 2941 if (rc) { 2942 dev_err(&pdev->dev, "ena device init failed\n"); 2943 if (rc == -ETIME) 2944 rc = -EPROBE_DEFER; 2945 goto err_free_region; 2946 } 2947 2948 ena_set_push_mode(pdev, ena_dev, &get_feat_ctx); 2949 2950 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 2951 ena_dev->mem_bar = ioremap_wc(pci_resource_start(pdev, ENA_MEM_BAR), 2952 pci_resource_len(pdev, ENA_MEM_BAR)); 2953 if (!ena_dev->mem_bar) { 2954 rc = -EFAULT; 2955 goto err_device_destroy; 2956 } 2957 } 2958 2959 /* initial Tx interrupt delay, Assumes 1 usec granularity. 2960 * Updated during device initialization with the real granularity 2961 */ 2962 ena_dev->intr_moder_tx_interval = ENA_INTR_INITIAL_TX_INTERVAL_USECS; 2963 io_queue_num = ena_calc_io_queue_num(pdev, ena_dev, &get_feat_ctx); 2964 queue_size = ena_calc_queue_size(pdev, ena_dev, &tx_sgl_size, 2965 &rx_sgl_size, &get_feat_ctx); 2966 if ((queue_size <= 0) || (io_queue_num <= 0)) { 2967 rc = -EFAULT; 2968 goto err_device_destroy; 2969 } 2970 2971 dev_info(&pdev->dev, "creating %d io queues. queue size: %d\n", 2972 io_queue_num, queue_size); 2973 2974 /* dev zeroed in init_etherdev */ 2975 netdev = alloc_etherdev_mq(sizeof(struct ena_adapter), io_queue_num); 2976 if (!netdev) { 2977 dev_err(&pdev->dev, "alloc_etherdev_mq failed\n"); 2978 rc = -ENOMEM; 2979 goto err_device_destroy; 2980 } 2981 2982 SET_NETDEV_DEV(netdev, &pdev->dev); 2983 2984 adapter = netdev_priv(netdev); 2985 pci_set_drvdata(pdev, adapter); 2986 2987 adapter->ena_dev = ena_dev; 2988 adapter->netdev = netdev; 2989 adapter->pdev = pdev; 2990 2991 ena_set_conf_feat_params(adapter, &get_feat_ctx); 2992 2993 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2994 2995 adapter->tx_ring_size = queue_size; 2996 adapter->rx_ring_size = queue_size; 2997 2998 adapter->max_tx_sgl_size = tx_sgl_size; 2999 adapter->max_rx_sgl_size = rx_sgl_size; 3000 3001 adapter->num_queues = io_queue_num; 3002 adapter->last_monitored_tx_qid = 0; 3003 3004 adapter->rx_copybreak = ENA_DEFAULT_RX_COPYBREAK; 3005 adapter->wd_state = wd_state; 3006 3007 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", adapters_found); 3008 3009 rc = ena_com_init_interrupt_moderation(adapter->ena_dev); 3010 if (rc) { 3011 dev_err(&pdev->dev, 3012 "Failed to query interrupt moderation feature\n"); 3013 goto err_netdev_destroy; 3014 } 3015 ena_init_io_rings(adapter); 3016 3017 netdev->netdev_ops = &ena_netdev_ops; 3018 netdev->watchdog_timeo = TX_TIMEOUT; 3019 ena_set_ethtool_ops(netdev); 3020 3021 netdev->priv_flags |= IFF_UNICAST_FLT; 3022 3023 u64_stats_init(&adapter->syncp); 3024 3025 rc = ena_enable_msix_and_set_admin_interrupts(adapter, io_queue_num); 3026 if (rc) { 3027 dev_err(&pdev->dev, 3028 "Failed to enable and set the admin interrupts\n"); 3029 goto err_worker_destroy; 3030 } 3031 rc = ena_rss_init_default(adapter); 3032 if (rc && (rc != -EPERM)) { 3033 dev_err(&pdev->dev, "Cannot init RSS rc: %d\n", rc); 3034 goto err_free_msix; 3035 } 3036 3037 ena_config_debug_area(adapter); 3038 3039 memcpy(adapter->netdev->perm_addr, adapter->mac_addr, netdev->addr_len); 3040 3041 netif_carrier_off(netdev); 3042 3043 rc = register_netdev(netdev); 3044 if (rc) { 3045 dev_err(&pdev->dev, "Cannot register net device\n"); 3046 goto err_rss; 3047 } 3048 3049 INIT_WORK(&adapter->suspend_io_task, ena_device_io_suspend); 3050 INIT_WORK(&adapter->resume_io_task, ena_device_io_resume); 3051 INIT_WORK(&adapter->reset_task, ena_fw_reset_device); 3052 3053 adapter->last_keep_alive_jiffies = jiffies; 3054 3055 setup_timer(&adapter->timer_service, ena_timer_service, 3056 (unsigned long)adapter); 3057 mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ)); 3058 3059 dev_info(&pdev->dev, "%s found at mem %lx, mac addr %pM Queues %d\n", 3060 DEVICE_NAME, (long)pci_resource_start(pdev, 0), 3061 netdev->dev_addr, io_queue_num); 3062 3063 set_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags); 3064 3065 adapters_found++; 3066 3067 return 0; 3068 3069 err_rss: 3070 ena_com_delete_debug_area(ena_dev); 3071 ena_com_rss_destroy(ena_dev); 3072 err_free_msix: 3073 ena_com_dev_reset(ena_dev); 3074 ena_free_mgmnt_irq(adapter); 3075 pci_free_irq_vectors(adapter->pdev); 3076 err_worker_destroy: 3077 ena_com_destroy_interrupt_moderation(ena_dev); 3078 del_timer(&adapter->timer_service); 3079 cancel_work_sync(&adapter->suspend_io_task); 3080 cancel_work_sync(&adapter->resume_io_task); 3081 err_netdev_destroy: 3082 free_netdev(netdev); 3083 err_device_destroy: 3084 ena_com_delete_host_info(ena_dev); 3085 ena_com_admin_destroy(ena_dev); 3086 err_free_region: 3087 ena_release_bars(ena_dev, pdev); 3088 err_free_ena_dev: 3089 vfree(ena_dev); 3090 err_disable_device: 3091 pci_disable_device(pdev); 3092 return rc; 3093 } 3094 3095 /*****************************************************************************/ 3096 static int ena_sriov_configure(struct pci_dev *dev, int numvfs) 3097 { 3098 int rc; 3099 3100 if (numvfs > 0) { 3101 rc = pci_enable_sriov(dev, numvfs); 3102 if (rc != 0) { 3103 dev_err(&dev->dev, 3104 "pci_enable_sriov failed to enable: %d vfs with the error: %d\n", 3105 numvfs, rc); 3106 return rc; 3107 } 3108 3109 return numvfs; 3110 } 3111 3112 if (numvfs == 0) { 3113 pci_disable_sriov(dev); 3114 return 0; 3115 } 3116 3117 return -EINVAL; 3118 } 3119 3120 /*****************************************************************************/ 3121 /*****************************************************************************/ 3122 3123 /* ena_remove - Device Removal Routine 3124 * @pdev: PCI device information struct 3125 * 3126 * ena_remove is called by the PCI subsystem to alert the driver 3127 * that it should release a PCI device. 3128 */ 3129 static void ena_remove(struct pci_dev *pdev) 3130 { 3131 struct ena_adapter *adapter = pci_get_drvdata(pdev); 3132 struct ena_com_dev *ena_dev; 3133 struct net_device *netdev; 3134 3135 ena_dev = adapter->ena_dev; 3136 netdev = adapter->netdev; 3137 3138 #ifdef CONFIG_RFS_ACCEL 3139 if ((adapter->msix_vecs >= 1) && (netdev->rx_cpu_rmap)) { 3140 free_irq_cpu_rmap(netdev->rx_cpu_rmap); 3141 netdev->rx_cpu_rmap = NULL; 3142 } 3143 #endif /* CONFIG_RFS_ACCEL */ 3144 3145 unregister_netdev(netdev); 3146 del_timer_sync(&adapter->timer_service); 3147 3148 cancel_work_sync(&adapter->reset_task); 3149 3150 cancel_work_sync(&adapter->suspend_io_task); 3151 3152 cancel_work_sync(&adapter->resume_io_task); 3153 3154 /* Reset the device only if the device is running. */ 3155 if (test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags)) 3156 ena_com_dev_reset(ena_dev); 3157 3158 ena_free_mgmnt_irq(adapter); 3159 3160 pci_free_irq_vectors(adapter->pdev); 3161 3162 free_netdev(netdev); 3163 3164 ena_com_mmio_reg_read_request_destroy(ena_dev); 3165 3166 ena_com_abort_admin_commands(ena_dev); 3167 3168 ena_com_wait_for_abort_completion(ena_dev); 3169 3170 ena_com_admin_destroy(ena_dev); 3171 3172 ena_com_rss_destroy(ena_dev); 3173 3174 ena_com_delete_debug_area(ena_dev); 3175 3176 ena_com_delete_host_info(ena_dev); 3177 3178 ena_release_bars(ena_dev, pdev); 3179 3180 pci_disable_device(pdev); 3181 3182 ena_com_destroy_interrupt_moderation(ena_dev); 3183 3184 vfree(ena_dev); 3185 } 3186 3187 static struct pci_driver ena_pci_driver = { 3188 .name = DRV_MODULE_NAME, 3189 .id_table = ena_pci_tbl, 3190 .probe = ena_probe, 3191 .remove = ena_remove, 3192 .sriov_configure = ena_sriov_configure, 3193 }; 3194 3195 static int __init ena_init(void) 3196 { 3197 pr_info("%s", version); 3198 3199 ena_wq = create_singlethread_workqueue(DRV_MODULE_NAME); 3200 if (!ena_wq) { 3201 pr_err("Failed to create workqueue\n"); 3202 return -ENOMEM; 3203 } 3204 3205 return pci_register_driver(&ena_pci_driver); 3206 } 3207 3208 static void __exit ena_cleanup(void) 3209 { 3210 pci_unregister_driver(&ena_pci_driver); 3211 3212 if (ena_wq) { 3213 destroy_workqueue(ena_wq); 3214 ena_wq = NULL; 3215 } 3216 } 3217 3218 /****************************************************************************** 3219 ******************************** AENQ Handlers ******************************* 3220 *****************************************************************************/ 3221 /* ena_update_on_link_change: 3222 * Notify the network interface about the change in link status 3223 */ 3224 static void ena_update_on_link_change(void *adapter_data, 3225 struct ena_admin_aenq_entry *aenq_e) 3226 { 3227 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 3228 struct ena_admin_aenq_link_change_desc *aenq_desc = 3229 (struct ena_admin_aenq_link_change_desc *)aenq_e; 3230 int status = aenq_desc->flags & 3231 ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK; 3232 3233 if (status) { 3234 netdev_dbg(adapter->netdev, "%s\n", __func__); 3235 set_bit(ENA_FLAG_LINK_UP, &adapter->flags); 3236 netif_carrier_on(adapter->netdev); 3237 } else { 3238 clear_bit(ENA_FLAG_LINK_UP, &adapter->flags); 3239 netif_carrier_off(adapter->netdev); 3240 } 3241 } 3242 3243 static void ena_keep_alive_wd(void *adapter_data, 3244 struct ena_admin_aenq_entry *aenq_e) 3245 { 3246 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 3247 3248 adapter->last_keep_alive_jiffies = jiffies; 3249 } 3250 3251 static void ena_notification(void *adapter_data, 3252 struct ena_admin_aenq_entry *aenq_e) 3253 { 3254 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 3255 3256 WARN(aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION, 3257 "Invalid group(%x) expected %x\n", 3258 aenq_e->aenq_common_desc.group, 3259 ENA_ADMIN_NOTIFICATION); 3260 3261 switch (aenq_e->aenq_common_desc.syndrom) { 3262 case ENA_ADMIN_SUSPEND: 3263 /* Suspend just the IO queues. 3264 * We deliberately don't suspend admin so the timer and 3265 * the keep_alive events should remain. 3266 */ 3267 queue_work(ena_wq, &adapter->suspend_io_task); 3268 break; 3269 case ENA_ADMIN_RESUME: 3270 queue_work(ena_wq, &adapter->resume_io_task); 3271 break; 3272 default: 3273 netif_err(adapter, drv, adapter->netdev, 3274 "Invalid aenq notification link state %d\n", 3275 aenq_e->aenq_common_desc.syndrom); 3276 } 3277 } 3278 3279 /* This handler will called for unknown event group or unimplemented handlers*/ 3280 static void unimplemented_aenq_handler(void *data, 3281 struct ena_admin_aenq_entry *aenq_e) 3282 { 3283 struct ena_adapter *adapter = (struct ena_adapter *)data; 3284 3285 netif_err(adapter, drv, adapter->netdev, 3286 "Unknown event was received or event with unimplemented handler\n"); 3287 } 3288 3289 static struct ena_aenq_handlers aenq_handlers = { 3290 .handlers = { 3291 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 3292 [ENA_ADMIN_NOTIFICATION] = ena_notification, 3293 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive_wd, 3294 }, 3295 .unimplemented_handler = unimplemented_aenq_handler 3296 }; 3297 3298 module_init(ena_init); 3299 module_exit(ena_cleanup); 3300