1 /* 2 * Copyright 2015 Amazon.com, Inc. or its affiliates. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 34 35 #ifdef CONFIG_RFS_ACCEL 36 #include <linux/cpu_rmap.h> 37 #endif /* CONFIG_RFS_ACCEL */ 38 #include <linux/ethtool.h> 39 #include <linux/if_vlan.h> 40 #include <linux/kernel.h> 41 #include <linux/module.h> 42 #include <linux/numa.h> 43 #include <linux/pci.h> 44 #include <linux/utsname.h> 45 #include <linux/version.h> 46 #include <linux/vmalloc.h> 47 #include <net/ip.h> 48 49 #include "ena_netdev.h" 50 #include "ena_pci_id_tbl.h" 51 52 static char version[] = DEVICE_NAME " v" DRV_MODULE_VERSION "\n"; 53 54 MODULE_AUTHOR("Amazon.com, Inc. or its affiliates"); 55 MODULE_DESCRIPTION(DEVICE_NAME); 56 MODULE_LICENSE("GPL"); 57 MODULE_VERSION(DRV_MODULE_VERSION); 58 59 /* Time in jiffies before concluding the transmitter is hung. */ 60 #define TX_TIMEOUT (5 * HZ) 61 62 #define ENA_NAPI_BUDGET 64 63 64 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | \ 65 NETIF_MSG_TX_DONE | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR) 66 static int debug = -1; 67 module_param(debug, int, 0); 68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 69 70 static struct ena_aenq_handlers aenq_handlers; 71 72 static struct workqueue_struct *ena_wq; 73 74 MODULE_DEVICE_TABLE(pci, ena_pci_tbl); 75 76 static int ena_rss_init_default(struct ena_adapter *adapter); 77 static void check_for_admin_com_state(struct ena_adapter *adapter); 78 static void ena_destroy_device(struct ena_adapter *adapter, bool graceful); 79 static int ena_restore_device(struct ena_adapter *adapter); 80 81 static void ena_tx_timeout(struct net_device *dev) 82 { 83 struct ena_adapter *adapter = netdev_priv(dev); 84 85 /* Change the state of the device to trigger reset 86 * Check that we are not in the middle or a trigger already 87 */ 88 89 if (test_and_set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags)) 90 return; 91 92 adapter->reset_reason = ENA_REGS_RESET_OS_NETDEV_WD; 93 u64_stats_update_begin(&adapter->syncp); 94 adapter->dev_stats.tx_timeout++; 95 u64_stats_update_end(&adapter->syncp); 96 97 netif_err(adapter, tx_err, dev, "Transmit time out\n"); 98 } 99 100 static void update_rx_ring_mtu(struct ena_adapter *adapter, int mtu) 101 { 102 int i; 103 104 for (i = 0; i < adapter->num_queues; i++) 105 adapter->rx_ring[i].mtu = mtu; 106 } 107 108 static int ena_change_mtu(struct net_device *dev, int new_mtu) 109 { 110 struct ena_adapter *adapter = netdev_priv(dev); 111 int ret; 112 113 ret = ena_com_set_dev_mtu(adapter->ena_dev, new_mtu); 114 if (!ret) { 115 netif_dbg(adapter, drv, dev, "set MTU to %d\n", new_mtu); 116 update_rx_ring_mtu(adapter, new_mtu); 117 dev->mtu = new_mtu; 118 } else { 119 netif_err(adapter, drv, dev, "Failed to set MTU to %d\n", 120 new_mtu); 121 } 122 123 return ret; 124 } 125 126 static int ena_init_rx_cpu_rmap(struct ena_adapter *adapter) 127 { 128 #ifdef CONFIG_RFS_ACCEL 129 u32 i; 130 int rc; 131 132 adapter->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(adapter->num_queues); 133 if (!adapter->netdev->rx_cpu_rmap) 134 return -ENOMEM; 135 for (i = 0; i < adapter->num_queues; i++) { 136 int irq_idx = ENA_IO_IRQ_IDX(i); 137 138 rc = irq_cpu_rmap_add(adapter->netdev->rx_cpu_rmap, 139 pci_irq_vector(adapter->pdev, irq_idx)); 140 if (rc) { 141 free_irq_cpu_rmap(adapter->netdev->rx_cpu_rmap); 142 adapter->netdev->rx_cpu_rmap = NULL; 143 return rc; 144 } 145 } 146 #endif /* CONFIG_RFS_ACCEL */ 147 return 0; 148 } 149 150 static void ena_init_io_rings_common(struct ena_adapter *adapter, 151 struct ena_ring *ring, u16 qid) 152 { 153 ring->qid = qid; 154 ring->pdev = adapter->pdev; 155 ring->dev = &adapter->pdev->dev; 156 ring->netdev = adapter->netdev; 157 ring->napi = &adapter->ena_napi[qid].napi; 158 ring->adapter = adapter; 159 ring->ena_dev = adapter->ena_dev; 160 ring->per_napi_packets = 0; 161 ring->per_napi_bytes = 0; 162 ring->cpu = 0; 163 ring->first_interrupt = false; 164 ring->no_interrupt_event_cnt = 0; 165 u64_stats_init(&ring->syncp); 166 } 167 168 static void ena_init_io_rings(struct ena_adapter *adapter) 169 { 170 struct ena_com_dev *ena_dev; 171 struct ena_ring *txr, *rxr; 172 int i; 173 174 ena_dev = adapter->ena_dev; 175 176 for (i = 0; i < adapter->num_queues; i++) { 177 txr = &adapter->tx_ring[i]; 178 rxr = &adapter->rx_ring[i]; 179 180 /* TX/RX common ring state */ 181 ena_init_io_rings_common(adapter, txr, i); 182 ena_init_io_rings_common(adapter, rxr, i); 183 184 /* TX specific ring state */ 185 txr->ring_size = adapter->tx_ring_size; 186 txr->tx_max_header_size = ena_dev->tx_max_header_size; 187 txr->tx_mem_queue_type = ena_dev->tx_mem_queue_type; 188 txr->sgl_size = adapter->max_tx_sgl_size; 189 txr->smoothed_interval = 190 ena_com_get_nonadaptive_moderation_interval_tx(ena_dev); 191 192 /* RX specific ring state */ 193 rxr->ring_size = adapter->rx_ring_size; 194 rxr->rx_copybreak = adapter->rx_copybreak; 195 rxr->sgl_size = adapter->max_rx_sgl_size; 196 rxr->smoothed_interval = 197 ena_com_get_nonadaptive_moderation_interval_rx(ena_dev); 198 rxr->empty_rx_queue = 0; 199 } 200 } 201 202 /* ena_setup_tx_resources - allocate I/O Tx resources (Descriptors) 203 * @adapter: network interface device structure 204 * @qid: queue index 205 * 206 * Return 0 on success, negative on failure 207 */ 208 static int ena_setup_tx_resources(struct ena_adapter *adapter, int qid) 209 { 210 struct ena_ring *tx_ring = &adapter->tx_ring[qid]; 211 struct ena_irq *ena_irq = &adapter->irq_tbl[ENA_IO_IRQ_IDX(qid)]; 212 int size, i, node; 213 214 if (tx_ring->tx_buffer_info) { 215 netif_err(adapter, ifup, 216 adapter->netdev, "tx_buffer_info info is not NULL"); 217 return -EEXIST; 218 } 219 220 size = sizeof(struct ena_tx_buffer) * tx_ring->ring_size; 221 node = cpu_to_node(ena_irq->cpu); 222 223 tx_ring->tx_buffer_info = vzalloc_node(size, node); 224 if (!tx_ring->tx_buffer_info) { 225 tx_ring->tx_buffer_info = vzalloc(size); 226 if (!tx_ring->tx_buffer_info) 227 goto err_tx_buffer_info; 228 } 229 230 size = sizeof(u16) * tx_ring->ring_size; 231 tx_ring->free_ids = vzalloc_node(size, node); 232 if (!tx_ring->free_ids) { 233 tx_ring->free_ids = vzalloc(size); 234 if (!tx_ring->free_ids) 235 goto err_tx_free_ids; 236 } 237 238 size = tx_ring->tx_max_header_size; 239 tx_ring->push_buf_intermediate_buf = vzalloc_node(size, node); 240 if (!tx_ring->push_buf_intermediate_buf) { 241 tx_ring->push_buf_intermediate_buf = vzalloc(size); 242 if (!tx_ring->push_buf_intermediate_buf) 243 goto err_push_buf_intermediate_buf; 244 } 245 246 /* Req id ring for TX out of order completions */ 247 for (i = 0; i < tx_ring->ring_size; i++) 248 tx_ring->free_ids[i] = i; 249 250 /* Reset tx statistics */ 251 memset(&tx_ring->tx_stats, 0x0, sizeof(tx_ring->tx_stats)); 252 253 tx_ring->next_to_use = 0; 254 tx_ring->next_to_clean = 0; 255 tx_ring->cpu = ena_irq->cpu; 256 return 0; 257 258 err_push_buf_intermediate_buf: 259 vfree(tx_ring->free_ids); 260 tx_ring->free_ids = NULL; 261 err_tx_free_ids: 262 vfree(tx_ring->tx_buffer_info); 263 tx_ring->tx_buffer_info = NULL; 264 err_tx_buffer_info: 265 return -ENOMEM; 266 } 267 268 /* ena_free_tx_resources - Free I/O Tx Resources per Queue 269 * @adapter: network interface device structure 270 * @qid: queue index 271 * 272 * Free all transmit software resources 273 */ 274 static void ena_free_tx_resources(struct ena_adapter *adapter, int qid) 275 { 276 struct ena_ring *tx_ring = &adapter->tx_ring[qid]; 277 278 vfree(tx_ring->tx_buffer_info); 279 tx_ring->tx_buffer_info = NULL; 280 281 vfree(tx_ring->free_ids); 282 tx_ring->free_ids = NULL; 283 284 vfree(tx_ring->push_buf_intermediate_buf); 285 tx_ring->push_buf_intermediate_buf = NULL; 286 } 287 288 /* ena_setup_all_tx_resources - allocate I/O Tx queues resources for All queues 289 * @adapter: private structure 290 * 291 * Return 0 on success, negative on failure 292 */ 293 static int ena_setup_all_tx_resources(struct ena_adapter *adapter) 294 { 295 int i, rc = 0; 296 297 for (i = 0; i < adapter->num_queues; i++) { 298 rc = ena_setup_tx_resources(adapter, i); 299 if (rc) 300 goto err_setup_tx; 301 } 302 303 return 0; 304 305 err_setup_tx: 306 307 netif_err(adapter, ifup, adapter->netdev, 308 "Tx queue %d: allocation failed\n", i); 309 310 /* rewind the index freeing the rings as we go */ 311 while (i--) 312 ena_free_tx_resources(adapter, i); 313 return rc; 314 } 315 316 /* ena_free_all_io_tx_resources - Free I/O Tx Resources for All Queues 317 * @adapter: board private structure 318 * 319 * Free all transmit software resources 320 */ 321 static void ena_free_all_io_tx_resources(struct ena_adapter *adapter) 322 { 323 int i; 324 325 for (i = 0; i < adapter->num_queues; i++) 326 ena_free_tx_resources(adapter, i); 327 } 328 329 static inline int validate_rx_req_id(struct ena_ring *rx_ring, u16 req_id) 330 { 331 if (likely(req_id < rx_ring->ring_size)) 332 return 0; 333 334 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev, 335 "Invalid rx req_id: %hu\n", req_id); 336 337 u64_stats_update_begin(&rx_ring->syncp); 338 rx_ring->rx_stats.bad_req_id++; 339 u64_stats_update_end(&rx_ring->syncp); 340 341 /* Trigger device reset */ 342 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; 343 set_bit(ENA_FLAG_TRIGGER_RESET, &rx_ring->adapter->flags); 344 return -EFAULT; 345 } 346 347 /* ena_setup_rx_resources - allocate I/O Rx resources (Descriptors) 348 * @adapter: network interface device structure 349 * @qid: queue index 350 * 351 * Returns 0 on success, negative on failure 352 */ 353 static int ena_setup_rx_resources(struct ena_adapter *adapter, 354 u32 qid) 355 { 356 struct ena_ring *rx_ring = &adapter->rx_ring[qid]; 357 struct ena_irq *ena_irq = &adapter->irq_tbl[ENA_IO_IRQ_IDX(qid)]; 358 int size, node, i; 359 360 if (rx_ring->rx_buffer_info) { 361 netif_err(adapter, ifup, adapter->netdev, 362 "rx_buffer_info is not NULL"); 363 return -EEXIST; 364 } 365 366 /* alloc extra element so in rx path 367 * we can always prefetch rx_info + 1 368 */ 369 size = sizeof(struct ena_rx_buffer) * (rx_ring->ring_size + 1); 370 node = cpu_to_node(ena_irq->cpu); 371 372 rx_ring->rx_buffer_info = vzalloc_node(size, node); 373 if (!rx_ring->rx_buffer_info) { 374 rx_ring->rx_buffer_info = vzalloc(size); 375 if (!rx_ring->rx_buffer_info) 376 return -ENOMEM; 377 } 378 379 size = sizeof(u16) * rx_ring->ring_size; 380 rx_ring->free_ids = vzalloc_node(size, node); 381 if (!rx_ring->free_ids) { 382 rx_ring->free_ids = vzalloc(size); 383 if (!rx_ring->free_ids) { 384 vfree(rx_ring->rx_buffer_info); 385 rx_ring->rx_buffer_info = NULL; 386 return -ENOMEM; 387 } 388 } 389 390 /* Req id ring for receiving RX pkts out of order */ 391 for (i = 0; i < rx_ring->ring_size; i++) 392 rx_ring->free_ids[i] = i; 393 394 /* Reset rx statistics */ 395 memset(&rx_ring->rx_stats, 0x0, sizeof(rx_ring->rx_stats)); 396 397 rx_ring->next_to_clean = 0; 398 rx_ring->next_to_use = 0; 399 rx_ring->cpu = ena_irq->cpu; 400 401 return 0; 402 } 403 404 /* ena_free_rx_resources - Free I/O Rx Resources 405 * @adapter: network interface device structure 406 * @qid: queue index 407 * 408 * Free all receive software resources 409 */ 410 static void ena_free_rx_resources(struct ena_adapter *adapter, 411 u32 qid) 412 { 413 struct ena_ring *rx_ring = &adapter->rx_ring[qid]; 414 415 vfree(rx_ring->rx_buffer_info); 416 rx_ring->rx_buffer_info = NULL; 417 418 vfree(rx_ring->free_ids); 419 rx_ring->free_ids = NULL; 420 } 421 422 /* ena_setup_all_rx_resources - allocate I/O Rx queues resources for all queues 423 * @adapter: board private structure 424 * 425 * Return 0 on success, negative on failure 426 */ 427 static int ena_setup_all_rx_resources(struct ena_adapter *adapter) 428 { 429 int i, rc = 0; 430 431 for (i = 0; i < adapter->num_queues; i++) { 432 rc = ena_setup_rx_resources(adapter, i); 433 if (rc) 434 goto err_setup_rx; 435 } 436 437 return 0; 438 439 err_setup_rx: 440 441 netif_err(adapter, ifup, adapter->netdev, 442 "Rx queue %d: allocation failed\n", i); 443 444 /* rewind the index freeing the rings as we go */ 445 while (i--) 446 ena_free_rx_resources(adapter, i); 447 return rc; 448 } 449 450 /* ena_free_all_io_rx_resources - Free I/O Rx Resources for All Queues 451 * @adapter: board private structure 452 * 453 * Free all receive software resources 454 */ 455 static void ena_free_all_io_rx_resources(struct ena_adapter *adapter) 456 { 457 int i; 458 459 for (i = 0; i < adapter->num_queues; i++) 460 ena_free_rx_resources(adapter, i); 461 } 462 463 static inline int ena_alloc_rx_page(struct ena_ring *rx_ring, 464 struct ena_rx_buffer *rx_info, gfp_t gfp) 465 { 466 struct ena_com_buf *ena_buf; 467 struct page *page; 468 dma_addr_t dma; 469 470 /* if previous allocated page is not used */ 471 if (unlikely(rx_info->page)) 472 return 0; 473 474 page = alloc_page(gfp); 475 if (unlikely(!page)) { 476 u64_stats_update_begin(&rx_ring->syncp); 477 rx_ring->rx_stats.page_alloc_fail++; 478 u64_stats_update_end(&rx_ring->syncp); 479 return -ENOMEM; 480 } 481 482 dma = dma_map_page(rx_ring->dev, page, 0, ENA_PAGE_SIZE, 483 DMA_FROM_DEVICE); 484 if (unlikely(dma_mapping_error(rx_ring->dev, dma))) { 485 u64_stats_update_begin(&rx_ring->syncp); 486 rx_ring->rx_stats.dma_mapping_err++; 487 u64_stats_update_end(&rx_ring->syncp); 488 489 __free_page(page); 490 return -EIO; 491 } 492 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev, 493 "alloc page %p, rx_info %p\n", page, rx_info); 494 495 rx_info->page = page; 496 rx_info->page_offset = 0; 497 ena_buf = &rx_info->ena_buf; 498 ena_buf->paddr = dma; 499 ena_buf->len = ENA_PAGE_SIZE; 500 501 return 0; 502 } 503 504 static void ena_free_rx_page(struct ena_ring *rx_ring, 505 struct ena_rx_buffer *rx_info) 506 { 507 struct page *page = rx_info->page; 508 struct ena_com_buf *ena_buf = &rx_info->ena_buf; 509 510 if (unlikely(!page)) { 511 netif_warn(rx_ring->adapter, rx_err, rx_ring->netdev, 512 "Trying to free unallocated buffer\n"); 513 return; 514 } 515 516 dma_unmap_page(rx_ring->dev, ena_buf->paddr, ENA_PAGE_SIZE, 517 DMA_FROM_DEVICE); 518 519 __free_page(page); 520 rx_info->page = NULL; 521 } 522 523 static int ena_refill_rx_bufs(struct ena_ring *rx_ring, u32 num) 524 { 525 u16 next_to_use, req_id; 526 u32 i; 527 int rc; 528 529 next_to_use = rx_ring->next_to_use; 530 531 for (i = 0; i < num; i++) { 532 struct ena_rx_buffer *rx_info; 533 534 req_id = rx_ring->free_ids[next_to_use]; 535 rc = validate_rx_req_id(rx_ring, req_id); 536 if (unlikely(rc < 0)) 537 break; 538 539 rx_info = &rx_ring->rx_buffer_info[req_id]; 540 541 542 rc = ena_alloc_rx_page(rx_ring, rx_info, 543 GFP_ATOMIC | __GFP_COMP); 544 if (unlikely(rc < 0)) { 545 netif_warn(rx_ring->adapter, rx_err, rx_ring->netdev, 546 "failed to alloc buffer for rx queue %d\n", 547 rx_ring->qid); 548 break; 549 } 550 rc = ena_com_add_single_rx_desc(rx_ring->ena_com_io_sq, 551 &rx_info->ena_buf, 552 req_id); 553 if (unlikely(rc)) { 554 netif_warn(rx_ring->adapter, rx_status, rx_ring->netdev, 555 "failed to add buffer for rx queue %d\n", 556 rx_ring->qid); 557 break; 558 } 559 next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use, 560 rx_ring->ring_size); 561 } 562 563 if (unlikely(i < num)) { 564 u64_stats_update_begin(&rx_ring->syncp); 565 rx_ring->rx_stats.refil_partial++; 566 u64_stats_update_end(&rx_ring->syncp); 567 netdev_warn(rx_ring->netdev, 568 "refilled rx qid %d with only %d buffers (from %d)\n", 569 rx_ring->qid, i, num); 570 } 571 572 /* ena_com_write_sq_doorbell issues a wmb() */ 573 if (likely(i)) 574 ena_com_write_sq_doorbell(rx_ring->ena_com_io_sq); 575 576 rx_ring->next_to_use = next_to_use; 577 578 return i; 579 } 580 581 static void ena_free_rx_bufs(struct ena_adapter *adapter, 582 u32 qid) 583 { 584 struct ena_ring *rx_ring = &adapter->rx_ring[qid]; 585 u32 i; 586 587 for (i = 0; i < rx_ring->ring_size; i++) { 588 struct ena_rx_buffer *rx_info = &rx_ring->rx_buffer_info[i]; 589 590 if (rx_info->page) 591 ena_free_rx_page(rx_ring, rx_info); 592 } 593 } 594 595 /* ena_refill_all_rx_bufs - allocate all queues Rx buffers 596 * @adapter: board private structure 597 * 598 */ 599 static void ena_refill_all_rx_bufs(struct ena_adapter *adapter) 600 { 601 struct ena_ring *rx_ring; 602 int i, rc, bufs_num; 603 604 for (i = 0; i < adapter->num_queues; i++) { 605 rx_ring = &adapter->rx_ring[i]; 606 bufs_num = rx_ring->ring_size - 1; 607 rc = ena_refill_rx_bufs(rx_ring, bufs_num); 608 609 if (unlikely(rc != bufs_num)) 610 netif_warn(rx_ring->adapter, rx_status, rx_ring->netdev, 611 "refilling Queue %d failed. allocated %d buffers from: %d\n", 612 i, rc, bufs_num); 613 } 614 } 615 616 static void ena_free_all_rx_bufs(struct ena_adapter *adapter) 617 { 618 int i; 619 620 for (i = 0; i < adapter->num_queues; i++) 621 ena_free_rx_bufs(adapter, i); 622 } 623 624 static inline void ena_unmap_tx_skb(struct ena_ring *tx_ring, 625 struct ena_tx_buffer *tx_info) 626 { 627 struct ena_com_buf *ena_buf; 628 u32 cnt; 629 int i; 630 631 ena_buf = tx_info->bufs; 632 cnt = tx_info->num_of_bufs; 633 634 if (unlikely(!cnt)) 635 return; 636 637 if (tx_info->map_linear_data) { 638 dma_unmap_single(tx_ring->dev, 639 dma_unmap_addr(ena_buf, paddr), 640 dma_unmap_len(ena_buf, len), 641 DMA_TO_DEVICE); 642 ena_buf++; 643 cnt--; 644 } 645 646 /* unmap remaining mapped pages */ 647 for (i = 0; i < cnt; i++) { 648 dma_unmap_page(tx_ring->dev, dma_unmap_addr(ena_buf, paddr), 649 dma_unmap_len(ena_buf, len), DMA_TO_DEVICE); 650 ena_buf++; 651 } 652 } 653 654 /* ena_free_tx_bufs - Free Tx Buffers per Queue 655 * @tx_ring: TX ring for which buffers be freed 656 */ 657 static void ena_free_tx_bufs(struct ena_ring *tx_ring) 658 { 659 bool print_once = true; 660 u32 i; 661 662 for (i = 0; i < tx_ring->ring_size; i++) { 663 struct ena_tx_buffer *tx_info = &tx_ring->tx_buffer_info[i]; 664 665 if (!tx_info->skb) 666 continue; 667 668 if (print_once) { 669 netdev_notice(tx_ring->netdev, 670 "free uncompleted tx skb qid %d idx 0x%x\n", 671 tx_ring->qid, i); 672 print_once = false; 673 } else { 674 netdev_dbg(tx_ring->netdev, 675 "free uncompleted tx skb qid %d idx 0x%x\n", 676 tx_ring->qid, i); 677 } 678 679 ena_unmap_tx_skb(tx_ring, tx_info); 680 681 dev_kfree_skb_any(tx_info->skb); 682 } 683 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev, 684 tx_ring->qid)); 685 } 686 687 static void ena_free_all_tx_bufs(struct ena_adapter *adapter) 688 { 689 struct ena_ring *tx_ring; 690 int i; 691 692 for (i = 0; i < adapter->num_queues; i++) { 693 tx_ring = &adapter->tx_ring[i]; 694 ena_free_tx_bufs(tx_ring); 695 } 696 } 697 698 static void ena_destroy_all_tx_queues(struct ena_adapter *adapter) 699 { 700 u16 ena_qid; 701 int i; 702 703 for (i = 0; i < adapter->num_queues; i++) { 704 ena_qid = ENA_IO_TXQ_IDX(i); 705 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid); 706 } 707 } 708 709 static void ena_destroy_all_rx_queues(struct ena_adapter *adapter) 710 { 711 u16 ena_qid; 712 int i; 713 714 for (i = 0; i < adapter->num_queues; i++) { 715 ena_qid = ENA_IO_RXQ_IDX(i); 716 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid); 717 } 718 } 719 720 static void ena_destroy_all_io_queues(struct ena_adapter *adapter) 721 { 722 ena_destroy_all_tx_queues(adapter); 723 ena_destroy_all_rx_queues(adapter); 724 } 725 726 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id) 727 { 728 struct ena_tx_buffer *tx_info = NULL; 729 730 if (likely(req_id < tx_ring->ring_size)) { 731 tx_info = &tx_ring->tx_buffer_info[req_id]; 732 if (likely(tx_info->skb)) 733 return 0; 734 } 735 736 if (tx_info) 737 netif_err(tx_ring->adapter, tx_done, tx_ring->netdev, 738 "tx_info doesn't have valid skb\n"); 739 else 740 netif_err(tx_ring->adapter, tx_done, tx_ring->netdev, 741 "Invalid req_id: %hu\n", req_id); 742 743 u64_stats_update_begin(&tx_ring->syncp); 744 tx_ring->tx_stats.bad_req_id++; 745 u64_stats_update_end(&tx_ring->syncp); 746 747 /* Trigger device reset */ 748 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID; 749 set_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags); 750 return -EFAULT; 751 } 752 753 static int ena_clean_tx_irq(struct ena_ring *tx_ring, u32 budget) 754 { 755 struct netdev_queue *txq; 756 bool above_thresh; 757 u32 tx_bytes = 0; 758 u32 total_done = 0; 759 u16 next_to_clean; 760 u16 req_id; 761 int tx_pkts = 0; 762 int rc; 763 764 next_to_clean = tx_ring->next_to_clean; 765 txq = netdev_get_tx_queue(tx_ring->netdev, tx_ring->qid); 766 767 while (tx_pkts < budget) { 768 struct ena_tx_buffer *tx_info; 769 struct sk_buff *skb; 770 771 rc = ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, 772 &req_id); 773 if (rc) 774 break; 775 776 rc = validate_tx_req_id(tx_ring, req_id); 777 if (rc) 778 break; 779 780 tx_info = &tx_ring->tx_buffer_info[req_id]; 781 skb = tx_info->skb; 782 783 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */ 784 prefetch(&skb->end); 785 786 tx_info->skb = NULL; 787 tx_info->last_jiffies = 0; 788 789 ena_unmap_tx_skb(tx_ring, tx_info); 790 791 netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev, 792 "tx_poll: q %d skb %p completed\n", tx_ring->qid, 793 skb); 794 795 tx_bytes += skb->len; 796 dev_kfree_skb(skb); 797 tx_pkts++; 798 total_done += tx_info->tx_descs; 799 800 tx_ring->free_ids[next_to_clean] = req_id; 801 next_to_clean = ENA_TX_RING_IDX_NEXT(next_to_clean, 802 tx_ring->ring_size); 803 } 804 805 tx_ring->next_to_clean = next_to_clean; 806 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_done); 807 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq); 808 809 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes); 810 811 netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev, 812 "tx_poll: q %d done. total pkts: %d\n", 813 tx_ring->qid, tx_pkts); 814 815 /* need to make the rings circular update visible to 816 * ena_start_xmit() before checking for netif_queue_stopped(). 817 */ 818 smp_mb(); 819 820 above_thresh = ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 821 ENA_TX_WAKEUP_THRESH); 822 if (unlikely(netif_tx_queue_stopped(txq) && above_thresh)) { 823 __netif_tx_lock(txq, smp_processor_id()); 824 above_thresh = 825 ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 826 ENA_TX_WAKEUP_THRESH); 827 if (netif_tx_queue_stopped(txq) && above_thresh) { 828 netif_tx_wake_queue(txq); 829 u64_stats_update_begin(&tx_ring->syncp); 830 tx_ring->tx_stats.queue_wakeup++; 831 u64_stats_update_end(&tx_ring->syncp); 832 } 833 __netif_tx_unlock(txq); 834 } 835 836 tx_ring->per_napi_bytes += tx_bytes; 837 tx_ring->per_napi_packets += tx_pkts; 838 839 return tx_pkts; 840 } 841 842 static struct sk_buff *ena_alloc_skb(struct ena_ring *rx_ring, bool frags) 843 { 844 struct sk_buff *skb; 845 846 if (frags) 847 skb = napi_get_frags(rx_ring->napi); 848 else 849 skb = netdev_alloc_skb_ip_align(rx_ring->netdev, 850 rx_ring->rx_copybreak); 851 852 if (unlikely(!skb)) { 853 u64_stats_update_begin(&rx_ring->syncp); 854 rx_ring->rx_stats.skb_alloc_fail++; 855 u64_stats_update_end(&rx_ring->syncp); 856 netif_dbg(rx_ring->adapter, rx_err, rx_ring->netdev, 857 "Failed to allocate skb. frags: %d\n", frags); 858 return NULL; 859 } 860 861 return skb; 862 } 863 864 static struct sk_buff *ena_rx_skb(struct ena_ring *rx_ring, 865 struct ena_com_rx_buf_info *ena_bufs, 866 u32 descs, 867 u16 *next_to_clean) 868 { 869 struct sk_buff *skb; 870 struct ena_rx_buffer *rx_info; 871 u16 len, req_id, buf = 0; 872 void *va; 873 874 len = ena_bufs[buf].len; 875 req_id = ena_bufs[buf].req_id; 876 rx_info = &rx_ring->rx_buffer_info[req_id]; 877 878 if (unlikely(!rx_info->page)) { 879 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev, 880 "Page is NULL\n"); 881 return NULL; 882 } 883 884 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev, 885 "rx_info %p page %p\n", 886 rx_info, rx_info->page); 887 888 /* save virt address of first buffer */ 889 va = page_address(rx_info->page) + rx_info->page_offset; 890 prefetch(va + NET_IP_ALIGN); 891 892 if (len <= rx_ring->rx_copybreak) { 893 skb = ena_alloc_skb(rx_ring, false); 894 if (unlikely(!skb)) 895 return NULL; 896 897 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev, 898 "rx allocated small packet. len %d. data_len %d\n", 899 skb->len, skb->data_len); 900 901 /* sync this buffer for CPU use */ 902 dma_sync_single_for_cpu(rx_ring->dev, 903 dma_unmap_addr(&rx_info->ena_buf, paddr), 904 len, 905 DMA_FROM_DEVICE); 906 skb_copy_to_linear_data(skb, va, len); 907 dma_sync_single_for_device(rx_ring->dev, 908 dma_unmap_addr(&rx_info->ena_buf, paddr), 909 len, 910 DMA_FROM_DEVICE); 911 912 skb_put(skb, len); 913 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 914 rx_ring->free_ids[*next_to_clean] = req_id; 915 *next_to_clean = ENA_RX_RING_IDX_ADD(*next_to_clean, descs, 916 rx_ring->ring_size); 917 return skb; 918 } 919 920 skb = ena_alloc_skb(rx_ring, true); 921 if (unlikely(!skb)) 922 return NULL; 923 924 do { 925 dma_unmap_page(rx_ring->dev, 926 dma_unmap_addr(&rx_info->ena_buf, paddr), 927 ENA_PAGE_SIZE, DMA_FROM_DEVICE); 928 929 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_info->page, 930 rx_info->page_offset, len, ENA_PAGE_SIZE); 931 932 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev, 933 "rx skb updated. len %d. data_len %d\n", 934 skb->len, skb->data_len); 935 936 rx_info->page = NULL; 937 938 rx_ring->free_ids[*next_to_clean] = req_id; 939 *next_to_clean = 940 ENA_RX_RING_IDX_NEXT(*next_to_clean, 941 rx_ring->ring_size); 942 if (likely(--descs == 0)) 943 break; 944 945 buf++; 946 len = ena_bufs[buf].len; 947 req_id = ena_bufs[buf].req_id; 948 rx_info = &rx_ring->rx_buffer_info[req_id]; 949 } while (1); 950 951 return skb; 952 } 953 954 /* ena_rx_checksum - indicate in skb if hw indicated a good cksum 955 * @adapter: structure containing adapter specific data 956 * @ena_rx_ctx: received packet context/metadata 957 * @skb: skb currently being received and modified 958 */ 959 static inline void ena_rx_checksum(struct ena_ring *rx_ring, 960 struct ena_com_rx_ctx *ena_rx_ctx, 961 struct sk_buff *skb) 962 { 963 /* Rx csum disabled */ 964 if (unlikely(!(rx_ring->netdev->features & NETIF_F_RXCSUM))) { 965 skb->ip_summed = CHECKSUM_NONE; 966 return; 967 } 968 969 /* For fragmented packets the checksum isn't valid */ 970 if (ena_rx_ctx->frag) { 971 skb->ip_summed = CHECKSUM_NONE; 972 return; 973 } 974 975 /* if IP and error */ 976 if (unlikely((ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) && 977 (ena_rx_ctx->l3_csum_err))) { 978 /* ipv4 checksum error */ 979 skb->ip_summed = CHECKSUM_NONE; 980 u64_stats_update_begin(&rx_ring->syncp); 981 rx_ring->rx_stats.bad_csum++; 982 u64_stats_update_end(&rx_ring->syncp); 983 netif_dbg(rx_ring->adapter, rx_err, rx_ring->netdev, 984 "RX IPv4 header checksum error\n"); 985 return; 986 } 987 988 /* if TCP/UDP */ 989 if (likely((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) || 990 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP))) { 991 if (unlikely(ena_rx_ctx->l4_csum_err)) { 992 /* TCP/UDP checksum error */ 993 u64_stats_update_begin(&rx_ring->syncp); 994 rx_ring->rx_stats.bad_csum++; 995 u64_stats_update_end(&rx_ring->syncp); 996 netif_dbg(rx_ring->adapter, rx_err, rx_ring->netdev, 997 "RX L4 checksum error\n"); 998 skb->ip_summed = CHECKSUM_NONE; 999 return; 1000 } 1001 1002 if (likely(ena_rx_ctx->l4_csum_checked)) { 1003 skb->ip_summed = CHECKSUM_UNNECESSARY; 1004 u64_stats_update_begin(&rx_ring->syncp); 1005 rx_ring->rx_stats.csum_good++; 1006 u64_stats_update_end(&rx_ring->syncp); 1007 } else { 1008 u64_stats_update_begin(&rx_ring->syncp); 1009 rx_ring->rx_stats.csum_unchecked++; 1010 u64_stats_update_end(&rx_ring->syncp); 1011 skb->ip_summed = CHECKSUM_NONE; 1012 } 1013 } else { 1014 skb->ip_summed = CHECKSUM_NONE; 1015 return; 1016 } 1017 1018 } 1019 1020 static void ena_set_rx_hash(struct ena_ring *rx_ring, 1021 struct ena_com_rx_ctx *ena_rx_ctx, 1022 struct sk_buff *skb) 1023 { 1024 enum pkt_hash_types hash_type; 1025 1026 if (likely(rx_ring->netdev->features & NETIF_F_RXHASH)) { 1027 if (likely((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) || 1028 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP))) 1029 1030 hash_type = PKT_HASH_TYPE_L4; 1031 else 1032 hash_type = PKT_HASH_TYPE_NONE; 1033 1034 /* Override hash type if the packet is fragmented */ 1035 if (ena_rx_ctx->frag) 1036 hash_type = PKT_HASH_TYPE_NONE; 1037 1038 skb_set_hash(skb, ena_rx_ctx->hash, hash_type); 1039 } 1040 } 1041 1042 /* ena_clean_rx_irq - Cleanup RX irq 1043 * @rx_ring: RX ring to clean 1044 * @napi: napi handler 1045 * @budget: how many packets driver is allowed to clean 1046 * 1047 * Returns the number of cleaned buffers. 1048 */ 1049 static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi, 1050 u32 budget) 1051 { 1052 u16 next_to_clean = rx_ring->next_to_clean; 1053 u32 res_budget, work_done; 1054 1055 struct ena_com_rx_ctx ena_rx_ctx; 1056 struct ena_adapter *adapter; 1057 struct sk_buff *skb; 1058 int refill_required; 1059 int refill_threshold; 1060 int rc = 0; 1061 int total_len = 0; 1062 int rx_copybreak_pkt = 0; 1063 int i; 1064 1065 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev, 1066 "%s qid %d\n", __func__, rx_ring->qid); 1067 res_budget = budget; 1068 1069 do { 1070 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 1071 ena_rx_ctx.max_bufs = rx_ring->sgl_size; 1072 ena_rx_ctx.descs = 0; 1073 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq, 1074 rx_ring->ena_com_io_sq, 1075 &ena_rx_ctx); 1076 if (unlikely(rc)) 1077 goto error; 1078 1079 if (unlikely(ena_rx_ctx.descs == 0)) 1080 break; 1081 1082 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev, 1083 "rx_poll: q %d got packet from ena. descs #: %d l3 proto %d l4 proto %d hash: %x\n", 1084 rx_ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto, 1085 ena_rx_ctx.l4_proto, ena_rx_ctx.hash); 1086 1087 /* allocate skb and fill it */ 1088 skb = ena_rx_skb(rx_ring, rx_ring->ena_bufs, ena_rx_ctx.descs, 1089 &next_to_clean); 1090 1091 /* exit if we failed to retrieve a buffer */ 1092 if (unlikely(!skb)) { 1093 for (i = 0; i < ena_rx_ctx.descs; i++) { 1094 rx_ring->free_ids[next_to_clean] = 1095 rx_ring->ena_bufs[i].req_id; 1096 next_to_clean = 1097 ENA_RX_RING_IDX_NEXT(next_to_clean, 1098 rx_ring->ring_size); 1099 } 1100 break; 1101 } 1102 1103 ena_rx_checksum(rx_ring, &ena_rx_ctx, skb); 1104 1105 ena_set_rx_hash(rx_ring, &ena_rx_ctx, skb); 1106 1107 skb_record_rx_queue(skb, rx_ring->qid); 1108 1109 if (rx_ring->ena_bufs[0].len <= rx_ring->rx_copybreak) { 1110 total_len += rx_ring->ena_bufs[0].len; 1111 rx_copybreak_pkt++; 1112 napi_gro_receive(napi, skb); 1113 } else { 1114 total_len += skb->len; 1115 napi_gro_frags(napi); 1116 } 1117 1118 res_budget--; 1119 } while (likely(res_budget)); 1120 1121 work_done = budget - res_budget; 1122 rx_ring->per_napi_bytes += total_len; 1123 rx_ring->per_napi_packets += work_done; 1124 u64_stats_update_begin(&rx_ring->syncp); 1125 rx_ring->rx_stats.bytes += total_len; 1126 rx_ring->rx_stats.cnt += work_done; 1127 rx_ring->rx_stats.rx_copybreak_pkt += rx_copybreak_pkt; 1128 u64_stats_update_end(&rx_ring->syncp); 1129 1130 rx_ring->next_to_clean = next_to_clean; 1131 1132 refill_required = ena_com_free_desc(rx_ring->ena_com_io_sq); 1133 refill_threshold = 1134 min_t(int, rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER, 1135 ENA_RX_REFILL_THRESH_PACKET); 1136 1137 /* Optimization, try to batch new rx buffers */ 1138 if (refill_required > refill_threshold) { 1139 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 1140 ena_refill_rx_bufs(rx_ring, refill_required); 1141 } 1142 1143 return work_done; 1144 1145 error: 1146 adapter = netdev_priv(rx_ring->netdev); 1147 1148 u64_stats_update_begin(&rx_ring->syncp); 1149 rx_ring->rx_stats.bad_desc_num++; 1150 u64_stats_update_end(&rx_ring->syncp); 1151 1152 /* Too many desc from the device. Trigger reset */ 1153 adapter->reset_reason = ENA_REGS_RESET_TOO_MANY_RX_DESCS; 1154 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags); 1155 1156 return 0; 1157 } 1158 1159 inline void ena_adjust_intr_moderation(struct ena_ring *rx_ring, 1160 struct ena_ring *tx_ring) 1161 { 1162 /* We apply adaptive moderation on Rx path only. 1163 * Tx uses static interrupt moderation. 1164 */ 1165 ena_com_calculate_interrupt_delay(rx_ring->ena_dev, 1166 rx_ring->per_napi_packets, 1167 rx_ring->per_napi_bytes, 1168 &rx_ring->smoothed_interval, 1169 &rx_ring->moder_tbl_idx); 1170 1171 /* Reset per napi packets/bytes */ 1172 tx_ring->per_napi_packets = 0; 1173 tx_ring->per_napi_bytes = 0; 1174 rx_ring->per_napi_packets = 0; 1175 rx_ring->per_napi_bytes = 0; 1176 } 1177 1178 static inline void ena_unmask_interrupt(struct ena_ring *tx_ring, 1179 struct ena_ring *rx_ring) 1180 { 1181 struct ena_eth_io_intr_reg intr_reg; 1182 1183 /* Update intr register: rx intr delay, 1184 * tx intr delay and interrupt unmask 1185 */ 1186 ena_com_update_intr_reg(&intr_reg, 1187 rx_ring->smoothed_interval, 1188 tx_ring->smoothed_interval, 1189 true); 1190 1191 /* It is a shared MSI-X. 1192 * Tx and Rx CQ have pointer to it. 1193 * So we use one of them to reach the intr reg 1194 */ 1195 ena_com_unmask_intr(rx_ring->ena_com_io_cq, &intr_reg); 1196 } 1197 1198 static inline void ena_update_ring_numa_node(struct ena_ring *tx_ring, 1199 struct ena_ring *rx_ring) 1200 { 1201 int cpu = get_cpu(); 1202 int numa_node; 1203 1204 /* Check only one ring since the 2 rings are running on the same cpu */ 1205 if (likely(tx_ring->cpu == cpu)) 1206 goto out; 1207 1208 numa_node = cpu_to_node(cpu); 1209 put_cpu(); 1210 1211 if (numa_node != NUMA_NO_NODE) { 1212 ena_com_update_numa_node(tx_ring->ena_com_io_cq, numa_node); 1213 ena_com_update_numa_node(rx_ring->ena_com_io_cq, numa_node); 1214 } 1215 1216 tx_ring->cpu = cpu; 1217 rx_ring->cpu = cpu; 1218 1219 return; 1220 out: 1221 put_cpu(); 1222 } 1223 1224 static int ena_io_poll(struct napi_struct *napi, int budget) 1225 { 1226 struct ena_napi *ena_napi = container_of(napi, struct ena_napi, napi); 1227 struct ena_ring *tx_ring, *rx_ring; 1228 1229 u32 tx_work_done; 1230 u32 rx_work_done; 1231 int tx_budget; 1232 int napi_comp_call = 0; 1233 int ret; 1234 1235 tx_ring = ena_napi->tx_ring; 1236 rx_ring = ena_napi->rx_ring; 1237 1238 tx_budget = tx_ring->ring_size / ENA_TX_POLL_BUDGET_DIVIDER; 1239 1240 if (!test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags) || 1241 test_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags)) { 1242 napi_complete_done(napi, 0); 1243 return 0; 1244 } 1245 1246 tx_work_done = ena_clean_tx_irq(tx_ring, tx_budget); 1247 rx_work_done = ena_clean_rx_irq(rx_ring, napi, budget); 1248 1249 /* If the device is about to reset or down, avoid unmask 1250 * the interrupt and return 0 so NAPI won't reschedule 1251 */ 1252 if (unlikely(!test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags) || 1253 test_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags))) { 1254 napi_complete_done(napi, 0); 1255 ret = 0; 1256 1257 } else if ((budget > rx_work_done) && (tx_budget > tx_work_done)) { 1258 napi_comp_call = 1; 1259 1260 /* Update numa and unmask the interrupt only when schedule 1261 * from the interrupt context (vs from sk_busy_loop) 1262 */ 1263 if (napi_complete_done(napi, rx_work_done)) { 1264 /* Tx and Rx share the same interrupt vector */ 1265 if (ena_com_get_adaptive_moderation_enabled(rx_ring->ena_dev)) 1266 ena_adjust_intr_moderation(rx_ring, tx_ring); 1267 1268 ena_unmask_interrupt(tx_ring, rx_ring); 1269 } 1270 1271 ena_update_ring_numa_node(tx_ring, rx_ring); 1272 1273 ret = rx_work_done; 1274 } else { 1275 ret = budget; 1276 } 1277 1278 u64_stats_update_begin(&tx_ring->syncp); 1279 tx_ring->tx_stats.napi_comp += napi_comp_call; 1280 tx_ring->tx_stats.tx_poll++; 1281 u64_stats_update_end(&tx_ring->syncp); 1282 1283 return ret; 1284 } 1285 1286 static irqreturn_t ena_intr_msix_mgmnt(int irq, void *data) 1287 { 1288 struct ena_adapter *adapter = (struct ena_adapter *)data; 1289 1290 ena_com_admin_q_comp_intr_handler(adapter->ena_dev); 1291 1292 /* Don't call the aenq handler before probe is done */ 1293 if (likely(test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags))) 1294 ena_com_aenq_intr_handler(adapter->ena_dev, data); 1295 1296 return IRQ_HANDLED; 1297 } 1298 1299 /* ena_intr_msix_io - MSI-X Interrupt Handler for Tx/Rx 1300 * @irq: interrupt number 1301 * @data: pointer to a network interface private napi device structure 1302 */ 1303 static irqreturn_t ena_intr_msix_io(int irq, void *data) 1304 { 1305 struct ena_napi *ena_napi = data; 1306 1307 ena_napi->tx_ring->first_interrupt = true; 1308 ena_napi->rx_ring->first_interrupt = true; 1309 1310 napi_schedule_irqoff(&ena_napi->napi); 1311 1312 return IRQ_HANDLED; 1313 } 1314 1315 /* Reserve a single MSI-X vector for management (admin + aenq). 1316 * plus reserve one vector for each potential io queue. 1317 * the number of potential io queues is the minimum of what the device 1318 * supports and the number of vCPUs. 1319 */ 1320 static int ena_enable_msix(struct ena_adapter *adapter, int num_queues) 1321 { 1322 int msix_vecs, irq_cnt; 1323 1324 if (test_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags)) { 1325 netif_err(adapter, probe, adapter->netdev, 1326 "Error, MSI-X is already enabled\n"); 1327 return -EPERM; 1328 } 1329 1330 /* Reserved the max msix vectors we might need */ 1331 msix_vecs = ENA_MAX_MSIX_VEC(num_queues); 1332 netif_dbg(adapter, probe, adapter->netdev, 1333 "trying to enable MSI-X, vectors %d\n", msix_vecs); 1334 1335 irq_cnt = pci_alloc_irq_vectors(adapter->pdev, ENA_MIN_MSIX_VEC, 1336 msix_vecs, PCI_IRQ_MSIX); 1337 1338 if (irq_cnt < 0) { 1339 netif_err(adapter, probe, adapter->netdev, 1340 "Failed to enable MSI-X. irq_cnt %d\n", irq_cnt); 1341 return -ENOSPC; 1342 } 1343 1344 if (irq_cnt != msix_vecs) { 1345 netif_notice(adapter, probe, adapter->netdev, 1346 "enable only %d MSI-X (out of %d), reduce the number of queues\n", 1347 irq_cnt, msix_vecs); 1348 adapter->num_queues = irq_cnt - ENA_ADMIN_MSIX_VEC; 1349 } 1350 1351 if (ena_init_rx_cpu_rmap(adapter)) 1352 netif_warn(adapter, probe, adapter->netdev, 1353 "Failed to map IRQs to CPUs\n"); 1354 1355 adapter->msix_vecs = irq_cnt; 1356 set_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags); 1357 1358 return 0; 1359 } 1360 1361 static void ena_setup_mgmnt_intr(struct ena_adapter *adapter) 1362 { 1363 u32 cpu; 1364 1365 snprintf(adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].name, 1366 ENA_IRQNAME_SIZE, "ena-mgmnt@pci:%s", 1367 pci_name(adapter->pdev)); 1368 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].handler = 1369 ena_intr_msix_mgmnt; 1370 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].data = adapter; 1371 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].vector = 1372 pci_irq_vector(adapter->pdev, ENA_MGMNT_IRQ_IDX); 1373 cpu = cpumask_first(cpu_online_mask); 1374 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].cpu = cpu; 1375 cpumask_set_cpu(cpu, 1376 &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].affinity_hint_mask); 1377 } 1378 1379 static void ena_setup_io_intr(struct ena_adapter *adapter) 1380 { 1381 struct net_device *netdev; 1382 int irq_idx, i, cpu; 1383 1384 netdev = adapter->netdev; 1385 1386 for (i = 0; i < adapter->num_queues; i++) { 1387 irq_idx = ENA_IO_IRQ_IDX(i); 1388 cpu = i % num_online_cpus(); 1389 1390 snprintf(adapter->irq_tbl[irq_idx].name, ENA_IRQNAME_SIZE, 1391 "%s-Tx-Rx-%d", netdev->name, i); 1392 adapter->irq_tbl[irq_idx].handler = ena_intr_msix_io; 1393 adapter->irq_tbl[irq_idx].data = &adapter->ena_napi[i]; 1394 adapter->irq_tbl[irq_idx].vector = 1395 pci_irq_vector(adapter->pdev, irq_idx); 1396 adapter->irq_tbl[irq_idx].cpu = cpu; 1397 1398 cpumask_set_cpu(cpu, 1399 &adapter->irq_tbl[irq_idx].affinity_hint_mask); 1400 } 1401 } 1402 1403 static int ena_request_mgmnt_irq(struct ena_adapter *adapter) 1404 { 1405 unsigned long flags = 0; 1406 struct ena_irq *irq; 1407 int rc; 1408 1409 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX]; 1410 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 1411 irq->data); 1412 if (rc) { 1413 netif_err(adapter, probe, adapter->netdev, 1414 "failed to request admin irq\n"); 1415 return rc; 1416 } 1417 1418 netif_dbg(adapter, probe, adapter->netdev, 1419 "set affinity hint of mgmnt irq.to 0x%lx (irq vector: %d)\n", 1420 irq->affinity_hint_mask.bits[0], irq->vector); 1421 1422 irq_set_affinity_hint(irq->vector, &irq->affinity_hint_mask); 1423 1424 return rc; 1425 } 1426 1427 static int ena_request_io_irq(struct ena_adapter *adapter) 1428 { 1429 unsigned long flags = 0; 1430 struct ena_irq *irq; 1431 int rc = 0, i, k; 1432 1433 if (!test_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags)) { 1434 netif_err(adapter, ifup, adapter->netdev, 1435 "Failed to request I/O IRQ: MSI-X is not enabled\n"); 1436 return -EINVAL; 1437 } 1438 1439 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) { 1440 irq = &adapter->irq_tbl[i]; 1441 rc = request_irq(irq->vector, irq->handler, flags, irq->name, 1442 irq->data); 1443 if (rc) { 1444 netif_err(adapter, ifup, adapter->netdev, 1445 "Failed to request I/O IRQ. index %d rc %d\n", 1446 i, rc); 1447 goto err; 1448 } 1449 1450 netif_dbg(adapter, ifup, adapter->netdev, 1451 "set affinity hint of irq. index %d to 0x%lx (irq vector: %d)\n", 1452 i, irq->affinity_hint_mask.bits[0], irq->vector); 1453 1454 irq_set_affinity_hint(irq->vector, &irq->affinity_hint_mask); 1455 } 1456 1457 return rc; 1458 1459 err: 1460 for (k = ENA_IO_IRQ_FIRST_IDX; k < i; k++) { 1461 irq = &adapter->irq_tbl[k]; 1462 free_irq(irq->vector, irq->data); 1463 } 1464 1465 return rc; 1466 } 1467 1468 static void ena_free_mgmnt_irq(struct ena_adapter *adapter) 1469 { 1470 struct ena_irq *irq; 1471 1472 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX]; 1473 synchronize_irq(irq->vector); 1474 irq_set_affinity_hint(irq->vector, NULL); 1475 free_irq(irq->vector, irq->data); 1476 } 1477 1478 static void ena_free_io_irq(struct ena_adapter *adapter) 1479 { 1480 struct ena_irq *irq; 1481 int i; 1482 1483 #ifdef CONFIG_RFS_ACCEL 1484 if (adapter->msix_vecs >= 1) { 1485 free_irq_cpu_rmap(adapter->netdev->rx_cpu_rmap); 1486 adapter->netdev->rx_cpu_rmap = NULL; 1487 } 1488 #endif /* CONFIG_RFS_ACCEL */ 1489 1490 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) { 1491 irq = &adapter->irq_tbl[i]; 1492 irq_set_affinity_hint(irq->vector, NULL); 1493 free_irq(irq->vector, irq->data); 1494 } 1495 } 1496 1497 static void ena_disable_msix(struct ena_adapter *adapter) 1498 { 1499 if (test_and_clear_bit(ENA_FLAG_MSIX_ENABLED, &adapter->flags)) 1500 pci_free_irq_vectors(adapter->pdev); 1501 } 1502 1503 static void ena_disable_io_intr_sync(struct ena_adapter *adapter) 1504 { 1505 int i; 1506 1507 if (!netif_running(adapter->netdev)) 1508 return; 1509 1510 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) 1511 synchronize_irq(adapter->irq_tbl[i].vector); 1512 } 1513 1514 static void ena_del_napi(struct ena_adapter *adapter) 1515 { 1516 int i; 1517 1518 for (i = 0; i < adapter->num_queues; i++) 1519 netif_napi_del(&adapter->ena_napi[i].napi); 1520 } 1521 1522 static void ena_init_napi(struct ena_adapter *adapter) 1523 { 1524 struct ena_napi *napi; 1525 int i; 1526 1527 for (i = 0; i < adapter->num_queues; i++) { 1528 napi = &adapter->ena_napi[i]; 1529 1530 netif_napi_add(adapter->netdev, 1531 &adapter->ena_napi[i].napi, 1532 ena_io_poll, 1533 ENA_NAPI_BUDGET); 1534 napi->rx_ring = &adapter->rx_ring[i]; 1535 napi->tx_ring = &adapter->tx_ring[i]; 1536 napi->qid = i; 1537 } 1538 } 1539 1540 static void ena_napi_disable_all(struct ena_adapter *adapter) 1541 { 1542 int i; 1543 1544 for (i = 0; i < adapter->num_queues; i++) 1545 napi_disable(&adapter->ena_napi[i].napi); 1546 } 1547 1548 static void ena_napi_enable_all(struct ena_adapter *adapter) 1549 { 1550 int i; 1551 1552 for (i = 0; i < adapter->num_queues; i++) 1553 napi_enable(&adapter->ena_napi[i].napi); 1554 } 1555 1556 static void ena_restore_ethtool_params(struct ena_adapter *adapter) 1557 { 1558 adapter->tx_usecs = 0; 1559 adapter->rx_usecs = 0; 1560 adapter->tx_frames = 1; 1561 adapter->rx_frames = 1; 1562 } 1563 1564 /* Configure the Rx forwarding */ 1565 static int ena_rss_configure(struct ena_adapter *adapter) 1566 { 1567 struct ena_com_dev *ena_dev = adapter->ena_dev; 1568 int rc; 1569 1570 /* In case the RSS table wasn't initialized by probe */ 1571 if (!ena_dev->rss.tbl_log_size) { 1572 rc = ena_rss_init_default(adapter); 1573 if (rc && (rc != -EOPNOTSUPP)) { 1574 netif_err(adapter, ifup, adapter->netdev, 1575 "Failed to init RSS rc: %d\n", rc); 1576 return rc; 1577 } 1578 } 1579 1580 /* Set indirect table */ 1581 rc = ena_com_indirect_table_set(ena_dev); 1582 if (unlikely(rc && rc != -EOPNOTSUPP)) 1583 return rc; 1584 1585 /* Configure hash function (if supported) */ 1586 rc = ena_com_set_hash_function(ena_dev); 1587 if (unlikely(rc && (rc != -EOPNOTSUPP))) 1588 return rc; 1589 1590 /* Configure hash inputs (if supported) */ 1591 rc = ena_com_set_hash_ctrl(ena_dev); 1592 if (unlikely(rc && (rc != -EOPNOTSUPP))) 1593 return rc; 1594 1595 return 0; 1596 } 1597 1598 static int ena_up_complete(struct ena_adapter *adapter) 1599 { 1600 int rc; 1601 1602 rc = ena_rss_configure(adapter); 1603 if (rc) 1604 return rc; 1605 1606 ena_change_mtu(adapter->netdev, adapter->netdev->mtu); 1607 1608 ena_refill_all_rx_bufs(adapter); 1609 1610 /* enable transmits */ 1611 netif_tx_start_all_queues(adapter->netdev); 1612 1613 ena_restore_ethtool_params(adapter); 1614 1615 ena_napi_enable_all(adapter); 1616 1617 return 0; 1618 } 1619 1620 static int ena_create_io_tx_queue(struct ena_adapter *adapter, int qid) 1621 { 1622 struct ena_com_create_io_ctx ctx; 1623 struct ena_com_dev *ena_dev; 1624 struct ena_ring *tx_ring; 1625 u32 msix_vector; 1626 u16 ena_qid; 1627 int rc; 1628 1629 ena_dev = adapter->ena_dev; 1630 1631 tx_ring = &adapter->tx_ring[qid]; 1632 msix_vector = ENA_IO_IRQ_IDX(qid); 1633 ena_qid = ENA_IO_TXQ_IDX(qid); 1634 1635 memset(&ctx, 0x0, sizeof(ctx)); 1636 1637 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1638 ctx.qid = ena_qid; 1639 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1640 ctx.msix_vector = msix_vector; 1641 ctx.queue_size = adapter->tx_ring_size; 1642 ctx.numa_node = cpu_to_node(tx_ring->cpu); 1643 1644 rc = ena_com_create_io_queue(ena_dev, &ctx); 1645 if (rc) { 1646 netif_err(adapter, ifup, adapter->netdev, 1647 "Failed to create I/O TX queue num %d rc: %d\n", 1648 qid, rc); 1649 return rc; 1650 } 1651 1652 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1653 &tx_ring->ena_com_io_sq, 1654 &tx_ring->ena_com_io_cq); 1655 if (rc) { 1656 netif_err(adapter, ifup, adapter->netdev, 1657 "Failed to get TX queue handlers. TX queue num %d rc: %d\n", 1658 qid, rc); 1659 ena_com_destroy_io_queue(ena_dev, ena_qid); 1660 return rc; 1661 } 1662 1663 ena_com_update_numa_node(tx_ring->ena_com_io_cq, ctx.numa_node); 1664 return rc; 1665 } 1666 1667 static int ena_create_all_io_tx_queues(struct ena_adapter *adapter) 1668 { 1669 struct ena_com_dev *ena_dev = adapter->ena_dev; 1670 int rc, i; 1671 1672 for (i = 0; i < adapter->num_queues; i++) { 1673 rc = ena_create_io_tx_queue(adapter, i); 1674 if (rc) 1675 goto create_err; 1676 } 1677 1678 return 0; 1679 1680 create_err: 1681 while (i--) 1682 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(i)); 1683 1684 return rc; 1685 } 1686 1687 static int ena_create_io_rx_queue(struct ena_adapter *adapter, int qid) 1688 { 1689 struct ena_com_dev *ena_dev; 1690 struct ena_com_create_io_ctx ctx; 1691 struct ena_ring *rx_ring; 1692 u32 msix_vector; 1693 u16 ena_qid; 1694 int rc; 1695 1696 ena_dev = adapter->ena_dev; 1697 1698 rx_ring = &adapter->rx_ring[qid]; 1699 msix_vector = ENA_IO_IRQ_IDX(qid); 1700 ena_qid = ENA_IO_RXQ_IDX(qid); 1701 1702 memset(&ctx, 0x0, sizeof(ctx)); 1703 1704 ctx.qid = ena_qid; 1705 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1706 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1707 ctx.msix_vector = msix_vector; 1708 ctx.queue_size = adapter->rx_ring_size; 1709 ctx.numa_node = cpu_to_node(rx_ring->cpu); 1710 1711 rc = ena_com_create_io_queue(ena_dev, &ctx); 1712 if (rc) { 1713 netif_err(adapter, ifup, adapter->netdev, 1714 "Failed to create I/O RX queue num %d rc: %d\n", 1715 qid, rc); 1716 return rc; 1717 } 1718 1719 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1720 &rx_ring->ena_com_io_sq, 1721 &rx_ring->ena_com_io_cq); 1722 if (rc) { 1723 netif_err(adapter, ifup, adapter->netdev, 1724 "Failed to get RX queue handlers. RX queue num %d rc: %d\n", 1725 qid, rc); 1726 ena_com_destroy_io_queue(ena_dev, ena_qid); 1727 return rc; 1728 } 1729 1730 ena_com_update_numa_node(rx_ring->ena_com_io_cq, ctx.numa_node); 1731 1732 return rc; 1733 } 1734 1735 static int ena_create_all_io_rx_queues(struct ena_adapter *adapter) 1736 { 1737 struct ena_com_dev *ena_dev = adapter->ena_dev; 1738 int rc, i; 1739 1740 for (i = 0; i < adapter->num_queues; i++) { 1741 rc = ena_create_io_rx_queue(adapter, i); 1742 if (rc) 1743 goto create_err; 1744 } 1745 1746 return 0; 1747 1748 create_err: 1749 while (i--) 1750 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(i)); 1751 1752 return rc; 1753 } 1754 1755 static int ena_up(struct ena_adapter *adapter) 1756 { 1757 int rc, i; 1758 1759 netdev_dbg(adapter->netdev, "%s\n", __func__); 1760 1761 ena_setup_io_intr(adapter); 1762 1763 /* napi poll functions should be initialized before running 1764 * request_irq(), to handle a rare condition where there is a pending 1765 * interrupt, causing the ISR to fire immediately while the poll 1766 * function wasn't set yet, causing a null dereference 1767 */ 1768 ena_init_napi(adapter); 1769 1770 rc = ena_request_io_irq(adapter); 1771 if (rc) 1772 goto err_req_irq; 1773 1774 /* allocate transmit descriptors */ 1775 rc = ena_setup_all_tx_resources(adapter); 1776 if (rc) 1777 goto err_setup_tx; 1778 1779 /* allocate receive descriptors */ 1780 rc = ena_setup_all_rx_resources(adapter); 1781 if (rc) 1782 goto err_setup_rx; 1783 1784 /* Create TX queues */ 1785 rc = ena_create_all_io_tx_queues(adapter); 1786 if (rc) 1787 goto err_create_tx_queues; 1788 1789 /* Create RX queues */ 1790 rc = ena_create_all_io_rx_queues(adapter); 1791 if (rc) 1792 goto err_create_rx_queues; 1793 1794 rc = ena_up_complete(adapter); 1795 if (rc) 1796 goto err_up; 1797 1798 if (test_bit(ENA_FLAG_LINK_UP, &adapter->flags)) 1799 netif_carrier_on(adapter->netdev); 1800 1801 u64_stats_update_begin(&adapter->syncp); 1802 adapter->dev_stats.interface_up++; 1803 u64_stats_update_end(&adapter->syncp); 1804 1805 set_bit(ENA_FLAG_DEV_UP, &adapter->flags); 1806 1807 /* Enable completion queues interrupt */ 1808 for (i = 0; i < adapter->num_queues; i++) 1809 ena_unmask_interrupt(&adapter->tx_ring[i], 1810 &adapter->rx_ring[i]); 1811 1812 /* schedule napi in case we had pending packets 1813 * from the last time we disable napi 1814 */ 1815 for (i = 0; i < adapter->num_queues; i++) 1816 napi_schedule(&adapter->ena_napi[i].napi); 1817 1818 return rc; 1819 1820 err_up: 1821 ena_destroy_all_rx_queues(adapter); 1822 err_create_rx_queues: 1823 ena_destroy_all_tx_queues(adapter); 1824 err_create_tx_queues: 1825 ena_free_all_io_rx_resources(adapter); 1826 err_setup_rx: 1827 ena_free_all_io_tx_resources(adapter); 1828 err_setup_tx: 1829 ena_free_io_irq(adapter); 1830 err_req_irq: 1831 ena_del_napi(adapter); 1832 1833 return rc; 1834 } 1835 1836 static void ena_down(struct ena_adapter *adapter) 1837 { 1838 netif_info(adapter, ifdown, adapter->netdev, "%s\n", __func__); 1839 1840 clear_bit(ENA_FLAG_DEV_UP, &adapter->flags); 1841 1842 u64_stats_update_begin(&adapter->syncp); 1843 adapter->dev_stats.interface_down++; 1844 u64_stats_update_end(&adapter->syncp); 1845 1846 netif_carrier_off(adapter->netdev); 1847 netif_tx_disable(adapter->netdev); 1848 1849 /* After this point the napi handler won't enable the tx queue */ 1850 ena_napi_disable_all(adapter); 1851 1852 /* After destroy the queue there won't be any new interrupts */ 1853 1854 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags)) { 1855 int rc; 1856 1857 rc = ena_com_dev_reset(adapter->ena_dev, adapter->reset_reason); 1858 if (rc) 1859 dev_err(&adapter->pdev->dev, "Device reset failed\n"); 1860 /* stop submitting admin commands on a device that was reset */ 1861 ena_com_set_admin_running_state(adapter->ena_dev, false); 1862 } 1863 1864 ena_destroy_all_io_queues(adapter); 1865 1866 ena_disable_io_intr_sync(adapter); 1867 ena_free_io_irq(adapter); 1868 ena_del_napi(adapter); 1869 1870 ena_free_all_tx_bufs(adapter); 1871 ena_free_all_rx_bufs(adapter); 1872 ena_free_all_io_tx_resources(adapter); 1873 ena_free_all_io_rx_resources(adapter); 1874 } 1875 1876 /* ena_open - Called when a network interface is made active 1877 * @netdev: network interface device structure 1878 * 1879 * Returns 0 on success, negative value on failure 1880 * 1881 * The open entry point is called when a network interface is made 1882 * active by the system (IFF_UP). At this point all resources needed 1883 * for transmit and receive operations are allocated, the interrupt 1884 * handler is registered with the OS, the watchdog timer is started, 1885 * and the stack is notified that the interface is ready. 1886 */ 1887 static int ena_open(struct net_device *netdev) 1888 { 1889 struct ena_adapter *adapter = netdev_priv(netdev); 1890 int rc; 1891 1892 /* Notify the stack of the actual queue counts. */ 1893 rc = netif_set_real_num_tx_queues(netdev, adapter->num_queues); 1894 if (rc) { 1895 netif_err(adapter, ifup, netdev, "Can't set num tx queues\n"); 1896 return rc; 1897 } 1898 1899 rc = netif_set_real_num_rx_queues(netdev, adapter->num_queues); 1900 if (rc) { 1901 netif_err(adapter, ifup, netdev, "Can't set num rx queues\n"); 1902 return rc; 1903 } 1904 1905 rc = ena_up(adapter); 1906 if (rc) 1907 return rc; 1908 1909 return rc; 1910 } 1911 1912 /* ena_close - Disables a network interface 1913 * @netdev: network interface device structure 1914 * 1915 * Returns 0, this is not allowed to fail 1916 * 1917 * The close entry point is called when an interface is de-activated 1918 * by the OS. The hardware is still under the drivers control, but 1919 * needs to be disabled. A global MAC reset is issued to stop the 1920 * hardware, and all transmit and receive resources are freed. 1921 */ 1922 static int ena_close(struct net_device *netdev) 1923 { 1924 struct ena_adapter *adapter = netdev_priv(netdev); 1925 1926 netif_dbg(adapter, ifdown, netdev, "%s\n", __func__); 1927 1928 if (!test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags)) 1929 return 0; 1930 1931 if (test_bit(ENA_FLAG_DEV_UP, &adapter->flags)) 1932 ena_down(adapter); 1933 1934 /* Check for device status and issue reset if needed*/ 1935 check_for_admin_com_state(adapter); 1936 if (unlikely(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) { 1937 netif_err(adapter, ifdown, adapter->netdev, 1938 "Destroy failure, restarting device\n"); 1939 ena_dump_stats_to_dmesg(adapter); 1940 /* rtnl lock already obtained in dev_ioctl() layer */ 1941 ena_destroy_device(adapter, false); 1942 ena_restore_device(adapter); 1943 } 1944 1945 return 0; 1946 } 1947 1948 static void ena_tx_csum(struct ena_com_tx_ctx *ena_tx_ctx, struct sk_buff *skb) 1949 { 1950 u32 mss = skb_shinfo(skb)->gso_size; 1951 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta; 1952 u8 l4_protocol = 0; 1953 1954 if ((skb->ip_summed == CHECKSUM_PARTIAL) || mss) { 1955 ena_tx_ctx->l4_csum_enable = 1; 1956 if (mss) { 1957 ena_tx_ctx->tso_enable = 1; 1958 ena_meta->l4_hdr_len = tcp_hdr(skb)->doff; 1959 ena_tx_ctx->l4_csum_partial = 0; 1960 } else { 1961 ena_tx_ctx->tso_enable = 0; 1962 ena_meta->l4_hdr_len = 0; 1963 ena_tx_ctx->l4_csum_partial = 1; 1964 } 1965 1966 switch (ip_hdr(skb)->version) { 1967 case IPVERSION: 1968 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 1969 if (ip_hdr(skb)->frag_off & htons(IP_DF)) 1970 ena_tx_ctx->df = 1; 1971 if (mss) 1972 ena_tx_ctx->l3_csum_enable = 1; 1973 l4_protocol = ip_hdr(skb)->protocol; 1974 break; 1975 case 6: 1976 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 1977 l4_protocol = ipv6_hdr(skb)->nexthdr; 1978 break; 1979 default: 1980 break; 1981 } 1982 1983 if (l4_protocol == IPPROTO_TCP) 1984 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 1985 else 1986 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 1987 1988 ena_meta->mss = mss; 1989 ena_meta->l3_hdr_len = skb_network_header_len(skb); 1990 ena_meta->l3_hdr_offset = skb_network_offset(skb); 1991 ena_tx_ctx->meta_valid = 1; 1992 1993 } else { 1994 ena_tx_ctx->meta_valid = 0; 1995 } 1996 } 1997 1998 static int ena_check_and_linearize_skb(struct ena_ring *tx_ring, 1999 struct sk_buff *skb) 2000 { 2001 int num_frags, header_len, rc; 2002 2003 num_frags = skb_shinfo(skb)->nr_frags; 2004 header_len = skb_headlen(skb); 2005 2006 if (num_frags < tx_ring->sgl_size) 2007 return 0; 2008 2009 if ((num_frags == tx_ring->sgl_size) && 2010 (header_len < tx_ring->tx_max_header_size)) 2011 return 0; 2012 2013 u64_stats_update_begin(&tx_ring->syncp); 2014 tx_ring->tx_stats.linearize++; 2015 u64_stats_update_end(&tx_ring->syncp); 2016 2017 rc = skb_linearize(skb); 2018 if (unlikely(rc)) { 2019 u64_stats_update_begin(&tx_ring->syncp); 2020 tx_ring->tx_stats.linearize_failed++; 2021 u64_stats_update_end(&tx_ring->syncp); 2022 } 2023 2024 return rc; 2025 } 2026 2027 static int ena_tx_map_skb(struct ena_ring *tx_ring, 2028 struct ena_tx_buffer *tx_info, 2029 struct sk_buff *skb, 2030 void **push_hdr, 2031 u16 *header_len) 2032 { 2033 struct ena_adapter *adapter = tx_ring->adapter; 2034 struct ena_com_buf *ena_buf; 2035 dma_addr_t dma; 2036 u32 skb_head_len, frag_len, last_frag; 2037 u16 push_len = 0; 2038 u16 delta = 0; 2039 int i = 0; 2040 2041 skb_head_len = skb_headlen(skb); 2042 tx_info->skb = skb; 2043 ena_buf = tx_info->bufs; 2044 2045 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 2046 /* When the device is LLQ mode, the driver will copy 2047 * the header into the device memory space. 2048 * the ena_com layer assume the header is in a linear 2049 * memory space. 2050 * This assumption might be wrong since part of the header 2051 * can be in the fragmented buffers. 2052 * Use skb_header_pointer to make sure the header is in a 2053 * linear memory space. 2054 */ 2055 2056 push_len = min_t(u32, skb->len, tx_ring->tx_max_header_size); 2057 *push_hdr = skb_header_pointer(skb, 0, push_len, 2058 tx_ring->push_buf_intermediate_buf); 2059 *header_len = push_len; 2060 if (unlikely(skb->data != *push_hdr)) { 2061 u64_stats_update_begin(&tx_ring->syncp); 2062 tx_ring->tx_stats.llq_buffer_copy++; 2063 u64_stats_update_end(&tx_ring->syncp); 2064 2065 delta = push_len - skb_head_len; 2066 } 2067 } else { 2068 *push_hdr = NULL; 2069 *header_len = min_t(u32, skb_head_len, 2070 tx_ring->tx_max_header_size); 2071 } 2072 2073 netif_dbg(adapter, tx_queued, adapter->netdev, 2074 "skb: %p header_buf->vaddr: %p push_len: %d\n", skb, 2075 *push_hdr, push_len); 2076 2077 if (skb_head_len > push_len) { 2078 dma = dma_map_single(tx_ring->dev, skb->data + push_len, 2079 skb_head_len - push_len, DMA_TO_DEVICE); 2080 if (unlikely(dma_mapping_error(tx_ring->dev, dma))) 2081 goto error_report_dma_error; 2082 2083 ena_buf->paddr = dma; 2084 ena_buf->len = skb_head_len - push_len; 2085 2086 ena_buf++; 2087 tx_info->num_of_bufs++; 2088 tx_info->map_linear_data = 1; 2089 } else { 2090 tx_info->map_linear_data = 0; 2091 } 2092 2093 last_frag = skb_shinfo(skb)->nr_frags; 2094 2095 for (i = 0; i < last_frag; i++) { 2096 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2097 2098 frag_len = skb_frag_size(frag); 2099 2100 if (unlikely(delta >= frag_len)) { 2101 delta -= frag_len; 2102 continue; 2103 } 2104 2105 dma = skb_frag_dma_map(tx_ring->dev, frag, delta, 2106 frag_len - delta, DMA_TO_DEVICE); 2107 if (unlikely(dma_mapping_error(tx_ring->dev, dma))) 2108 goto error_report_dma_error; 2109 2110 ena_buf->paddr = dma; 2111 ena_buf->len = frag_len - delta; 2112 ena_buf++; 2113 tx_info->num_of_bufs++; 2114 delta = 0; 2115 } 2116 2117 return 0; 2118 2119 error_report_dma_error: 2120 u64_stats_update_begin(&tx_ring->syncp); 2121 tx_ring->tx_stats.dma_mapping_err++; 2122 u64_stats_update_end(&tx_ring->syncp); 2123 netdev_warn(adapter->netdev, "failed to map skb\n"); 2124 2125 tx_info->skb = NULL; 2126 2127 tx_info->num_of_bufs += i; 2128 ena_unmap_tx_skb(tx_ring, tx_info); 2129 2130 return -EINVAL; 2131 } 2132 2133 /* Called with netif_tx_lock. */ 2134 static netdev_tx_t ena_start_xmit(struct sk_buff *skb, struct net_device *dev) 2135 { 2136 struct ena_adapter *adapter = netdev_priv(dev); 2137 struct ena_tx_buffer *tx_info; 2138 struct ena_com_tx_ctx ena_tx_ctx; 2139 struct ena_ring *tx_ring; 2140 struct netdev_queue *txq; 2141 void *push_hdr; 2142 u16 next_to_use, req_id, header_len; 2143 int qid, rc, nb_hw_desc; 2144 2145 netif_dbg(adapter, tx_queued, dev, "%s skb %p\n", __func__, skb); 2146 /* Determine which tx ring we will be placed on */ 2147 qid = skb_get_queue_mapping(skb); 2148 tx_ring = &adapter->tx_ring[qid]; 2149 txq = netdev_get_tx_queue(dev, qid); 2150 2151 rc = ena_check_and_linearize_skb(tx_ring, skb); 2152 if (unlikely(rc)) 2153 goto error_drop_packet; 2154 2155 skb_tx_timestamp(skb); 2156 2157 next_to_use = tx_ring->next_to_use; 2158 req_id = tx_ring->free_ids[next_to_use]; 2159 tx_info = &tx_ring->tx_buffer_info[req_id]; 2160 tx_info->num_of_bufs = 0; 2161 2162 WARN(tx_info->skb, "SKB isn't NULL req_id %d\n", req_id); 2163 2164 rc = ena_tx_map_skb(tx_ring, tx_info, skb, &push_hdr, &header_len); 2165 if (unlikely(rc)) 2166 goto error_drop_packet; 2167 2168 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx)); 2169 ena_tx_ctx.ena_bufs = tx_info->bufs; 2170 ena_tx_ctx.push_header = push_hdr; 2171 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 2172 ena_tx_ctx.req_id = req_id; 2173 ena_tx_ctx.header_len = header_len; 2174 2175 /* set flags and meta data */ 2176 ena_tx_csum(&ena_tx_ctx, skb); 2177 2178 if (unlikely(ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq, &ena_tx_ctx))) { 2179 netif_dbg(adapter, tx_queued, dev, 2180 "llq tx max burst size of queue %d achieved, writing doorbell to send burst\n", 2181 qid); 2182 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2183 } 2184 2185 /* prepare the packet's descriptors to dma engine */ 2186 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx, 2187 &nb_hw_desc); 2188 2189 /* ena_com_prepare_tx() can't fail due to overflow of tx queue, 2190 * since the number of free descriptors in the queue is checked 2191 * after sending the previous packet. In case there isn't enough 2192 * space in the queue for the next packet, it is stopped 2193 * until there is again enough available space in the queue. 2194 * All other failure reasons of ena_com_prepare_tx() are fatal 2195 * and therefore require a device reset. 2196 */ 2197 if (unlikely(rc)) { 2198 netif_err(adapter, tx_queued, dev, 2199 "failed to prepare tx bufs\n"); 2200 u64_stats_update_begin(&tx_ring->syncp); 2201 tx_ring->tx_stats.prepare_ctx_err++; 2202 u64_stats_update_end(&tx_ring->syncp); 2203 adapter->reset_reason = ENA_REGS_RESET_DRIVER_INVALID_STATE; 2204 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags); 2205 goto error_unmap_dma; 2206 } 2207 2208 netdev_tx_sent_queue(txq, skb->len); 2209 2210 u64_stats_update_begin(&tx_ring->syncp); 2211 tx_ring->tx_stats.cnt++; 2212 tx_ring->tx_stats.bytes += skb->len; 2213 u64_stats_update_end(&tx_ring->syncp); 2214 2215 tx_info->tx_descs = nb_hw_desc; 2216 tx_info->last_jiffies = jiffies; 2217 tx_info->print_once = 0; 2218 2219 tx_ring->next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use, 2220 tx_ring->ring_size); 2221 2222 /* stop the queue when no more space available, the packet can have up 2223 * to sgl_size + 2. one for the meta descriptor and one for header 2224 * (if the header is larger than tx_max_header_size). 2225 */ 2226 if (unlikely(!ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 2227 tx_ring->sgl_size + 2))) { 2228 netif_dbg(adapter, tx_queued, dev, "%s stop queue %d\n", 2229 __func__, qid); 2230 2231 netif_tx_stop_queue(txq); 2232 u64_stats_update_begin(&tx_ring->syncp); 2233 tx_ring->tx_stats.queue_stop++; 2234 u64_stats_update_end(&tx_ring->syncp); 2235 2236 /* There is a rare condition where this function decide to 2237 * stop the queue but meanwhile clean_tx_irq updates 2238 * next_to_completion and terminates. 2239 * The queue will remain stopped forever. 2240 * To solve this issue add a mb() to make sure that 2241 * netif_tx_stop_queue() write is vissible before checking if 2242 * there is additional space in the queue. 2243 */ 2244 smp_mb(); 2245 2246 if (ena_com_sq_have_enough_space(tx_ring->ena_com_io_sq, 2247 ENA_TX_WAKEUP_THRESH)) { 2248 netif_tx_wake_queue(txq); 2249 u64_stats_update_begin(&tx_ring->syncp); 2250 tx_ring->tx_stats.queue_wakeup++; 2251 u64_stats_update_end(&tx_ring->syncp); 2252 } 2253 } 2254 2255 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) { 2256 /* trigger the dma engine. ena_com_write_sq_doorbell() 2257 * has a mb 2258 */ 2259 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2260 u64_stats_update_begin(&tx_ring->syncp); 2261 tx_ring->tx_stats.doorbells++; 2262 u64_stats_update_end(&tx_ring->syncp); 2263 } 2264 2265 return NETDEV_TX_OK; 2266 2267 error_unmap_dma: 2268 ena_unmap_tx_skb(tx_ring, tx_info); 2269 tx_info->skb = NULL; 2270 2271 error_drop_packet: 2272 dev_kfree_skb(skb); 2273 return NETDEV_TX_OK; 2274 } 2275 2276 static u16 ena_select_queue(struct net_device *dev, struct sk_buff *skb, 2277 struct net_device *sb_dev) 2278 { 2279 u16 qid; 2280 /* we suspect that this is good for in--kernel network services that 2281 * want to loop incoming skb rx to tx in normal user generated traffic, 2282 * most probably we will not get to this 2283 */ 2284 if (skb_rx_queue_recorded(skb)) 2285 qid = skb_get_rx_queue(skb); 2286 else 2287 qid = netdev_pick_tx(dev, skb, NULL); 2288 2289 return qid; 2290 } 2291 2292 static void ena_config_host_info(struct ena_com_dev *ena_dev, 2293 struct pci_dev *pdev) 2294 { 2295 struct ena_admin_host_info *host_info; 2296 int rc; 2297 2298 /* Allocate only the host info */ 2299 rc = ena_com_allocate_host_info(ena_dev); 2300 if (rc) { 2301 pr_err("Cannot allocate host info\n"); 2302 return; 2303 } 2304 2305 host_info = ena_dev->host_attr.host_info; 2306 2307 host_info->bdf = (pdev->bus->number << 8) | pdev->devfn; 2308 host_info->os_type = ENA_ADMIN_OS_LINUX; 2309 host_info->kernel_ver = LINUX_VERSION_CODE; 2310 strlcpy(host_info->kernel_ver_str, utsname()->version, 2311 sizeof(host_info->kernel_ver_str) - 1); 2312 host_info->os_dist = 0; 2313 strncpy(host_info->os_dist_str, utsname()->release, 2314 sizeof(host_info->os_dist_str) - 1); 2315 host_info->driver_version = 2316 (DRV_MODULE_VER_MAJOR) | 2317 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 2318 (DRV_MODULE_VER_SUBMINOR << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) | 2319 ("K"[0] << ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT); 2320 host_info->num_cpus = num_online_cpus(); 2321 2322 rc = ena_com_set_host_attributes(ena_dev); 2323 if (rc) { 2324 if (rc == -EOPNOTSUPP) 2325 pr_warn("Cannot set host attributes\n"); 2326 else 2327 pr_err("Cannot set host attributes\n"); 2328 2329 goto err; 2330 } 2331 2332 return; 2333 2334 err: 2335 ena_com_delete_host_info(ena_dev); 2336 } 2337 2338 static void ena_config_debug_area(struct ena_adapter *adapter) 2339 { 2340 u32 debug_area_size; 2341 int rc, ss_count; 2342 2343 ss_count = ena_get_sset_count(adapter->netdev, ETH_SS_STATS); 2344 if (ss_count <= 0) { 2345 netif_err(adapter, drv, adapter->netdev, 2346 "SS count is negative\n"); 2347 return; 2348 } 2349 2350 /* allocate 32 bytes for each string and 64bit for the value */ 2351 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count; 2352 2353 rc = ena_com_allocate_debug_area(adapter->ena_dev, debug_area_size); 2354 if (rc) { 2355 pr_err("Cannot allocate debug area\n"); 2356 return; 2357 } 2358 2359 rc = ena_com_set_host_attributes(adapter->ena_dev); 2360 if (rc) { 2361 if (rc == -EOPNOTSUPP) 2362 netif_warn(adapter, drv, adapter->netdev, 2363 "Cannot set host attributes\n"); 2364 else 2365 netif_err(adapter, drv, adapter->netdev, 2366 "Cannot set host attributes\n"); 2367 goto err; 2368 } 2369 2370 return; 2371 err: 2372 ena_com_delete_debug_area(adapter->ena_dev); 2373 } 2374 2375 static void ena_extra_properties_strings_destroy(struct net_device *netdev) 2376 { 2377 struct ena_adapter *adapter = netdev_priv(netdev); 2378 2379 ena_com_delete_extra_properties_strings(adapter->ena_dev); 2380 adapter->ena_extra_properties_count = 0; 2381 } 2382 2383 static void ena_get_stats64(struct net_device *netdev, 2384 struct rtnl_link_stats64 *stats) 2385 { 2386 struct ena_adapter *adapter = netdev_priv(netdev); 2387 struct ena_ring *rx_ring, *tx_ring; 2388 unsigned int start; 2389 u64 rx_drops; 2390 int i; 2391 2392 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags)) 2393 return; 2394 2395 for (i = 0; i < adapter->num_queues; i++) { 2396 u64 bytes, packets; 2397 2398 tx_ring = &adapter->tx_ring[i]; 2399 2400 do { 2401 start = u64_stats_fetch_begin_irq(&tx_ring->syncp); 2402 packets = tx_ring->tx_stats.cnt; 2403 bytes = tx_ring->tx_stats.bytes; 2404 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start)); 2405 2406 stats->tx_packets += packets; 2407 stats->tx_bytes += bytes; 2408 2409 rx_ring = &adapter->rx_ring[i]; 2410 2411 do { 2412 start = u64_stats_fetch_begin_irq(&rx_ring->syncp); 2413 packets = rx_ring->rx_stats.cnt; 2414 bytes = rx_ring->rx_stats.bytes; 2415 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start)); 2416 2417 stats->rx_packets += packets; 2418 stats->rx_bytes += bytes; 2419 } 2420 2421 do { 2422 start = u64_stats_fetch_begin_irq(&adapter->syncp); 2423 rx_drops = adapter->dev_stats.rx_drops; 2424 } while (u64_stats_fetch_retry_irq(&adapter->syncp, start)); 2425 2426 stats->rx_dropped = rx_drops; 2427 2428 stats->multicast = 0; 2429 stats->collisions = 0; 2430 2431 stats->rx_length_errors = 0; 2432 stats->rx_crc_errors = 0; 2433 stats->rx_frame_errors = 0; 2434 stats->rx_fifo_errors = 0; 2435 stats->rx_missed_errors = 0; 2436 stats->tx_window_errors = 0; 2437 2438 stats->rx_errors = 0; 2439 stats->tx_errors = 0; 2440 } 2441 2442 static const struct net_device_ops ena_netdev_ops = { 2443 .ndo_open = ena_open, 2444 .ndo_stop = ena_close, 2445 .ndo_start_xmit = ena_start_xmit, 2446 .ndo_select_queue = ena_select_queue, 2447 .ndo_get_stats64 = ena_get_stats64, 2448 .ndo_tx_timeout = ena_tx_timeout, 2449 .ndo_change_mtu = ena_change_mtu, 2450 .ndo_set_mac_address = NULL, 2451 .ndo_validate_addr = eth_validate_addr, 2452 }; 2453 2454 static int ena_device_validate_params(struct ena_adapter *adapter, 2455 struct ena_com_dev_get_features_ctx *get_feat_ctx) 2456 { 2457 struct net_device *netdev = adapter->netdev; 2458 int rc; 2459 2460 rc = ether_addr_equal(get_feat_ctx->dev_attr.mac_addr, 2461 adapter->mac_addr); 2462 if (!rc) { 2463 netif_err(adapter, drv, netdev, 2464 "Error, mac address are different\n"); 2465 return -EINVAL; 2466 } 2467 2468 if ((get_feat_ctx->max_queues.max_cq_num < adapter->num_queues) || 2469 (get_feat_ctx->max_queues.max_sq_num < adapter->num_queues)) { 2470 netif_err(adapter, drv, netdev, 2471 "Error, device doesn't support enough queues\n"); 2472 return -EINVAL; 2473 } 2474 2475 if (get_feat_ctx->dev_attr.max_mtu < netdev->mtu) { 2476 netif_err(adapter, drv, netdev, 2477 "Error, device max mtu is smaller than netdev MTU\n"); 2478 return -EINVAL; 2479 } 2480 2481 return 0; 2482 } 2483 2484 static int ena_device_init(struct ena_com_dev *ena_dev, struct pci_dev *pdev, 2485 struct ena_com_dev_get_features_ctx *get_feat_ctx, 2486 bool *wd_state) 2487 { 2488 struct device *dev = &pdev->dev; 2489 bool readless_supported; 2490 u32 aenq_groups; 2491 int dma_width; 2492 int rc; 2493 2494 rc = ena_com_mmio_reg_read_request_init(ena_dev); 2495 if (rc) { 2496 dev_err(dev, "failed to init mmio read less\n"); 2497 return rc; 2498 } 2499 2500 /* The PCIe configuration space revision id indicate if mmio reg 2501 * read is disabled 2502 */ 2503 readless_supported = !(pdev->revision & ENA_MMIO_DISABLE_REG_READ); 2504 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 2505 2506 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 2507 if (rc) { 2508 dev_err(dev, "Can not reset device\n"); 2509 goto err_mmio_read_less; 2510 } 2511 2512 rc = ena_com_validate_version(ena_dev); 2513 if (rc) { 2514 dev_err(dev, "device version is too low\n"); 2515 goto err_mmio_read_less; 2516 } 2517 2518 dma_width = ena_com_get_dma_width(ena_dev); 2519 if (dma_width < 0) { 2520 dev_err(dev, "Invalid dma width value %d", dma_width); 2521 rc = dma_width; 2522 goto err_mmio_read_less; 2523 } 2524 2525 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(dma_width)); 2526 if (rc) { 2527 dev_err(dev, "pci_set_dma_mask failed 0x%x\n", rc); 2528 goto err_mmio_read_less; 2529 } 2530 2531 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(dma_width)); 2532 if (rc) { 2533 dev_err(dev, "err_pci_set_consistent_dma_mask failed 0x%x\n", 2534 rc); 2535 goto err_mmio_read_less; 2536 } 2537 2538 /* ENA admin level init */ 2539 rc = ena_com_admin_init(ena_dev, &aenq_handlers); 2540 if (rc) { 2541 dev_err(dev, 2542 "Can not initialize ena admin queue with device\n"); 2543 goto err_mmio_read_less; 2544 } 2545 2546 /* To enable the msix interrupts the driver needs to know the number 2547 * of queues. So the driver uses polling mode to retrieve this 2548 * information 2549 */ 2550 ena_com_set_admin_polling_mode(ena_dev, true); 2551 2552 ena_config_host_info(ena_dev, pdev); 2553 2554 /* Get Device Attributes*/ 2555 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 2556 if (rc) { 2557 dev_err(dev, "Cannot get attribute for ena device rc=%d\n", rc); 2558 goto err_admin_init; 2559 } 2560 2561 /* Try to turn all the available aenq groups */ 2562 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | 2563 BIT(ENA_ADMIN_FATAL_ERROR) | 2564 BIT(ENA_ADMIN_WARNING) | 2565 BIT(ENA_ADMIN_NOTIFICATION) | 2566 BIT(ENA_ADMIN_KEEP_ALIVE); 2567 2568 aenq_groups &= get_feat_ctx->aenq.supported_groups; 2569 2570 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 2571 if (rc) { 2572 dev_err(dev, "Cannot configure aenq groups rc= %d\n", rc); 2573 goto err_admin_init; 2574 } 2575 2576 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 2577 2578 return 0; 2579 2580 err_admin_init: 2581 ena_com_delete_host_info(ena_dev); 2582 ena_com_admin_destroy(ena_dev); 2583 err_mmio_read_less: 2584 ena_com_mmio_reg_read_request_destroy(ena_dev); 2585 2586 return rc; 2587 } 2588 2589 static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *adapter, 2590 int io_vectors) 2591 { 2592 struct ena_com_dev *ena_dev = adapter->ena_dev; 2593 struct device *dev = &adapter->pdev->dev; 2594 int rc; 2595 2596 rc = ena_enable_msix(adapter, io_vectors); 2597 if (rc) { 2598 dev_err(dev, "Can not reserve msix vectors\n"); 2599 return rc; 2600 } 2601 2602 ena_setup_mgmnt_intr(adapter); 2603 2604 rc = ena_request_mgmnt_irq(adapter); 2605 if (rc) { 2606 dev_err(dev, "Can not setup management interrupts\n"); 2607 goto err_disable_msix; 2608 } 2609 2610 ena_com_set_admin_polling_mode(ena_dev, false); 2611 2612 ena_com_admin_aenq_enable(ena_dev); 2613 2614 return 0; 2615 2616 err_disable_msix: 2617 ena_disable_msix(adapter); 2618 2619 return rc; 2620 } 2621 2622 static void ena_destroy_device(struct ena_adapter *adapter, bool graceful) 2623 { 2624 struct net_device *netdev = adapter->netdev; 2625 struct ena_com_dev *ena_dev = adapter->ena_dev; 2626 bool dev_up; 2627 2628 if (!test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags)) 2629 return; 2630 2631 netif_carrier_off(netdev); 2632 2633 del_timer_sync(&adapter->timer_service); 2634 2635 dev_up = test_bit(ENA_FLAG_DEV_UP, &adapter->flags); 2636 adapter->dev_up_before_reset = dev_up; 2637 if (!graceful) 2638 ena_com_set_admin_running_state(ena_dev, false); 2639 2640 if (test_bit(ENA_FLAG_DEV_UP, &adapter->flags)) 2641 ena_down(adapter); 2642 2643 /* Stop the device from sending AENQ events (in case reset flag is set 2644 * and device is up, ena_down() already reset the device. 2645 */ 2646 if (!(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags) && dev_up)) 2647 ena_com_dev_reset(adapter->ena_dev, adapter->reset_reason); 2648 2649 ena_free_mgmnt_irq(adapter); 2650 2651 ena_disable_msix(adapter); 2652 2653 ena_com_abort_admin_commands(ena_dev); 2654 2655 ena_com_wait_for_abort_completion(ena_dev); 2656 2657 ena_com_admin_destroy(ena_dev); 2658 2659 ena_com_mmio_reg_read_request_destroy(ena_dev); 2660 2661 adapter->reset_reason = ENA_REGS_RESET_NORMAL; 2662 2663 clear_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags); 2664 clear_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags); 2665 } 2666 2667 static int ena_restore_device(struct ena_adapter *adapter) 2668 { 2669 struct ena_com_dev_get_features_ctx get_feat_ctx; 2670 struct ena_com_dev *ena_dev = adapter->ena_dev; 2671 struct pci_dev *pdev = adapter->pdev; 2672 bool wd_state; 2673 int rc; 2674 2675 set_bit(ENA_FLAG_ONGOING_RESET, &adapter->flags); 2676 rc = ena_device_init(ena_dev, adapter->pdev, &get_feat_ctx, &wd_state); 2677 if (rc) { 2678 dev_err(&pdev->dev, "Can not initialize device\n"); 2679 goto err; 2680 } 2681 adapter->wd_state = wd_state; 2682 2683 rc = ena_device_validate_params(adapter, &get_feat_ctx); 2684 if (rc) { 2685 dev_err(&pdev->dev, "Validation of device parameters failed\n"); 2686 goto err_device_destroy; 2687 } 2688 2689 rc = ena_enable_msix_and_set_admin_interrupts(adapter, 2690 adapter->num_queues); 2691 if (rc) { 2692 dev_err(&pdev->dev, "Enable MSI-X failed\n"); 2693 goto err_device_destroy; 2694 } 2695 /* If the interface was up before the reset bring it up */ 2696 if (adapter->dev_up_before_reset) { 2697 rc = ena_up(adapter); 2698 if (rc) { 2699 dev_err(&pdev->dev, "Failed to create I/O queues\n"); 2700 goto err_disable_msix; 2701 } 2702 } 2703 2704 set_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags); 2705 2706 clear_bit(ENA_FLAG_ONGOING_RESET, &adapter->flags); 2707 if (test_bit(ENA_FLAG_LINK_UP, &adapter->flags)) 2708 netif_carrier_on(adapter->netdev); 2709 2710 mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ)); 2711 dev_err(&pdev->dev, 2712 "Device reset completed successfully, Driver info: %s\n", 2713 version); 2714 2715 return rc; 2716 err_disable_msix: 2717 ena_free_mgmnt_irq(adapter); 2718 ena_disable_msix(adapter); 2719 err_device_destroy: 2720 ena_com_abort_admin_commands(ena_dev); 2721 ena_com_wait_for_abort_completion(ena_dev); 2722 ena_com_admin_destroy(ena_dev); 2723 ena_com_dev_reset(ena_dev, ENA_REGS_RESET_DRIVER_INVALID_STATE); 2724 ena_com_mmio_reg_read_request_destroy(ena_dev); 2725 err: 2726 clear_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags); 2727 clear_bit(ENA_FLAG_ONGOING_RESET, &adapter->flags); 2728 dev_err(&pdev->dev, 2729 "Reset attempt failed. Can not reset the device\n"); 2730 2731 return rc; 2732 } 2733 2734 static void ena_fw_reset_device(struct work_struct *work) 2735 { 2736 struct ena_adapter *adapter = 2737 container_of(work, struct ena_adapter, reset_task); 2738 struct pci_dev *pdev = adapter->pdev; 2739 2740 if (unlikely(!test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) { 2741 dev_err(&pdev->dev, 2742 "device reset schedule while reset bit is off\n"); 2743 return; 2744 } 2745 rtnl_lock(); 2746 ena_destroy_device(adapter, false); 2747 ena_restore_device(adapter); 2748 rtnl_unlock(); 2749 } 2750 2751 static int check_for_rx_interrupt_queue(struct ena_adapter *adapter, 2752 struct ena_ring *rx_ring) 2753 { 2754 if (likely(rx_ring->first_interrupt)) 2755 return 0; 2756 2757 if (ena_com_cq_empty(rx_ring->ena_com_io_cq)) 2758 return 0; 2759 2760 rx_ring->no_interrupt_event_cnt++; 2761 2762 if (rx_ring->no_interrupt_event_cnt == ENA_MAX_NO_INTERRUPT_ITERATIONS) { 2763 netif_err(adapter, rx_err, adapter->netdev, 2764 "Potential MSIX issue on Rx side Queue = %d. Reset the device\n", 2765 rx_ring->qid); 2766 adapter->reset_reason = ENA_REGS_RESET_MISS_INTERRUPT; 2767 smp_mb__before_atomic(); 2768 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags); 2769 return -EIO; 2770 } 2771 2772 return 0; 2773 } 2774 2775 static int check_missing_comp_in_tx_queue(struct ena_adapter *adapter, 2776 struct ena_ring *tx_ring) 2777 { 2778 struct ena_tx_buffer *tx_buf; 2779 unsigned long last_jiffies; 2780 u32 missed_tx = 0; 2781 int i, rc = 0; 2782 2783 for (i = 0; i < tx_ring->ring_size; i++) { 2784 tx_buf = &tx_ring->tx_buffer_info[i]; 2785 last_jiffies = tx_buf->last_jiffies; 2786 2787 if (last_jiffies == 0) 2788 /* no pending Tx at this location */ 2789 continue; 2790 2791 if (unlikely(!tx_ring->first_interrupt && time_is_before_jiffies(last_jiffies + 2792 2 * adapter->missing_tx_completion_to))) { 2793 /* If after graceful period interrupt is still not 2794 * received, we schedule a reset 2795 */ 2796 netif_err(adapter, tx_err, adapter->netdev, 2797 "Potential MSIX issue on Tx side Queue = %d. Reset the device\n", 2798 tx_ring->qid); 2799 adapter->reset_reason = ENA_REGS_RESET_MISS_INTERRUPT; 2800 smp_mb__before_atomic(); 2801 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags); 2802 return -EIO; 2803 } 2804 2805 if (unlikely(time_is_before_jiffies(last_jiffies + 2806 adapter->missing_tx_completion_to))) { 2807 if (!tx_buf->print_once) 2808 netif_notice(adapter, tx_err, adapter->netdev, 2809 "Found a Tx that wasn't completed on time, qid %d, index %d.\n", 2810 tx_ring->qid, i); 2811 2812 tx_buf->print_once = 1; 2813 missed_tx++; 2814 } 2815 } 2816 2817 if (unlikely(missed_tx > adapter->missing_tx_completion_threshold)) { 2818 netif_err(adapter, tx_err, adapter->netdev, 2819 "The number of lost tx completions is above the threshold (%d > %d). Reset the device\n", 2820 missed_tx, 2821 adapter->missing_tx_completion_threshold); 2822 adapter->reset_reason = 2823 ENA_REGS_RESET_MISS_TX_CMPL; 2824 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags); 2825 rc = -EIO; 2826 } 2827 2828 u64_stats_update_begin(&tx_ring->syncp); 2829 tx_ring->tx_stats.missed_tx = missed_tx; 2830 u64_stats_update_end(&tx_ring->syncp); 2831 2832 return rc; 2833 } 2834 2835 static void check_for_missing_completions(struct ena_adapter *adapter) 2836 { 2837 struct ena_ring *tx_ring; 2838 struct ena_ring *rx_ring; 2839 int i, budget, rc; 2840 2841 /* Make sure the driver doesn't turn the device in other process */ 2842 smp_rmb(); 2843 2844 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags)) 2845 return; 2846 2847 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags)) 2848 return; 2849 2850 if (adapter->missing_tx_completion_to == ENA_HW_HINTS_NO_TIMEOUT) 2851 return; 2852 2853 budget = ENA_MONITORED_TX_QUEUES; 2854 2855 for (i = adapter->last_monitored_tx_qid; i < adapter->num_queues; i++) { 2856 tx_ring = &adapter->tx_ring[i]; 2857 rx_ring = &adapter->rx_ring[i]; 2858 2859 rc = check_missing_comp_in_tx_queue(adapter, tx_ring); 2860 if (unlikely(rc)) 2861 return; 2862 2863 rc = check_for_rx_interrupt_queue(adapter, rx_ring); 2864 if (unlikely(rc)) 2865 return; 2866 2867 budget--; 2868 if (!budget) 2869 break; 2870 } 2871 2872 adapter->last_monitored_tx_qid = i % adapter->num_queues; 2873 } 2874 2875 /* trigger napi schedule after 2 consecutive detections */ 2876 #define EMPTY_RX_REFILL 2 2877 /* For the rare case where the device runs out of Rx descriptors and the 2878 * napi handler failed to refill new Rx descriptors (due to a lack of memory 2879 * for example). 2880 * This case will lead to a deadlock: 2881 * The device won't send interrupts since all the new Rx packets will be dropped 2882 * The napi handler won't allocate new Rx descriptors so the device will be 2883 * able to send new packets. 2884 * 2885 * This scenario can happen when the kernel's vm.min_free_kbytes is too small. 2886 * It is recommended to have at least 512MB, with a minimum of 128MB for 2887 * constrained environment). 2888 * 2889 * When such a situation is detected - Reschedule napi 2890 */ 2891 static void check_for_empty_rx_ring(struct ena_adapter *adapter) 2892 { 2893 struct ena_ring *rx_ring; 2894 int i, refill_required; 2895 2896 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags)) 2897 return; 2898 2899 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags)) 2900 return; 2901 2902 for (i = 0; i < adapter->num_queues; i++) { 2903 rx_ring = &adapter->rx_ring[i]; 2904 2905 refill_required = 2906 ena_com_free_desc(rx_ring->ena_com_io_sq); 2907 if (unlikely(refill_required == (rx_ring->ring_size - 1))) { 2908 rx_ring->empty_rx_queue++; 2909 2910 if (rx_ring->empty_rx_queue >= EMPTY_RX_REFILL) { 2911 u64_stats_update_begin(&rx_ring->syncp); 2912 rx_ring->rx_stats.empty_rx_ring++; 2913 u64_stats_update_end(&rx_ring->syncp); 2914 2915 netif_err(adapter, drv, adapter->netdev, 2916 "trigger refill for ring %d\n", i); 2917 2918 napi_schedule(rx_ring->napi); 2919 rx_ring->empty_rx_queue = 0; 2920 } 2921 } else { 2922 rx_ring->empty_rx_queue = 0; 2923 } 2924 } 2925 } 2926 2927 /* Check for keep alive expiration */ 2928 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 2929 { 2930 unsigned long keep_alive_expired; 2931 2932 if (!adapter->wd_state) 2933 return; 2934 2935 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT) 2936 return; 2937 2938 keep_alive_expired = round_jiffies(adapter->last_keep_alive_jiffies + 2939 adapter->keep_alive_timeout); 2940 if (unlikely(time_is_before_jiffies(keep_alive_expired))) { 2941 netif_err(adapter, drv, adapter->netdev, 2942 "Keep alive watchdog timeout.\n"); 2943 u64_stats_update_begin(&adapter->syncp); 2944 adapter->dev_stats.wd_expired++; 2945 u64_stats_update_end(&adapter->syncp); 2946 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; 2947 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags); 2948 } 2949 } 2950 2951 static void check_for_admin_com_state(struct ena_adapter *adapter) 2952 { 2953 if (unlikely(!ena_com_get_admin_running_state(adapter->ena_dev))) { 2954 netif_err(adapter, drv, adapter->netdev, 2955 "ENA admin queue is not in running state!\n"); 2956 u64_stats_update_begin(&adapter->syncp); 2957 adapter->dev_stats.admin_q_pause++; 2958 u64_stats_update_end(&adapter->syncp); 2959 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; 2960 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags); 2961 } 2962 } 2963 2964 static void ena_update_hints(struct ena_adapter *adapter, 2965 struct ena_admin_ena_hw_hints *hints) 2966 { 2967 struct net_device *netdev = adapter->netdev; 2968 2969 if (hints->admin_completion_tx_timeout) 2970 adapter->ena_dev->admin_queue.completion_timeout = 2971 hints->admin_completion_tx_timeout * 1000; 2972 2973 if (hints->mmio_read_timeout) 2974 /* convert to usec */ 2975 adapter->ena_dev->mmio_read.reg_read_to = 2976 hints->mmio_read_timeout * 1000; 2977 2978 if (hints->missed_tx_completion_count_threshold_to_reset) 2979 adapter->missing_tx_completion_threshold = 2980 hints->missed_tx_completion_count_threshold_to_reset; 2981 2982 if (hints->missing_tx_completion_timeout) { 2983 if (hints->missing_tx_completion_timeout == ENA_HW_HINTS_NO_TIMEOUT) 2984 adapter->missing_tx_completion_to = ENA_HW_HINTS_NO_TIMEOUT; 2985 else 2986 adapter->missing_tx_completion_to = 2987 msecs_to_jiffies(hints->missing_tx_completion_timeout); 2988 } 2989 2990 if (hints->netdev_wd_timeout) 2991 netdev->watchdog_timeo = msecs_to_jiffies(hints->netdev_wd_timeout); 2992 2993 if (hints->driver_watchdog_timeout) { 2994 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT) 2995 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT; 2996 else 2997 adapter->keep_alive_timeout = 2998 msecs_to_jiffies(hints->driver_watchdog_timeout); 2999 } 3000 } 3001 3002 static void ena_update_host_info(struct ena_admin_host_info *host_info, 3003 struct net_device *netdev) 3004 { 3005 host_info->supported_network_features[0] = 3006 netdev->features & GENMASK_ULL(31, 0); 3007 host_info->supported_network_features[1] = 3008 (netdev->features & GENMASK_ULL(63, 32)) >> 32; 3009 } 3010 3011 static void ena_timer_service(struct timer_list *t) 3012 { 3013 struct ena_adapter *adapter = from_timer(adapter, t, timer_service); 3014 u8 *debug_area = adapter->ena_dev->host_attr.debug_area_virt_addr; 3015 struct ena_admin_host_info *host_info = 3016 adapter->ena_dev->host_attr.host_info; 3017 3018 check_for_missing_keep_alive(adapter); 3019 3020 check_for_admin_com_state(adapter); 3021 3022 check_for_missing_completions(adapter); 3023 3024 check_for_empty_rx_ring(adapter); 3025 3026 if (debug_area) 3027 ena_dump_stats_to_buf(adapter, debug_area); 3028 3029 if (host_info) 3030 ena_update_host_info(host_info, adapter->netdev); 3031 3032 if (unlikely(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) { 3033 netif_err(adapter, drv, adapter->netdev, 3034 "Trigger reset is on\n"); 3035 ena_dump_stats_to_dmesg(adapter); 3036 queue_work(ena_wq, &adapter->reset_task); 3037 return; 3038 } 3039 3040 /* Reset the timer */ 3041 mod_timer(&adapter->timer_service, jiffies + HZ); 3042 } 3043 3044 static int ena_calc_io_queue_num(struct pci_dev *pdev, 3045 struct ena_com_dev *ena_dev, 3046 struct ena_com_dev_get_features_ctx *get_feat_ctx) 3047 { 3048 int io_sq_num, io_queue_num; 3049 3050 /* In case of LLQ use the llq number in the get feature cmd */ 3051 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) 3052 io_sq_num = get_feat_ctx->llq.max_llq_num; 3053 else 3054 io_sq_num = get_feat_ctx->max_queues.max_sq_num; 3055 3056 io_queue_num = min_t(int, num_online_cpus(), ENA_MAX_NUM_IO_QUEUES); 3057 io_queue_num = min_t(int, io_queue_num, io_sq_num); 3058 io_queue_num = min_t(int, io_queue_num, 3059 get_feat_ctx->max_queues.max_cq_num); 3060 /* 1 IRQ for for mgmnt and 1 IRQs for each IO direction */ 3061 io_queue_num = min_t(int, io_queue_num, pci_msix_vec_count(pdev) - 1); 3062 if (unlikely(!io_queue_num)) { 3063 dev_err(&pdev->dev, "The device doesn't have io queues\n"); 3064 return -EFAULT; 3065 } 3066 3067 return io_queue_num; 3068 } 3069 3070 static int ena_set_queues_placement_policy(struct pci_dev *pdev, 3071 struct ena_com_dev *ena_dev, 3072 struct ena_admin_feature_llq_desc *llq, 3073 struct ena_llq_configurations *llq_default_configurations) 3074 { 3075 bool has_mem_bar; 3076 int rc; 3077 u32 llq_feature_mask; 3078 3079 llq_feature_mask = 1 << ENA_ADMIN_LLQ; 3080 if (!(ena_dev->supported_features & llq_feature_mask)) { 3081 dev_err(&pdev->dev, 3082 "LLQ is not supported Fallback to host mode policy.\n"); 3083 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 3084 return 0; 3085 } 3086 3087 has_mem_bar = pci_select_bars(pdev, IORESOURCE_MEM) & BIT(ENA_MEM_BAR); 3088 3089 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations); 3090 if (unlikely(rc)) { 3091 dev_err(&pdev->dev, 3092 "Failed to configure the device mode. Fallback to host mode policy.\n"); 3093 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 3094 return 0; 3095 } 3096 3097 /* Nothing to config, exit */ 3098 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 3099 return 0; 3100 3101 if (!has_mem_bar) { 3102 dev_err(&pdev->dev, 3103 "ENA device does not expose LLQ bar. Fallback to host mode policy.\n"); 3104 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 3105 return 0; 3106 } 3107 3108 ena_dev->mem_bar = devm_ioremap_wc(&pdev->dev, 3109 pci_resource_start(pdev, ENA_MEM_BAR), 3110 pci_resource_len(pdev, ENA_MEM_BAR)); 3111 3112 if (!ena_dev->mem_bar) 3113 return -EFAULT; 3114 3115 return 0; 3116 } 3117 3118 static void ena_set_dev_offloads(struct ena_com_dev_get_features_ctx *feat, 3119 struct net_device *netdev) 3120 { 3121 netdev_features_t dev_features = 0; 3122 3123 /* Set offload features */ 3124 if (feat->offload.tx & 3125 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) 3126 dev_features |= NETIF_F_IP_CSUM; 3127 3128 if (feat->offload.tx & 3129 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) 3130 dev_features |= NETIF_F_IPV6_CSUM; 3131 3132 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) 3133 dev_features |= NETIF_F_TSO; 3134 3135 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) 3136 dev_features |= NETIF_F_TSO6; 3137 3138 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK) 3139 dev_features |= NETIF_F_TSO_ECN; 3140 3141 if (feat->offload.rx_supported & 3142 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) 3143 dev_features |= NETIF_F_RXCSUM; 3144 3145 if (feat->offload.rx_supported & 3146 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) 3147 dev_features |= NETIF_F_RXCSUM; 3148 3149 netdev->features = 3150 dev_features | 3151 NETIF_F_SG | 3152 NETIF_F_RXHASH | 3153 NETIF_F_HIGHDMA; 3154 3155 netdev->hw_features |= netdev->features; 3156 netdev->vlan_features |= netdev->features; 3157 } 3158 3159 static void ena_set_conf_feat_params(struct ena_adapter *adapter, 3160 struct ena_com_dev_get_features_ctx *feat) 3161 { 3162 struct net_device *netdev = adapter->netdev; 3163 3164 /* Copy mac address */ 3165 if (!is_valid_ether_addr(feat->dev_attr.mac_addr)) { 3166 eth_hw_addr_random(netdev); 3167 ether_addr_copy(adapter->mac_addr, netdev->dev_addr); 3168 } else { 3169 ether_addr_copy(adapter->mac_addr, feat->dev_attr.mac_addr); 3170 ether_addr_copy(netdev->dev_addr, adapter->mac_addr); 3171 } 3172 3173 /* Set offload features */ 3174 ena_set_dev_offloads(feat, netdev); 3175 3176 adapter->max_mtu = feat->dev_attr.max_mtu; 3177 netdev->max_mtu = adapter->max_mtu; 3178 netdev->min_mtu = ENA_MIN_MTU; 3179 } 3180 3181 static int ena_rss_init_default(struct ena_adapter *adapter) 3182 { 3183 struct ena_com_dev *ena_dev = adapter->ena_dev; 3184 struct device *dev = &adapter->pdev->dev; 3185 int rc, i; 3186 u32 val; 3187 3188 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 3189 if (unlikely(rc)) { 3190 dev_err(dev, "Cannot init indirect table\n"); 3191 goto err_rss_init; 3192 } 3193 3194 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 3195 val = ethtool_rxfh_indir_default(i, adapter->num_queues); 3196 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 3197 ENA_IO_RXQ_IDX(val)); 3198 if (unlikely(rc && (rc != -EOPNOTSUPP))) { 3199 dev_err(dev, "Cannot fill indirect table\n"); 3200 goto err_fill_indir; 3201 } 3202 } 3203 3204 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 3205 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 3206 if (unlikely(rc && (rc != -EOPNOTSUPP))) { 3207 dev_err(dev, "Cannot fill hash function\n"); 3208 goto err_fill_indir; 3209 } 3210 3211 rc = ena_com_set_default_hash_ctrl(ena_dev); 3212 if (unlikely(rc && (rc != -EOPNOTSUPP))) { 3213 dev_err(dev, "Cannot fill hash control\n"); 3214 goto err_fill_indir; 3215 } 3216 3217 return 0; 3218 3219 err_fill_indir: 3220 ena_com_rss_destroy(ena_dev); 3221 err_rss_init: 3222 3223 return rc; 3224 } 3225 3226 static void ena_release_bars(struct ena_com_dev *ena_dev, struct pci_dev *pdev) 3227 { 3228 int release_bars = pci_select_bars(pdev, IORESOURCE_MEM) & ENA_BAR_MASK; 3229 3230 pci_release_selected_regions(pdev, release_bars); 3231 } 3232 3233 static inline void set_default_llq_configurations(struct ena_llq_configurations *llq_config) 3234 { 3235 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER; 3236 llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B; 3237 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY; 3238 llq_config->llq_num_decs_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2; 3239 llq_config->llq_ring_entry_size_value = 128; 3240 } 3241 3242 static int ena_calc_queue_size(struct pci_dev *pdev, 3243 struct ena_com_dev *ena_dev, 3244 u16 *max_tx_sgl_size, 3245 u16 *max_rx_sgl_size, 3246 struct ena_com_dev_get_features_ctx *get_feat_ctx) 3247 { 3248 u32 queue_size = ENA_DEFAULT_RING_SIZE; 3249 3250 queue_size = min_t(u32, queue_size, 3251 get_feat_ctx->max_queues.max_cq_depth); 3252 queue_size = min_t(u32, queue_size, 3253 get_feat_ctx->max_queues.max_sq_depth); 3254 3255 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) 3256 queue_size = min_t(u32, queue_size, 3257 get_feat_ctx->llq.max_llq_depth); 3258 3259 queue_size = rounddown_pow_of_two(queue_size); 3260 3261 if (unlikely(!queue_size)) { 3262 dev_err(&pdev->dev, "Invalid queue size\n"); 3263 return -EFAULT; 3264 } 3265 3266 *max_tx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS, 3267 get_feat_ctx->max_queues.max_packet_tx_descs); 3268 *max_rx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS, 3269 get_feat_ctx->max_queues.max_packet_rx_descs); 3270 3271 return queue_size; 3272 } 3273 3274 /* ena_probe - Device Initialization Routine 3275 * @pdev: PCI device information struct 3276 * @ent: entry in ena_pci_tbl 3277 * 3278 * Returns 0 on success, negative on failure 3279 * 3280 * ena_probe initializes an adapter identified by a pci_dev structure. 3281 * The OS initialization, configuring of the adapter private structure, 3282 * and a hardware reset occur. 3283 */ 3284 static int ena_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 3285 { 3286 struct ena_com_dev_get_features_ctx get_feat_ctx; 3287 struct ena_llq_configurations llq_config; 3288 struct ena_com_dev *ena_dev = NULL; 3289 struct ena_adapter *adapter; 3290 int io_queue_num, bars, rc; 3291 struct net_device *netdev; 3292 static int adapters_found; 3293 char *queue_type_str; 3294 u16 tx_sgl_size = 0; 3295 u16 rx_sgl_size = 0; 3296 int queue_size; 3297 bool wd_state; 3298 3299 dev_dbg(&pdev->dev, "%s\n", __func__); 3300 3301 dev_info_once(&pdev->dev, "%s", version); 3302 3303 rc = pci_enable_device_mem(pdev); 3304 if (rc) { 3305 dev_err(&pdev->dev, "pci_enable_device_mem() failed!\n"); 3306 return rc; 3307 } 3308 3309 pci_set_master(pdev); 3310 3311 ena_dev = vzalloc(sizeof(*ena_dev)); 3312 if (!ena_dev) { 3313 rc = -ENOMEM; 3314 goto err_disable_device; 3315 } 3316 3317 bars = pci_select_bars(pdev, IORESOURCE_MEM) & ENA_BAR_MASK; 3318 rc = pci_request_selected_regions(pdev, bars, DRV_MODULE_NAME); 3319 if (rc) { 3320 dev_err(&pdev->dev, "pci_request_selected_regions failed %d\n", 3321 rc); 3322 goto err_free_ena_dev; 3323 } 3324 3325 ena_dev->reg_bar = devm_ioremap(&pdev->dev, 3326 pci_resource_start(pdev, ENA_REG_BAR), 3327 pci_resource_len(pdev, ENA_REG_BAR)); 3328 if (!ena_dev->reg_bar) { 3329 dev_err(&pdev->dev, "failed to remap regs bar\n"); 3330 rc = -EFAULT; 3331 goto err_free_region; 3332 } 3333 3334 ena_dev->dmadev = &pdev->dev; 3335 3336 rc = ena_device_init(ena_dev, pdev, &get_feat_ctx, &wd_state); 3337 if (rc) { 3338 dev_err(&pdev->dev, "ena device init failed\n"); 3339 if (rc == -ETIME) 3340 rc = -EPROBE_DEFER; 3341 goto err_free_region; 3342 } 3343 3344 set_default_llq_configurations(&llq_config); 3345 3346 rc = ena_set_queues_placement_policy(pdev, ena_dev, &get_feat_ctx.llq, 3347 &llq_config); 3348 if (rc) { 3349 dev_err(&pdev->dev, "ena device init failed\n"); 3350 goto err_device_destroy; 3351 } 3352 3353 /* initial Tx interrupt delay, Assumes 1 usec granularity. 3354 * Updated during device initialization with the real granularity 3355 */ 3356 ena_dev->intr_moder_tx_interval = ENA_INTR_INITIAL_TX_INTERVAL_USECS; 3357 io_queue_num = ena_calc_io_queue_num(pdev, ena_dev, &get_feat_ctx); 3358 queue_size = ena_calc_queue_size(pdev, ena_dev, &tx_sgl_size, 3359 &rx_sgl_size, &get_feat_ctx); 3360 if ((queue_size <= 0) || (io_queue_num <= 0)) { 3361 rc = -EFAULT; 3362 goto err_device_destroy; 3363 } 3364 3365 dev_info(&pdev->dev, "creating %d io queues. queue size: %d. LLQ is %s\n", 3366 io_queue_num, queue_size, 3367 (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) ? 3368 "ENABLED" : "DISABLED"); 3369 3370 /* dev zeroed in init_etherdev */ 3371 netdev = alloc_etherdev_mq(sizeof(struct ena_adapter), io_queue_num); 3372 if (!netdev) { 3373 dev_err(&pdev->dev, "alloc_etherdev_mq failed\n"); 3374 rc = -ENOMEM; 3375 goto err_device_destroy; 3376 } 3377 3378 SET_NETDEV_DEV(netdev, &pdev->dev); 3379 3380 adapter = netdev_priv(netdev); 3381 pci_set_drvdata(pdev, adapter); 3382 3383 adapter->ena_dev = ena_dev; 3384 adapter->netdev = netdev; 3385 adapter->pdev = pdev; 3386 3387 ena_set_conf_feat_params(adapter, &get_feat_ctx); 3388 3389 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 3390 adapter->reset_reason = ENA_REGS_RESET_NORMAL; 3391 3392 adapter->tx_ring_size = queue_size; 3393 adapter->rx_ring_size = queue_size; 3394 3395 adapter->max_tx_sgl_size = tx_sgl_size; 3396 adapter->max_rx_sgl_size = rx_sgl_size; 3397 3398 adapter->num_queues = io_queue_num; 3399 adapter->last_monitored_tx_qid = 0; 3400 3401 adapter->rx_copybreak = ENA_DEFAULT_RX_COPYBREAK; 3402 adapter->wd_state = wd_state; 3403 3404 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", adapters_found); 3405 3406 rc = ena_com_init_interrupt_moderation(adapter->ena_dev); 3407 if (rc) { 3408 dev_err(&pdev->dev, 3409 "Failed to query interrupt moderation feature\n"); 3410 goto err_netdev_destroy; 3411 } 3412 ena_init_io_rings(adapter); 3413 3414 netdev->netdev_ops = &ena_netdev_ops; 3415 netdev->watchdog_timeo = TX_TIMEOUT; 3416 ena_set_ethtool_ops(netdev); 3417 3418 netdev->priv_flags |= IFF_UNICAST_FLT; 3419 3420 u64_stats_init(&adapter->syncp); 3421 3422 rc = ena_enable_msix_and_set_admin_interrupts(adapter, io_queue_num); 3423 if (rc) { 3424 dev_err(&pdev->dev, 3425 "Failed to enable and set the admin interrupts\n"); 3426 goto err_worker_destroy; 3427 } 3428 rc = ena_rss_init_default(adapter); 3429 if (rc && (rc != -EOPNOTSUPP)) { 3430 dev_err(&pdev->dev, "Cannot init RSS rc: %d\n", rc); 3431 goto err_free_msix; 3432 } 3433 3434 ena_config_debug_area(adapter); 3435 3436 adapter->ena_extra_properties_count = 3437 ena_com_extra_properties_strings_init(ena_dev); 3438 3439 memcpy(adapter->netdev->perm_addr, adapter->mac_addr, netdev->addr_len); 3440 3441 netif_carrier_off(netdev); 3442 3443 rc = register_netdev(netdev); 3444 if (rc) { 3445 dev_err(&pdev->dev, "Cannot register net device\n"); 3446 goto err_rss; 3447 } 3448 3449 INIT_WORK(&adapter->reset_task, ena_fw_reset_device); 3450 3451 adapter->last_keep_alive_jiffies = jiffies; 3452 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT; 3453 adapter->missing_tx_completion_to = TX_TIMEOUT; 3454 adapter->missing_tx_completion_threshold = MAX_NUM_OF_TIMEOUTED_PACKETS; 3455 3456 ena_update_hints(adapter, &get_feat_ctx.hw_hints); 3457 3458 timer_setup(&adapter->timer_service, ena_timer_service, 0); 3459 mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ)); 3460 3461 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 3462 queue_type_str = "Regular"; 3463 else 3464 queue_type_str = "Low Latency"; 3465 3466 dev_info(&pdev->dev, 3467 "%s found at mem %lx, mac addr %pM Queues %d, Placement policy: %s\n", 3468 DEVICE_NAME, (long)pci_resource_start(pdev, 0), 3469 netdev->dev_addr, io_queue_num, queue_type_str); 3470 3471 set_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags); 3472 3473 adapters_found++; 3474 3475 return 0; 3476 3477 err_rss: 3478 ena_extra_properties_strings_destroy(netdev); 3479 ena_com_delete_debug_area(ena_dev); 3480 ena_com_rss_destroy(ena_dev); 3481 err_free_msix: 3482 ena_com_dev_reset(ena_dev, ENA_REGS_RESET_INIT_ERR); 3483 /* stop submitting admin commands on a device that was reset */ 3484 ena_com_set_admin_running_state(ena_dev, false); 3485 ena_free_mgmnt_irq(adapter); 3486 ena_disable_msix(adapter); 3487 err_worker_destroy: 3488 ena_com_destroy_interrupt_moderation(ena_dev); 3489 del_timer(&adapter->timer_service); 3490 err_netdev_destroy: 3491 free_netdev(netdev); 3492 err_device_destroy: 3493 ena_com_delete_host_info(ena_dev); 3494 ena_com_admin_destroy(ena_dev); 3495 err_free_region: 3496 ena_release_bars(ena_dev, pdev); 3497 err_free_ena_dev: 3498 vfree(ena_dev); 3499 err_disable_device: 3500 pci_disable_device(pdev); 3501 return rc; 3502 } 3503 3504 /*****************************************************************************/ 3505 3506 /* ena_remove - Device Removal Routine 3507 * @pdev: PCI device information struct 3508 * 3509 * ena_remove is called by the PCI subsystem to alert the driver 3510 * that it should release a PCI device. 3511 */ 3512 static void ena_remove(struct pci_dev *pdev) 3513 { 3514 struct ena_adapter *adapter = pci_get_drvdata(pdev); 3515 struct ena_com_dev *ena_dev; 3516 struct net_device *netdev; 3517 3518 ena_dev = adapter->ena_dev; 3519 netdev = adapter->netdev; 3520 3521 #ifdef CONFIG_RFS_ACCEL 3522 if ((adapter->msix_vecs >= 1) && (netdev->rx_cpu_rmap)) { 3523 free_irq_cpu_rmap(netdev->rx_cpu_rmap); 3524 netdev->rx_cpu_rmap = NULL; 3525 } 3526 #endif /* CONFIG_RFS_ACCEL */ 3527 del_timer_sync(&adapter->timer_service); 3528 3529 cancel_work_sync(&adapter->reset_task); 3530 3531 rtnl_lock(); 3532 ena_destroy_device(adapter, true); 3533 rtnl_unlock(); 3534 3535 unregister_netdev(netdev); 3536 3537 free_netdev(netdev); 3538 3539 ena_com_rss_destroy(ena_dev); 3540 3541 ena_com_delete_debug_area(ena_dev); 3542 3543 ena_com_delete_host_info(ena_dev); 3544 3545 ena_extra_properties_strings_destroy(netdev); 3546 3547 ena_release_bars(ena_dev, pdev); 3548 3549 pci_disable_device(pdev); 3550 3551 ena_com_destroy_interrupt_moderation(ena_dev); 3552 3553 vfree(ena_dev); 3554 } 3555 3556 #ifdef CONFIG_PM 3557 /* ena_suspend - PM suspend callback 3558 * @pdev: PCI device information struct 3559 * @state:power state 3560 */ 3561 static int ena_suspend(struct pci_dev *pdev, pm_message_t state) 3562 { 3563 struct ena_adapter *adapter = pci_get_drvdata(pdev); 3564 3565 u64_stats_update_begin(&adapter->syncp); 3566 adapter->dev_stats.suspend++; 3567 u64_stats_update_end(&adapter->syncp); 3568 3569 rtnl_lock(); 3570 if (unlikely(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) { 3571 dev_err(&pdev->dev, 3572 "ignoring device reset request as the device is being suspended\n"); 3573 clear_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags); 3574 } 3575 ena_destroy_device(adapter, true); 3576 rtnl_unlock(); 3577 return 0; 3578 } 3579 3580 /* ena_resume - PM resume callback 3581 * @pdev: PCI device information struct 3582 * 3583 */ 3584 static int ena_resume(struct pci_dev *pdev) 3585 { 3586 struct ena_adapter *adapter = pci_get_drvdata(pdev); 3587 int rc; 3588 3589 u64_stats_update_begin(&adapter->syncp); 3590 adapter->dev_stats.resume++; 3591 u64_stats_update_end(&adapter->syncp); 3592 3593 rtnl_lock(); 3594 rc = ena_restore_device(adapter); 3595 rtnl_unlock(); 3596 return rc; 3597 } 3598 #endif 3599 3600 static struct pci_driver ena_pci_driver = { 3601 .name = DRV_MODULE_NAME, 3602 .id_table = ena_pci_tbl, 3603 .probe = ena_probe, 3604 .remove = ena_remove, 3605 #ifdef CONFIG_PM 3606 .suspend = ena_suspend, 3607 .resume = ena_resume, 3608 #endif 3609 .sriov_configure = pci_sriov_configure_simple, 3610 }; 3611 3612 static int __init ena_init(void) 3613 { 3614 pr_info("%s", version); 3615 3616 ena_wq = create_singlethread_workqueue(DRV_MODULE_NAME); 3617 if (!ena_wq) { 3618 pr_err("Failed to create workqueue\n"); 3619 return -ENOMEM; 3620 } 3621 3622 return pci_register_driver(&ena_pci_driver); 3623 } 3624 3625 static void __exit ena_cleanup(void) 3626 { 3627 pci_unregister_driver(&ena_pci_driver); 3628 3629 if (ena_wq) { 3630 destroy_workqueue(ena_wq); 3631 ena_wq = NULL; 3632 } 3633 } 3634 3635 /****************************************************************************** 3636 ******************************** AENQ Handlers ******************************* 3637 *****************************************************************************/ 3638 /* ena_update_on_link_change: 3639 * Notify the network interface about the change in link status 3640 */ 3641 static void ena_update_on_link_change(void *adapter_data, 3642 struct ena_admin_aenq_entry *aenq_e) 3643 { 3644 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 3645 struct ena_admin_aenq_link_change_desc *aenq_desc = 3646 (struct ena_admin_aenq_link_change_desc *)aenq_e; 3647 int status = aenq_desc->flags & 3648 ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK; 3649 3650 if (status) { 3651 netdev_dbg(adapter->netdev, "%s\n", __func__); 3652 set_bit(ENA_FLAG_LINK_UP, &adapter->flags); 3653 if (!test_bit(ENA_FLAG_ONGOING_RESET, &adapter->flags)) 3654 netif_carrier_on(adapter->netdev); 3655 } else { 3656 clear_bit(ENA_FLAG_LINK_UP, &adapter->flags); 3657 netif_carrier_off(adapter->netdev); 3658 } 3659 } 3660 3661 static void ena_keep_alive_wd(void *adapter_data, 3662 struct ena_admin_aenq_entry *aenq_e) 3663 { 3664 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 3665 struct ena_admin_aenq_keep_alive_desc *desc; 3666 u64 rx_drops; 3667 3668 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; 3669 adapter->last_keep_alive_jiffies = jiffies; 3670 3671 rx_drops = ((u64)desc->rx_drops_high << 32) | desc->rx_drops_low; 3672 3673 u64_stats_update_begin(&adapter->syncp); 3674 adapter->dev_stats.rx_drops = rx_drops; 3675 u64_stats_update_end(&adapter->syncp); 3676 } 3677 3678 static void ena_notification(void *adapter_data, 3679 struct ena_admin_aenq_entry *aenq_e) 3680 { 3681 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data; 3682 struct ena_admin_ena_hw_hints *hints; 3683 3684 WARN(aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION, 3685 "Invalid group(%x) expected %x\n", 3686 aenq_e->aenq_common_desc.group, 3687 ENA_ADMIN_NOTIFICATION); 3688 3689 switch (aenq_e->aenq_common_desc.syndrom) { 3690 case ENA_ADMIN_UPDATE_HINTS: 3691 hints = (struct ena_admin_ena_hw_hints *) 3692 (&aenq_e->inline_data_w4); 3693 ena_update_hints(adapter, hints); 3694 break; 3695 default: 3696 netif_err(adapter, drv, adapter->netdev, 3697 "Invalid aenq notification link state %d\n", 3698 aenq_e->aenq_common_desc.syndrom); 3699 } 3700 } 3701 3702 /* This handler will called for unknown event group or unimplemented handlers*/ 3703 static void unimplemented_aenq_handler(void *data, 3704 struct ena_admin_aenq_entry *aenq_e) 3705 { 3706 struct ena_adapter *adapter = (struct ena_adapter *)data; 3707 3708 netif_err(adapter, drv, adapter->netdev, 3709 "Unknown event was received or event with unimplemented handler\n"); 3710 } 3711 3712 static struct ena_aenq_handlers aenq_handlers = { 3713 .handlers = { 3714 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 3715 [ENA_ADMIN_NOTIFICATION] = ena_notification, 3716 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive_wd, 3717 }, 3718 .unimplemented_handler = unimplemented_aenq_handler 3719 }; 3720 3721 module_init(ena_init); 3722 module_exit(ena_cleanup); 3723