1 /* 2 * Copyright 2015 Amazon.com, Inc. or its affiliates. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include "ena_com.h" 34 35 /*****************************************************************************/ 36 /*****************************************************************************/ 37 38 /* Timeout in micro-sec */ 39 #define ADMIN_CMD_TIMEOUT_US (3000000) 40 41 #define ENA_ASYNC_QUEUE_DEPTH 16 42 #define ENA_ADMIN_QUEUE_DEPTH 32 43 44 45 #define ENA_CTRL_MAJOR 0 46 #define ENA_CTRL_MINOR 0 47 #define ENA_CTRL_SUB_MINOR 1 48 49 #define MIN_ENA_CTRL_VER \ 50 (((ENA_CTRL_MAJOR) << \ 51 (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \ 52 ((ENA_CTRL_MINOR) << \ 53 (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \ 54 (ENA_CTRL_SUB_MINOR)) 55 56 #define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x))) 57 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32)) 58 59 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF 60 61 #define ENA_COM_BOUNCE_BUFFER_CNTRL_CNT 4 62 63 #define ENA_REGS_ADMIN_INTR_MASK 1 64 65 #define ENA_POLL_MS 5 66 67 /*****************************************************************************/ 68 /*****************************************************************************/ 69 /*****************************************************************************/ 70 71 enum ena_cmd_status { 72 ENA_CMD_SUBMITTED, 73 ENA_CMD_COMPLETED, 74 /* Abort - canceled by the driver */ 75 ENA_CMD_ABORTED, 76 }; 77 78 struct ena_comp_ctx { 79 struct completion wait_event; 80 struct ena_admin_acq_entry *user_cqe; 81 u32 comp_size; 82 enum ena_cmd_status status; 83 /* status from the device */ 84 u8 comp_status; 85 u8 cmd_opcode; 86 bool occupied; 87 }; 88 89 struct ena_com_stats_ctx { 90 struct ena_admin_aq_get_stats_cmd get_cmd; 91 struct ena_admin_acq_get_stats_resp get_resp; 92 }; 93 94 static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev, 95 struct ena_common_mem_addr *ena_addr, 96 dma_addr_t addr) 97 { 98 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) { 99 pr_err("dma address has more bits that the device supports\n"); 100 return -EINVAL; 101 } 102 103 ena_addr->mem_addr_low = lower_32_bits(addr); 104 ena_addr->mem_addr_high = (u16)upper_32_bits(addr); 105 106 return 0; 107 } 108 109 static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue) 110 { 111 struct ena_com_admin_sq *sq = &queue->sq; 112 u16 size = ADMIN_SQ_SIZE(queue->q_depth); 113 114 sq->entries = dma_alloc_coherent(queue->q_dmadev, size, &sq->dma_addr, 115 GFP_KERNEL); 116 117 if (!sq->entries) { 118 pr_err("memory allocation failed\n"); 119 return -ENOMEM; 120 } 121 122 sq->head = 0; 123 sq->tail = 0; 124 sq->phase = 1; 125 126 sq->db_addr = NULL; 127 128 return 0; 129 } 130 131 static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue) 132 { 133 struct ena_com_admin_cq *cq = &queue->cq; 134 u16 size = ADMIN_CQ_SIZE(queue->q_depth); 135 136 cq->entries = dma_alloc_coherent(queue->q_dmadev, size, &cq->dma_addr, 137 GFP_KERNEL); 138 139 if (!cq->entries) { 140 pr_err("memory allocation failed\n"); 141 return -ENOMEM; 142 } 143 144 cq->head = 0; 145 cq->phase = 1; 146 147 return 0; 148 } 149 150 static int ena_com_admin_init_aenq(struct ena_com_dev *dev, 151 struct ena_aenq_handlers *aenq_handlers) 152 { 153 struct ena_com_aenq *aenq = &dev->aenq; 154 u32 addr_low, addr_high, aenq_caps; 155 u16 size; 156 157 dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH; 158 size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH); 159 aenq->entries = dma_alloc_coherent(dev->dmadev, size, &aenq->dma_addr, 160 GFP_KERNEL); 161 162 if (!aenq->entries) { 163 pr_err("memory allocation failed\n"); 164 return -ENOMEM; 165 } 166 167 aenq->head = aenq->q_depth; 168 aenq->phase = 1; 169 170 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr); 171 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr); 172 173 writel(addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF); 174 writel(addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF); 175 176 aenq_caps = 0; 177 aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK; 178 aenq_caps |= (sizeof(struct ena_admin_aenq_entry) 179 << ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) & 180 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK; 181 writel(aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF); 182 183 if (unlikely(!aenq_handlers)) { 184 pr_err("aenq handlers pointer is NULL\n"); 185 return -EINVAL; 186 } 187 188 aenq->aenq_handlers = aenq_handlers; 189 190 return 0; 191 } 192 193 static void comp_ctxt_release(struct ena_com_admin_queue *queue, 194 struct ena_comp_ctx *comp_ctx) 195 { 196 comp_ctx->occupied = false; 197 atomic_dec(&queue->outstanding_cmds); 198 } 199 200 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue, 201 u16 command_id, bool capture) 202 { 203 if (unlikely(!queue->comp_ctx)) { 204 pr_err("Completion context is NULL\n"); 205 return NULL; 206 } 207 208 if (unlikely(command_id >= queue->q_depth)) { 209 pr_err("command id is larger than the queue size. cmd_id: %u queue size %d\n", 210 command_id, queue->q_depth); 211 return NULL; 212 } 213 214 if (unlikely(queue->comp_ctx[command_id].occupied && capture)) { 215 pr_err("Completion context is occupied\n"); 216 return NULL; 217 } 218 219 if (capture) { 220 atomic_inc(&queue->outstanding_cmds); 221 queue->comp_ctx[command_id].occupied = true; 222 } 223 224 return &queue->comp_ctx[command_id]; 225 } 226 227 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue, 228 struct ena_admin_aq_entry *cmd, 229 size_t cmd_size_in_bytes, 230 struct ena_admin_acq_entry *comp, 231 size_t comp_size_in_bytes) 232 { 233 struct ena_comp_ctx *comp_ctx; 234 u16 tail_masked, cmd_id; 235 u16 queue_size_mask; 236 u16 cnt; 237 238 queue_size_mask = admin_queue->q_depth - 1; 239 240 tail_masked = admin_queue->sq.tail & queue_size_mask; 241 242 /* In case of queue FULL */ 243 cnt = (u16)atomic_read(&admin_queue->outstanding_cmds); 244 if (cnt >= admin_queue->q_depth) { 245 pr_debug("admin queue is full.\n"); 246 admin_queue->stats.out_of_space++; 247 return ERR_PTR(-ENOSPC); 248 } 249 250 cmd_id = admin_queue->curr_cmd_id; 251 252 cmd->aq_common_descriptor.flags |= admin_queue->sq.phase & 253 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK; 254 255 cmd->aq_common_descriptor.command_id |= cmd_id & 256 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK; 257 258 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true); 259 if (unlikely(!comp_ctx)) 260 return ERR_PTR(-EINVAL); 261 262 comp_ctx->status = ENA_CMD_SUBMITTED; 263 comp_ctx->comp_size = (u32)comp_size_in_bytes; 264 comp_ctx->user_cqe = comp; 265 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode; 266 267 reinit_completion(&comp_ctx->wait_event); 268 269 memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes); 270 271 admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) & 272 queue_size_mask; 273 274 admin_queue->sq.tail++; 275 admin_queue->stats.submitted_cmd++; 276 277 if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0)) 278 admin_queue->sq.phase = !admin_queue->sq.phase; 279 280 writel(admin_queue->sq.tail, admin_queue->sq.db_addr); 281 282 return comp_ctx; 283 } 284 285 static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue) 286 { 287 size_t size = queue->q_depth * sizeof(struct ena_comp_ctx); 288 struct ena_comp_ctx *comp_ctx; 289 u16 i; 290 291 queue->comp_ctx = devm_kzalloc(queue->q_dmadev, size, GFP_KERNEL); 292 if (unlikely(!queue->comp_ctx)) { 293 pr_err("memory allocation failed\n"); 294 return -ENOMEM; 295 } 296 297 for (i = 0; i < queue->q_depth; i++) { 298 comp_ctx = get_comp_ctxt(queue, i, false); 299 if (comp_ctx) 300 init_completion(&comp_ctx->wait_event); 301 } 302 303 return 0; 304 } 305 306 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue, 307 struct ena_admin_aq_entry *cmd, 308 size_t cmd_size_in_bytes, 309 struct ena_admin_acq_entry *comp, 310 size_t comp_size_in_bytes) 311 { 312 unsigned long flags = 0; 313 struct ena_comp_ctx *comp_ctx; 314 315 spin_lock_irqsave(&admin_queue->q_lock, flags); 316 if (unlikely(!admin_queue->running_state)) { 317 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 318 return ERR_PTR(-ENODEV); 319 } 320 comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd, 321 cmd_size_in_bytes, 322 comp, 323 comp_size_in_bytes); 324 if (IS_ERR(comp_ctx)) 325 admin_queue->running_state = false; 326 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 327 328 return comp_ctx; 329 } 330 331 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev, 332 struct ena_com_create_io_ctx *ctx, 333 struct ena_com_io_sq *io_sq) 334 { 335 size_t size; 336 int dev_node = 0; 337 338 memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr)); 339 340 io_sq->dma_addr_bits = (u8)ena_dev->dma_addr_bits; 341 io_sq->desc_entry_size = 342 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ? 343 sizeof(struct ena_eth_io_tx_desc) : 344 sizeof(struct ena_eth_io_rx_desc); 345 346 size = io_sq->desc_entry_size * io_sq->q_depth; 347 348 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) { 349 dev_node = dev_to_node(ena_dev->dmadev); 350 set_dev_node(ena_dev->dmadev, ctx->numa_node); 351 io_sq->desc_addr.virt_addr = 352 dma_alloc_coherent(ena_dev->dmadev, size, 353 &io_sq->desc_addr.phys_addr, 354 GFP_KERNEL); 355 set_dev_node(ena_dev->dmadev, dev_node); 356 if (!io_sq->desc_addr.virt_addr) { 357 io_sq->desc_addr.virt_addr = 358 dma_alloc_coherent(ena_dev->dmadev, size, 359 &io_sq->desc_addr.phys_addr, 360 GFP_KERNEL); 361 } 362 363 if (!io_sq->desc_addr.virt_addr) { 364 pr_err("memory allocation failed\n"); 365 return -ENOMEM; 366 } 367 } 368 369 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 370 /* Allocate bounce buffers */ 371 io_sq->bounce_buf_ctrl.buffer_size = 372 ena_dev->llq_info.desc_list_entry_size; 373 io_sq->bounce_buf_ctrl.buffers_num = 374 ENA_COM_BOUNCE_BUFFER_CNTRL_CNT; 375 io_sq->bounce_buf_ctrl.next_to_use = 0; 376 377 size = io_sq->bounce_buf_ctrl.buffer_size * 378 io_sq->bounce_buf_ctrl.buffers_num; 379 380 dev_node = dev_to_node(ena_dev->dmadev); 381 set_dev_node(ena_dev->dmadev, ctx->numa_node); 382 io_sq->bounce_buf_ctrl.base_buffer = 383 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL); 384 set_dev_node(ena_dev->dmadev, dev_node); 385 if (!io_sq->bounce_buf_ctrl.base_buffer) 386 io_sq->bounce_buf_ctrl.base_buffer = 387 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL); 388 389 if (!io_sq->bounce_buf_ctrl.base_buffer) { 390 pr_err("bounce buffer memory allocation failed\n"); 391 return -ENOMEM; 392 } 393 394 memcpy(&io_sq->llq_info, &ena_dev->llq_info, 395 sizeof(io_sq->llq_info)); 396 397 /* Initiate the first bounce buffer */ 398 io_sq->llq_buf_ctrl.curr_bounce_buf = 399 ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl); 400 memset(io_sq->llq_buf_ctrl.curr_bounce_buf, 401 0x0, io_sq->llq_info.desc_list_entry_size); 402 io_sq->llq_buf_ctrl.descs_left_in_line = 403 io_sq->llq_info.descs_num_before_header; 404 405 if (io_sq->llq_info.max_entries_in_tx_burst > 0) 406 io_sq->entries_in_tx_burst_left = 407 io_sq->llq_info.max_entries_in_tx_burst; 408 } 409 410 io_sq->tail = 0; 411 io_sq->next_to_comp = 0; 412 io_sq->phase = 1; 413 414 return 0; 415 } 416 417 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev, 418 struct ena_com_create_io_ctx *ctx, 419 struct ena_com_io_cq *io_cq) 420 { 421 size_t size; 422 int prev_node = 0; 423 424 memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr)); 425 426 /* Use the basic completion descriptor for Rx */ 427 io_cq->cdesc_entry_size_in_bytes = 428 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ? 429 sizeof(struct ena_eth_io_tx_cdesc) : 430 sizeof(struct ena_eth_io_rx_cdesc_base); 431 432 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth; 433 434 prev_node = dev_to_node(ena_dev->dmadev); 435 set_dev_node(ena_dev->dmadev, ctx->numa_node); 436 io_cq->cdesc_addr.virt_addr = 437 dma_alloc_coherent(ena_dev->dmadev, size, 438 &io_cq->cdesc_addr.phys_addr, GFP_KERNEL); 439 set_dev_node(ena_dev->dmadev, prev_node); 440 if (!io_cq->cdesc_addr.virt_addr) { 441 io_cq->cdesc_addr.virt_addr = 442 dma_alloc_coherent(ena_dev->dmadev, size, 443 &io_cq->cdesc_addr.phys_addr, 444 GFP_KERNEL); 445 } 446 447 if (!io_cq->cdesc_addr.virt_addr) { 448 pr_err("memory allocation failed\n"); 449 return -ENOMEM; 450 } 451 452 io_cq->phase = 1; 453 io_cq->head = 0; 454 455 return 0; 456 } 457 458 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue, 459 struct ena_admin_acq_entry *cqe) 460 { 461 struct ena_comp_ctx *comp_ctx; 462 u16 cmd_id; 463 464 cmd_id = cqe->acq_common_descriptor.command & 465 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK; 466 467 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false); 468 if (unlikely(!comp_ctx)) { 469 pr_err("comp_ctx is NULL. Changing the admin queue running state\n"); 470 admin_queue->running_state = false; 471 return; 472 } 473 474 comp_ctx->status = ENA_CMD_COMPLETED; 475 comp_ctx->comp_status = cqe->acq_common_descriptor.status; 476 477 if (comp_ctx->user_cqe) 478 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size); 479 480 if (!admin_queue->polling) 481 complete(&comp_ctx->wait_event); 482 } 483 484 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue) 485 { 486 struct ena_admin_acq_entry *cqe = NULL; 487 u16 comp_num = 0; 488 u16 head_masked; 489 u8 phase; 490 491 head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1); 492 phase = admin_queue->cq.phase; 493 494 cqe = &admin_queue->cq.entries[head_masked]; 495 496 /* Go over all the completions */ 497 while ((READ_ONCE(cqe->acq_common_descriptor.flags) & 498 ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) { 499 /* Do not read the rest of the completion entry before the 500 * phase bit was validated 501 */ 502 dma_rmb(); 503 ena_com_handle_single_admin_completion(admin_queue, cqe); 504 505 head_masked++; 506 comp_num++; 507 if (unlikely(head_masked == admin_queue->q_depth)) { 508 head_masked = 0; 509 phase = !phase; 510 } 511 512 cqe = &admin_queue->cq.entries[head_masked]; 513 } 514 515 admin_queue->cq.head += comp_num; 516 admin_queue->cq.phase = phase; 517 admin_queue->sq.head += comp_num; 518 admin_queue->stats.completed_cmd += comp_num; 519 } 520 521 static int ena_com_comp_status_to_errno(u8 comp_status) 522 { 523 if (unlikely(comp_status != 0)) 524 pr_err("admin command failed[%u]\n", comp_status); 525 526 if (unlikely(comp_status > ENA_ADMIN_UNKNOWN_ERROR)) 527 return -EINVAL; 528 529 switch (comp_status) { 530 case ENA_ADMIN_SUCCESS: 531 return 0; 532 case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE: 533 return -ENOMEM; 534 case ENA_ADMIN_UNSUPPORTED_OPCODE: 535 return -EOPNOTSUPP; 536 case ENA_ADMIN_BAD_OPCODE: 537 case ENA_ADMIN_MALFORMED_REQUEST: 538 case ENA_ADMIN_ILLEGAL_PARAMETER: 539 case ENA_ADMIN_UNKNOWN_ERROR: 540 return -EINVAL; 541 } 542 543 return 0; 544 } 545 546 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx, 547 struct ena_com_admin_queue *admin_queue) 548 { 549 unsigned long flags = 0; 550 unsigned long timeout; 551 int ret; 552 553 timeout = jiffies + usecs_to_jiffies(admin_queue->completion_timeout); 554 555 while (1) { 556 spin_lock_irqsave(&admin_queue->q_lock, flags); 557 ena_com_handle_admin_completion(admin_queue); 558 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 559 560 if (comp_ctx->status != ENA_CMD_SUBMITTED) 561 break; 562 563 if (time_is_before_jiffies(timeout)) { 564 pr_err("Wait for completion (polling) timeout\n"); 565 /* ENA didn't have any completion */ 566 spin_lock_irqsave(&admin_queue->q_lock, flags); 567 admin_queue->stats.no_completion++; 568 admin_queue->running_state = false; 569 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 570 571 ret = -ETIME; 572 goto err; 573 } 574 575 msleep(ENA_POLL_MS); 576 } 577 578 if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) { 579 pr_err("Command was aborted\n"); 580 spin_lock_irqsave(&admin_queue->q_lock, flags); 581 admin_queue->stats.aborted_cmd++; 582 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 583 ret = -ENODEV; 584 goto err; 585 } 586 587 WARN(comp_ctx->status != ENA_CMD_COMPLETED, "Invalid comp status %d\n", 588 comp_ctx->status); 589 590 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status); 591 err: 592 comp_ctxt_release(admin_queue, comp_ctx); 593 return ret; 594 } 595 596 /** 597 * Set the LLQ configurations of the firmware 598 * 599 * The driver provides only the enabled feature values to the device, 600 * which in turn, checks if they are supported. 601 */ 602 static int ena_com_set_llq(struct ena_com_dev *ena_dev) 603 { 604 struct ena_com_admin_queue *admin_queue; 605 struct ena_admin_set_feat_cmd cmd; 606 struct ena_admin_set_feat_resp resp; 607 struct ena_com_llq_info *llq_info = &ena_dev->llq_info; 608 int ret; 609 610 memset(&cmd, 0x0, sizeof(cmd)); 611 admin_queue = &ena_dev->admin_queue; 612 613 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 614 cmd.feat_common.feature_id = ENA_ADMIN_LLQ; 615 616 cmd.u.llq.header_location_ctrl_enabled = llq_info->header_location_ctrl; 617 cmd.u.llq.entry_size_ctrl_enabled = llq_info->desc_list_entry_size_ctrl; 618 cmd.u.llq.desc_num_before_header_enabled = llq_info->descs_num_before_header; 619 cmd.u.llq.descriptors_stride_ctrl_enabled = llq_info->desc_stride_ctrl; 620 621 ret = ena_com_execute_admin_command(admin_queue, 622 (struct ena_admin_aq_entry *)&cmd, 623 sizeof(cmd), 624 (struct ena_admin_acq_entry *)&resp, 625 sizeof(resp)); 626 627 if (unlikely(ret)) 628 pr_err("Failed to set LLQ configurations: %d\n", ret); 629 630 return ret; 631 } 632 633 static int ena_com_config_llq_info(struct ena_com_dev *ena_dev, 634 struct ena_admin_feature_llq_desc *llq_features, 635 struct ena_llq_configurations *llq_default_cfg) 636 { 637 struct ena_com_llq_info *llq_info = &ena_dev->llq_info; 638 u16 supported_feat; 639 int rc; 640 641 memset(llq_info, 0, sizeof(*llq_info)); 642 643 supported_feat = llq_features->header_location_ctrl_supported; 644 645 if (likely(supported_feat & llq_default_cfg->llq_header_location)) { 646 llq_info->header_location_ctrl = 647 llq_default_cfg->llq_header_location; 648 } else { 649 pr_err("Invalid header location control, supported: 0x%x\n", 650 supported_feat); 651 return -EINVAL; 652 } 653 654 if (likely(llq_info->header_location_ctrl == ENA_ADMIN_INLINE_HEADER)) { 655 supported_feat = llq_features->descriptors_stride_ctrl_supported; 656 if (likely(supported_feat & llq_default_cfg->llq_stride_ctrl)) { 657 llq_info->desc_stride_ctrl = llq_default_cfg->llq_stride_ctrl; 658 } else { 659 if (supported_feat & ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) { 660 llq_info->desc_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY; 661 } else if (supported_feat & ENA_ADMIN_SINGLE_DESC_PER_ENTRY) { 662 llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY; 663 } else { 664 pr_err("Invalid desc_stride_ctrl, supported: 0x%x\n", 665 supported_feat); 666 return -EINVAL; 667 } 668 669 pr_err("Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", 670 llq_default_cfg->llq_stride_ctrl, supported_feat, 671 llq_info->desc_stride_ctrl); 672 } 673 } else { 674 llq_info->desc_stride_ctrl = 0; 675 } 676 677 supported_feat = llq_features->entry_size_ctrl_supported; 678 if (likely(supported_feat & llq_default_cfg->llq_ring_entry_size)) { 679 llq_info->desc_list_entry_size_ctrl = llq_default_cfg->llq_ring_entry_size; 680 llq_info->desc_list_entry_size = llq_default_cfg->llq_ring_entry_size_value; 681 } else { 682 if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_128B) { 683 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_128B; 684 llq_info->desc_list_entry_size = 128; 685 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_192B) { 686 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_192B; 687 llq_info->desc_list_entry_size = 192; 688 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_256B) { 689 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_256B; 690 llq_info->desc_list_entry_size = 256; 691 } else { 692 pr_err("Invalid entry_size_ctrl, supported: 0x%x\n", 693 supported_feat); 694 return -EINVAL; 695 } 696 697 pr_err("Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", 698 llq_default_cfg->llq_ring_entry_size, supported_feat, 699 llq_info->desc_list_entry_size); 700 } 701 if (unlikely(llq_info->desc_list_entry_size & 0x7)) { 702 /* The desc list entry size should be whole multiply of 8 703 * This requirement comes from __iowrite64_copy() 704 */ 705 pr_err("illegal entry size %d\n", 706 llq_info->desc_list_entry_size); 707 return -EINVAL; 708 } 709 710 if (llq_info->desc_stride_ctrl == ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) 711 llq_info->descs_per_entry = llq_info->desc_list_entry_size / 712 sizeof(struct ena_eth_io_tx_desc); 713 else 714 llq_info->descs_per_entry = 1; 715 716 supported_feat = llq_features->desc_num_before_header_supported; 717 if (likely(supported_feat & llq_default_cfg->llq_num_decs_before_header)) { 718 llq_info->descs_num_before_header = llq_default_cfg->llq_num_decs_before_header; 719 } else { 720 if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2) { 721 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2; 722 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1) { 723 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1; 724 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4) { 725 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4; 726 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8) { 727 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8; 728 } else { 729 pr_err("Invalid descs_num_before_header, supported: 0x%x\n", 730 supported_feat); 731 return -EINVAL; 732 } 733 734 pr_err("Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", 735 llq_default_cfg->llq_num_decs_before_header, 736 supported_feat, llq_info->descs_num_before_header); 737 } 738 739 llq_info->max_entries_in_tx_burst = 740 (u16)(llq_features->max_tx_burst_size / llq_default_cfg->llq_ring_entry_size_value); 741 742 rc = ena_com_set_llq(ena_dev); 743 if (rc) 744 pr_err("Cannot set LLQ configuration: %d\n", rc); 745 746 return rc; 747 } 748 749 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx, 750 struct ena_com_admin_queue *admin_queue) 751 { 752 unsigned long flags = 0; 753 int ret; 754 755 wait_for_completion_timeout(&comp_ctx->wait_event, 756 usecs_to_jiffies( 757 admin_queue->completion_timeout)); 758 759 /* In case the command wasn't completed find out the root cause. 760 * There might be 2 kinds of errors 761 * 1) No completion (timeout reached) 762 * 2) There is completion but the device didn't get any msi-x interrupt. 763 */ 764 if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) { 765 spin_lock_irqsave(&admin_queue->q_lock, flags); 766 ena_com_handle_admin_completion(admin_queue); 767 admin_queue->stats.no_completion++; 768 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 769 770 if (comp_ctx->status == ENA_CMD_COMPLETED) { 771 pr_err("The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d), autopolling mode is %s\n", 772 comp_ctx->cmd_opcode, 773 admin_queue->auto_polling ? "ON" : "OFF"); 774 /* Check if fallback to polling is enabled */ 775 if (admin_queue->auto_polling) 776 admin_queue->polling = true; 777 } else { 778 pr_err("The ena device doesn't send a completion for the admin cmd %d status %d\n", 779 comp_ctx->cmd_opcode, comp_ctx->status); 780 } 781 /* Check if shifted to polling mode. 782 * This will happen if there is a completion without an interrupt 783 * and autopolling mode is enabled. Continuing normal execution in such case 784 */ 785 if (!admin_queue->polling) { 786 admin_queue->running_state = false; 787 ret = -ETIME; 788 goto err; 789 } 790 } 791 792 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status); 793 err: 794 comp_ctxt_release(admin_queue, comp_ctx); 795 return ret; 796 } 797 798 /* This method read the hardware device register through posting writes 799 * and waiting for response 800 * On timeout the function will return ENA_MMIO_READ_TIMEOUT 801 */ 802 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset) 803 { 804 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 805 volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp = 806 mmio_read->read_resp; 807 u32 mmio_read_reg, ret, i; 808 unsigned long flags = 0; 809 u32 timeout = mmio_read->reg_read_to; 810 811 might_sleep(); 812 813 if (timeout == 0) 814 timeout = ENA_REG_READ_TIMEOUT; 815 816 /* If readless is disabled, perform regular read */ 817 if (!mmio_read->readless_supported) 818 return readl(ena_dev->reg_bar + offset); 819 820 spin_lock_irqsave(&mmio_read->lock, flags); 821 mmio_read->seq_num++; 822 823 read_resp->req_id = mmio_read->seq_num + 0xDEAD; 824 mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) & 825 ENA_REGS_MMIO_REG_READ_REG_OFF_MASK; 826 mmio_read_reg |= mmio_read->seq_num & 827 ENA_REGS_MMIO_REG_READ_REQ_ID_MASK; 828 829 writel(mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF); 830 831 for (i = 0; i < timeout; i++) { 832 if (READ_ONCE(read_resp->req_id) == mmio_read->seq_num) 833 break; 834 835 udelay(1); 836 } 837 838 if (unlikely(i == timeout)) { 839 pr_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n", 840 mmio_read->seq_num, offset, read_resp->req_id, 841 read_resp->reg_off); 842 ret = ENA_MMIO_READ_TIMEOUT; 843 goto err; 844 } 845 846 if (read_resp->reg_off != offset) { 847 pr_err("Read failure: wrong offset provided\n"); 848 ret = ENA_MMIO_READ_TIMEOUT; 849 } else { 850 ret = read_resp->reg_val; 851 } 852 err: 853 spin_unlock_irqrestore(&mmio_read->lock, flags); 854 855 return ret; 856 } 857 858 /* There are two types to wait for completion. 859 * Polling mode - wait until the completion is available. 860 * Async mode - wait on wait queue until the completion is ready 861 * (or the timeout expired). 862 * It is expected that the IRQ called ena_com_handle_admin_completion 863 * to mark the completions. 864 */ 865 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx, 866 struct ena_com_admin_queue *admin_queue) 867 { 868 if (admin_queue->polling) 869 return ena_com_wait_and_process_admin_cq_polling(comp_ctx, 870 admin_queue); 871 872 return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx, 873 admin_queue); 874 } 875 876 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev, 877 struct ena_com_io_sq *io_sq) 878 { 879 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 880 struct ena_admin_aq_destroy_sq_cmd destroy_cmd; 881 struct ena_admin_acq_destroy_sq_resp_desc destroy_resp; 882 u8 direction; 883 int ret; 884 885 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd)); 886 887 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 888 direction = ENA_ADMIN_SQ_DIRECTION_TX; 889 else 890 direction = ENA_ADMIN_SQ_DIRECTION_RX; 891 892 destroy_cmd.sq.sq_identity |= (direction << 893 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & 894 ENA_ADMIN_SQ_SQ_DIRECTION_MASK; 895 896 destroy_cmd.sq.sq_idx = io_sq->idx; 897 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ; 898 899 ret = ena_com_execute_admin_command(admin_queue, 900 (struct ena_admin_aq_entry *)&destroy_cmd, 901 sizeof(destroy_cmd), 902 (struct ena_admin_acq_entry *)&destroy_resp, 903 sizeof(destroy_resp)); 904 905 if (unlikely(ret && (ret != -ENODEV))) 906 pr_err("failed to destroy io sq error: %d\n", ret); 907 908 return ret; 909 } 910 911 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev, 912 struct ena_com_io_sq *io_sq, 913 struct ena_com_io_cq *io_cq) 914 { 915 size_t size; 916 917 if (io_cq->cdesc_addr.virt_addr) { 918 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth; 919 920 dma_free_coherent(ena_dev->dmadev, size, 921 io_cq->cdesc_addr.virt_addr, 922 io_cq->cdesc_addr.phys_addr); 923 924 io_cq->cdesc_addr.virt_addr = NULL; 925 } 926 927 if (io_sq->desc_addr.virt_addr) { 928 size = io_sq->desc_entry_size * io_sq->q_depth; 929 930 dma_free_coherent(ena_dev->dmadev, size, 931 io_sq->desc_addr.virt_addr, 932 io_sq->desc_addr.phys_addr); 933 934 io_sq->desc_addr.virt_addr = NULL; 935 } 936 937 if (io_sq->bounce_buf_ctrl.base_buffer) { 938 devm_kfree(ena_dev->dmadev, io_sq->bounce_buf_ctrl.base_buffer); 939 io_sq->bounce_buf_ctrl.base_buffer = NULL; 940 } 941 } 942 943 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout, 944 u16 exp_state) 945 { 946 u32 val, i; 947 948 /* Convert timeout from resolution of 100ms to ENA_POLL_MS */ 949 timeout = (timeout * 100) / ENA_POLL_MS; 950 951 for (i = 0; i < timeout; i++) { 952 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 953 954 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) { 955 pr_err("Reg read timeout occurred\n"); 956 return -ETIME; 957 } 958 959 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) == 960 exp_state) 961 return 0; 962 963 msleep(ENA_POLL_MS); 964 } 965 966 return -ETIME; 967 } 968 969 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev, 970 enum ena_admin_aq_feature_id feature_id) 971 { 972 u32 feature_mask = 1 << feature_id; 973 974 /* Device attributes is always supported */ 975 if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) && 976 !(ena_dev->supported_features & feature_mask)) 977 return false; 978 979 return true; 980 } 981 982 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev, 983 struct ena_admin_get_feat_resp *get_resp, 984 enum ena_admin_aq_feature_id feature_id, 985 dma_addr_t control_buf_dma_addr, 986 u32 control_buff_size, 987 u8 feature_ver) 988 { 989 struct ena_com_admin_queue *admin_queue; 990 struct ena_admin_get_feat_cmd get_cmd; 991 int ret; 992 993 if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) { 994 pr_debug("Feature %d isn't supported\n", feature_id); 995 return -EOPNOTSUPP; 996 } 997 998 memset(&get_cmd, 0x0, sizeof(get_cmd)); 999 admin_queue = &ena_dev->admin_queue; 1000 1001 get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE; 1002 1003 if (control_buff_size) 1004 get_cmd.aq_common_descriptor.flags = 1005 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 1006 else 1007 get_cmd.aq_common_descriptor.flags = 0; 1008 1009 ret = ena_com_mem_addr_set(ena_dev, 1010 &get_cmd.control_buffer.address, 1011 control_buf_dma_addr); 1012 if (unlikely(ret)) { 1013 pr_err("memory address set failed\n"); 1014 return ret; 1015 } 1016 1017 get_cmd.control_buffer.length = control_buff_size; 1018 get_cmd.feat_common.feature_version = feature_ver; 1019 get_cmd.feat_common.feature_id = feature_id; 1020 1021 ret = ena_com_execute_admin_command(admin_queue, 1022 (struct ena_admin_aq_entry *) 1023 &get_cmd, 1024 sizeof(get_cmd), 1025 (struct ena_admin_acq_entry *) 1026 get_resp, 1027 sizeof(*get_resp)); 1028 1029 if (unlikely(ret)) 1030 pr_err("Failed to submit get_feature command %d error: %d\n", 1031 feature_id, ret); 1032 1033 return ret; 1034 } 1035 1036 static int ena_com_get_feature(struct ena_com_dev *ena_dev, 1037 struct ena_admin_get_feat_resp *get_resp, 1038 enum ena_admin_aq_feature_id feature_id, 1039 u8 feature_ver) 1040 { 1041 return ena_com_get_feature_ex(ena_dev, 1042 get_resp, 1043 feature_id, 1044 0, 1045 0, 1046 feature_ver); 1047 } 1048 1049 int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev) 1050 { 1051 return ena_dev->rss.hash_func; 1052 } 1053 1054 static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev) 1055 { 1056 struct ena_admin_feature_rss_flow_hash_control *hash_key = 1057 (ena_dev->rss).hash_key; 1058 1059 netdev_rss_key_fill(&hash_key->key, sizeof(hash_key->key)); 1060 /* The key is stored in the device in u32 array 1061 * as well as the API requires the key to be passed in this 1062 * format. Thus the size of our array should be divided by 4 1063 */ 1064 hash_key->keys_num = sizeof(hash_key->key) / sizeof(u32); 1065 } 1066 1067 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev) 1068 { 1069 struct ena_rss *rss = &ena_dev->rss; 1070 1071 if (!ena_com_check_supported_feature_id(ena_dev, 1072 ENA_ADMIN_RSS_HASH_FUNCTION)) 1073 return -EOPNOTSUPP; 1074 1075 rss->hash_key = 1076 dma_alloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_key), 1077 &rss->hash_key_dma_addr, GFP_KERNEL); 1078 1079 if (unlikely(!rss->hash_key)) 1080 return -ENOMEM; 1081 1082 return 0; 1083 } 1084 1085 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev) 1086 { 1087 struct ena_rss *rss = &ena_dev->rss; 1088 1089 if (rss->hash_key) 1090 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_key), 1091 rss->hash_key, rss->hash_key_dma_addr); 1092 rss->hash_key = NULL; 1093 } 1094 1095 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev) 1096 { 1097 struct ena_rss *rss = &ena_dev->rss; 1098 1099 rss->hash_ctrl = 1100 dma_alloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl), 1101 &rss->hash_ctrl_dma_addr, GFP_KERNEL); 1102 1103 if (unlikely(!rss->hash_ctrl)) 1104 return -ENOMEM; 1105 1106 return 0; 1107 } 1108 1109 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev) 1110 { 1111 struct ena_rss *rss = &ena_dev->rss; 1112 1113 if (rss->hash_ctrl) 1114 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl), 1115 rss->hash_ctrl, rss->hash_ctrl_dma_addr); 1116 rss->hash_ctrl = NULL; 1117 } 1118 1119 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev, 1120 u16 log_size) 1121 { 1122 struct ena_rss *rss = &ena_dev->rss; 1123 struct ena_admin_get_feat_resp get_resp; 1124 size_t tbl_size; 1125 int ret; 1126 1127 ret = ena_com_get_feature(ena_dev, &get_resp, 1128 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 0); 1129 if (unlikely(ret)) 1130 return ret; 1131 1132 if ((get_resp.u.ind_table.min_size > log_size) || 1133 (get_resp.u.ind_table.max_size < log_size)) { 1134 pr_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n", 1135 1 << log_size, 1 << get_resp.u.ind_table.min_size, 1136 1 << get_resp.u.ind_table.max_size); 1137 return -EINVAL; 1138 } 1139 1140 tbl_size = (1ULL << log_size) * 1141 sizeof(struct ena_admin_rss_ind_table_entry); 1142 1143 rss->rss_ind_tbl = 1144 dma_alloc_coherent(ena_dev->dmadev, tbl_size, 1145 &rss->rss_ind_tbl_dma_addr, GFP_KERNEL); 1146 if (unlikely(!rss->rss_ind_tbl)) 1147 goto mem_err1; 1148 1149 tbl_size = (1ULL << log_size) * sizeof(u16); 1150 rss->host_rss_ind_tbl = 1151 devm_kzalloc(ena_dev->dmadev, tbl_size, GFP_KERNEL); 1152 if (unlikely(!rss->host_rss_ind_tbl)) 1153 goto mem_err2; 1154 1155 rss->tbl_log_size = log_size; 1156 1157 return 0; 1158 1159 mem_err2: 1160 tbl_size = (1ULL << log_size) * 1161 sizeof(struct ena_admin_rss_ind_table_entry); 1162 1163 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl, 1164 rss->rss_ind_tbl_dma_addr); 1165 rss->rss_ind_tbl = NULL; 1166 mem_err1: 1167 rss->tbl_log_size = 0; 1168 return -ENOMEM; 1169 } 1170 1171 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev) 1172 { 1173 struct ena_rss *rss = &ena_dev->rss; 1174 size_t tbl_size = (1ULL << rss->tbl_log_size) * 1175 sizeof(struct ena_admin_rss_ind_table_entry); 1176 1177 if (rss->rss_ind_tbl) 1178 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl, 1179 rss->rss_ind_tbl_dma_addr); 1180 rss->rss_ind_tbl = NULL; 1181 1182 if (rss->host_rss_ind_tbl) 1183 devm_kfree(ena_dev->dmadev, rss->host_rss_ind_tbl); 1184 rss->host_rss_ind_tbl = NULL; 1185 } 1186 1187 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev, 1188 struct ena_com_io_sq *io_sq, u16 cq_idx) 1189 { 1190 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1191 struct ena_admin_aq_create_sq_cmd create_cmd; 1192 struct ena_admin_acq_create_sq_resp_desc cmd_completion; 1193 u8 direction; 1194 int ret; 1195 1196 memset(&create_cmd, 0x0, sizeof(create_cmd)); 1197 1198 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ; 1199 1200 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 1201 direction = ENA_ADMIN_SQ_DIRECTION_TX; 1202 else 1203 direction = ENA_ADMIN_SQ_DIRECTION_RX; 1204 1205 create_cmd.sq_identity |= (direction << 1206 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & 1207 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK; 1208 1209 create_cmd.sq_caps_2 |= io_sq->mem_queue_type & 1210 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK; 1211 1212 create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC << 1213 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & 1214 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK; 1215 1216 create_cmd.sq_caps_3 |= 1217 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK; 1218 1219 create_cmd.cq_idx = cq_idx; 1220 create_cmd.sq_depth = io_sq->q_depth; 1221 1222 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) { 1223 ret = ena_com_mem_addr_set(ena_dev, 1224 &create_cmd.sq_ba, 1225 io_sq->desc_addr.phys_addr); 1226 if (unlikely(ret)) { 1227 pr_err("memory address set failed\n"); 1228 return ret; 1229 } 1230 } 1231 1232 ret = ena_com_execute_admin_command(admin_queue, 1233 (struct ena_admin_aq_entry *)&create_cmd, 1234 sizeof(create_cmd), 1235 (struct ena_admin_acq_entry *)&cmd_completion, 1236 sizeof(cmd_completion)); 1237 if (unlikely(ret)) { 1238 pr_err("Failed to create IO SQ. error: %d\n", ret); 1239 return ret; 1240 } 1241 1242 io_sq->idx = cmd_completion.sq_idx; 1243 1244 io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1245 (uintptr_t)cmd_completion.sq_doorbell_offset); 1246 1247 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 1248 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar 1249 + cmd_completion.llq_headers_offset); 1250 1251 io_sq->desc_addr.pbuf_dev_addr = 1252 (u8 __iomem *)((uintptr_t)ena_dev->mem_bar + 1253 cmd_completion.llq_descriptors_offset); 1254 } 1255 1256 pr_debug("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth); 1257 1258 return ret; 1259 } 1260 1261 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev) 1262 { 1263 struct ena_rss *rss = &ena_dev->rss; 1264 struct ena_com_io_sq *io_sq; 1265 u16 qid; 1266 int i; 1267 1268 for (i = 0; i < 1 << rss->tbl_log_size; i++) { 1269 qid = rss->host_rss_ind_tbl[i]; 1270 if (qid >= ENA_TOTAL_NUM_QUEUES) 1271 return -EINVAL; 1272 1273 io_sq = &ena_dev->io_sq_queues[qid]; 1274 1275 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX) 1276 return -EINVAL; 1277 1278 rss->rss_ind_tbl[i].cq_idx = io_sq->idx; 1279 } 1280 1281 return 0; 1282 } 1283 1284 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev, 1285 u16 intr_delay_resolution) 1286 { 1287 /* Initial value of intr_delay_resolution might be 0 */ 1288 u16 prev_intr_delay_resolution = 1289 ena_dev->intr_delay_resolution ? 1290 ena_dev->intr_delay_resolution : 1291 ENA_DEFAULT_INTR_DELAY_RESOLUTION; 1292 1293 if (!intr_delay_resolution) { 1294 pr_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n"); 1295 intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION; 1296 } 1297 1298 /* update Rx */ 1299 ena_dev->intr_moder_rx_interval = 1300 ena_dev->intr_moder_rx_interval * 1301 prev_intr_delay_resolution / 1302 intr_delay_resolution; 1303 1304 /* update Tx */ 1305 ena_dev->intr_moder_tx_interval = 1306 ena_dev->intr_moder_tx_interval * 1307 prev_intr_delay_resolution / 1308 intr_delay_resolution; 1309 1310 ena_dev->intr_delay_resolution = intr_delay_resolution; 1311 } 1312 1313 /*****************************************************************************/ 1314 /******************************* API ******************************/ 1315 /*****************************************************************************/ 1316 1317 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, 1318 struct ena_admin_aq_entry *cmd, 1319 size_t cmd_size, 1320 struct ena_admin_acq_entry *comp, 1321 size_t comp_size) 1322 { 1323 struct ena_comp_ctx *comp_ctx; 1324 int ret; 1325 1326 comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size, 1327 comp, comp_size); 1328 if (IS_ERR(comp_ctx)) { 1329 if (comp_ctx == ERR_PTR(-ENODEV)) 1330 pr_debug("Failed to submit command [%ld]\n", 1331 PTR_ERR(comp_ctx)); 1332 else 1333 pr_err("Failed to submit command [%ld]\n", 1334 PTR_ERR(comp_ctx)); 1335 1336 return PTR_ERR(comp_ctx); 1337 } 1338 1339 ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue); 1340 if (unlikely(ret)) { 1341 if (admin_queue->running_state) 1342 pr_err("Failed to process command. ret = %d\n", ret); 1343 else 1344 pr_debug("Failed to process command. ret = %d\n", ret); 1345 } 1346 return ret; 1347 } 1348 1349 int ena_com_create_io_cq(struct ena_com_dev *ena_dev, 1350 struct ena_com_io_cq *io_cq) 1351 { 1352 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1353 struct ena_admin_aq_create_cq_cmd create_cmd; 1354 struct ena_admin_acq_create_cq_resp_desc cmd_completion; 1355 int ret; 1356 1357 memset(&create_cmd, 0x0, sizeof(create_cmd)); 1358 1359 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ; 1360 1361 create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) & 1362 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK; 1363 create_cmd.cq_caps_1 |= 1364 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK; 1365 1366 create_cmd.msix_vector = io_cq->msix_vector; 1367 create_cmd.cq_depth = io_cq->q_depth; 1368 1369 ret = ena_com_mem_addr_set(ena_dev, 1370 &create_cmd.cq_ba, 1371 io_cq->cdesc_addr.phys_addr); 1372 if (unlikely(ret)) { 1373 pr_err("memory address set failed\n"); 1374 return ret; 1375 } 1376 1377 ret = ena_com_execute_admin_command(admin_queue, 1378 (struct ena_admin_aq_entry *)&create_cmd, 1379 sizeof(create_cmd), 1380 (struct ena_admin_acq_entry *)&cmd_completion, 1381 sizeof(cmd_completion)); 1382 if (unlikely(ret)) { 1383 pr_err("Failed to create IO CQ. error: %d\n", ret); 1384 return ret; 1385 } 1386 1387 io_cq->idx = cmd_completion.cq_idx; 1388 1389 io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1390 cmd_completion.cq_interrupt_unmask_register_offset); 1391 1392 if (cmd_completion.cq_head_db_register_offset) 1393 io_cq->cq_head_db_reg = 1394 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1395 cmd_completion.cq_head_db_register_offset); 1396 1397 if (cmd_completion.numa_node_register_offset) 1398 io_cq->numa_node_cfg_reg = 1399 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1400 cmd_completion.numa_node_register_offset); 1401 1402 pr_debug("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth); 1403 1404 return ret; 1405 } 1406 1407 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid, 1408 struct ena_com_io_sq **io_sq, 1409 struct ena_com_io_cq **io_cq) 1410 { 1411 if (qid >= ENA_TOTAL_NUM_QUEUES) { 1412 pr_err("Invalid queue number %d but the max is %d\n", qid, 1413 ENA_TOTAL_NUM_QUEUES); 1414 return -EINVAL; 1415 } 1416 1417 *io_sq = &ena_dev->io_sq_queues[qid]; 1418 *io_cq = &ena_dev->io_cq_queues[qid]; 1419 1420 return 0; 1421 } 1422 1423 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev) 1424 { 1425 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1426 struct ena_comp_ctx *comp_ctx; 1427 u16 i; 1428 1429 if (!admin_queue->comp_ctx) 1430 return; 1431 1432 for (i = 0; i < admin_queue->q_depth; i++) { 1433 comp_ctx = get_comp_ctxt(admin_queue, i, false); 1434 if (unlikely(!comp_ctx)) 1435 break; 1436 1437 comp_ctx->status = ENA_CMD_ABORTED; 1438 1439 complete(&comp_ctx->wait_event); 1440 } 1441 } 1442 1443 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev) 1444 { 1445 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1446 unsigned long flags = 0; 1447 1448 spin_lock_irqsave(&admin_queue->q_lock, flags); 1449 while (atomic_read(&admin_queue->outstanding_cmds) != 0) { 1450 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 1451 msleep(ENA_POLL_MS); 1452 spin_lock_irqsave(&admin_queue->q_lock, flags); 1453 } 1454 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 1455 } 1456 1457 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev, 1458 struct ena_com_io_cq *io_cq) 1459 { 1460 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1461 struct ena_admin_aq_destroy_cq_cmd destroy_cmd; 1462 struct ena_admin_acq_destroy_cq_resp_desc destroy_resp; 1463 int ret; 1464 1465 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd)); 1466 1467 destroy_cmd.cq_idx = io_cq->idx; 1468 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ; 1469 1470 ret = ena_com_execute_admin_command(admin_queue, 1471 (struct ena_admin_aq_entry *)&destroy_cmd, 1472 sizeof(destroy_cmd), 1473 (struct ena_admin_acq_entry *)&destroy_resp, 1474 sizeof(destroy_resp)); 1475 1476 if (unlikely(ret && (ret != -ENODEV))) 1477 pr_err("Failed to destroy IO CQ. error: %d\n", ret); 1478 1479 return ret; 1480 } 1481 1482 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev) 1483 { 1484 return ena_dev->admin_queue.running_state; 1485 } 1486 1487 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state) 1488 { 1489 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1490 unsigned long flags = 0; 1491 1492 spin_lock_irqsave(&admin_queue->q_lock, flags); 1493 ena_dev->admin_queue.running_state = state; 1494 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 1495 } 1496 1497 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev) 1498 { 1499 u16 depth = ena_dev->aenq.q_depth; 1500 1501 WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n"); 1502 1503 /* Init head_db to mark that all entries in the queue 1504 * are initially available 1505 */ 1506 writel(depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); 1507 } 1508 1509 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag) 1510 { 1511 struct ena_com_admin_queue *admin_queue; 1512 struct ena_admin_set_feat_cmd cmd; 1513 struct ena_admin_set_feat_resp resp; 1514 struct ena_admin_get_feat_resp get_resp; 1515 int ret; 1516 1517 ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0); 1518 if (ret) { 1519 pr_info("Can't get aenq configuration\n"); 1520 return ret; 1521 } 1522 1523 if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) { 1524 pr_warn("Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n", 1525 get_resp.u.aenq.supported_groups, groups_flag); 1526 return -EOPNOTSUPP; 1527 } 1528 1529 memset(&cmd, 0x0, sizeof(cmd)); 1530 admin_queue = &ena_dev->admin_queue; 1531 1532 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 1533 cmd.aq_common_descriptor.flags = 0; 1534 cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG; 1535 cmd.u.aenq.enabled_groups = groups_flag; 1536 1537 ret = ena_com_execute_admin_command(admin_queue, 1538 (struct ena_admin_aq_entry *)&cmd, 1539 sizeof(cmd), 1540 (struct ena_admin_acq_entry *)&resp, 1541 sizeof(resp)); 1542 1543 if (unlikely(ret)) 1544 pr_err("Failed to config AENQ ret: %d\n", ret); 1545 1546 return ret; 1547 } 1548 1549 int ena_com_get_dma_width(struct ena_com_dev *ena_dev) 1550 { 1551 u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); 1552 int width; 1553 1554 if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) { 1555 pr_err("Reg read timeout occurred\n"); 1556 return -ETIME; 1557 } 1558 1559 width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >> 1560 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT; 1561 1562 pr_debug("ENA dma width: %d\n", width); 1563 1564 if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) { 1565 pr_err("DMA width illegal value: %d\n", width); 1566 return -EINVAL; 1567 } 1568 1569 ena_dev->dma_addr_bits = width; 1570 1571 return width; 1572 } 1573 1574 int ena_com_validate_version(struct ena_com_dev *ena_dev) 1575 { 1576 u32 ver; 1577 u32 ctrl_ver; 1578 u32 ctrl_ver_masked; 1579 1580 /* Make sure the ENA version and the controller version are at least 1581 * as the driver expects 1582 */ 1583 ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF); 1584 ctrl_ver = ena_com_reg_bar_read32(ena_dev, 1585 ENA_REGS_CONTROLLER_VERSION_OFF); 1586 1587 if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) || 1588 (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) { 1589 pr_err("Reg read timeout occurred\n"); 1590 return -ETIME; 1591 } 1592 1593 pr_info("ena device version: %d.%d\n", 1594 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >> 1595 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT, 1596 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK); 1597 1598 pr_info("ena controller version: %d.%d.%d implementation version %d\n", 1599 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) >> 1600 ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT, 1601 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) >> 1602 ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT, 1603 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK), 1604 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >> 1605 ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT); 1606 1607 ctrl_ver_masked = 1608 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) | 1609 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) | 1610 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK); 1611 1612 /* Validate the ctrl version without the implementation ID */ 1613 if (ctrl_ver_masked < MIN_ENA_CTRL_VER) { 1614 pr_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n"); 1615 return -1; 1616 } 1617 1618 return 0; 1619 } 1620 1621 void ena_com_admin_destroy(struct ena_com_dev *ena_dev) 1622 { 1623 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1624 struct ena_com_admin_cq *cq = &admin_queue->cq; 1625 struct ena_com_admin_sq *sq = &admin_queue->sq; 1626 struct ena_com_aenq *aenq = &ena_dev->aenq; 1627 u16 size; 1628 1629 if (admin_queue->comp_ctx) 1630 devm_kfree(ena_dev->dmadev, admin_queue->comp_ctx); 1631 admin_queue->comp_ctx = NULL; 1632 size = ADMIN_SQ_SIZE(admin_queue->q_depth); 1633 if (sq->entries) 1634 dma_free_coherent(ena_dev->dmadev, size, sq->entries, 1635 sq->dma_addr); 1636 sq->entries = NULL; 1637 1638 size = ADMIN_CQ_SIZE(admin_queue->q_depth); 1639 if (cq->entries) 1640 dma_free_coherent(ena_dev->dmadev, size, cq->entries, 1641 cq->dma_addr); 1642 cq->entries = NULL; 1643 1644 size = ADMIN_AENQ_SIZE(aenq->q_depth); 1645 if (ena_dev->aenq.entries) 1646 dma_free_coherent(ena_dev->dmadev, size, aenq->entries, 1647 aenq->dma_addr); 1648 aenq->entries = NULL; 1649 } 1650 1651 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling) 1652 { 1653 u32 mask_value = 0; 1654 1655 if (polling) 1656 mask_value = ENA_REGS_ADMIN_INTR_MASK; 1657 1658 writel(mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF); 1659 ena_dev->admin_queue.polling = polling; 1660 } 1661 1662 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev, 1663 bool polling) 1664 { 1665 ena_dev->admin_queue.auto_polling = polling; 1666 } 1667 1668 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev) 1669 { 1670 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1671 1672 spin_lock_init(&mmio_read->lock); 1673 mmio_read->read_resp = 1674 dma_alloc_coherent(ena_dev->dmadev, 1675 sizeof(*mmio_read->read_resp), 1676 &mmio_read->read_resp_dma_addr, GFP_KERNEL); 1677 if (unlikely(!mmio_read->read_resp)) 1678 goto err; 1679 1680 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev); 1681 1682 mmio_read->read_resp->req_id = 0x0; 1683 mmio_read->seq_num = 0x0; 1684 mmio_read->readless_supported = true; 1685 1686 return 0; 1687 1688 err: 1689 1690 return -ENOMEM; 1691 } 1692 1693 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported) 1694 { 1695 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1696 1697 mmio_read->readless_supported = readless_supported; 1698 } 1699 1700 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev) 1701 { 1702 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1703 1704 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF); 1705 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF); 1706 1707 dma_free_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp), 1708 mmio_read->read_resp, mmio_read->read_resp_dma_addr); 1709 1710 mmio_read->read_resp = NULL; 1711 } 1712 1713 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev) 1714 { 1715 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1716 u32 addr_low, addr_high; 1717 1718 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr); 1719 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr); 1720 1721 writel(addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF); 1722 writel(addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF); 1723 } 1724 1725 int ena_com_admin_init(struct ena_com_dev *ena_dev, 1726 struct ena_aenq_handlers *aenq_handlers) 1727 { 1728 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1729 u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high; 1730 int ret; 1731 1732 dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 1733 1734 if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) { 1735 pr_err("Reg read timeout occurred\n"); 1736 return -ETIME; 1737 } 1738 1739 if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) { 1740 pr_err("Device isn't ready, abort com init\n"); 1741 return -ENODEV; 1742 } 1743 1744 admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH; 1745 1746 admin_queue->q_dmadev = ena_dev->dmadev; 1747 admin_queue->polling = false; 1748 admin_queue->curr_cmd_id = 0; 1749 1750 atomic_set(&admin_queue->outstanding_cmds, 0); 1751 1752 spin_lock_init(&admin_queue->q_lock); 1753 1754 ret = ena_com_init_comp_ctxt(admin_queue); 1755 if (ret) 1756 goto error; 1757 1758 ret = ena_com_admin_init_sq(admin_queue); 1759 if (ret) 1760 goto error; 1761 1762 ret = ena_com_admin_init_cq(admin_queue); 1763 if (ret) 1764 goto error; 1765 1766 admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1767 ENA_REGS_AQ_DB_OFF); 1768 1769 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr); 1770 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr); 1771 1772 writel(addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF); 1773 writel(addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF); 1774 1775 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr); 1776 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr); 1777 1778 writel(addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF); 1779 writel(addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF); 1780 1781 aq_caps = 0; 1782 aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK; 1783 aq_caps |= (sizeof(struct ena_admin_aq_entry) << 1784 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) & 1785 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK; 1786 1787 acq_caps = 0; 1788 acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK; 1789 acq_caps |= (sizeof(struct ena_admin_acq_entry) << 1790 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) & 1791 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK; 1792 1793 writel(aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF); 1794 writel(acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF); 1795 ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers); 1796 if (ret) 1797 goto error; 1798 1799 admin_queue->running_state = true; 1800 1801 return 0; 1802 error: 1803 ena_com_admin_destroy(ena_dev); 1804 1805 return ret; 1806 } 1807 1808 int ena_com_create_io_queue(struct ena_com_dev *ena_dev, 1809 struct ena_com_create_io_ctx *ctx) 1810 { 1811 struct ena_com_io_sq *io_sq; 1812 struct ena_com_io_cq *io_cq; 1813 int ret; 1814 1815 if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) { 1816 pr_err("Qid (%d) is bigger than max num of queues (%d)\n", 1817 ctx->qid, ENA_TOTAL_NUM_QUEUES); 1818 return -EINVAL; 1819 } 1820 1821 io_sq = &ena_dev->io_sq_queues[ctx->qid]; 1822 io_cq = &ena_dev->io_cq_queues[ctx->qid]; 1823 1824 memset(io_sq, 0x0, sizeof(*io_sq)); 1825 memset(io_cq, 0x0, sizeof(*io_cq)); 1826 1827 /* Init CQ */ 1828 io_cq->q_depth = ctx->queue_size; 1829 io_cq->direction = ctx->direction; 1830 io_cq->qid = ctx->qid; 1831 1832 io_cq->msix_vector = ctx->msix_vector; 1833 1834 io_sq->q_depth = ctx->queue_size; 1835 io_sq->direction = ctx->direction; 1836 io_sq->qid = ctx->qid; 1837 1838 io_sq->mem_queue_type = ctx->mem_queue_type; 1839 1840 if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 1841 /* header length is limited to 8 bits */ 1842 io_sq->tx_max_header_size = 1843 min_t(u32, ena_dev->tx_max_header_size, SZ_256); 1844 1845 ret = ena_com_init_io_sq(ena_dev, ctx, io_sq); 1846 if (ret) 1847 goto error; 1848 ret = ena_com_init_io_cq(ena_dev, ctx, io_cq); 1849 if (ret) 1850 goto error; 1851 1852 ret = ena_com_create_io_cq(ena_dev, io_cq); 1853 if (ret) 1854 goto error; 1855 1856 ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx); 1857 if (ret) 1858 goto destroy_io_cq; 1859 1860 return 0; 1861 1862 destroy_io_cq: 1863 ena_com_destroy_io_cq(ena_dev, io_cq); 1864 error: 1865 ena_com_io_queue_free(ena_dev, io_sq, io_cq); 1866 return ret; 1867 } 1868 1869 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid) 1870 { 1871 struct ena_com_io_sq *io_sq; 1872 struct ena_com_io_cq *io_cq; 1873 1874 if (qid >= ENA_TOTAL_NUM_QUEUES) { 1875 pr_err("Qid (%d) is bigger than max num of queues (%d)\n", qid, 1876 ENA_TOTAL_NUM_QUEUES); 1877 return; 1878 } 1879 1880 io_sq = &ena_dev->io_sq_queues[qid]; 1881 io_cq = &ena_dev->io_cq_queues[qid]; 1882 1883 ena_com_destroy_io_sq(ena_dev, io_sq); 1884 ena_com_destroy_io_cq(ena_dev, io_cq); 1885 1886 ena_com_io_queue_free(ena_dev, io_sq, io_cq); 1887 } 1888 1889 int ena_com_get_link_params(struct ena_com_dev *ena_dev, 1890 struct ena_admin_get_feat_resp *resp) 1891 { 1892 return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0); 1893 } 1894 1895 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, 1896 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1897 { 1898 struct ena_admin_get_feat_resp get_resp; 1899 int rc; 1900 1901 rc = ena_com_get_feature(ena_dev, &get_resp, 1902 ENA_ADMIN_DEVICE_ATTRIBUTES, 0); 1903 if (rc) 1904 return rc; 1905 1906 memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr, 1907 sizeof(get_resp.u.dev_attr)); 1908 ena_dev->supported_features = get_resp.u.dev_attr.supported_features; 1909 1910 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 1911 rc = ena_com_get_feature(ena_dev, &get_resp, 1912 ENA_ADMIN_MAX_QUEUES_EXT, 1913 ENA_FEATURE_MAX_QUEUE_EXT_VER); 1914 if (rc) 1915 return rc; 1916 1917 if (get_resp.u.max_queue_ext.version != ENA_FEATURE_MAX_QUEUE_EXT_VER) 1918 return -EINVAL; 1919 1920 memcpy(&get_feat_ctx->max_queue_ext, &get_resp.u.max_queue_ext, 1921 sizeof(get_resp.u.max_queue_ext)); 1922 ena_dev->tx_max_header_size = 1923 get_resp.u.max_queue_ext.max_queue_ext.max_tx_header_size; 1924 } else { 1925 rc = ena_com_get_feature(ena_dev, &get_resp, 1926 ENA_ADMIN_MAX_QUEUES_NUM, 0); 1927 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue, 1928 sizeof(get_resp.u.max_queue)); 1929 ena_dev->tx_max_header_size = 1930 get_resp.u.max_queue.max_header_size; 1931 1932 if (rc) 1933 return rc; 1934 } 1935 1936 rc = ena_com_get_feature(ena_dev, &get_resp, 1937 ENA_ADMIN_AENQ_CONFIG, 0); 1938 if (rc) 1939 return rc; 1940 1941 memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq, 1942 sizeof(get_resp.u.aenq)); 1943 1944 rc = ena_com_get_feature(ena_dev, &get_resp, 1945 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0); 1946 if (rc) 1947 return rc; 1948 1949 memcpy(&get_feat_ctx->offload, &get_resp.u.offload, 1950 sizeof(get_resp.u.offload)); 1951 1952 /* Driver hints isn't mandatory admin command. So in case the 1953 * command isn't supported set driver hints to 0 1954 */ 1955 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS, 0); 1956 1957 if (!rc) 1958 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints, 1959 sizeof(get_resp.u.hw_hints)); 1960 else if (rc == -EOPNOTSUPP) 1961 memset(&get_feat_ctx->hw_hints, 0x0, 1962 sizeof(get_feat_ctx->hw_hints)); 1963 else 1964 return rc; 1965 1966 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ, 0); 1967 if (!rc) 1968 memcpy(&get_feat_ctx->llq, &get_resp.u.llq, 1969 sizeof(get_resp.u.llq)); 1970 else if (rc == -EOPNOTSUPP) 1971 memset(&get_feat_ctx->llq, 0x0, sizeof(get_feat_ctx->llq)); 1972 else 1973 return rc; 1974 1975 return 0; 1976 } 1977 1978 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev) 1979 { 1980 ena_com_handle_admin_completion(&ena_dev->admin_queue); 1981 } 1982 1983 /* ena_handle_specific_aenq_event: 1984 * return the handler that is relevant to the specific event group 1985 */ 1986 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev, 1987 u16 group) 1988 { 1989 struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers; 1990 1991 if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group]) 1992 return aenq_handlers->handlers[group]; 1993 1994 return aenq_handlers->unimplemented_handler; 1995 } 1996 1997 /* ena_aenq_intr_handler: 1998 * handles the aenq incoming events. 1999 * pop events from the queue and apply the specific handler 2000 */ 2001 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data) 2002 { 2003 struct ena_admin_aenq_entry *aenq_e; 2004 struct ena_admin_aenq_common_desc *aenq_common; 2005 struct ena_com_aenq *aenq = &dev->aenq; 2006 unsigned long long timestamp; 2007 ena_aenq_handler handler_cb; 2008 u16 masked_head, processed = 0; 2009 u8 phase; 2010 2011 masked_head = aenq->head & (aenq->q_depth - 1); 2012 phase = aenq->phase; 2013 aenq_e = &aenq->entries[masked_head]; /* Get first entry */ 2014 aenq_common = &aenq_e->aenq_common_desc; 2015 2016 /* Go over all the events */ 2017 while ((READ_ONCE(aenq_common->flags) & 2018 ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) { 2019 /* Make sure the phase bit (ownership) is as expected before 2020 * reading the rest of the descriptor. 2021 */ 2022 dma_rmb(); 2023 2024 timestamp = 2025 (unsigned long long)aenq_common->timestamp_low | 2026 ((unsigned long long)aenq_common->timestamp_high << 32); 2027 pr_debug("AENQ! Group[%x] Syndrom[%x] timestamp: [%llus]\n", 2028 aenq_common->group, aenq_common->syndrom, timestamp); 2029 2030 /* Handle specific event*/ 2031 handler_cb = ena_com_get_specific_aenq_cb(dev, 2032 aenq_common->group); 2033 handler_cb(data, aenq_e); /* call the actual event handler*/ 2034 2035 /* Get next event entry */ 2036 masked_head++; 2037 processed++; 2038 2039 if (unlikely(masked_head == aenq->q_depth)) { 2040 masked_head = 0; 2041 phase = !phase; 2042 } 2043 aenq_e = &aenq->entries[masked_head]; 2044 aenq_common = &aenq_e->aenq_common_desc; 2045 } 2046 2047 aenq->head += processed; 2048 aenq->phase = phase; 2049 2050 /* Don't update aenq doorbell if there weren't any processed events */ 2051 if (!processed) 2052 return; 2053 2054 /* write the aenq doorbell after all AENQ descriptors were read */ 2055 mb(); 2056 writel_relaxed((u32)aenq->head, 2057 dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); 2058 } 2059 2060 int ena_com_dev_reset(struct ena_com_dev *ena_dev, 2061 enum ena_regs_reset_reason_types reset_reason) 2062 { 2063 u32 stat, timeout, cap, reset_val; 2064 int rc; 2065 2066 stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 2067 cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); 2068 2069 if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) || 2070 (cap == ENA_MMIO_READ_TIMEOUT))) { 2071 pr_err("Reg read32 timeout occurred\n"); 2072 return -ETIME; 2073 } 2074 2075 if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) { 2076 pr_err("Device isn't ready, can't reset device\n"); 2077 return -EINVAL; 2078 } 2079 2080 timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >> 2081 ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT; 2082 if (timeout == 0) { 2083 pr_err("Invalid timeout value\n"); 2084 return -EINVAL; 2085 } 2086 2087 /* start reset */ 2088 reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK; 2089 reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) & 2090 ENA_REGS_DEV_CTL_RESET_REASON_MASK; 2091 writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); 2092 2093 /* Write again the MMIO read request address */ 2094 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev); 2095 2096 rc = wait_for_reset_state(ena_dev, timeout, 2097 ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK); 2098 if (rc != 0) { 2099 pr_err("Reset indication didn't turn on\n"); 2100 return rc; 2101 } 2102 2103 /* reset done */ 2104 writel(0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); 2105 rc = wait_for_reset_state(ena_dev, timeout, 0); 2106 if (rc != 0) { 2107 pr_err("Reset indication didn't turn off\n"); 2108 return rc; 2109 } 2110 2111 timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >> 2112 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT; 2113 if (timeout) 2114 /* the resolution of timeout reg is 100ms */ 2115 ena_dev->admin_queue.completion_timeout = timeout * 100000; 2116 else 2117 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US; 2118 2119 return 0; 2120 } 2121 2122 static int ena_get_dev_stats(struct ena_com_dev *ena_dev, 2123 struct ena_com_stats_ctx *ctx, 2124 enum ena_admin_get_stats_type type) 2125 { 2126 struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd; 2127 struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp; 2128 struct ena_com_admin_queue *admin_queue; 2129 int ret; 2130 2131 admin_queue = &ena_dev->admin_queue; 2132 2133 get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS; 2134 get_cmd->aq_common_descriptor.flags = 0; 2135 get_cmd->type = type; 2136 2137 ret = ena_com_execute_admin_command(admin_queue, 2138 (struct ena_admin_aq_entry *)get_cmd, 2139 sizeof(*get_cmd), 2140 (struct ena_admin_acq_entry *)get_resp, 2141 sizeof(*get_resp)); 2142 2143 if (unlikely(ret)) 2144 pr_err("Failed to get stats. error: %d\n", ret); 2145 2146 return ret; 2147 } 2148 2149 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev, 2150 struct ena_admin_basic_stats *stats) 2151 { 2152 struct ena_com_stats_ctx ctx; 2153 int ret; 2154 2155 memset(&ctx, 0x0, sizeof(ctx)); 2156 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC); 2157 if (likely(ret == 0)) 2158 memcpy(stats, &ctx.get_resp.basic_stats, 2159 sizeof(ctx.get_resp.basic_stats)); 2160 2161 return ret; 2162 } 2163 2164 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu) 2165 { 2166 struct ena_com_admin_queue *admin_queue; 2167 struct ena_admin_set_feat_cmd cmd; 2168 struct ena_admin_set_feat_resp resp; 2169 int ret; 2170 2171 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) { 2172 pr_debug("Feature %d isn't supported\n", ENA_ADMIN_MTU); 2173 return -EOPNOTSUPP; 2174 } 2175 2176 memset(&cmd, 0x0, sizeof(cmd)); 2177 admin_queue = &ena_dev->admin_queue; 2178 2179 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2180 cmd.aq_common_descriptor.flags = 0; 2181 cmd.feat_common.feature_id = ENA_ADMIN_MTU; 2182 cmd.u.mtu.mtu = mtu; 2183 2184 ret = ena_com_execute_admin_command(admin_queue, 2185 (struct ena_admin_aq_entry *)&cmd, 2186 sizeof(cmd), 2187 (struct ena_admin_acq_entry *)&resp, 2188 sizeof(resp)); 2189 2190 if (unlikely(ret)) 2191 pr_err("Failed to set mtu %d. error: %d\n", mtu, ret); 2192 2193 return ret; 2194 } 2195 2196 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev, 2197 struct ena_admin_feature_offload_desc *offload) 2198 { 2199 int ret; 2200 struct ena_admin_get_feat_resp resp; 2201 2202 ret = ena_com_get_feature(ena_dev, &resp, 2203 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0); 2204 if (unlikely(ret)) { 2205 pr_err("Failed to get offload capabilities %d\n", ret); 2206 return ret; 2207 } 2208 2209 memcpy(offload, &resp.u.offload, sizeof(resp.u.offload)); 2210 2211 return 0; 2212 } 2213 2214 int ena_com_set_hash_function(struct ena_com_dev *ena_dev) 2215 { 2216 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 2217 struct ena_rss *rss = &ena_dev->rss; 2218 struct ena_admin_set_feat_cmd cmd; 2219 struct ena_admin_set_feat_resp resp; 2220 struct ena_admin_get_feat_resp get_resp; 2221 int ret; 2222 2223 if (!ena_com_check_supported_feature_id(ena_dev, 2224 ENA_ADMIN_RSS_HASH_FUNCTION)) { 2225 pr_debug("Feature %d isn't supported\n", 2226 ENA_ADMIN_RSS_HASH_FUNCTION); 2227 return -EOPNOTSUPP; 2228 } 2229 2230 /* Validate hash function is supported */ 2231 ret = ena_com_get_feature(ena_dev, &get_resp, 2232 ENA_ADMIN_RSS_HASH_FUNCTION, 0); 2233 if (unlikely(ret)) 2234 return ret; 2235 2236 if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) { 2237 pr_err("Func hash %d isn't supported by device, abort\n", 2238 rss->hash_func); 2239 return -EOPNOTSUPP; 2240 } 2241 2242 memset(&cmd, 0x0, sizeof(cmd)); 2243 2244 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2245 cmd.aq_common_descriptor.flags = 2246 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2247 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION; 2248 cmd.u.flow_hash_func.init_val = rss->hash_init_val; 2249 cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func; 2250 2251 ret = ena_com_mem_addr_set(ena_dev, 2252 &cmd.control_buffer.address, 2253 rss->hash_key_dma_addr); 2254 if (unlikely(ret)) { 2255 pr_err("memory address set failed\n"); 2256 return ret; 2257 } 2258 2259 cmd.control_buffer.length = sizeof(*rss->hash_key); 2260 2261 ret = ena_com_execute_admin_command(admin_queue, 2262 (struct ena_admin_aq_entry *)&cmd, 2263 sizeof(cmd), 2264 (struct ena_admin_acq_entry *)&resp, 2265 sizeof(resp)); 2266 if (unlikely(ret)) { 2267 pr_err("Failed to set hash function %d. error: %d\n", 2268 rss->hash_func, ret); 2269 return -EINVAL; 2270 } 2271 2272 return 0; 2273 } 2274 2275 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, 2276 enum ena_admin_hash_functions func, 2277 const u8 *key, u16 key_len, u32 init_val) 2278 { 2279 struct ena_rss *rss = &ena_dev->rss; 2280 struct ena_admin_get_feat_resp get_resp; 2281 struct ena_admin_feature_rss_flow_hash_control *hash_key = 2282 rss->hash_key; 2283 enum ena_admin_hash_functions old_func; 2284 int rc; 2285 2286 /* Make sure size is a mult of DWs */ 2287 if (unlikely(key_len & 0x3)) 2288 return -EINVAL; 2289 2290 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2291 ENA_ADMIN_RSS_HASH_FUNCTION, 2292 rss->hash_key_dma_addr, 2293 sizeof(*rss->hash_key), 0); 2294 if (unlikely(rc)) 2295 return rc; 2296 2297 if (!((1 << func) & get_resp.u.flow_hash_func.supported_func)) { 2298 pr_err("Flow hash function %d isn't supported\n", func); 2299 return -EOPNOTSUPP; 2300 } 2301 2302 switch (func) { 2303 case ENA_ADMIN_TOEPLITZ: 2304 if (key) { 2305 if (key_len != sizeof(hash_key->key)) { 2306 pr_err("key len (%hu) doesn't equal the supported size (%zu)\n", 2307 key_len, sizeof(hash_key->key)); 2308 return -EINVAL; 2309 } 2310 memcpy(hash_key->key, key, key_len); 2311 rss->hash_init_val = init_val; 2312 hash_key->keys_num = key_len >> 2; 2313 } 2314 break; 2315 case ENA_ADMIN_CRC32: 2316 rss->hash_init_val = init_val; 2317 break; 2318 default: 2319 pr_err("Invalid hash function (%d)\n", func); 2320 return -EINVAL; 2321 } 2322 2323 old_func = rss->hash_func; 2324 rss->hash_func = func; 2325 rc = ena_com_set_hash_function(ena_dev); 2326 2327 /* Restore the old function */ 2328 if (unlikely(rc)) 2329 rss->hash_func = old_func; 2330 2331 return rc; 2332 } 2333 2334 int ena_com_get_hash_function(struct ena_com_dev *ena_dev, 2335 enum ena_admin_hash_functions *func) 2336 { 2337 struct ena_rss *rss = &ena_dev->rss; 2338 struct ena_admin_get_feat_resp get_resp; 2339 int rc; 2340 2341 if (unlikely(!func)) 2342 return -EINVAL; 2343 2344 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2345 ENA_ADMIN_RSS_HASH_FUNCTION, 2346 rss->hash_key_dma_addr, 2347 sizeof(*rss->hash_key), 0); 2348 if (unlikely(rc)) 2349 return rc; 2350 2351 /* ffs() returns 1 in case the lsb is set */ 2352 rss->hash_func = ffs(get_resp.u.flow_hash_func.selected_func); 2353 if (rss->hash_func) 2354 rss->hash_func--; 2355 2356 *func = rss->hash_func; 2357 2358 return 0; 2359 } 2360 2361 int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key) 2362 { 2363 struct ena_admin_feature_rss_flow_hash_control *hash_key = 2364 ena_dev->rss.hash_key; 2365 2366 if (key) 2367 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2); 2368 2369 return 0; 2370 } 2371 2372 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev, 2373 enum ena_admin_flow_hash_proto proto, 2374 u16 *fields) 2375 { 2376 struct ena_rss *rss = &ena_dev->rss; 2377 struct ena_admin_get_feat_resp get_resp; 2378 int rc; 2379 2380 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2381 ENA_ADMIN_RSS_HASH_INPUT, 2382 rss->hash_ctrl_dma_addr, 2383 sizeof(*rss->hash_ctrl), 0); 2384 if (unlikely(rc)) 2385 return rc; 2386 2387 if (fields) 2388 *fields = rss->hash_ctrl->selected_fields[proto].fields; 2389 2390 return 0; 2391 } 2392 2393 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev) 2394 { 2395 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 2396 struct ena_rss *rss = &ena_dev->rss; 2397 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl; 2398 struct ena_admin_set_feat_cmd cmd; 2399 struct ena_admin_set_feat_resp resp; 2400 int ret; 2401 2402 if (!ena_com_check_supported_feature_id(ena_dev, 2403 ENA_ADMIN_RSS_HASH_INPUT)) { 2404 pr_debug("Feature %d isn't supported\n", 2405 ENA_ADMIN_RSS_HASH_INPUT); 2406 return -EOPNOTSUPP; 2407 } 2408 2409 memset(&cmd, 0x0, sizeof(cmd)); 2410 2411 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2412 cmd.aq_common_descriptor.flags = 2413 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2414 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT; 2415 cmd.u.flow_hash_input.enabled_input_sort = 2416 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK | 2417 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK; 2418 2419 ret = ena_com_mem_addr_set(ena_dev, 2420 &cmd.control_buffer.address, 2421 rss->hash_ctrl_dma_addr); 2422 if (unlikely(ret)) { 2423 pr_err("memory address set failed\n"); 2424 return ret; 2425 } 2426 cmd.control_buffer.length = sizeof(*hash_ctrl); 2427 2428 ret = ena_com_execute_admin_command(admin_queue, 2429 (struct ena_admin_aq_entry *)&cmd, 2430 sizeof(cmd), 2431 (struct ena_admin_acq_entry *)&resp, 2432 sizeof(resp)); 2433 if (unlikely(ret)) 2434 pr_err("Failed to set hash input. error: %d\n", ret); 2435 2436 return ret; 2437 } 2438 2439 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev) 2440 { 2441 struct ena_rss *rss = &ena_dev->rss; 2442 struct ena_admin_feature_rss_hash_control *hash_ctrl = 2443 rss->hash_ctrl; 2444 u16 available_fields = 0; 2445 int rc, i; 2446 2447 /* Get the supported hash input */ 2448 rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2449 if (unlikely(rc)) 2450 return rc; 2451 2452 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields = 2453 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2454 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2455 2456 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields = 2457 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2458 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2459 2460 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields = 2461 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2462 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2463 2464 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields = 2465 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2466 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2467 2468 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields = 2469 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2470 2471 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields = 2472 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2473 2474 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields = 2475 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2476 2477 hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields = 2478 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA; 2479 2480 for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) { 2481 available_fields = hash_ctrl->selected_fields[i].fields & 2482 hash_ctrl->supported_fields[i].fields; 2483 if (available_fields != hash_ctrl->selected_fields[i].fields) { 2484 pr_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n", 2485 i, hash_ctrl->supported_fields[i].fields, 2486 hash_ctrl->selected_fields[i].fields); 2487 return -EOPNOTSUPP; 2488 } 2489 } 2490 2491 rc = ena_com_set_hash_ctrl(ena_dev); 2492 2493 /* In case of failure, restore the old hash ctrl */ 2494 if (unlikely(rc)) 2495 ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2496 2497 return rc; 2498 } 2499 2500 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev, 2501 enum ena_admin_flow_hash_proto proto, 2502 u16 hash_fields) 2503 { 2504 struct ena_rss *rss = &ena_dev->rss; 2505 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl; 2506 u16 supported_fields; 2507 int rc; 2508 2509 if (proto >= ENA_ADMIN_RSS_PROTO_NUM) { 2510 pr_err("Invalid proto num (%u)\n", proto); 2511 return -EINVAL; 2512 } 2513 2514 /* Get the ctrl table */ 2515 rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL); 2516 if (unlikely(rc)) 2517 return rc; 2518 2519 /* Make sure all the fields are supported */ 2520 supported_fields = hash_ctrl->supported_fields[proto].fields; 2521 if ((hash_fields & supported_fields) != hash_fields) { 2522 pr_err("proto %d doesn't support the required fields %x. supports only: %x\n", 2523 proto, hash_fields, supported_fields); 2524 } 2525 2526 hash_ctrl->selected_fields[proto].fields = hash_fields; 2527 2528 rc = ena_com_set_hash_ctrl(ena_dev); 2529 2530 /* In case of failure, restore the old hash ctrl */ 2531 if (unlikely(rc)) 2532 ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2533 2534 return 0; 2535 } 2536 2537 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev, 2538 u16 entry_idx, u16 entry_value) 2539 { 2540 struct ena_rss *rss = &ena_dev->rss; 2541 2542 if (unlikely(entry_idx >= (1 << rss->tbl_log_size))) 2543 return -EINVAL; 2544 2545 if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES))) 2546 return -EINVAL; 2547 2548 rss->host_rss_ind_tbl[entry_idx] = entry_value; 2549 2550 return 0; 2551 } 2552 2553 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) 2554 { 2555 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 2556 struct ena_rss *rss = &ena_dev->rss; 2557 struct ena_admin_set_feat_cmd cmd; 2558 struct ena_admin_set_feat_resp resp; 2559 int ret; 2560 2561 if (!ena_com_check_supported_feature_id( 2562 ena_dev, ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) { 2563 pr_debug("Feature %d isn't supported\n", 2564 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG); 2565 return -EOPNOTSUPP; 2566 } 2567 2568 ret = ena_com_ind_tbl_convert_to_device(ena_dev); 2569 if (ret) { 2570 pr_err("Failed to convert host indirection table to device table\n"); 2571 return ret; 2572 } 2573 2574 memset(&cmd, 0x0, sizeof(cmd)); 2575 2576 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2577 cmd.aq_common_descriptor.flags = 2578 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2579 cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG; 2580 cmd.u.ind_table.size = rss->tbl_log_size; 2581 cmd.u.ind_table.inline_index = 0xFFFFFFFF; 2582 2583 ret = ena_com_mem_addr_set(ena_dev, 2584 &cmd.control_buffer.address, 2585 rss->rss_ind_tbl_dma_addr); 2586 if (unlikely(ret)) { 2587 pr_err("memory address set failed\n"); 2588 return ret; 2589 } 2590 2591 cmd.control_buffer.length = (1ULL << rss->tbl_log_size) * 2592 sizeof(struct ena_admin_rss_ind_table_entry); 2593 2594 ret = ena_com_execute_admin_command(admin_queue, 2595 (struct ena_admin_aq_entry *)&cmd, 2596 sizeof(cmd), 2597 (struct ena_admin_acq_entry *)&resp, 2598 sizeof(resp)); 2599 2600 if (unlikely(ret)) 2601 pr_err("Failed to set indirect table. error: %d\n", ret); 2602 2603 return ret; 2604 } 2605 2606 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl) 2607 { 2608 struct ena_rss *rss = &ena_dev->rss; 2609 struct ena_admin_get_feat_resp get_resp; 2610 u32 tbl_size; 2611 int i, rc; 2612 2613 tbl_size = (1ULL << rss->tbl_log_size) * 2614 sizeof(struct ena_admin_rss_ind_table_entry); 2615 2616 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2617 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 2618 rss->rss_ind_tbl_dma_addr, 2619 tbl_size, 0); 2620 if (unlikely(rc)) 2621 return rc; 2622 2623 if (!ind_tbl) 2624 return 0; 2625 2626 for (i = 0; i < (1 << rss->tbl_log_size); i++) 2627 ind_tbl[i] = rss->host_rss_ind_tbl[i]; 2628 2629 return 0; 2630 } 2631 2632 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size) 2633 { 2634 int rc; 2635 2636 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss)); 2637 2638 rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size); 2639 if (unlikely(rc)) 2640 goto err_indr_tbl; 2641 2642 /* The following function might return unsupported in case the 2643 * device doesn't support setting the key / hash function. We can safely 2644 * ignore this error and have indirection table support only. 2645 */ 2646 rc = ena_com_hash_key_allocate(ena_dev); 2647 if (likely(!rc)) 2648 ena_com_hash_key_fill_default_key(ena_dev); 2649 else if (rc != -EOPNOTSUPP) 2650 goto err_hash_key; 2651 2652 rc = ena_com_hash_ctrl_init(ena_dev); 2653 if (unlikely(rc)) 2654 goto err_hash_ctrl; 2655 2656 return 0; 2657 2658 err_hash_ctrl: 2659 ena_com_hash_key_destroy(ena_dev); 2660 err_hash_key: 2661 ena_com_indirect_table_destroy(ena_dev); 2662 err_indr_tbl: 2663 2664 return rc; 2665 } 2666 2667 void ena_com_rss_destroy(struct ena_com_dev *ena_dev) 2668 { 2669 ena_com_indirect_table_destroy(ena_dev); 2670 ena_com_hash_key_destroy(ena_dev); 2671 ena_com_hash_ctrl_destroy(ena_dev); 2672 2673 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss)); 2674 } 2675 2676 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev) 2677 { 2678 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2679 2680 host_attr->host_info = 2681 dma_alloc_coherent(ena_dev->dmadev, SZ_4K, 2682 &host_attr->host_info_dma_addr, GFP_KERNEL); 2683 if (unlikely(!host_attr->host_info)) 2684 return -ENOMEM; 2685 2686 host_attr->host_info->ena_spec_version = ((ENA_COMMON_SPEC_VERSION_MAJOR << 2687 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) | 2688 (ENA_COMMON_SPEC_VERSION_MINOR)); 2689 2690 return 0; 2691 } 2692 2693 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev, 2694 u32 debug_area_size) 2695 { 2696 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2697 2698 host_attr->debug_area_virt_addr = 2699 dma_alloc_coherent(ena_dev->dmadev, debug_area_size, 2700 &host_attr->debug_area_dma_addr, 2701 GFP_KERNEL); 2702 if (unlikely(!host_attr->debug_area_virt_addr)) { 2703 host_attr->debug_area_size = 0; 2704 return -ENOMEM; 2705 } 2706 2707 host_attr->debug_area_size = debug_area_size; 2708 2709 return 0; 2710 } 2711 2712 void ena_com_delete_host_info(struct ena_com_dev *ena_dev) 2713 { 2714 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2715 2716 if (host_attr->host_info) { 2717 dma_free_coherent(ena_dev->dmadev, SZ_4K, host_attr->host_info, 2718 host_attr->host_info_dma_addr); 2719 host_attr->host_info = NULL; 2720 } 2721 } 2722 2723 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev) 2724 { 2725 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2726 2727 if (host_attr->debug_area_virt_addr) { 2728 dma_free_coherent(ena_dev->dmadev, host_attr->debug_area_size, 2729 host_attr->debug_area_virt_addr, 2730 host_attr->debug_area_dma_addr); 2731 host_attr->debug_area_virt_addr = NULL; 2732 } 2733 } 2734 2735 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev) 2736 { 2737 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2738 struct ena_com_admin_queue *admin_queue; 2739 struct ena_admin_set_feat_cmd cmd; 2740 struct ena_admin_set_feat_resp resp; 2741 2742 int ret; 2743 2744 /* Host attribute config is called before ena_com_get_dev_attr_feat 2745 * so ena_com can't check if the feature is supported. 2746 */ 2747 2748 memset(&cmd, 0x0, sizeof(cmd)); 2749 admin_queue = &ena_dev->admin_queue; 2750 2751 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2752 cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG; 2753 2754 ret = ena_com_mem_addr_set(ena_dev, 2755 &cmd.u.host_attr.debug_ba, 2756 host_attr->debug_area_dma_addr); 2757 if (unlikely(ret)) { 2758 pr_err("memory address set failed\n"); 2759 return ret; 2760 } 2761 2762 ret = ena_com_mem_addr_set(ena_dev, 2763 &cmd.u.host_attr.os_info_ba, 2764 host_attr->host_info_dma_addr); 2765 if (unlikely(ret)) { 2766 pr_err("memory address set failed\n"); 2767 return ret; 2768 } 2769 2770 cmd.u.host_attr.debug_area_size = host_attr->debug_area_size; 2771 2772 ret = ena_com_execute_admin_command(admin_queue, 2773 (struct ena_admin_aq_entry *)&cmd, 2774 sizeof(cmd), 2775 (struct ena_admin_acq_entry *)&resp, 2776 sizeof(resp)); 2777 2778 if (unlikely(ret)) 2779 pr_err("Failed to set host attributes: %d\n", ret); 2780 2781 return ret; 2782 } 2783 2784 /* Interrupt moderation */ 2785 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev) 2786 { 2787 return ena_com_check_supported_feature_id(ena_dev, 2788 ENA_ADMIN_INTERRUPT_MODERATION); 2789 } 2790 2791 static int ena_com_update_nonadaptive_moderation_interval(u32 coalesce_usecs, 2792 u32 intr_delay_resolution, 2793 u32 *intr_moder_interval) 2794 { 2795 if (!intr_delay_resolution) { 2796 pr_err("Illegal interrupt delay granularity value\n"); 2797 return -EFAULT; 2798 } 2799 2800 *intr_moder_interval = coalesce_usecs / intr_delay_resolution; 2801 2802 return 0; 2803 } 2804 2805 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev, 2806 u32 tx_coalesce_usecs) 2807 { 2808 return ena_com_update_nonadaptive_moderation_interval(tx_coalesce_usecs, 2809 ena_dev->intr_delay_resolution, 2810 &ena_dev->intr_moder_tx_interval); 2811 } 2812 2813 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev, 2814 u32 rx_coalesce_usecs) 2815 { 2816 return ena_com_update_nonadaptive_moderation_interval(rx_coalesce_usecs, 2817 ena_dev->intr_delay_resolution, 2818 &ena_dev->intr_moder_rx_interval); 2819 } 2820 2821 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev) 2822 { 2823 struct ena_admin_get_feat_resp get_resp; 2824 u16 delay_resolution; 2825 int rc; 2826 2827 rc = ena_com_get_feature(ena_dev, &get_resp, 2828 ENA_ADMIN_INTERRUPT_MODERATION, 0); 2829 2830 if (rc) { 2831 if (rc == -EOPNOTSUPP) { 2832 pr_debug("Feature %d isn't supported\n", 2833 ENA_ADMIN_INTERRUPT_MODERATION); 2834 rc = 0; 2835 } else { 2836 pr_err("Failed to get interrupt moderation admin cmd. rc: %d\n", 2837 rc); 2838 } 2839 2840 /* no moderation supported, disable adaptive support */ 2841 ena_com_disable_adaptive_moderation(ena_dev); 2842 return rc; 2843 } 2844 2845 /* if moderation is supported by device we set adaptive moderation */ 2846 delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution; 2847 ena_com_update_intr_delay_resolution(ena_dev, delay_resolution); 2848 2849 /* Disable adaptive moderation by default - can be enabled later */ 2850 ena_com_disable_adaptive_moderation(ena_dev); 2851 2852 return 0; 2853 } 2854 2855 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev) 2856 { 2857 return ena_dev->intr_moder_tx_interval; 2858 } 2859 2860 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev) 2861 { 2862 return ena_dev->intr_moder_rx_interval; 2863 } 2864 2865 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev, 2866 struct ena_admin_feature_llq_desc *llq_features, 2867 struct ena_llq_configurations *llq_default_cfg) 2868 { 2869 struct ena_com_llq_info *llq_info = &ena_dev->llq_info; 2870 int rc; 2871 2872 if (!llq_features->max_llq_num) { 2873 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 2874 return 0; 2875 } 2876 2877 rc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg); 2878 if (rc) 2879 return rc; 2880 2881 ena_dev->tx_max_header_size = llq_info->desc_list_entry_size - 2882 (llq_info->descs_num_before_header * sizeof(struct ena_eth_io_tx_desc)); 2883 2884 if (unlikely(ena_dev->tx_max_header_size == 0)) { 2885 pr_err("the size of the LLQ entry is smaller than needed\n"); 2886 return -EINVAL; 2887 } 2888 2889 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV; 2890 2891 return 0; 2892 } 2893