1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2 /* 3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved. 4 */ 5 6 #include "ena_com.h" 7 8 /*****************************************************************************/ 9 /*****************************************************************************/ 10 11 /* Timeout in micro-sec */ 12 #define ADMIN_CMD_TIMEOUT_US (3000000) 13 14 #define ENA_ASYNC_QUEUE_DEPTH 16 15 #define ENA_ADMIN_QUEUE_DEPTH 32 16 17 18 #define ENA_CTRL_MAJOR 0 19 #define ENA_CTRL_MINOR 0 20 #define ENA_CTRL_SUB_MINOR 1 21 22 #define MIN_ENA_CTRL_VER \ 23 (((ENA_CTRL_MAJOR) << \ 24 (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \ 25 ((ENA_CTRL_MINOR) << \ 26 (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \ 27 (ENA_CTRL_SUB_MINOR)) 28 29 #define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x))) 30 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32)) 31 32 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF 33 34 #define ENA_COM_BOUNCE_BUFFER_CNTRL_CNT 4 35 36 #define ENA_REGS_ADMIN_INTR_MASK 1 37 38 #define ENA_MAX_BACKOFF_DELAY_EXP 16U 39 40 #define ENA_MIN_ADMIN_POLL_US 100 41 42 #define ENA_MAX_ADMIN_POLL_US 5000 43 44 /*****************************************************************************/ 45 /*****************************************************************************/ 46 /*****************************************************************************/ 47 48 enum ena_cmd_status { 49 ENA_CMD_SUBMITTED, 50 ENA_CMD_COMPLETED, 51 /* Abort - canceled by the driver */ 52 ENA_CMD_ABORTED, 53 }; 54 55 struct ena_comp_ctx { 56 struct completion wait_event; 57 struct ena_admin_acq_entry *user_cqe; 58 u32 comp_size; 59 enum ena_cmd_status status; 60 /* status from the device */ 61 u8 comp_status; 62 u8 cmd_opcode; 63 bool occupied; 64 }; 65 66 struct ena_com_stats_ctx { 67 struct ena_admin_aq_get_stats_cmd get_cmd; 68 struct ena_admin_acq_get_stats_resp get_resp; 69 }; 70 71 static int ena_com_mem_addr_set(struct ena_com_dev *ena_dev, 72 struct ena_common_mem_addr *ena_addr, 73 dma_addr_t addr) 74 { 75 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) { 76 netdev_err(ena_dev->net_device, 77 "DMA address has more bits that the device supports\n"); 78 return -EINVAL; 79 } 80 81 ena_addr->mem_addr_low = lower_32_bits(addr); 82 ena_addr->mem_addr_high = (u16)upper_32_bits(addr); 83 84 return 0; 85 } 86 87 static int ena_com_admin_init_sq(struct ena_com_admin_queue *admin_queue) 88 { 89 struct ena_com_dev *ena_dev = admin_queue->ena_dev; 90 struct ena_com_admin_sq *sq = &admin_queue->sq; 91 u16 size = ADMIN_SQ_SIZE(admin_queue->q_depth); 92 93 sq->entries = dma_alloc_coherent(admin_queue->q_dmadev, size, &sq->dma_addr, GFP_KERNEL); 94 95 if (!sq->entries) { 96 netdev_err(ena_dev->net_device, "Memory allocation failed\n"); 97 return -ENOMEM; 98 } 99 100 sq->head = 0; 101 sq->tail = 0; 102 sq->phase = 1; 103 104 sq->db_addr = NULL; 105 106 return 0; 107 } 108 109 static int ena_com_admin_init_cq(struct ena_com_admin_queue *admin_queue) 110 { 111 struct ena_com_dev *ena_dev = admin_queue->ena_dev; 112 struct ena_com_admin_cq *cq = &admin_queue->cq; 113 u16 size = ADMIN_CQ_SIZE(admin_queue->q_depth); 114 115 cq->entries = dma_alloc_coherent(admin_queue->q_dmadev, size, &cq->dma_addr, GFP_KERNEL); 116 117 if (!cq->entries) { 118 netdev_err(ena_dev->net_device, "Memory allocation failed\n"); 119 return -ENOMEM; 120 } 121 122 cq->head = 0; 123 cq->phase = 1; 124 125 return 0; 126 } 127 128 static int ena_com_admin_init_aenq(struct ena_com_dev *ena_dev, 129 struct ena_aenq_handlers *aenq_handlers) 130 { 131 struct ena_com_aenq *aenq = &ena_dev->aenq; 132 u32 addr_low, addr_high, aenq_caps; 133 u16 size; 134 135 ena_dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH; 136 size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH); 137 aenq->entries = dma_alloc_coherent(ena_dev->dmadev, size, &aenq->dma_addr, GFP_KERNEL); 138 139 if (!aenq->entries) { 140 netdev_err(ena_dev->net_device, "Memory allocation failed\n"); 141 return -ENOMEM; 142 } 143 144 aenq->head = aenq->q_depth; 145 aenq->phase = 1; 146 147 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr); 148 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr); 149 150 writel(addr_low, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF); 151 writel(addr_high, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF); 152 153 aenq_caps = 0; 154 aenq_caps |= ena_dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK; 155 aenq_caps |= 156 (sizeof(struct ena_admin_aenq_entry) << ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) & 157 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK; 158 writel(aenq_caps, ena_dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF); 159 160 if (unlikely(!aenq_handlers)) { 161 netdev_err(ena_dev->net_device, "AENQ handlers pointer is NULL\n"); 162 return -EINVAL; 163 } 164 165 aenq->aenq_handlers = aenq_handlers; 166 167 return 0; 168 } 169 170 static void comp_ctxt_release(struct ena_com_admin_queue *queue, 171 struct ena_comp_ctx *comp_ctx) 172 { 173 comp_ctx->occupied = false; 174 atomic_dec(&queue->outstanding_cmds); 175 } 176 177 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *admin_queue, 178 u16 command_id, bool capture) 179 { 180 if (unlikely(command_id >= admin_queue->q_depth)) { 181 netdev_err(admin_queue->ena_dev->net_device, 182 "Command id is larger than the queue size. cmd_id: %u queue size %d\n", 183 command_id, admin_queue->q_depth); 184 return NULL; 185 } 186 187 if (unlikely(!admin_queue->comp_ctx)) { 188 netdev_err(admin_queue->ena_dev->net_device, "Completion context is NULL\n"); 189 return NULL; 190 } 191 192 if (unlikely(admin_queue->comp_ctx[command_id].occupied && capture)) { 193 netdev_err(admin_queue->ena_dev->net_device, "Completion context is occupied\n"); 194 return NULL; 195 } 196 197 if (capture) { 198 atomic_inc(&admin_queue->outstanding_cmds); 199 admin_queue->comp_ctx[command_id].occupied = true; 200 } 201 202 return &admin_queue->comp_ctx[command_id]; 203 } 204 205 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue, 206 struct ena_admin_aq_entry *cmd, 207 size_t cmd_size_in_bytes, 208 struct ena_admin_acq_entry *comp, 209 size_t comp_size_in_bytes) 210 { 211 struct ena_comp_ctx *comp_ctx; 212 u16 tail_masked, cmd_id; 213 u16 queue_size_mask; 214 u16 cnt; 215 216 queue_size_mask = admin_queue->q_depth - 1; 217 218 tail_masked = admin_queue->sq.tail & queue_size_mask; 219 220 /* In case of queue FULL */ 221 cnt = (u16)atomic_read(&admin_queue->outstanding_cmds); 222 if (cnt >= admin_queue->q_depth) { 223 netdev_dbg(admin_queue->ena_dev->net_device, "Admin queue is full.\n"); 224 admin_queue->stats.out_of_space++; 225 return ERR_PTR(-ENOSPC); 226 } 227 228 cmd_id = admin_queue->curr_cmd_id; 229 230 cmd->aq_common_descriptor.flags |= admin_queue->sq.phase & 231 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK; 232 233 cmd->aq_common_descriptor.command_id |= cmd_id & 234 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK; 235 236 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true); 237 if (unlikely(!comp_ctx)) 238 return ERR_PTR(-EINVAL); 239 240 comp_ctx->status = ENA_CMD_SUBMITTED; 241 comp_ctx->comp_size = (u32)comp_size_in_bytes; 242 comp_ctx->user_cqe = comp; 243 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode; 244 245 reinit_completion(&comp_ctx->wait_event); 246 247 memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes); 248 249 admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) & 250 queue_size_mask; 251 252 admin_queue->sq.tail++; 253 admin_queue->stats.submitted_cmd++; 254 255 if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0)) 256 admin_queue->sq.phase = !admin_queue->sq.phase; 257 258 writel(admin_queue->sq.tail, admin_queue->sq.db_addr); 259 260 return comp_ctx; 261 } 262 263 static int ena_com_init_comp_ctxt(struct ena_com_admin_queue *admin_queue) 264 { 265 struct ena_com_dev *ena_dev = admin_queue->ena_dev; 266 size_t size = admin_queue->q_depth * sizeof(struct ena_comp_ctx); 267 struct ena_comp_ctx *comp_ctx; 268 u16 i; 269 270 admin_queue->comp_ctx = devm_kzalloc(admin_queue->q_dmadev, size, GFP_KERNEL); 271 if (unlikely(!admin_queue->comp_ctx)) { 272 netdev_err(ena_dev->net_device, "Memory allocation failed\n"); 273 return -ENOMEM; 274 } 275 276 for (i = 0; i < admin_queue->q_depth; i++) { 277 comp_ctx = get_comp_ctxt(admin_queue, i, false); 278 if (comp_ctx) 279 init_completion(&comp_ctx->wait_event); 280 } 281 282 return 0; 283 } 284 285 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue, 286 struct ena_admin_aq_entry *cmd, 287 size_t cmd_size_in_bytes, 288 struct ena_admin_acq_entry *comp, 289 size_t comp_size_in_bytes) 290 { 291 unsigned long flags = 0; 292 struct ena_comp_ctx *comp_ctx; 293 294 spin_lock_irqsave(&admin_queue->q_lock, flags); 295 if (unlikely(!admin_queue->running_state)) { 296 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 297 return ERR_PTR(-ENODEV); 298 } 299 comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd, 300 cmd_size_in_bytes, 301 comp, 302 comp_size_in_bytes); 303 if (IS_ERR(comp_ctx)) 304 admin_queue->running_state = false; 305 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 306 307 return comp_ctx; 308 } 309 310 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev, 311 struct ena_com_create_io_ctx *ctx, 312 struct ena_com_io_sq *io_sq) 313 { 314 size_t size; 315 316 memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr)); 317 318 io_sq->dma_addr_bits = (u8)ena_dev->dma_addr_bits; 319 io_sq->desc_entry_size = 320 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ? 321 sizeof(struct ena_eth_io_tx_desc) : 322 sizeof(struct ena_eth_io_rx_desc); 323 324 size = io_sq->desc_entry_size * io_sq->q_depth; 325 326 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) { 327 io_sq->desc_addr.virt_addr = 328 dma_alloc_coherent(ena_dev->dmadev, size, &io_sq->desc_addr.phys_addr, 329 GFP_KERNEL); 330 if (!io_sq->desc_addr.virt_addr) { 331 io_sq->desc_addr.virt_addr = 332 dma_alloc_coherent(ena_dev->dmadev, size, 333 &io_sq->desc_addr.phys_addr, GFP_KERNEL); 334 } 335 336 if (!io_sq->desc_addr.virt_addr) { 337 netdev_err(ena_dev->net_device, "Memory allocation failed\n"); 338 return -ENOMEM; 339 } 340 } 341 342 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 343 /* Allocate bounce buffers */ 344 io_sq->bounce_buf_ctrl.buffer_size = 345 ena_dev->llq_info.desc_list_entry_size; 346 io_sq->bounce_buf_ctrl.buffers_num = 347 ENA_COM_BOUNCE_BUFFER_CNTRL_CNT; 348 io_sq->bounce_buf_ctrl.next_to_use = 0; 349 350 size = (size_t)io_sq->bounce_buf_ctrl.buffer_size * 351 io_sq->bounce_buf_ctrl.buffers_num; 352 353 io_sq->bounce_buf_ctrl.base_buffer = devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL); 354 if (!io_sq->bounce_buf_ctrl.base_buffer) 355 io_sq->bounce_buf_ctrl.base_buffer = 356 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL); 357 358 if (!io_sq->bounce_buf_ctrl.base_buffer) { 359 netdev_err(ena_dev->net_device, "Bounce buffer memory allocation failed\n"); 360 return -ENOMEM; 361 } 362 363 memcpy(&io_sq->llq_info, &ena_dev->llq_info, 364 sizeof(io_sq->llq_info)); 365 366 /* Initiate the first bounce buffer */ 367 io_sq->llq_buf_ctrl.curr_bounce_buf = 368 ena_com_get_next_bounce_buffer(&io_sq->bounce_buf_ctrl); 369 memset(io_sq->llq_buf_ctrl.curr_bounce_buf, 370 0x0, io_sq->llq_info.desc_list_entry_size); 371 io_sq->llq_buf_ctrl.descs_left_in_line = 372 io_sq->llq_info.descs_num_before_header; 373 io_sq->disable_meta_caching = 374 io_sq->llq_info.disable_meta_caching; 375 376 if (io_sq->llq_info.max_entries_in_tx_burst > 0) 377 io_sq->entries_in_tx_burst_left = 378 io_sq->llq_info.max_entries_in_tx_burst; 379 } 380 381 io_sq->tail = 0; 382 io_sq->next_to_comp = 0; 383 io_sq->phase = 1; 384 385 return 0; 386 } 387 388 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev, 389 struct ena_com_create_io_ctx *ctx, 390 struct ena_com_io_cq *io_cq) 391 { 392 size_t size; 393 394 memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr)); 395 396 /* Use the basic completion descriptor for Rx */ 397 io_cq->cdesc_entry_size_in_bytes = 398 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ? 399 sizeof(struct ena_eth_io_tx_cdesc) : 400 sizeof(struct ena_eth_io_rx_cdesc_base); 401 402 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth; 403 404 io_cq->cdesc_addr.virt_addr = 405 dma_alloc_coherent(ena_dev->dmadev, size, &io_cq->cdesc_addr.phys_addr, GFP_KERNEL); 406 if (!io_cq->cdesc_addr.virt_addr) { 407 io_cq->cdesc_addr.virt_addr = 408 dma_alloc_coherent(ena_dev->dmadev, size, &io_cq->cdesc_addr.phys_addr, 409 GFP_KERNEL); 410 } 411 412 if (!io_cq->cdesc_addr.virt_addr) { 413 netdev_err(ena_dev->net_device, "Memory allocation failed\n"); 414 return -ENOMEM; 415 } 416 417 io_cq->phase = 1; 418 io_cq->head = 0; 419 420 return 0; 421 } 422 423 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue, 424 struct ena_admin_acq_entry *cqe) 425 { 426 struct ena_comp_ctx *comp_ctx; 427 u16 cmd_id; 428 429 cmd_id = cqe->acq_common_descriptor.command & 430 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK; 431 432 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false); 433 if (unlikely(!comp_ctx)) { 434 netdev_err(admin_queue->ena_dev->net_device, 435 "comp_ctx is NULL. Changing the admin queue running state\n"); 436 admin_queue->running_state = false; 437 return; 438 } 439 440 comp_ctx->status = ENA_CMD_COMPLETED; 441 comp_ctx->comp_status = cqe->acq_common_descriptor.status; 442 443 if (comp_ctx->user_cqe) 444 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size); 445 446 if (!admin_queue->polling) 447 complete(&comp_ctx->wait_event); 448 } 449 450 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue) 451 { 452 struct ena_admin_acq_entry *cqe = NULL; 453 u16 comp_num = 0; 454 u16 head_masked; 455 u8 phase; 456 457 head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1); 458 phase = admin_queue->cq.phase; 459 460 cqe = &admin_queue->cq.entries[head_masked]; 461 462 /* Go over all the completions */ 463 while ((READ_ONCE(cqe->acq_common_descriptor.flags) & 464 ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) { 465 /* Do not read the rest of the completion entry before the 466 * phase bit was validated 467 */ 468 dma_rmb(); 469 ena_com_handle_single_admin_completion(admin_queue, cqe); 470 471 head_masked++; 472 comp_num++; 473 if (unlikely(head_masked == admin_queue->q_depth)) { 474 head_masked = 0; 475 phase = !phase; 476 } 477 478 cqe = &admin_queue->cq.entries[head_masked]; 479 } 480 481 admin_queue->cq.head += comp_num; 482 admin_queue->cq.phase = phase; 483 admin_queue->sq.head += comp_num; 484 admin_queue->stats.completed_cmd += comp_num; 485 } 486 487 static int ena_com_comp_status_to_errno(struct ena_com_admin_queue *admin_queue, 488 u8 comp_status) 489 { 490 if (unlikely(comp_status != 0)) 491 netdev_err(admin_queue->ena_dev->net_device, "Admin command failed[%u]\n", 492 comp_status); 493 494 switch (comp_status) { 495 case ENA_ADMIN_SUCCESS: 496 return 0; 497 case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE: 498 return -ENOMEM; 499 case ENA_ADMIN_UNSUPPORTED_OPCODE: 500 return -EOPNOTSUPP; 501 case ENA_ADMIN_BAD_OPCODE: 502 case ENA_ADMIN_MALFORMED_REQUEST: 503 case ENA_ADMIN_ILLEGAL_PARAMETER: 504 case ENA_ADMIN_UNKNOWN_ERROR: 505 return -EINVAL; 506 case ENA_ADMIN_RESOURCE_BUSY: 507 return -EAGAIN; 508 } 509 510 return -EINVAL; 511 } 512 513 static void ena_delay_exponential_backoff_us(u32 exp, u32 delay_us) 514 { 515 exp = min_t(u32, exp, ENA_MAX_BACKOFF_DELAY_EXP); 516 delay_us = max_t(u32, ENA_MIN_ADMIN_POLL_US, delay_us); 517 delay_us = min_t(u32, delay_us * (1U << exp), ENA_MAX_ADMIN_POLL_US); 518 usleep_range(delay_us, 2 * delay_us); 519 } 520 521 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx, 522 struct ena_com_admin_queue *admin_queue) 523 { 524 unsigned long flags = 0; 525 unsigned long timeout; 526 int ret; 527 u32 exp = 0; 528 529 timeout = jiffies + usecs_to_jiffies(admin_queue->completion_timeout); 530 531 while (1) { 532 spin_lock_irqsave(&admin_queue->q_lock, flags); 533 ena_com_handle_admin_completion(admin_queue); 534 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 535 536 if (comp_ctx->status != ENA_CMD_SUBMITTED) 537 break; 538 539 if (time_is_before_jiffies(timeout)) { 540 netdev_err(admin_queue->ena_dev->net_device, 541 "Wait for completion (polling) timeout\n"); 542 /* ENA didn't have any completion */ 543 spin_lock_irqsave(&admin_queue->q_lock, flags); 544 admin_queue->stats.no_completion++; 545 admin_queue->running_state = false; 546 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 547 548 ret = -ETIME; 549 goto err; 550 } 551 552 ena_delay_exponential_backoff_us(exp++, 553 admin_queue->ena_dev->ena_min_poll_delay_us); 554 } 555 556 if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) { 557 netdev_err(admin_queue->ena_dev->net_device, "Command was aborted\n"); 558 spin_lock_irqsave(&admin_queue->q_lock, flags); 559 admin_queue->stats.aborted_cmd++; 560 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 561 ret = -ENODEV; 562 goto err; 563 } 564 565 WARN(comp_ctx->status != ENA_CMD_COMPLETED, "Invalid comp status %d\n", comp_ctx->status); 566 567 ret = ena_com_comp_status_to_errno(admin_queue, comp_ctx->comp_status); 568 err: 569 comp_ctxt_release(admin_queue, comp_ctx); 570 return ret; 571 } 572 573 /* 574 * Set the LLQ configurations of the firmware 575 * 576 * The driver provides only the enabled feature values to the device, 577 * which in turn, checks if they are supported. 578 */ 579 static int ena_com_set_llq(struct ena_com_dev *ena_dev) 580 { 581 struct ena_com_admin_queue *admin_queue; 582 struct ena_admin_set_feat_cmd cmd; 583 struct ena_admin_set_feat_resp resp; 584 struct ena_com_llq_info *llq_info = &ena_dev->llq_info; 585 int ret; 586 587 memset(&cmd, 0x0, sizeof(cmd)); 588 admin_queue = &ena_dev->admin_queue; 589 590 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 591 cmd.feat_common.feature_id = ENA_ADMIN_LLQ; 592 593 cmd.u.llq.header_location_ctrl_enabled = llq_info->header_location_ctrl; 594 cmd.u.llq.entry_size_ctrl_enabled = llq_info->desc_list_entry_size_ctrl; 595 cmd.u.llq.desc_num_before_header_enabled = llq_info->descs_num_before_header; 596 cmd.u.llq.descriptors_stride_ctrl_enabled = llq_info->desc_stride_ctrl; 597 598 cmd.u.llq.accel_mode.u.set.enabled_flags = 599 BIT(ENA_ADMIN_DISABLE_META_CACHING) | 600 BIT(ENA_ADMIN_LIMIT_TX_BURST); 601 602 ret = ena_com_execute_admin_command(admin_queue, 603 (struct ena_admin_aq_entry *)&cmd, 604 sizeof(cmd), 605 (struct ena_admin_acq_entry *)&resp, 606 sizeof(resp)); 607 608 if (unlikely(ret)) 609 netdev_err(ena_dev->net_device, "Failed to set LLQ configurations: %d\n", ret); 610 611 return ret; 612 } 613 614 static int ena_com_config_llq_info(struct ena_com_dev *ena_dev, 615 struct ena_admin_feature_llq_desc *llq_features, 616 struct ena_llq_configurations *llq_default_cfg) 617 { 618 struct ena_com_llq_info *llq_info = &ena_dev->llq_info; 619 struct ena_admin_accel_mode_get llq_accel_mode_get; 620 u16 supported_feat; 621 int rc; 622 623 memset(llq_info, 0, sizeof(*llq_info)); 624 625 supported_feat = llq_features->header_location_ctrl_supported; 626 627 if (likely(supported_feat & llq_default_cfg->llq_header_location)) { 628 llq_info->header_location_ctrl = 629 llq_default_cfg->llq_header_location; 630 } else { 631 netdev_err(ena_dev->net_device, 632 "Invalid header location control, supported: 0x%x\n", supported_feat); 633 return -EINVAL; 634 } 635 636 if (likely(llq_info->header_location_ctrl == ENA_ADMIN_INLINE_HEADER)) { 637 supported_feat = llq_features->descriptors_stride_ctrl_supported; 638 if (likely(supported_feat & llq_default_cfg->llq_stride_ctrl)) { 639 llq_info->desc_stride_ctrl = llq_default_cfg->llq_stride_ctrl; 640 } else { 641 if (supported_feat & ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) { 642 llq_info->desc_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY; 643 } else if (supported_feat & ENA_ADMIN_SINGLE_DESC_PER_ENTRY) { 644 llq_info->desc_stride_ctrl = ENA_ADMIN_SINGLE_DESC_PER_ENTRY; 645 } else { 646 netdev_err(ena_dev->net_device, 647 "Invalid desc_stride_ctrl, supported: 0x%x\n", 648 supported_feat); 649 return -EINVAL; 650 } 651 652 netdev_err(ena_dev->net_device, 653 "Default llq stride ctrl is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", 654 llq_default_cfg->llq_stride_ctrl, supported_feat, 655 llq_info->desc_stride_ctrl); 656 } 657 } else { 658 llq_info->desc_stride_ctrl = 0; 659 } 660 661 supported_feat = llq_features->entry_size_ctrl_supported; 662 if (likely(supported_feat & llq_default_cfg->llq_ring_entry_size)) { 663 llq_info->desc_list_entry_size_ctrl = llq_default_cfg->llq_ring_entry_size; 664 llq_info->desc_list_entry_size = llq_default_cfg->llq_ring_entry_size_value; 665 } else { 666 if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_128B) { 667 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_128B; 668 llq_info->desc_list_entry_size = 128; 669 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_192B) { 670 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_192B; 671 llq_info->desc_list_entry_size = 192; 672 } else if (supported_feat & ENA_ADMIN_LIST_ENTRY_SIZE_256B) { 673 llq_info->desc_list_entry_size_ctrl = ENA_ADMIN_LIST_ENTRY_SIZE_256B; 674 llq_info->desc_list_entry_size = 256; 675 } else { 676 netdev_err(ena_dev->net_device, 677 "Invalid entry_size_ctrl, supported: 0x%x\n", supported_feat); 678 return -EINVAL; 679 } 680 681 netdev_err(ena_dev->net_device, 682 "Default llq ring entry size is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", 683 llq_default_cfg->llq_ring_entry_size, supported_feat, 684 llq_info->desc_list_entry_size); 685 } 686 if (unlikely(llq_info->desc_list_entry_size & 0x7)) { 687 /* The desc list entry size should be whole multiply of 8 688 * This requirement comes from __iowrite64_copy() 689 */ 690 netdev_err(ena_dev->net_device, "Illegal entry size %d\n", 691 llq_info->desc_list_entry_size); 692 return -EINVAL; 693 } 694 695 if (llq_info->desc_stride_ctrl == ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY) 696 llq_info->descs_per_entry = llq_info->desc_list_entry_size / 697 sizeof(struct ena_eth_io_tx_desc); 698 else 699 llq_info->descs_per_entry = 1; 700 701 supported_feat = llq_features->desc_num_before_header_supported; 702 if (likely(supported_feat & llq_default_cfg->llq_num_decs_before_header)) { 703 llq_info->descs_num_before_header = llq_default_cfg->llq_num_decs_before_header; 704 } else { 705 if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2) { 706 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2; 707 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1) { 708 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1; 709 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4) { 710 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4; 711 } else if (supported_feat & ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8) { 712 llq_info->descs_num_before_header = ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8; 713 } else { 714 netdev_err(ena_dev->net_device, 715 "Invalid descs_num_before_header, supported: 0x%x\n", 716 supported_feat); 717 return -EINVAL; 718 } 719 720 netdev_err(ena_dev->net_device, 721 "Default llq num descs before header is not supported, performing fallback, default: 0x%x, supported: 0x%x, used: 0x%x\n", 722 llq_default_cfg->llq_num_decs_before_header, supported_feat, 723 llq_info->descs_num_before_header); 724 } 725 /* Check for accelerated queue supported */ 726 llq_accel_mode_get = llq_features->accel_mode.u.get; 727 728 llq_info->disable_meta_caching = 729 !!(llq_accel_mode_get.supported_flags & 730 BIT(ENA_ADMIN_DISABLE_META_CACHING)); 731 732 if (llq_accel_mode_get.supported_flags & BIT(ENA_ADMIN_LIMIT_TX_BURST)) 733 llq_info->max_entries_in_tx_burst = 734 llq_accel_mode_get.max_tx_burst_size / 735 llq_default_cfg->llq_ring_entry_size_value; 736 737 rc = ena_com_set_llq(ena_dev); 738 if (rc) 739 netdev_err(ena_dev->net_device, "Cannot set LLQ configuration: %d\n", rc); 740 741 return rc; 742 } 743 744 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx, 745 struct ena_com_admin_queue *admin_queue) 746 { 747 unsigned long flags = 0; 748 int ret; 749 750 wait_for_completion_timeout(&comp_ctx->wait_event, 751 usecs_to_jiffies(admin_queue->completion_timeout)); 752 753 /* In case the command wasn't completed find out the root cause. 754 * There might be 2 kinds of errors 755 * 1) No completion (timeout reached) 756 * 2) There is completion but the device didn't get any msi-x interrupt. 757 */ 758 if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) { 759 spin_lock_irqsave(&admin_queue->q_lock, flags); 760 ena_com_handle_admin_completion(admin_queue); 761 admin_queue->stats.no_completion++; 762 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 763 764 if (comp_ctx->status == ENA_CMD_COMPLETED) { 765 netdev_err(admin_queue->ena_dev->net_device, 766 "The ena device sent a completion but the driver didn't receive a MSI-X interrupt (cmd %d), autopolling mode is %s\n", 767 comp_ctx->cmd_opcode, admin_queue->auto_polling ? "ON" : "OFF"); 768 /* Check if fallback to polling is enabled */ 769 if (admin_queue->auto_polling) 770 admin_queue->polling = true; 771 } else { 772 netdev_err(admin_queue->ena_dev->net_device, 773 "The ena device didn't send a completion for the admin cmd %d status %d\n", 774 comp_ctx->cmd_opcode, comp_ctx->status); 775 } 776 /* Check if shifted to polling mode. 777 * This will happen if there is a completion without an interrupt 778 * and autopolling mode is enabled. Continuing normal execution in such case 779 */ 780 if (!admin_queue->polling) { 781 admin_queue->running_state = false; 782 ret = -ETIME; 783 goto err; 784 } 785 } 786 787 ret = ena_com_comp_status_to_errno(admin_queue, comp_ctx->comp_status); 788 err: 789 comp_ctxt_release(admin_queue, comp_ctx); 790 return ret; 791 } 792 793 /* This method read the hardware device register through posting writes 794 * and waiting for response 795 * On timeout the function will return ENA_MMIO_READ_TIMEOUT 796 */ 797 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset) 798 { 799 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 800 volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp = 801 mmio_read->read_resp; 802 u32 mmio_read_reg, ret, i; 803 unsigned long flags = 0; 804 u32 timeout = mmio_read->reg_read_to; 805 806 might_sleep(); 807 808 if (timeout == 0) 809 timeout = ENA_REG_READ_TIMEOUT; 810 811 /* If readless is disabled, perform regular read */ 812 if (!mmio_read->readless_supported) 813 return readl(ena_dev->reg_bar + offset); 814 815 spin_lock_irqsave(&mmio_read->lock, flags); 816 mmio_read->seq_num++; 817 818 read_resp->req_id = mmio_read->seq_num + 0xDEAD; 819 mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) & 820 ENA_REGS_MMIO_REG_READ_REG_OFF_MASK; 821 mmio_read_reg |= mmio_read->seq_num & 822 ENA_REGS_MMIO_REG_READ_REQ_ID_MASK; 823 824 writel(mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF); 825 826 for (i = 0; i < timeout; i++) { 827 if (READ_ONCE(read_resp->req_id) == mmio_read->seq_num) 828 break; 829 830 udelay(1); 831 } 832 833 if (unlikely(i == timeout)) { 834 netdev_err(ena_dev->net_device, 835 "Reading reg failed for timeout. expected: req id[%u] offset[%u] actual: req id[%u] offset[%u]\n", 836 mmio_read->seq_num, offset, read_resp->req_id, read_resp->reg_off); 837 ret = ENA_MMIO_READ_TIMEOUT; 838 goto err; 839 } 840 841 if (read_resp->reg_off != offset) { 842 netdev_err(ena_dev->net_device, "Read failure: wrong offset provided\n"); 843 ret = ENA_MMIO_READ_TIMEOUT; 844 } else { 845 ret = read_resp->reg_val; 846 } 847 err: 848 spin_unlock_irqrestore(&mmio_read->lock, flags); 849 850 return ret; 851 } 852 853 /* There are two types to wait for completion. 854 * Polling mode - wait until the completion is available. 855 * Async mode - wait on wait queue until the completion is ready 856 * (or the timeout expired). 857 * It is expected that the IRQ called ena_com_handle_admin_completion 858 * to mark the completions. 859 */ 860 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx, 861 struct ena_com_admin_queue *admin_queue) 862 { 863 if (admin_queue->polling) 864 return ena_com_wait_and_process_admin_cq_polling(comp_ctx, 865 admin_queue); 866 867 return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx, 868 admin_queue); 869 } 870 871 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev, 872 struct ena_com_io_sq *io_sq) 873 { 874 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 875 struct ena_admin_aq_destroy_sq_cmd destroy_cmd; 876 struct ena_admin_acq_destroy_sq_resp_desc destroy_resp; 877 u8 direction; 878 int ret; 879 880 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd)); 881 882 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 883 direction = ENA_ADMIN_SQ_DIRECTION_TX; 884 else 885 direction = ENA_ADMIN_SQ_DIRECTION_RX; 886 887 destroy_cmd.sq.sq_identity |= (direction << 888 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & 889 ENA_ADMIN_SQ_SQ_DIRECTION_MASK; 890 891 destroy_cmd.sq.sq_idx = io_sq->idx; 892 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ; 893 894 ret = ena_com_execute_admin_command(admin_queue, 895 (struct ena_admin_aq_entry *)&destroy_cmd, 896 sizeof(destroy_cmd), 897 (struct ena_admin_acq_entry *)&destroy_resp, 898 sizeof(destroy_resp)); 899 900 if (unlikely(ret && (ret != -ENODEV))) 901 netdev_err(ena_dev->net_device, "Failed to destroy io sq error: %d\n", ret); 902 903 return ret; 904 } 905 906 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev, 907 struct ena_com_io_sq *io_sq, 908 struct ena_com_io_cq *io_cq) 909 { 910 size_t size; 911 912 if (io_cq->cdesc_addr.virt_addr) { 913 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth; 914 915 dma_free_coherent(ena_dev->dmadev, size, io_cq->cdesc_addr.virt_addr, 916 io_cq->cdesc_addr.phys_addr); 917 918 io_cq->cdesc_addr.virt_addr = NULL; 919 } 920 921 if (io_sq->desc_addr.virt_addr) { 922 size = io_sq->desc_entry_size * io_sq->q_depth; 923 924 dma_free_coherent(ena_dev->dmadev, size, io_sq->desc_addr.virt_addr, 925 io_sq->desc_addr.phys_addr); 926 927 io_sq->desc_addr.virt_addr = NULL; 928 } 929 930 if (io_sq->bounce_buf_ctrl.base_buffer) { 931 devm_kfree(ena_dev->dmadev, io_sq->bounce_buf_ctrl.base_buffer); 932 io_sq->bounce_buf_ctrl.base_buffer = NULL; 933 } 934 } 935 936 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout, 937 u16 exp_state) 938 { 939 u32 val, exp = 0; 940 unsigned long timeout_stamp; 941 942 /* Convert timeout from resolution of 100ms to us resolution. */ 943 timeout_stamp = jiffies + usecs_to_jiffies(100 * 1000 * timeout); 944 945 while (1) { 946 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 947 948 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) { 949 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n"); 950 return -ETIME; 951 } 952 953 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) == 954 exp_state) 955 return 0; 956 957 if (time_is_before_jiffies(timeout_stamp)) 958 return -ETIME; 959 960 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us); 961 } 962 } 963 964 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev, 965 enum ena_admin_aq_feature_id feature_id) 966 { 967 u32 feature_mask = 1 << feature_id; 968 969 /* Device attributes is always supported */ 970 if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) && 971 !(ena_dev->supported_features & feature_mask)) 972 return false; 973 974 return true; 975 } 976 977 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev, 978 struct ena_admin_get_feat_resp *get_resp, 979 enum ena_admin_aq_feature_id feature_id, 980 dma_addr_t control_buf_dma_addr, 981 u32 control_buff_size, 982 u8 feature_ver) 983 { 984 struct ena_com_admin_queue *admin_queue; 985 struct ena_admin_get_feat_cmd get_cmd; 986 int ret; 987 988 if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) { 989 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n", feature_id); 990 return -EOPNOTSUPP; 991 } 992 993 memset(&get_cmd, 0x0, sizeof(get_cmd)); 994 admin_queue = &ena_dev->admin_queue; 995 996 get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE; 997 998 if (control_buff_size) 999 get_cmd.aq_common_descriptor.flags = 1000 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 1001 else 1002 get_cmd.aq_common_descriptor.flags = 0; 1003 1004 ret = ena_com_mem_addr_set(ena_dev, 1005 &get_cmd.control_buffer.address, 1006 control_buf_dma_addr); 1007 if (unlikely(ret)) { 1008 netdev_err(ena_dev->net_device, "Memory address set failed\n"); 1009 return ret; 1010 } 1011 1012 get_cmd.control_buffer.length = control_buff_size; 1013 get_cmd.feat_common.feature_version = feature_ver; 1014 get_cmd.feat_common.feature_id = feature_id; 1015 1016 ret = ena_com_execute_admin_command(admin_queue, 1017 (struct ena_admin_aq_entry *) 1018 &get_cmd, 1019 sizeof(get_cmd), 1020 (struct ena_admin_acq_entry *) 1021 get_resp, 1022 sizeof(*get_resp)); 1023 1024 if (unlikely(ret)) 1025 netdev_err(ena_dev->net_device, 1026 "Failed to submit get_feature command %d error: %d\n", feature_id, ret); 1027 1028 return ret; 1029 } 1030 1031 static int ena_com_get_feature(struct ena_com_dev *ena_dev, 1032 struct ena_admin_get_feat_resp *get_resp, 1033 enum ena_admin_aq_feature_id feature_id, 1034 u8 feature_ver) 1035 { 1036 return ena_com_get_feature_ex(ena_dev, 1037 get_resp, 1038 feature_id, 1039 0, 1040 0, 1041 feature_ver); 1042 } 1043 1044 int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev) 1045 { 1046 return ena_dev->rss.hash_func; 1047 } 1048 1049 static void ena_com_hash_key_fill_default_key(struct ena_com_dev *ena_dev) 1050 { 1051 struct ena_admin_feature_rss_flow_hash_control *hash_key = 1052 (ena_dev->rss).hash_key; 1053 1054 netdev_rss_key_fill(&hash_key->key, sizeof(hash_key->key)); 1055 /* The key buffer is stored in the device in an array of 1056 * uint32 elements. 1057 */ 1058 hash_key->key_parts = ENA_ADMIN_RSS_KEY_PARTS; 1059 } 1060 1061 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev) 1062 { 1063 struct ena_rss *rss = &ena_dev->rss; 1064 1065 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_HASH_FUNCTION)) 1066 return -EOPNOTSUPP; 1067 1068 rss->hash_key = dma_alloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_key), 1069 &rss->hash_key_dma_addr, GFP_KERNEL); 1070 1071 if (unlikely(!rss->hash_key)) 1072 return -ENOMEM; 1073 1074 return 0; 1075 } 1076 1077 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev) 1078 { 1079 struct ena_rss *rss = &ena_dev->rss; 1080 1081 if (rss->hash_key) 1082 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_key), rss->hash_key, 1083 rss->hash_key_dma_addr); 1084 rss->hash_key = NULL; 1085 } 1086 1087 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev) 1088 { 1089 struct ena_rss *rss = &ena_dev->rss; 1090 1091 rss->hash_ctrl = dma_alloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl), 1092 &rss->hash_ctrl_dma_addr, GFP_KERNEL); 1093 1094 if (unlikely(!rss->hash_ctrl)) 1095 return -ENOMEM; 1096 1097 return 0; 1098 } 1099 1100 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev) 1101 { 1102 struct ena_rss *rss = &ena_dev->rss; 1103 1104 if (rss->hash_ctrl) 1105 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl), rss->hash_ctrl, 1106 rss->hash_ctrl_dma_addr); 1107 rss->hash_ctrl = NULL; 1108 } 1109 1110 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev, 1111 u16 log_size) 1112 { 1113 struct ena_rss *rss = &ena_dev->rss; 1114 struct ena_admin_get_feat_resp get_resp; 1115 size_t tbl_size; 1116 int ret; 1117 1118 ret = ena_com_get_feature(ena_dev, &get_resp, 1119 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG, 0); 1120 if (unlikely(ret)) 1121 return ret; 1122 1123 if ((get_resp.u.ind_table.min_size > log_size) || 1124 (get_resp.u.ind_table.max_size < log_size)) { 1125 netdev_err(ena_dev->net_device, 1126 "Indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n", 1127 1 << log_size, 1 << get_resp.u.ind_table.min_size, 1128 1 << get_resp.u.ind_table.max_size); 1129 return -EINVAL; 1130 } 1131 1132 tbl_size = (1ULL << log_size) * 1133 sizeof(struct ena_admin_rss_ind_table_entry); 1134 1135 rss->rss_ind_tbl = dma_alloc_coherent(ena_dev->dmadev, tbl_size, &rss->rss_ind_tbl_dma_addr, 1136 GFP_KERNEL); 1137 if (unlikely(!rss->rss_ind_tbl)) 1138 goto mem_err1; 1139 1140 tbl_size = (1ULL << log_size) * sizeof(u16); 1141 rss->host_rss_ind_tbl = devm_kzalloc(ena_dev->dmadev, tbl_size, GFP_KERNEL); 1142 if (unlikely(!rss->host_rss_ind_tbl)) 1143 goto mem_err2; 1144 1145 rss->tbl_log_size = log_size; 1146 1147 return 0; 1148 1149 mem_err2: 1150 tbl_size = (1ULL << log_size) * 1151 sizeof(struct ena_admin_rss_ind_table_entry); 1152 1153 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl, rss->rss_ind_tbl_dma_addr); 1154 rss->rss_ind_tbl = NULL; 1155 mem_err1: 1156 rss->tbl_log_size = 0; 1157 return -ENOMEM; 1158 } 1159 1160 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev) 1161 { 1162 struct ena_rss *rss = &ena_dev->rss; 1163 size_t tbl_size = (1ULL << rss->tbl_log_size) * 1164 sizeof(struct ena_admin_rss_ind_table_entry); 1165 1166 if (rss->rss_ind_tbl) 1167 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl, 1168 rss->rss_ind_tbl_dma_addr); 1169 rss->rss_ind_tbl = NULL; 1170 1171 if (rss->host_rss_ind_tbl) 1172 devm_kfree(ena_dev->dmadev, rss->host_rss_ind_tbl); 1173 rss->host_rss_ind_tbl = NULL; 1174 } 1175 1176 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev, 1177 struct ena_com_io_sq *io_sq, u16 cq_idx) 1178 { 1179 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1180 struct ena_admin_aq_create_sq_cmd create_cmd; 1181 struct ena_admin_acq_create_sq_resp_desc cmd_completion; 1182 u8 direction; 1183 int ret; 1184 1185 memset(&create_cmd, 0x0, sizeof(create_cmd)); 1186 1187 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ; 1188 1189 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 1190 direction = ENA_ADMIN_SQ_DIRECTION_TX; 1191 else 1192 direction = ENA_ADMIN_SQ_DIRECTION_RX; 1193 1194 create_cmd.sq_identity |= (direction << 1195 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & 1196 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK; 1197 1198 create_cmd.sq_caps_2 |= io_sq->mem_queue_type & 1199 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK; 1200 1201 create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC << 1202 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & 1203 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK; 1204 1205 create_cmd.sq_caps_3 |= 1206 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK; 1207 1208 create_cmd.cq_idx = cq_idx; 1209 create_cmd.sq_depth = io_sq->q_depth; 1210 1211 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) { 1212 ret = ena_com_mem_addr_set(ena_dev, 1213 &create_cmd.sq_ba, 1214 io_sq->desc_addr.phys_addr); 1215 if (unlikely(ret)) { 1216 netdev_err(ena_dev->net_device, "Memory address set failed\n"); 1217 return ret; 1218 } 1219 } 1220 1221 ret = ena_com_execute_admin_command(admin_queue, 1222 (struct ena_admin_aq_entry *)&create_cmd, 1223 sizeof(create_cmd), 1224 (struct ena_admin_acq_entry *)&cmd_completion, 1225 sizeof(cmd_completion)); 1226 if (unlikely(ret)) { 1227 netdev_err(ena_dev->net_device, "Failed to create IO SQ. error: %d\n", ret); 1228 return ret; 1229 } 1230 1231 io_sq->idx = cmd_completion.sq_idx; 1232 1233 io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1234 (uintptr_t)cmd_completion.sq_doorbell_offset); 1235 1236 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 1237 io_sq->desc_addr.pbuf_dev_addr = 1238 (u8 __iomem *)((uintptr_t)ena_dev->mem_bar + 1239 cmd_completion.llq_descriptors_offset); 1240 } 1241 1242 netdev_dbg(ena_dev->net_device, "Created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth); 1243 1244 return ret; 1245 } 1246 1247 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev) 1248 { 1249 struct ena_rss *rss = &ena_dev->rss; 1250 struct ena_com_io_sq *io_sq; 1251 u16 qid; 1252 int i; 1253 1254 for (i = 0; i < 1 << rss->tbl_log_size; i++) { 1255 qid = rss->host_rss_ind_tbl[i]; 1256 if (qid >= ENA_TOTAL_NUM_QUEUES) 1257 return -EINVAL; 1258 1259 io_sq = &ena_dev->io_sq_queues[qid]; 1260 1261 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX) 1262 return -EINVAL; 1263 1264 rss->rss_ind_tbl[i].cq_idx = io_sq->idx; 1265 } 1266 1267 return 0; 1268 } 1269 1270 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev, 1271 u16 intr_delay_resolution) 1272 { 1273 u16 prev_intr_delay_resolution = ena_dev->intr_delay_resolution; 1274 1275 if (unlikely(!intr_delay_resolution)) { 1276 netdev_err(ena_dev->net_device, 1277 "Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n"); 1278 intr_delay_resolution = ENA_DEFAULT_INTR_DELAY_RESOLUTION; 1279 } 1280 1281 /* update Rx */ 1282 ena_dev->intr_moder_rx_interval = 1283 ena_dev->intr_moder_rx_interval * 1284 prev_intr_delay_resolution / 1285 intr_delay_resolution; 1286 1287 /* update Tx */ 1288 ena_dev->intr_moder_tx_interval = 1289 ena_dev->intr_moder_tx_interval * 1290 prev_intr_delay_resolution / 1291 intr_delay_resolution; 1292 1293 ena_dev->intr_delay_resolution = intr_delay_resolution; 1294 } 1295 1296 /*****************************************************************************/ 1297 /******************************* API ******************************/ 1298 /*****************************************************************************/ 1299 1300 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, 1301 struct ena_admin_aq_entry *cmd, 1302 size_t cmd_size, 1303 struct ena_admin_acq_entry *comp, 1304 size_t comp_size) 1305 { 1306 struct ena_comp_ctx *comp_ctx; 1307 int ret; 1308 1309 comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size, 1310 comp, comp_size); 1311 if (IS_ERR(comp_ctx)) { 1312 ret = PTR_ERR(comp_ctx); 1313 if (ret == -ENODEV) 1314 netdev_dbg(admin_queue->ena_dev->net_device, 1315 "Failed to submit command [%d]\n", ret); 1316 else 1317 netdev_err(admin_queue->ena_dev->net_device, 1318 "Failed to submit command [%d]\n", ret); 1319 1320 return ret; 1321 } 1322 1323 ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue); 1324 if (unlikely(ret)) { 1325 if (admin_queue->running_state) 1326 netdev_err(admin_queue->ena_dev->net_device, 1327 "Failed to process command. ret = %d\n", ret); 1328 else 1329 netdev_dbg(admin_queue->ena_dev->net_device, 1330 "Failed to process command. ret = %d\n", ret); 1331 } 1332 return ret; 1333 } 1334 1335 int ena_com_create_io_cq(struct ena_com_dev *ena_dev, 1336 struct ena_com_io_cq *io_cq) 1337 { 1338 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1339 struct ena_admin_aq_create_cq_cmd create_cmd; 1340 struct ena_admin_acq_create_cq_resp_desc cmd_completion; 1341 int ret; 1342 1343 memset(&create_cmd, 0x0, sizeof(create_cmd)); 1344 1345 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ; 1346 1347 create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) & 1348 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK; 1349 create_cmd.cq_caps_1 |= 1350 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK; 1351 1352 create_cmd.msix_vector = io_cq->msix_vector; 1353 create_cmd.cq_depth = io_cq->q_depth; 1354 1355 ret = ena_com_mem_addr_set(ena_dev, 1356 &create_cmd.cq_ba, 1357 io_cq->cdesc_addr.phys_addr); 1358 if (unlikely(ret)) { 1359 netdev_err(ena_dev->net_device, "Memory address set failed\n"); 1360 return ret; 1361 } 1362 1363 ret = ena_com_execute_admin_command(admin_queue, 1364 (struct ena_admin_aq_entry *)&create_cmd, 1365 sizeof(create_cmd), 1366 (struct ena_admin_acq_entry *)&cmd_completion, 1367 sizeof(cmd_completion)); 1368 if (unlikely(ret)) { 1369 netdev_err(ena_dev->net_device, "Failed to create IO CQ. error: %d\n", ret); 1370 return ret; 1371 } 1372 1373 io_cq->idx = cmd_completion.cq_idx; 1374 1375 io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1376 cmd_completion.cq_interrupt_unmask_register_offset); 1377 1378 if (cmd_completion.numa_node_register_offset) 1379 io_cq->numa_node_cfg_reg = 1380 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1381 cmd_completion.numa_node_register_offset); 1382 1383 netdev_dbg(ena_dev->net_device, "Created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth); 1384 1385 return ret; 1386 } 1387 1388 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid, 1389 struct ena_com_io_sq **io_sq, 1390 struct ena_com_io_cq **io_cq) 1391 { 1392 if (qid >= ENA_TOTAL_NUM_QUEUES) { 1393 netdev_err(ena_dev->net_device, "Invalid queue number %d but the max is %d\n", qid, 1394 ENA_TOTAL_NUM_QUEUES); 1395 return -EINVAL; 1396 } 1397 1398 *io_sq = &ena_dev->io_sq_queues[qid]; 1399 *io_cq = &ena_dev->io_cq_queues[qid]; 1400 1401 return 0; 1402 } 1403 1404 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev) 1405 { 1406 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1407 struct ena_comp_ctx *comp_ctx; 1408 u16 i; 1409 1410 if (!admin_queue->comp_ctx) 1411 return; 1412 1413 for (i = 0; i < admin_queue->q_depth; i++) { 1414 comp_ctx = get_comp_ctxt(admin_queue, i, false); 1415 if (unlikely(!comp_ctx)) 1416 break; 1417 1418 comp_ctx->status = ENA_CMD_ABORTED; 1419 1420 complete(&comp_ctx->wait_event); 1421 } 1422 } 1423 1424 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev) 1425 { 1426 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1427 unsigned long flags = 0; 1428 u32 exp = 0; 1429 1430 spin_lock_irqsave(&admin_queue->q_lock, flags); 1431 while (atomic_read(&admin_queue->outstanding_cmds) != 0) { 1432 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 1433 ena_delay_exponential_backoff_us(exp++, ena_dev->ena_min_poll_delay_us); 1434 spin_lock_irqsave(&admin_queue->q_lock, flags); 1435 } 1436 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 1437 } 1438 1439 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev, 1440 struct ena_com_io_cq *io_cq) 1441 { 1442 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1443 struct ena_admin_aq_destroy_cq_cmd destroy_cmd; 1444 struct ena_admin_acq_destroy_cq_resp_desc destroy_resp; 1445 int ret; 1446 1447 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd)); 1448 1449 destroy_cmd.cq_idx = io_cq->idx; 1450 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ; 1451 1452 ret = ena_com_execute_admin_command(admin_queue, 1453 (struct ena_admin_aq_entry *)&destroy_cmd, 1454 sizeof(destroy_cmd), 1455 (struct ena_admin_acq_entry *)&destroy_resp, 1456 sizeof(destroy_resp)); 1457 1458 if (unlikely(ret && (ret != -ENODEV))) 1459 netdev_err(ena_dev->net_device, "Failed to destroy IO CQ. error: %d\n", ret); 1460 1461 return ret; 1462 } 1463 1464 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev) 1465 { 1466 return ena_dev->admin_queue.running_state; 1467 } 1468 1469 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state) 1470 { 1471 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1472 unsigned long flags = 0; 1473 1474 spin_lock_irqsave(&admin_queue->q_lock, flags); 1475 ena_dev->admin_queue.running_state = state; 1476 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 1477 } 1478 1479 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev) 1480 { 1481 u16 depth = ena_dev->aenq.q_depth; 1482 1483 WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n"); 1484 1485 /* Init head_db to mark that all entries in the queue 1486 * are initially available 1487 */ 1488 writel(depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); 1489 } 1490 1491 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag) 1492 { 1493 struct ena_com_admin_queue *admin_queue; 1494 struct ena_admin_set_feat_cmd cmd; 1495 struct ena_admin_set_feat_resp resp; 1496 struct ena_admin_get_feat_resp get_resp; 1497 int ret; 1498 1499 ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG, 0); 1500 if (ret) { 1501 dev_info(ena_dev->dmadev, "Can't get aenq configuration\n"); 1502 return ret; 1503 } 1504 1505 if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) { 1506 netdev_warn(ena_dev->net_device, 1507 "Trying to set unsupported aenq events. supported flag: 0x%x asked flag: 0x%x\n", 1508 get_resp.u.aenq.supported_groups, groups_flag); 1509 return -EOPNOTSUPP; 1510 } 1511 1512 memset(&cmd, 0x0, sizeof(cmd)); 1513 admin_queue = &ena_dev->admin_queue; 1514 1515 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 1516 cmd.aq_common_descriptor.flags = 0; 1517 cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG; 1518 cmd.u.aenq.enabled_groups = groups_flag; 1519 1520 ret = ena_com_execute_admin_command(admin_queue, 1521 (struct ena_admin_aq_entry *)&cmd, 1522 sizeof(cmd), 1523 (struct ena_admin_acq_entry *)&resp, 1524 sizeof(resp)); 1525 1526 if (unlikely(ret)) 1527 netdev_err(ena_dev->net_device, "Failed to config AENQ ret: %d\n", ret); 1528 1529 return ret; 1530 } 1531 1532 int ena_com_get_dma_width(struct ena_com_dev *ena_dev) 1533 { 1534 u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); 1535 u32 width; 1536 1537 if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) { 1538 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n"); 1539 return -ETIME; 1540 } 1541 1542 width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >> 1543 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT; 1544 1545 netdev_dbg(ena_dev->net_device, "ENA dma width: %d\n", width); 1546 1547 if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) { 1548 netdev_err(ena_dev->net_device, "DMA width illegal value: %d\n", width); 1549 return -EINVAL; 1550 } 1551 1552 ena_dev->dma_addr_bits = width; 1553 1554 return width; 1555 } 1556 1557 int ena_com_validate_version(struct ena_com_dev *ena_dev) 1558 { 1559 u32 ver; 1560 u32 ctrl_ver; 1561 u32 ctrl_ver_masked; 1562 1563 /* Make sure the ENA version and the controller version are at least 1564 * as the driver expects 1565 */ 1566 ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF); 1567 ctrl_ver = ena_com_reg_bar_read32(ena_dev, 1568 ENA_REGS_CONTROLLER_VERSION_OFF); 1569 1570 if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) || (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) { 1571 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n"); 1572 return -ETIME; 1573 } 1574 1575 dev_info(ena_dev->dmadev, "ENA device version: %d.%d\n", 1576 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >> ENA_REGS_VERSION_MAJOR_VERSION_SHIFT, 1577 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK); 1578 1579 dev_info(ena_dev->dmadev, "ENA controller version: %d.%d.%d implementation version %d\n", 1580 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) >> 1581 ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT, 1582 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) >> 1583 ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT, 1584 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK), 1585 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >> 1586 ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT); 1587 1588 ctrl_ver_masked = 1589 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) | 1590 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) | 1591 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK); 1592 1593 /* Validate the ctrl version without the implementation ID */ 1594 if (ctrl_ver_masked < MIN_ENA_CTRL_VER) { 1595 netdev_err(ena_dev->net_device, 1596 "ENA ctrl version is lower than the minimal ctrl version the driver supports\n"); 1597 return -1; 1598 } 1599 1600 return 0; 1601 } 1602 1603 static void 1604 ena_com_free_ena_admin_queue_comp_ctx(struct ena_com_dev *ena_dev, 1605 struct ena_com_admin_queue *admin_queue) 1606 1607 { 1608 if (!admin_queue->comp_ctx) 1609 return; 1610 1611 devm_kfree(ena_dev->dmadev, admin_queue->comp_ctx); 1612 1613 admin_queue->comp_ctx = NULL; 1614 } 1615 1616 void ena_com_admin_destroy(struct ena_com_dev *ena_dev) 1617 { 1618 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1619 struct ena_com_admin_cq *cq = &admin_queue->cq; 1620 struct ena_com_admin_sq *sq = &admin_queue->sq; 1621 struct ena_com_aenq *aenq = &ena_dev->aenq; 1622 u16 size; 1623 1624 ena_com_free_ena_admin_queue_comp_ctx(ena_dev, admin_queue); 1625 1626 size = ADMIN_SQ_SIZE(admin_queue->q_depth); 1627 if (sq->entries) 1628 dma_free_coherent(ena_dev->dmadev, size, sq->entries, sq->dma_addr); 1629 sq->entries = NULL; 1630 1631 size = ADMIN_CQ_SIZE(admin_queue->q_depth); 1632 if (cq->entries) 1633 dma_free_coherent(ena_dev->dmadev, size, cq->entries, cq->dma_addr); 1634 cq->entries = NULL; 1635 1636 size = ADMIN_AENQ_SIZE(aenq->q_depth); 1637 if (ena_dev->aenq.entries) 1638 dma_free_coherent(ena_dev->dmadev, size, aenq->entries, aenq->dma_addr); 1639 aenq->entries = NULL; 1640 } 1641 1642 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling) 1643 { 1644 u32 mask_value = 0; 1645 1646 if (polling) 1647 mask_value = ENA_REGS_ADMIN_INTR_MASK; 1648 1649 writel(mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF); 1650 ena_dev->admin_queue.polling = polling; 1651 } 1652 1653 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev, 1654 bool polling) 1655 { 1656 ena_dev->admin_queue.auto_polling = polling; 1657 } 1658 1659 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev) 1660 { 1661 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1662 1663 spin_lock_init(&mmio_read->lock); 1664 mmio_read->read_resp = dma_alloc_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp), 1665 &mmio_read->read_resp_dma_addr, GFP_KERNEL); 1666 if (unlikely(!mmio_read->read_resp)) 1667 goto err; 1668 1669 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev); 1670 1671 mmio_read->read_resp->req_id = 0x0; 1672 mmio_read->seq_num = 0x0; 1673 mmio_read->readless_supported = true; 1674 1675 return 0; 1676 1677 err: 1678 1679 return -ENOMEM; 1680 } 1681 1682 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported) 1683 { 1684 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1685 1686 mmio_read->readless_supported = readless_supported; 1687 } 1688 1689 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev) 1690 { 1691 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1692 1693 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF); 1694 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF); 1695 1696 dma_free_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp), mmio_read->read_resp, 1697 mmio_read->read_resp_dma_addr); 1698 1699 mmio_read->read_resp = NULL; 1700 } 1701 1702 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev) 1703 { 1704 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1705 u32 addr_low, addr_high; 1706 1707 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr); 1708 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr); 1709 1710 writel(addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF); 1711 writel(addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF); 1712 } 1713 1714 int ena_com_admin_init(struct ena_com_dev *ena_dev, 1715 struct ena_aenq_handlers *aenq_handlers) 1716 { 1717 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1718 u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high; 1719 int ret; 1720 1721 dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 1722 1723 if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) { 1724 netdev_err(ena_dev->net_device, "Reg read timeout occurred\n"); 1725 return -ETIME; 1726 } 1727 1728 if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) { 1729 netdev_err(ena_dev->net_device, "Device isn't ready, abort com init\n"); 1730 return -ENODEV; 1731 } 1732 1733 admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH; 1734 1735 admin_queue->q_dmadev = ena_dev->dmadev; 1736 admin_queue->polling = false; 1737 admin_queue->curr_cmd_id = 0; 1738 1739 atomic_set(&admin_queue->outstanding_cmds, 0); 1740 1741 spin_lock_init(&admin_queue->q_lock); 1742 1743 ret = ena_com_init_comp_ctxt(admin_queue); 1744 if (ret) 1745 goto error; 1746 1747 ret = ena_com_admin_init_sq(admin_queue); 1748 if (ret) 1749 goto error; 1750 1751 ret = ena_com_admin_init_cq(admin_queue); 1752 if (ret) 1753 goto error; 1754 1755 admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1756 ENA_REGS_AQ_DB_OFF); 1757 1758 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr); 1759 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr); 1760 1761 writel(addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF); 1762 writel(addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF); 1763 1764 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr); 1765 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr); 1766 1767 writel(addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF); 1768 writel(addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF); 1769 1770 aq_caps = 0; 1771 aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK; 1772 aq_caps |= (sizeof(struct ena_admin_aq_entry) << 1773 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) & 1774 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK; 1775 1776 acq_caps = 0; 1777 acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK; 1778 acq_caps |= (sizeof(struct ena_admin_acq_entry) << 1779 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) & 1780 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK; 1781 1782 writel(aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF); 1783 writel(acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF); 1784 ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers); 1785 if (ret) 1786 goto error; 1787 1788 admin_queue->ena_dev = ena_dev; 1789 admin_queue->running_state = true; 1790 1791 return 0; 1792 error: 1793 ena_com_admin_destroy(ena_dev); 1794 1795 return ret; 1796 } 1797 1798 int ena_com_create_io_queue(struct ena_com_dev *ena_dev, 1799 struct ena_com_create_io_ctx *ctx) 1800 { 1801 struct ena_com_io_sq *io_sq; 1802 struct ena_com_io_cq *io_cq; 1803 int ret; 1804 1805 if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) { 1806 netdev_err(ena_dev->net_device, "Qid (%d) is bigger than max num of queues (%d)\n", 1807 ctx->qid, ENA_TOTAL_NUM_QUEUES); 1808 return -EINVAL; 1809 } 1810 1811 io_sq = &ena_dev->io_sq_queues[ctx->qid]; 1812 io_cq = &ena_dev->io_cq_queues[ctx->qid]; 1813 1814 memset(io_sq, 0x0, sizeof(*io_sq)); 1815 memset(io_cq, 0x0, sizeof(*io_cq)); 1816 1817 /* Init CQ */ 1818 io_cq->q_depth = ctx->queue_size; 1819 io_cq->direction = ctx->direction; 1820 io_cq->qid = ctx->qid; 1821 1822 io_cq->msix_vector = ctx->msix_vector; 1823 1824 io_sq->q_depth = ctx->queue_size; 1825 io_sq->direction = ctx->direction; 1826 io_sq->qid = ctx->qid; 1827 1828 io_sq->mem_queue_type = ctx->mem_queue_type; 1829 1830 if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 1831 /* header length is limited to 8 bits */ 1832 io_sq->tx_max_header_size = min_t(u32, ena_dev->tx_max_header_size, SZ_256); 1833 1834 ret = ena_com_init_io_sq(ena_dev, ctx, io_sq); 1835 if (ret) 1836 goto error; 1837 ret = ena_com_init_io_cq(ena_dev, ctx, io_cq); 1838 if (ret) 1839 goto error; 1840 1841 ret = ena_com_create_io_cq(ena_dev, io_cq); 1842 if (ret) 1843 goto error; 1844 1845 ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx); 1846 if (ret) 1847 goto destroy_io_cq; 1848 1849 return 0; 1850 1851 destroy_io_cq: 1852 ena_com_destroy_io_cq(ena_dev, io_cq); 1853 error: 1854 ena_com_io_queue_free(ena_dev, io_sq, io_cq); 1855 return ret; 1856 } 1857 1858 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid) 1859 { 1860 struct ena_com_io_sq *io_sq; 1861 struct ena_com_io_cq *io_cq; 1862 1863 if (qid >= ENA_TOTAL_NUM_QUEUES) { 1864 netdev_err(ena_dev->net_device, "Qid (%d) is bigger than max num of queues (%d)\n", 1865 qid, ENA_TOTAL_NUM_QUEUES); 1866 return; 1867 } 1868 1869 io_sq = &ena_dev->io_sq_queues[qid]; 1870 io_cq = &ena_dev->io_cq_queues[qid]; 1871 1872 ena_com_destroy_io_sq(ena_dev, io_sq); 1873 ena_com_destroy_io_cq(ena_dev, io_cq); 1874 1875 ena_com_io_queue_free(ena_dev, io_sq, io_cq); 1876 } 1877 1878 int ena_com_get_link_params(struct ena_com_dev *ena_dev, 1879 struct ena_admin_get_feat_resp *resp) 1880 { 1881 return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG, 0); 1882 } 1883 1884 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, 1885 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1886 { 1887 struct ena_admin_get_feat_resp get_resp; 1888 int rc; 1889 1890 rc = ena_com_get_feature(ena_dev, &get_resp, 1891 ENA_ADMIN_DEVICE_ATTRIBUTES, 0); 1892 if (rc) 1893 return rc; 1894 1895 memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr, 1896 sizeof(get_resp.u.dev_attr)); 1897 1898 ena_dev->supported_features = get_resp.u.dev_attr.supported_features; 1899 ena_dev->capabilities = get_resp.u.dev_attr.capabilities; 1900 1901 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 1902 rc = ena_com_get_feature(ena_dev, &get_resp, 1903 ENA_ADMIN_MAX_QUEUES_EXT, 1904 ENA_FEATURE_MAX_QUEUE_EXT_VER); 1905 if (rc) 1906 return rc; 1907 1908 if (get_resp.u.max_queue_ext.version != ENA_FEATURE_MAX_QUEUE_EXT_VER) 1909 return -EINVAL; 1910 1911 memcpy(&get_feat_ctx->max_queue_ext, &get_resp.u.max_queue_ext, 1912 sizeof(get_resp.u.max_queue_ext)); 1913 ena_dev->tx_max_header_size = 1914 get_resp.u.max_queue_ext.max_queue_ext.max_tx_header_size; 1915 } else { 1916 rc = ena_com_get_feature(ena_dev, &get_resp, 1917 ENA_ADMIN_MAX_QUEUES_NUM, 0); 1918 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue, 1919 sizeof(get_resp.u.max_queue)); 1920 ena_dev->tx_max_header_size = 1921 get_resp.u.max_queue.max_header_size; 1922 1923 if (rc) 1924 return rc; 1925 } 1926 1927 rc = ena_com_get_feature(ena_dev, &get_resp, 1928 ENA_ADMIN_AENQ_CONFIG, 0); 1929 if (rc) 1930 return rc; 1931 1932 memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq, 1933 sizeof(get_resp.u.aenq)); 1934 1935 rc = ena_com_get_feature(ena_dev, &get_resp, 1936 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0); 1937 if (rc) 1938 return rc; 1939 1940 memcpy(&get_feat_ctx->offload, &get_resp.u.offload, 1941 sizeof(get_resp.u.offload)); 1942 1943 /* Driver hints isn't mandatory admin command. So in case the 1944 * command isn't supported set driver hints to 0 1945 */ 1946 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS, 0); 1947 1948 if (!rc) 1949 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints, sizeof(get_resp.u.hw_hints)); 1950 else if (rc == -EOPNOTSUPP) 1951 memset(&get_feat_ctx->hw_hints, 0x0, sizeof(get_feat_ctx->hw_hints)); 1952 else 1953 return rc; 1954 1955 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_LLQ, 0); 1956 if (!rc) 1957 memcpy(&get_feat_ctx->llq, &get_resp.u.llq, sizeof(get_resp.u.llq)); 1958 else if (rc == -EOPNOTSUPP) 1959 memset(&get_feat_ctx->llq, 0x0, sizeof(get_feat_ctx->llq)); 1960 else 1961 return rc; 1962 1963 return 0; 1964 } 1965 1966 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev) 1967 { 1968 ena_com_handle_admin_completion(&ena_dev->admin_queue); 1969 } 1970 1971 /* ena_handle_specific_aenq_event: 1972 * return the handler that is relevant to the specific event group 1973 */ 1974 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *ena_dev, 1975 u16 group) 1976 { 1977 struct ena_aenq_handlers *aenq_handlers = ena_dev->aenq.aenq_handlers; 1978 1979 if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group]) 1980 return aenq_handlers->handlers[group]; 1981 1982 return aenq_handlers->unimplemented_handler; 1983 } 1984 1985 /* ena_aenq_intr_handler: 1986 * handles the aenq incoming events. 1987 * pop events from the queue and apply the specific handler 1988 */ 1989 void ena_com_aenq_intr_handler(struct ena_com_dev *ena_dev, void *data) 1990 { 1991 struct ena_admin_aenq_entry *aenq_e; 1992 struct ena_admin_aenq_common_desc *aenq_common; 1993 struct ena_com_aenq *aenq = &ena_dev->aenq; 1994 u64 timestamp; 1995 ena_aenq_handler handler_cb; 1996 u16 masked_head, processed = 0; 1997 u8 phase; 1998 1999 masked_head = aenq->head & (aenq->q_depth - 1); 2000 phase = aenq->phase; 2001 aenq_e = &aenq->entries[masked_head]; /* Get first entry */ 2002 aenq_common = &aenq_e->aenq_common_desc; 2003 2004 /* Go over all the events */ 2005 while ((READ_ONCE(aenq_common->flags) & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) { 2006 /* Make sure the phase bit (ownership) is as expected before 2007 * reading the rest of the descriptor. 2008 */ 2009 dma_rmb(); 2010 2011 timestamp = (u64)aenq_common->timestamp_low | 2012 ((u64)aenq_common->timestamp_high << 32); 2013 2014 netdev_dbg(ena_dev->net_device, "AENQ! Group[%x] Syndrome[%x] timestamp: [%llus]\n", 2015 aenq_common->group, aenq_common->syndrome, timestamp); 2016 2017 /* Handle specific event*/ 2018 handler_cb = ena_com_get_specific_aenq_cb(ena_dev, 2019 aenq_common->group); 2020 handler_cb(data, aenq_e); /* call the actual event handler*/ 2021 2022 /* Get next event entry */ 2023 masked_head++; 2024 processed++; 2025 2026 if (unlikely(masked_head == aenq->q_depth)) { 2027 masked_head = 0; 2028 phase = !phase; 2029 } 2030 aenq_e = &aenq->entries[masked_head]; 2031 aenq_common = &aenq_e->aenq_common_desc; 2032 } 2033 2034 aenq->head += processed; 2035 aenq->phase = phase; 2036 2037 /* Don't update aenq doorbell if there weren't any processed events */ 2038 if (!processed) 2039 return; 2040 2041 /* write the aenq doorbell after all AENQ descriptors were read */ 2042 mb(); 2043 writel_relaxed((u32)aenq->head, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); 2044 } 2045 2046 int ena_com_dev_reset(struct ena_com_dev *ena_dev, 2047 enum ena_regs_reset_reason_types reset_reason) 2048 { 2049 u32 stat, timeout, cap, reset_val; 2050 int rc; 2051 2052 stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 2053 cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); 2054 2055 if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) || (cap == ENA_MMIO_READ_TIMEOUT))) { 2056 netdev_err(ena_dev->net_device, "Reg read32 timeout occurred\n"); 2057 return -ETIME; 2058 } 2059 2060 if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) { 2061 netdev_err(ena_dev->net_device, "Device isn't ready, can't reset device\n"); 2062 return -EINVAL; 2063 } 2064 2065 timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >> 2066 ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT; 2067 if (timeout == 0) { 2068 netdev_err(ena_dev->net_device, "Invalid timeout value\n"); 2069 return -EINVAL; 2070 } 2071 2072 /* start reset */ 2073 reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK; 2074 reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) & 2075 ENA_REGS_DEV_CTL_RESET_REASON_MASK; 2076 writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); 2077 2078 /* Write again the MMIO read request address */ 2079 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev); 2080 2081 rc = wait_for_reset_state(ena_dev, timeout, 2082 ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK); 2083 if (rc != 0) { 2084 netdev_err(ena_dev->net_device, "Reset indication didn't turn on\n"); 2085 return rc; 2086 } 2087 2088 /* reset done */ 2089 writel(0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); 2090 rc = wait_for_reset_state(ena_dev, timeout, 0); 2091 if (rc != 0) { 2092 netdev_err(ena_dev->net_device, "Reset indication didn't turn off\n"); 2093 return rc; 2094 } 2095 2096 timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >> 2097 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT; 2098 if (timeout) 2099 /* the resolution of timeout reg is 100ms */ 2100 ena_dev->admin_queue.completion_timeout = timeout * 100000; 2101 else 2102 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US; 2103 2104 return 0; 2105 } 2106 2107 static int ena_get_dev_stats(struct ena_com_dev *ena_dev, 2108 struct ena_com_stats_ctx *ctx, 2109 enum ena_admin_get_stats_type type) 2110 { 2111 struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd; 2112 struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp; 2113 struct ena_com_admin_queue *admin_queue; 2114 int ret; 2115 2116 admin_queue = &ena_dev->admin_queue; 2117 2118 get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS; 2119 get_cmd->aq_common_descriptor.flags = 0; 2120 get_cmd->type = type; 2121 2122 ret = ena_com_execute_admin_command(admin_queue, 2123 (struct ena_admin_aq_entry *)get_cmd, 2124 sizeof(*get_cmd), 2125 (struct ena_admin_acq_entry *)get_resp, 2126 sizeof(*get_resp)); 2127 2128 if (unlikely(ret)) 2129 netdev_err(ena_dev->net_device, "Failed to get stats. error: %d\n", ret); 2130 2131 return ret; 2132 } 2133 2134 int ena_com_get_eni_stats(struct ena_com_dev *ena_dev, 2135 struct ena_admin_eni_stats *stats) 2136 { 2137 struct ena_com_stats_ctx ctx; 2138 int ret; 2139 2140 if (!ena_com_get_cap(ena_dev, ENA_ADMIN_ENI_STATS)) { 2141 netdev_err(ena_dev->net_device, "Capability %d isn't supported\n", 2142 ENA_ADMIN_ENI_STATS); 2143 return -EOPNOTSUPP; 2144 } 2145 2146 memset(&ctx, 0x0, sizeof(ctx)); 2147 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_ENI); 2148 if (likely(ret == 0)) 2149 memcpy(stats, &ctx.get_resp.u.eni_stats, 2150 sizeof(ctx.get_resp.u.eni_stats)); 2151 2152 return ret; 2153 } 2154 2155 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev, 2156 struct ena_admin_basic_stats *stats) 2157 { 2158 struct ena_com_stats_ctx ctx; 2159 int ret; 2160 2161 memset(&ctx, 0x0, sizeof(ctx)); 2162 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC); 2163 if (likely(ret == 0)) 2164 memcpy(stats, &ctx.get_resp.u.basic_stats, 2165 sizeof(ctx.get_resp.u.basic_stats)); 2166 2167 return ret; 2168 } 2169 2170 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, u32 mtu) 2171 { 2172 struct ena_com_admin_queue *admin_queue; 2173 struct ena_admin_set_feat_cmd cmd; 2174 struct ena_admin_set_feat_resp resp; 2175 int ret; 2176 2177 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) { 2178 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n", ENA_ADMIN_MTU); 2179 return -EOPNOTSUPP; 2180 } 2181 2182 memset(&cmd, 0x0, sizeof(cmd)); 2183 admin_queue = &ena_dev->admin_queue; 2184 2185 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2186 cmd.aq_common_descriptor.flags = 0; 2187 cmd.feat_common.feature_id = ENA_ADMIN_MTU; 2188 cmd.u.mtu.mtu = mtu; 2189 2190 ret = ena_com_execute_admin_command(admin_queue, 2191 (struct ena_admin_aq_entry *)&cmd, 2192 sizeof(cmd), 2193 (struct ena_admin_acq_entry *)&resp, 2194 sizeof(resp)); 2195 2196 if (unlikely(ret)) 2197 netdev_err(ena_dev->net_device, "Failed to set mtu %d. error: %d\n", mtu, ret); 2198 2199 return ret; 2200 } 2201 2202 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev, 2203 struct ena_admin_feature_offload_desc *offload) 2204 { 2205 int ret; 2206 struct ena_admin_get_feat_resp resp; 2207 2208 ret = ena_com_get_feature(ena_dev, &resp, 2209 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG, 0); 2210 if (unlikely(ret)) { 2211 netdev_err(ena_dev->net_device, "Failed to get offload capabilities %d\n", ret); 2212 return ret; 2213 } 2214 2215 memcpy(offload, &resp.u.offload, sizeof(resp.u.offload)); 2216 2217 return 0; 2218 } 2219 2220 int ena_com_set_hash_function(struct ena_com_dev *ena_dev) 2221 { 2222 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 2223 struct ena_rss *rss = &ena_dev->rss; 2224 struct ena_admin_set_feat_cmd cmd; 2225 struct ena_admin_set_feat_resp resp; 2226 struct ena_admin_get_feat_resp get_resp; 2227 int ret; 2228 2229 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_HASH_FUNCTION)) { 2230 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n", 2231 ENA_ADMIN_RSS_HASH_FUNCTION); 2232 return -EOPNOTSUPP; 2233 } 2234 2235 /* Validate hash function is supported */ 2236 ret = ena_com_get_feature(ena_dev, &get_resp, 2237 ENA_ADMIN_RSS_HASH_FUNCTION, 0); 2238 if (unlikely(ret)) 2239 return ret; 2240 2241 if (!(get_resp.u.flow_hash_func.supported_func & BIT(rss->hash_func))) { 2242 netdev_err(ena_dev->net_device, "Func hash %d isn't supported by device, abort\n", 2243 rss->hash_func); 2244 return -EOPNOTSUPP; 2245 } 2246 2247 memset(&cmd, 0x0, sizeof(cmd)); 2248 2249 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2250 cmd.aq_common_descriptor.flags = 2251 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2252 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION; 2253 cmd.u.flow_hash_func.init_val = rss->hash_init_val; 2254 cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func; 2255 2256 ret = ena_com_mem_addr_set(ena_dev, 2257 &cmd.control_buffer.address, 2258 rss->hash_key_dma_addr); 2259 if (unlikely(ret)) { 2260 netdev_err(ena_dev->net_device, "Memory address set failed\n"); 2261 return ret; 2262 } 2263 2264 cmd.control_buffer.length = sizeof(*rss->hash_key); 2265 2266 ret = ena_com_execute_admin_command(admin_queue, 2267 (struct ena_admin_aq_entry *)&cmd, 2268 sizeof(cmd), 2269 (struct ena_admin_acq_entry *)&resp, 2270 sizeof(resp)); 2271 if (unlikely(ret)) { 2272 netdev_err(ena_dev->net_device, "Failed to set hash function %d. error: %d\n", 2273 rss->hash_func, ret); 2274 return -EINVAL; 2275 } 2276 2277 return 0; 2278 } 2279 2280 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, 2281 enum ena_admin_hash_functions func, 2282 const u8 *key, u16 key_len, u32 init_val) 2283 { 2284 struct ena_admin_feature_rss_flow_hash_control *hash_key; 2285 struct ena_admin_get_feat_resp get_resp; 2286 enum ena_admin_hash_functions old_func; 2287 struct ena_rss *rss = &ena_dev->rss; 2288 int rc; 2289 2290 hash_key = rss->hash_key; 2291 2292 /* Make sure size is a mult of DWs */ 2293 if (unlikely(key_len & 0x3)) 2294 return -EINVAL; 2295 2296 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2297 ENA_ADMIN_RSS_HASH_FUNCTION, 2298 rss->hash_key_dma_addr, 2299 sizeof(*rss->hash_key), 0); 2300 if (unlikely(rc)) 2301 return rc; 2302 2303 if (!(BIT(func) & get_resp.u.flow_hash_func.supported_func)) { 2304 netdev_err(ena_dev->net_device, "Flow hash function %d isn't supported\n", func); 2305 return -EOPNOTSUPP; 2306 } 2307 2308 if ((func == ENA_ADMIN_TOEPLITZ) && key) { 2309 if (key_len != sizeof(hash_key->key)) { 2310 netdev_err(ena_dev->net_device, 2311 "key len (%u) doesn't equal the supported size (%zu)\n", key_len, 2312 sizeof(hash_key->key)); 2313 return -EINVAL; 2314 } 2315 memcpy(hash_key->key, key, key_len); 2316 hash_key->key_parts = key_len / sizeof(hash_key->key[0]); 2317 } 2318 2319 rss->hash_init_val = init_val; 2320 old_func = rss->hash_func; 2321 rss->hash_func = func; 2322 rc = ena_com_set_hash_function(ena_dev); 2323 2324 /* Restore the old function */ 2325 if (unlikely(rc)) 2326 rss->hash_func = old_func; 2327 2328 return rc; 2329 } 2330 2331 int ena_com_get_hash_function(struct ena_com_dev *ena_dev, 2332 enum ena_admin_hash_functions *func) 2333 { 2334 struct ena_rss *rss = &ena_dev->rss; 2335 struct ena_admin_get_feat_resp get_resp; 2336 int rc; 2337 2338 if (unlikely(!func)) 2339 return -EINVAL; 2340 2341 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2342 ENA_ADMIN_RSS_HASH_FUNCTION, 2343 rss->hash_key_dma_addr, 2344 sizeof(*rss->hash_key), 0); 2345 if (unlikely(rc)) 2346 return rc; 2347 2348 /* ffs() returns 1 in case the lsb is set */ 2349 rss->hash_func = ffs(get_resp.u.flow_hash_func.selected_func); 2350 if (rss->hash_func) 2351 rss->hash_func--; 2352 2353 *func = rss->hash_func; 2354 2355 return 0; 2356 } 2357 2358 int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key) 2359 { 2360 struct ena_admin_feature_rss_flow_hash_control *hash_key = 2361 ena_dev->rss.hash_key; 2362 2363 if (key) 2364 memcpy(key, hash_key->key, 2365 (size_t)(hash_key->key_parts) * sizeof(hash_key->key[0])); 2366 2367 return 0; 2368 } 2369 2370 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev, 2371 enum ena_admin_flow_hash_proto proto, 2372 u16 *fields) 2373 { 2374 struct ena_rss *rss = &ena_dev->rss; 2375 struct ena_admin_get_feat_resp get_resp; 2376 int rc; 2377 2378 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2379 ENA_ADMIN_RSS_HASH_INPUT, 2380 rss->hash_ctrl_dma_addr, 2381 sizeof(*rss->hash_ctrl), 0); 2382 if (unlikely(rc)) 2383 return rc; 2384 2385 if (fields) 2386 *fields = rss->hash_ctrl->selected_fields[proto].fields; 2387 2388 return 0; 2389 } 2390 2391 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev) 2392 { 2393 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 2394 struct ena_rss *rss = &ena_dev->rss; 2395 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl; 2396 struct ena_admin_set_feat_cmd cmd; 2397 struct ena_admin_set_feat_resp resp; 2398 int ret; 2399 2400 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_HASH_INPUT)) { 2401 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n", 2402 ENA_ADMIN_RSS_HASH_INPUT); 2403 return -EOPNOTSUPP; 2404 } 2405 2406 memset(&cmd, 0x0, sizeof(cmd)); 2407 2408 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2409 cmd.aq_common_descriptor.flags = 2410 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2411 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT; 2412 cmd.u.flow_hash_input.enabled_input_sort = 2413 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK | 2414 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK; 2415 2416 ret = ena_com_mem_addr_set(ena_dev, 2417 &cmd.control_buffer.address, 2418 rss->hash_ctrl_dma_addr); 2419 if (unlikely(ret)) { 2420 netdev_err(ena_dev->net_device, "Memory address set failed\n"); 2421 return ret; 2422 } 2423 cmd.control_buffer.length = sizeof(*hash_ctrl); 2424 2425 ret = ena_com_execute_admin_command(admin_queue, 2426 (struct ena_admin_aq_entry *)&cmd, 2427 sizeof(cmd), 2428 (struct ena_admin_acq_entry *)&resp, 2429 sizeof(resp)); 2430 if (unlikely(ret)) 2431 netdev_err(ena_dev->net_device, "Failed to set hash input. error: %d\n", ret); 2432 2433 return ret; 2434 } 2435 2436 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev) 2437 { 2438 struct ena_rss *rss = &ena_dev->rss; 2439 struct ena_admin_feature_rss_hash_control *hash_ctrl = 2440 rss->hash_ctrl; 2441 u16 available_fields = 0; 2442 int rc, i; 2443 2444 /* Get the supported hash input */ 2445 rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2446 if (unlikely(rc)) 2447 return rc; 2448 2449 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields = 2450 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2451 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2452 2453 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields = 2454 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2455 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2456 2457 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields = 2458 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2459 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2460 2461 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields = 2462 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2463 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2464 2465 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields = 2466 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2467 2468 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields = 2469 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2470 2471 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields = 2472 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2473 2474 hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields = 2475 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA; 2476 2477 for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) { 2478 available_fields = hash_ctrl->selected_fields[i].fields & 2479 hash_ctrl->supported_fields[i].fields; 2480 if (available_fields != hash_ctrl->selected_fields[i].fields) { 2481 netdev_err(ena_dev->net_device, 2482 "Hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n", 2483 i, hash_ctrl->supported_fields[i].fields, 2484 hash_ctrl->selected_fields[i].fields); 2485 return -EOPNOTSUPP; 2486 } 2487 } 2488 2489 rc = ena_com_set_hash_ctrl(ena_dev); 2490 2491 /* In case of failure, restore the old hash ctrl */ 2492 if (unlikely(rc)) 2493 ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2494 2495 return rc; 2496 } 2497 2498 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev, 2499 enum ena_admin_flow_hash_proto proto, 2500 u16 hash_fields) 2501 { 2502 struct ena_rss *rss = &ena_dev->rss; 2503 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl; 2504 u16 supported_fields; 2505 int rc; 2506 2507 if (proto >= ENA_ADMIN_RSS_PROTO_NUM) { 2508 netdev_err(ena_dev->net_device, "Invalid proto num (%u)\n", proto); 2509 return -EINVAL; 2510 } 2511 2512 /* Get the ctrl table */ 2513 rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL); 2514 if (unlikely(rc)) 2515 return rc; 2516 2517 /* Make sure all the fields are supported */ 2518 supported_fields = hash_ctrl->supported_fields[proto].fields; 2519 if ((hash_fields & supported_fields) != hash_fields) { 2520 netdev_err(ena_dev->net_device, 2521 "Proto %d doesn't support the required fields %x. supports only: %x\n", 2522 proto, hash_fields, supported_fields); 2523 } 2524 2525 hash_ctrl->selected_fields[proto].fields = hash_fields; 2526 2527 rc = ena_com_set_hash_ctrl(ena_dev); 2528 2529 /* In case of failure, restore the old hash ctrl */ 2530 if (unlikely(rc)) 2531 ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2532 2533 return 0; 2534 } 2535 2536 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev, 2537 u16 entry_idx, u16 entry_value) 2538 { 2539 struct ena_rss *rss = &ena_dev->rss; 2540 2541 if (unlikely(entry_idx >= (1 << rss->tbl_log_size))) 2542 return -EINVAL; 2543 2544 if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES))) 2545 return -EINVAL; 2546 2547 rss->host_rss_ind_tbl[entry_idx] = entry_value; 2548 2549 return 0; 2550 } 2551 2552 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) 2553 { 2554 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 2555 struct ena_rss *rss = &ena_dev->rss; 2556 struct ena_admin_set_feat_cmd cmd; 2557 struct ena_admin_set_feat_resp resp; 2558 int ret; 2559 2560 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG)) { 2561 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n", 2562 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG); 2563 return -EOPNOTSUPP; 2564 } 2565 2566 ret = ena_com_ind_tbl_convert_to_device(ena_dev); 2567 if (ret) { 2568 netdev_err(ena_dev->net_device, 2569 "Failed to convert host indirection table to device table\n"); 2570 return ret; 2571 } 2572 2573 memset(&cmd, 0x0, sizeof(cmd)); 2574 2575 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2576 cmd.aq_common_descriptor.flags = 2577 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2578 cmd.feat_common.feature_id = ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG; 2579 cmd.u.ind_table.size = rss->tbl_log_size; 2580 cmd.u.ind_table.inline_index = 0xFFFFFFFF; 2581 2582 ret = ena_com_mem_addr_set(ena_dev, 2583 &cmd.control_buffer.address, 2584 rss->rss_ind_tbl_dma_addr); 2585 if (unlikely(ret)) { 2586 netdev_err(ena_dev->net_device, "Memory address set failed\n"); 2587 return ret; 2588 } 2589 2590 cmd.control_buffer.length = (1ULL << rss->tbl_log_size) * 2591 sizeof(struct ena_admin_rss_ind_table_entry); 2592 2593 ret = ena_com_execute_admin_command(admin_queue, 2594 (struct ena_admin_aq_entry *)&cmd, 2595 sizeof(cmd), 2596 (struct ena_admin_acq_entry *)&resp, 2597 sizeof(resp)); 2598 2599 if (unlikely(ret)) 2600 netdev_err(ena_dev->net_device, "Failed to set indirect table. error: %d\n", ret); 2601 2602 return ret; 2603 } 2604 2605 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl) 2606 { 2607 struct ena_rss *rss = &ena_dev->rss; 2608 struct ena_admin_get_feat_resp get_resp; 2609 u32 tbl_size; 2610 int i, rc; 2611 2612 tbl_size = (1ULL << rss->tbl_log_size) * 2613 sizeof(struct ena_admin_rss_ind_table_entry); 2614 2615 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2616 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG, 2617 rss->rss_ind_tbl_dma_addr, 2618 tbl_size, 0); 2619 if (unlikely(rc)) 2620 return rc; 2621 2622 if (!ind_tbl) 2623 return 0; 2624 2625 for (i = 0; i < (1 << rss->tbl_log_size); i++) 2626 ind_tbl[i] = rss->host_rss_ind_tbl[i]; 2627 2628 return 0; 2629 } 2630 2631 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size) 2632 { 2633 int rc; 2634 2635 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss)); 2636 2637 rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size); 2638 if (unlikely(rc)) 2639 goto err_indr_tbl; 2640 2641 /* The following function might return unsupported in case the 2642 * device doesn't support setting the key / hash function. We can safely 2643 * ignore this error and have indirection table support only. 2644 */ 2645 rc = ena_com_hash_key_allocate(ena_dev); 2646 if (likely(!rc)) 2647 ena_com_hash_key_fill_default_key(ena_dev); 2648 else if (rc != -EOPNOTSUPP) 2649 goto err_hash_key; 2650 2651 rc = ena_com_hash_ctrl_init(ena_dev); 2652 if (unlikely(rc)) 2653 goto err_hash_ctrl; 2654 2655 return 0; 2656 2657 err_hash_ctrl: 2658 ena_com_hash_key_destroy(ena_dev); 2659 err_hash_key: 2660 ena_com_indirect_table_destroy(ena_dev); 2661 err_indr_tbl: 2662 2663 return rc; 2664 } 2665 2666 void ena_com_rss_destroy(struct ena_com_dev *ena_dev) 2667 { 2668 ena_com_indirect_table_destroy(ena_dev); 2669 ena_com_hash_key_destroy(ena_dev); 2670 ena_com_hash_ctrl_destroy(ena_dev); 2671 2672 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss)); 2673 } 2674 2675 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev) 2676 { 2677 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2678 2679 host_attr->host_info = dma_alloc_coherent(ena_dev->dmadev, SZ_4K, 2680 &host_attr->host_info_dma_addr, GFP_KERNEL); 2681 if (unlikely(!host_attr->host_info)) 2682 return -ENOMEM; 2683 2684 host_attr->host_info->ena_spec_version = ((ENA_COMMON_SPEC_VERSION_MAJOR << 2685 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) | 2686 (ENA_COMMON_SPEC_VERSION_MINOR)); 2687 2688 return 0; 2689 } 2690 2691 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev, 2692 u32 debug_area_size) 2693 { 2694 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2695 2696 host_attr->debug_area_virt_addr = 2697 dma_alloc_coherent(ena_dev->dmadev, debug_area_size, 2698 &host_attr->debug_area_dma_addr, GFP_KERNEL); 2699 if (unlikely(!host_attr->debug_area_virt_addr)) { 2700 host_attr->debug_area_size = 0; 2701 return -ENOMEM; 2702 } 2703 2704 host_attr->debug_area_size = debug_area_size; 2705 2706 return 0; 2707 } 2708 2709 void ena_com_delete_host_info(struct ena_com_dev *ena_dev) 2710 { 2711 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2712 2713 if (host_attr->host_info) { 2714 dma_free_coherent(ena_dev->dmadev, SZ_4K, host_attr->host_info, 2715 host_attr->host_info_dma_addr); 2716 host_attr->host_info = NULL; 2717 } 2718 } 2719 2720 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev) 2721 { 2722 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2723 2724 if (host_attr->debug_area_virt_addr) { 2725 dma_free_coherent(ena_dev->dmadev, host_attr->debug_area_size, 2726 host_attr->debug_area_virt_addr, host_attr->debug_area_dma_addr); 2727 host_attr->debug_area_virt_addr = NULL; 2728 } 2729 } 2730 2731 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev) 2732 { 2733 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2734 struct ena_com_admin_queue *admin_queue; 2735 struct ena_admin_set_feat_cmd cmd; 2736 struct ena_admin_set_feat_resp resp; 2737 2738 int ret; 2739 2740 /* Host attribute config is called before ena_com_get_dev_attr_feat 2741 * so ena_com can't check if the feature is supported. 2742 */ 2743 2744 memset(&cmd, 0x0, sizeof(cmd)); 2745 admin_queue = &ena_dev->admin_queue; 2746 2747 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2748 cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG; 2749 2750 ret = ena_com_mem_addr_set(ena_dev, 2751 &cmd.u.host_attr.debug_ba, 2752 host_attr->debug_area_dma_addr); 2753 if (unlikely(ret)) { 2754 netdev_err(ena_dev->net_device, "Memory address set failed\n"); 2755 return ret; 2756 } 2757 2758 ret = ena_com_mem_addr_set(ena_dev, 2759 &cmd.u.host_attr.os_info_ba, 2760 host_attr->host_info_dma_addr); 2761 if (unlikely(ret)) { 2762 netdev_err(ena_dev->net_device, "Memory address set failed\n"); 2763 return ret; 2764 } 2765 2766 cmd.u.host_attr.debug_area_size = host_attr->debug_area_size; 2767 2768 ret = ena_com_execute_admin_command(admin_queue, 2769 (struct ena_admin_aq_entry *)&cmd, 2770 sizeof(cmd), 2771 (struct ena_admin_acq_entry *)&resp, 2772 sizeof(resp)); 2773 2774 if (unlikely(ret)) 2775 netdev_err(ena_dev->net_device, "Failed to set host attributes: %d\n", ret); 2776 2777 return ret; 2778 } 2779 2780 /* Interrupt moderation */ 2781 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev) 2782 { 2783 return ena_com_check_supported_feature_id(ena_dev, 2784 ENA_ADMIN_INTERRUPT_MODERATION); 2785 } 2786 2787 static int ena_com_update_nonadaptive_moderation_interval(struct ena_com_dev *ena_dev, 2788 u32 coalesce_usecs, 2789 u32 intr_delay_resolution, 2790 u32 *intr_moder_interval) 2791 { 2792 if (!intr_delay_resolution) { 2793 netdev_err(ena_dev->net_device, "Illegal interrupt delay granularity value\n"); 2794 return -EFAULT; 2795 } 2796 2797 *intr_moder_interval = coalesce_usecs / intr_delay_resolution; 2798 2799 return 0; 2800 } 2801 2802 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev, 2803 u32 tx_coalesce_usecs) 2804 { 2805 return ena_com_update_nonadaptive_moderation_interval(ena_dev, 2806 tx_coalesce_usecs, 2807 ena_dev->intr_delay_resolution, 2808 &ena_dev->intr_moder_tx_interval); 2809 } 2810 2811 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev, 2812 u32 rx_coalesce_usecs) 2813 { 2814 return ena_com_update_nonadaptive_moderation_interval(ena_dev, 2815 rx_coalesce_usecs, 2816 ena_dev->intr_delay_resolution, 2817 &ena_dev->intr_moder_rx_interval); 2818 } 2819 2820 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev) 2821 { 2822 struct ena_admin_get_feat_resp get_resp; 2823 u16 delay_resolution; 2824 int rc; 2825 2826 rc = ena_com_get_feature(ena_dev, &get_resp, 2827 ENA_ADMIN_INTERRUPT_MODERATION, 0); 2828 2829 if (rc) { 2830 if (rc == -EOPNOTSUPP) { 2831 netdev_dbg(ena_dev->net_device, "Feature %d isn't supported\n", 2832 ENA_ADMIN_INTERRUPT_MODERATION); 2833 rc = 0; 2834 } else { 2835 netdev_err(ena_dev->net_device, 2836 "Failed to get interrupt moderation admin cmd. rc: %d\n", rc); 2837 } 2838 2839 /* no moderation supported, disable adaptive support */ 2840 ena_com_disable_adaptive_moderation(ena_dev); 2841 return rc; 2842 } 2843 2844 /* if moderation is supported by device we set adaptive moderation */ 2845 delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution; 2846 ena_com_update_intr_delay_resolution(ena_dev, delay_resolution); 2847 2848 /* Disable adaptive moderation by default - can be enabled later */ 2849 ena_com_disable_adaptive_moderation(ena_dev); 2850 2851 return 0; 2852 } 2853 2854 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev) 2855 { 2856 return ena_dev->intr_moder_tx_interval; 2857 } 2858 2859 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev) 2860 { 2861 return ena_dev->intr_moder_rx_interval; 2862 } 2863 2864 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev, 2865 struct ena_admin_feature_llq_desc *llq_features, 2866 struct ena_llq_configurations *llq_default_cfg) 2867 { 2868 struct ena_com_llq_info *llq_info = &ena_dev->llq_info; 2869 int rc; 2870 2871 if (!llq_features->max_llq_num) { 2872 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 2873 return 0; 2874 } 2875 2876 rc = ena_com_config_llq_info(ena_dev, llq_features, llq_default_cfg); 2877 if (rc) 2878 return rc; 2879 2880 ena_dev->tx_max_header_size = llq_info->desc_list_entry_size - 2881 (llq_info->descs_num_before_header * sizeof(struct ena_eth_io_tx_desc)); 2882 2883 if (unlikely(ena_dev->tx_max_header_size == 0)) { 2884 netdev_err(ena_dev->net_device, "The size of the LLQ entry is smaller than needed\n"); 2885 return -EINVAL; 2886 } 2887 2888 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV; 2889 2890 return 0; 2891 } 2892