1 /* 2 * Copyright 2015 - 2016 Amazon.com, Inc. or its affiliates. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef _ENA_ADMIN_H_ 33 #define _ENA_ADMIN_H_ 34 35 36 enum ena_admin_aq_opcode { 37 ENA_ADMIN_CREATE_SQ = 1, 38 ENA_ADMIN_DESTROY_SQ = 2, 39 ENA_ADMIN_CREATE_CQ = 3, 40 ENA_ADMIN_DESTROY_CQ = 4, 41 ENA_ADMIN_GET_FEATURE = 8, 42 ENA_ADMIN_SET_FEATURE = 9, 43 ENA_ADMIN_GET_STATS = 11, 44 }; 45 46 enum ena_admin_aq_completion_status { 47 ENA_ADMIN_SUCCESS = 0, 48 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1, 49 ENA_ADMIN_BAD_OPCODE = 2, 50 ENA_ADMIN_UNSUPPORTED_OPCODE = 3, 51 ENA_ADMIN_MALFORMED_REQUEST = 4, 52 /* Additional status is provided in ACQ entry extended_status */ 53 ENA_ADMIN_ILLEGAL_PARAMETER = 5, 54 ENA_ADMIN_UNKNOWN_ERROR = 6, 55 ENA_ADMIN_RESOURCE_BUSY = 7, 56 }; 57 58 enum ena_admin_aq_feature_id { 59 ENA_ADMIN_DEVICE_ATTRIBUTES = 1, 60 ENA_ADMIN_MAX_QUEUES_NUM = 2, 61 ENA_ADMIN_HW_HINTS = 3, 62 ENA_ADMIN_LLQ = 4, 63 ENA_ADMIN_MAX_QUEUES_EXT = 7, 64 ENA_ADMIN_RSS_HASH_FUNCTION = 10, 65 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11, 66 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12, 67 ENA_ADMIN_MTU = 14, 68 ENA_ADMIN_RSS_HASH_INPUT = 18, 69 ENA_ADMIN_INTERRUPT_MODERATION = 20, 70 ENA_ADMIN_AENQ_CONFIG = 26, 71 ENA_ADMIN_LINK_CONFIG = 27, 72 ENA_ADMIN_HOST_ATTR_CONFIG = 28, 73 ENA_ADMIN_FEATURES_OPCODE_NUM = 32, 74 }; 75 76 enum ena_admin_placement_policy_type { 77 /* descriptors and headers are in host memory */ 78 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1, 79 /* descriptors and headers are in device memory (a.k.a Low Latency 80 * Queue) 81 */ 82 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3, 83 }; 84 85 enum ena_admin_link_types { 86 ENA_ADMIN_LINK_SPEED_1G = 0x1, 87 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2, 88 ENA_ADMIN_LINK_SPEED_5G = 0x4, 89 ENA_ADMIN_LINK_SPEED_10G = 0x8, 90 ENA_ADMIN_LINK_SPEED_25G = 0x10, 91 ENA_ADMIN_LINK_SPEED_40G = 0x20, 92 ENA_ADMIN_LINK_SPEED_50G = 0x40, 93 ENA_ADMIN_LINK_SPEED_100G = 0x80, 94 ENA_ADMIN_LINK_SPEED_200G = 0x100, 95 ENA_ADMIN_LINK_SPEED_400G = 0x200, 96 }; 97 98 enum ena_admin_completion_policy_type { 99 /* completion queue entry for each sq descriptor */ 100 ENA_ADMIN_COMPLETION_POLICY_DESC = 0, 101 /* completion queue entry upon request in sq descriptor */ 102 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1, 103 /* current queue head pointer is updated in OS memory upon sq 104 * descriptor request 105 */ 106 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2, 107 /* current queue head pointer is updated in OS memory for each sq 108 * descriptor 109 */ 110 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3, 111 }; 112 113 /* basic stats return ena_admin_basic_stats while extanded stats return a 114 * buffer (string format) with additional statistics per queue and per 115 * device id 116 */ 117 enum ena_admin_get_stats_type { 118 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0, 119 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1, 120 }; 121 122 enum ena_admin_get_stats_scope { 123 ENA_ADMIN_SPECIFIC_QUEUE = 0, 124 ENA_ADMIN_ETH_TRAFFIC = 1, 125 }; 126 127 struct ena_admin_aq_common_desc { 128 /* 11:0 : command_id 129 * 15:12 : reserved12 130 */ 131 u16 command_id; 132 133 /* as appears in ena_admin_aq_opcode */ 134 u8 opcode; 135 136 /* 0 : phase 137 * 1 : ctrl_data - control buffer address valid 138 * 2 : ctrl_data_indirect - control buffer address 139 * points to list of pages with addresses of control 140 * buffers 141 * 7:3 : reserved3 142 */ 143 u8 flags; 144 }; 145 146 /* used in ena_admin_aq_entry. Can point directly to control data, or to a 147 * page list chunk. Used also at the end of indirect mode page list chunks, 148 * for chaining. 149 */ 150 struct ena_admin_ctrl_buff_info { 151 u32 length; 152 153 struct ena_common_mem_addr address; 154 }; 155 156 struct ena_admin_sq { 157 u16 sq_idx; 158 159 /* 4:0 : reserved 160 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx 161 */ 162 u8 sq_identity; 163 164 u8 reserved1; 165 }; 166 167 struct ena_admin_aq_entry { 168 struct ena_admin_aq_common_desc aq_common_descriptor; 169 170 union { 171 u32 inline_data_w1[3]; 172 173 struct ena_admin_ctrl_buff_info control_buffer; 174 } u; 175 176 u32 inline_data_w4[12]; 177 }; 178 179 struct ena_admin_acq_common_desc { 180 /* command identifier to associate it with the aq descriptor 181 * 11:0 : command_id 182 * 15:12 : reserved12 183 */ 184 u16 command; 185 186 u8 status; 187 188 /* 0 : phase 189 * 7:1 : reserved1 190 */ 191 u8 flags; 192 193 u16 extended_status; 194 195 /* indicates to the driver which AQ entry has been consumed by the 196 * device and could be reused 197 */ 198 u16 sq_head_indx; 199 }; 200 201 struct ena_admin_acq_entry { 202 struct ena_admin_acq_common_desc acq_common_descriptor; 203 204 u32 response_specific_data[14]; 205 }; 206 207 struct ena_admin_aq_create_sq_cmd { 208 struct ena_admin_aq_common_desc aq_common_descriptor; 209 210 /* 4:0 : reserved0_w1 211 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx 212 */ 213 u8 sq_identity; 214 215 u8 reserved8_w1; 216 217 /* 3:0 : placement_policy - Describing where the SQ 218 * descriptor ring and the SQ packet headers reside: 219 * 0x1 - descriptors and headers are in OS memory, 220 * 0x3 - descriptors and headers in device memory 221 * (a.k.a Low Latency Queue) 222 * 6:4 : completion_policy - Describing what policy 223 * to use for generation completion entry (cqe) in 224 * the CQ associated with this SQ: 0x0 - cqe for each 225 * sq descriptor, 0x1 - cqe upon request in sq 226 * descriptor, 0x2 - current queue head pointer is 227 * updated in OS memory upon sq descriptor request 228 * 0x3 - current queue head pointer is updated in OS 229 * memory for each sq descriptor 230 * 7 : reserved15_w1 231 */ 232 u8 sq_caps_2; 233 234 /* 0 : is_physically_contiguous - Described if the 235 * queue ring memory is allocated in physical 236 * contiguous pages or split. 237 * 7:1 : reserved17_w1 238 */ 239 u8 sq_caps_3; 240 241 /* associated completion queue id. This CQ must be created prior to 242 * SQ creation 243 */ 244 u16 cq_idx; 245 246 /* submission queue depth in entries */ 247 u16 sq_depth; 248 249 /* SQ physical base address in OS memory. This field should not be 250 * used for Low Latency queues. Has to be page aligned. 251 */ 252 struct ena_common_mem_addr sq_ba; 253 254 /* specifies queue head writeback location in OS memory. Valid if 255 * completion_policy is set to completion_policy_head_on_demand or 256 * completion_policy_head. Has to be cache aligned 257 */ 258 struct ena_common_mem_addr sq_head_writeback; 259 260 u32 reserved0_w7; 261 262 u32 reserved0_w8; 263 }; 264 265 enum ena_admin_sq_direction { 266 ENA_ADMIN_SQ_DIRECTION_TX = 1, 267 ENA_ADMIN_SQ_DIRECTION_RX = 2, 268 }; 269 270 struct ena_admin_acq_create_sq_resp_desc { 271 struct ena_admin_acq_common_desc acq_common_desc; 272 273 u16 sq_idx; 274 275 u16 reserved; 276 277 /* queue doorbell address as an offset to PCIe MMIO REG BAR */ 278 u32 sq_doorbell_offset; 279 280 /* low latency queue ring base address as an offset to PCIe MMIO 281 * LLQ_MEM BAR 282 */ 283 u32 llq_descriptors_offset; 284 285 /* low latency queue headers' memory as an offset to PCIe MMIO 286 * LLQ_MEM BAR 287 */ 288 u32 llq_headers_offset; 289 }; 290 291 struct ena_admin_aq_destroy_sq_cmd { 292 struct ena_admin_aq_common_desc aq_common_descriptor; 293 294 struct ena_admin_sq sq; 295 }; 296 297 struct ena_admin_acq_destroy_sq_resp_desc { 298 struct ena_admin_acq_common_desc acq_common_desc; 299 }; 300 301 struct ena_admin_aq_create_cq_cmd { 302 struct ena_admin_aq_common_desc aq_common_descriptor; 303 304 /* 4:0 : reserved5 305 * 5 : interrupt_mode_enabled - if set, cq operates 306 * in interrupt mode, otherwise - polling 307 * 7:6 : reserved6 308 */ 309 u8 cq_caps_1; 310 311 /* 4:0 : cq_entry_size_words - size of CQ entry in 312 * 32-bit words, valid values: 4, 8. 313 * 7:5 : reserved7 314 */ 315 u8 cq_caps_2; 316 317 /* completion queue depth in # of entries. must be power of 2 */ 318 u16 cq_depth; 319 320 /* msix vector assigned to this cq */ 321 u32 msix_vector; 322 323 /* cq physical base address in OS memory. CQ must be physically 324 * contiguous 325 */ 326 struct ena_common_mem_addr cq_ba; 327 }; 328 329 struct ena_admin_acq_create_cq_resp_desc { 330 struct ena_admin_acq_common_desc acq_common_desc; 331 332 u16 cq_idx; 333 334 /* actual cq depth in number of entries */ 335 u16 cq_actual_depth; 336 337 u32 numa_node_register_offset; 338 339 u32 cq_head_db_register_offset; 340 341 u32 cq_interrupt_unmask_register_offset; 342 }; 343 344 struct ena_admin_aq_destroy_cq_cmd { 345 struct ena_admin_aq_common_desc aq_common_descriptor; 346 347 u16 cq_idx; 348 349 u16 reserved1; 350 }; 351 352 struct ena_admin_acq_destroy_cq_resp_desc { 353 struct ena_admin_acq_common_desc acq_common_desc; 354 }; 355 356 /* ENA AQ Get Statistics command. Extended statistics are placed in control 357 * buffer pointed by AQ entry 358 */ 359 struct ena_admin_aq_get_stats_cmd { 360 struct ena_admin_aq_common_desc aq_common_descriptor; 361 362 union { 363 /* command specific inline data */ 364 u32 inline_data_w1[3]; 365 366 struct ena_admin_ctrl_buff_info control_buffer; 367 } u; 368 369 /* stats type as defined in enum ena_admin_get_stats_type */ 370 u8 type; 371 372 /* stats scope defined in enum ena_admin_get_stats_scope */ 373 u8 scope; 374 375 u16 reserved3; 376 377 /* queue id. used when scope is specific_queue */ 378 u16 queue_idx; 379 380 /* device id, value 0xFFFF means mine. only privileged device can get 381 * stats of other device 382 */ 383 u16 device_id; 384 }; 385 386 /* Basic Statistics Command. */ 387 struct ena_admin_basic_stats { 388 u32 tx_bytes_low; 389 390 u32 tx_bytes_high; 391 392 u32 tx_pkts_low; 393 394 u32 tx_pkts_high; 395 396 u32 rx_bytes_low; 397 398 u32 rx_bytes_high; 399 400 u32 rx_pkts_low; 401 402 u32 rx_pkts_high; 403 404 u32 rx_drops_low; 405 406 u32 rx_drops_high; 407 408 u32 tx_drops_low; 409 410 u32 tx_drops_high; 411 }; 412 413 struct ena_admin_acq_get_stats_resp { 414 struct ena_admin_acq_common_desc acq_common_desc; 415 416 struct ena_admin_basic_stats basic_stats; 417 }; 418 419 struct ena_admin_get_set_feature_common_desc { 420 /* 1:0 : select - 0x1 - current value; 0x3 - default 421 * value 422 * 7:3 : reserved3 423 */ 424 u8 flags; 425 426 /* as appears in ena_admin_aq_feature_id */ 427 u8 feature_id; 428 429 /* The driver specifies the max feature version it supports and the 430 * device responds with the currently supported feature version. The 431 * field is zero based 432 */ 433 u8 feature_version; 434 435 u8 reserved8; 436 }; 437 438 struct ena_admin_device_attr_feature_desc { 439 u32 impl_id; 440 441 u32 device_version; 442 443 /* bitmap of ena_admin_aq_feature_id */ 444 u32 supported_features; 445 446 u32 reserved3; 447 448 /* Indicates how many bits are used physical address access. */ 449 u32 phys_addr_width; 450 451 /* Indicates how many bits are used virtual address access. */ 452 u32 virt_addr_width; 453 454 /* unicast MAC address (in Network byte order) */ 455 u8 mac_addr[6]; 456 457 u8 reserved7[2]; 458 459 u32 max_mtu; 460 }; 461 462 enum ena_admin_llq_header_location { 463 /* header is in descriptor list */ 464 ENA_ADMIN_INLINE_HEADER = 1, 465 /* header in a separate ring, implies 16B descriptor list entry */ 466 ENA_ADMIN_HEADER_RING = 2, 467 }; 468 469 enum ena_admin_llq_ring_entry_size { 470 ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1, 471 ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2, 472 ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4, 473 }; 474 475 enum ena_admin_llq_num_descs_before_header { 476 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0, 477 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1, 478 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2, 479 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4, 480 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8, 481 }; 482 483 /* packet descriptor list entry always starts with one or more descriptors, 484 * followed by a header. The rest of the descriptors are located in the 485 * beginning of the subsequent entry. Stride refers to how the rest of the 486 * descriptors are placed. This field is relevant only for inline header 487 * mode 488 */ 489 enum ena_admin_llq_stride_ctrl { 490 ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1, 491 ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2, 492 }; 493 494 struct ena_admin_feature_llq_desc { 495 u32 max_llq_num; 496 497 u32 max_llq_depth; 498 499 /* specify the header locations the device supports. bitfield of 500 * enum ena_admin_llq_header_location. 501 */ 502 u16 header_location_ctrl_supported; 503 504 /* the header location the driver selected to use. */ 505 u16 header_location_ctrl_enabled; 506 507 /* if inline header is specified - this is the size of descriptor 508 * list entry. If header in a separate ring is specified - this is 509 * the size of header ring entry. bitfield of enum 510 * ena_admin_llq_ring_entry_size. specify the entry sizes the device 511 * supports 512 */ 513 u16 entry_size_ctrl_supported; 514 515 /* the entry size the driver selected to use. */ 516 u16 entry_size_ctrl_enabled; 517 518 /* valid only if inline header is specified. First entry associated 519 * with the packet includes descriptors and header. Rest of the 520 * entries occupied by descriptors. This parameter defines the max 521 * number of descriptors precedding the header in the first entry. 522 * The field is bitfield of enum 523 * ena_admin_llq_num_descs_before_header and specify the values the 524 * device supports 525 */ 526 u16 desc_num_before_header_supported; 527 528 /* the desire field the driver selected to use */ 529 u16 desc_num_before_header_enabled; 530 531 /* valid only if inline was chosen. bitfield of enum 532 * ena_admin_llq_stride_ctrl 533 */ 534 u16 descriptors_stride_ctrl_supported; 535 536 /* the stride control the driver selected to use */ 537 u16 descriptors_stride_ctrl_enabled; 538 539 /* Maximum size in bytes taken by llq entries in a single tx burst. 540 * Set to 0 when there is no such limit. 541 */ 542 u32 max_tx_burst_size; 543 }; 544 545 struct ena_admin_queue_ext_feature_fields { 546 u32 max_tx_sq_num; 547 548 u32 max_tx_cq_num; 549 550 u32 max_rx_sq_num; 551 552 u32 max_rx_cq_num; 553 554 u32 max_tx_sq_depth; 555 556 u32 max_tx_cq_depth; 557 558 u32 max_rx_sq_depth; 559 560 u32 max_rx_cq_depth; 561 562 u32 max_tx_header_size; 563 564 /* Maximum Descriptors number, including meta descriptor, allowed for 565 * a single Tx packet 566 */ 567 u16 max_per_packet_tx_descs; 568 569 /* Maximum Descriptors number allowed for a single Rx packet */ 570 u16 max_per_packet_rx_descs; 571 }; 572 573 struct ena_admin_queue_feature_desc { 574 u32 max_sq_num; 575 576 u32 max_sq_depth; 577 578 u32 max_cq_num; 579 580 u32 max_cq_depth; 581 582 u32 max_legacy_llq_num; 583 584 u32 max_legacy_llq_depth; 585 586 u32 max_header_size; 587 588 /* Maximum Descriptors number, including meta descriptor, allowed for 589 * a single Tx packet 590 */ 591 u16 max_packet_tx_descs; 592 593 /* Maximum Descriptors number allowed for a single Rx packet */ 594 u16 max_packet_rx_descs; 595 }; 596 597 struct ena_admin_set_feature_mtu_desc { 598 /* exclude L2 */ 599 u32 mtu; 600 }; 601 602 struct ena_admin_set_feature_host_attr_desc { 603 /* host OS info base address in OS memory. host info is 4KB of 604 * physically contiguous 605 */ 606 struct ena_common_mem_addr os_info_ba; 607 608 /* host debug area base address in OS memory. debug area must be 609 * physically contiguous 610 */ 611 struct ena_common_mem_addr debug_ba; 612 613 /* debug area size */ 614 u32 debug_area_size; 615 }; 616 617 struct ena_admin_feature_intr_moder_desc { 618 /* interrupt delay granularity in usec */ 619 u16 intr_delay_resolution; 620 621 u16 reserved; 622 }; 623 624 struct ena_admin_get_feature_link_desc { 625 /* Link speed in Mb */ 626 u32 speed; 627 628 /* bit field of enum ena_admin_link types */ 629 u32 supported; 630 631 /* 0 : autoneg 632 * 1 : duplex - Full Duplex 633 * 31:2 : reserved2 634 */ 635 u32 flags; 636 }; 637 638 struct ena_admin_feature_aenq_desc { 639 /* bitmask for AENQ groups the device can report */ 640 u32 supported_groups; 641 642 /* bitmask for AENQ groups to report */ 643 u32 enabled_groups; 644 }; 645 646 struct ena_admin_feature_offload_desc { 647 /* 0 : TX_L3_csum_ipv4 648 * 1 : TX_L4_ipv4_csum_part - The checksum field 649 * should be initialized with pseudo header checksum 650 * 2 : TX_L4_ipv4_csum_full 651 * 3 : TX_L4_ipv6_csum_part - The checksum field 652 * should be initialized with pseudo header checksum 653 * 4 : TX_L4_ipv6_csum_full 654 * 5 : tso_ipv4 655 * 6 : tso_ipv6 656 * 7 : tso_ecn 657 */ 658 u32 tx; 659 660 /* Receive side supported stateless offload 661 * 0 : RX_L3_csum_ipv4 - IPv4 checksum 662 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum 663 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum 664 * 3 : RX_hash - Hash calculation 665 */ 666 u32 rx_supported; 667 668 u32 rx_enabled; 669 }; 670 671 enum ena_admin_hash_functions { 672 ENA_ADMIN_TOEPLITZ = 1, 673 ENA_ADMIN_CRC32 = 2, 674 }; 675 676 struct ena_admin_feature_rss_flow_hash_control { 677 u32 keys_num; 678 679 u32 reserved; 680 681 u32 key[10]; 682 }; 683 684 struct ena_admin_feature_rss_flow_hash_function { 685 /* 7:0 : funcs - bitmask of ena_admin_hash_functions */ 686 u32 supported_func; 687 688 /* 7:0 : selected_func - bitmask of 689 * ena_admin_hash_functions 690 */ 691 u32 selected_func; 692 693 /* initial value */ 694 u32 init_val; 695 }; 696 697 /* RSS flow hash protocols */ 698 enum ena_admin_flow_hash_proto { 699 ENA_ADMIN_RSS_TCP4 = 0, 700 ENA_ADMIN_RSS_UDP4 = 1, 701 ENA_ADMIN_RSS_TCP6 = 2, 702 ENA_ADMIN_RSS_UDP6 = 3, 703 ENA_ADMIN_RSS_IP4 = 4, 704 ENA_ADMIN_RSS_IP6 = 5, 705 ENA_ADMIN_RSS_IP4_FRAG = 6, 706 ENA_ADMIN_RSS_NOT_IP = 7, 707 /* TCPv6 with extension header */ 708 ENA_ADMIN_RSS_TCP6_EX = 8, 709 /* IPv6 with extension header */ 710 ENA_ADMIN_RSS_IP6_EX = 9, 711 ENA_ADMIN_RSS_PROTO_NUM = 16, 712 }; 713 714 /* RSS flow hash fields */ 715 enum ena_admin_flow_hash_fields { 716 /* Ethernet Dest Addr */ 717 ENA_ADMIN_RSS_L2_DA = BIT(0), 718 /* Ethernet Src Addr */ 719 ENA_ADMIN_RSS_L2_SA = BIT(1), 720 /* ipv4/6 Dest Addr */ 721 ENA_ADMIN_RSS_L3_DA = BIT(2), 722 /* ipv4/6 Src Addr */ 723 ENA_ADMIN_RSS_L3_SA = BIT(3), 724 /* tcp/udp Dest Port */ 725 ENA_ADMIN_RSS_L4_DP = BIT(4), 726 /* tcp/udp Src Port */ 727 ENA_ADMIN_RSS_L4_SP = BIT(5), 728 }; 729 730 struct ena_admin_proto_input { 731 /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */ 732 u16 fields; 733 734 u16 reserved2; 735 }; 736 737 struct ena_admin_feature_rss_hash_control { 738 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM]; 739 740 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM]; 741 742 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM]; 743 744 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM]; 745 }; 746 747 struct ena_admin_feature_rss_flow_hash_input { 748 /* supported hash input sorting 749 * 1 : L3_sort - support swap L3 addresses if DA is 750 * smaller than SA 751 * 2 : L4_sort - support swap L4 ports if DP smaller 752 * SP 753 */ 754 u16 supported_input_sort; 755 756 /* enabled hash input sorting 757 * 1 : enable_L3_sort - enable swap L3 addresses if 758 * DA smaller than SA 759 * 2 : enable_L4_sort - enable swap L4 ports if DP 760 * smaller than SP 761 */ 762 u16 enabled_input_sort; 763 }; 764 765 enum ena_admin_os_type { 766 ENA_ADMIN_OS_LINUX = 1, 767 ENA_ADMIN_OS_WIN = 2, 768 ENA_ADMIN_OS_DPDK = 3, 769 ENA_ADMIN_OS_FREEBSD = 4, 770 ENA_ADMIN_OS_IPXE = 5, 771 ENA_ADMIN_OS_ESXI = 6, 772 ENA_ADMIN_OS_GROUPS_NUM = 6, 773 }; 774 775 struct ena_admin_host_info { 776 /* defined in enum ena_admin_os_type */ 777 u32 os_type; 778 779 /* os distribution string format */ 780 u8 os_dist_str[128]; 781 782 /* OS distribution numeric format */ 783 u32 os_dist; 784 785 /* kernel version string format */ 786 u8 kernel_ver_str[32]; 787 788 /* Kernel version numeric format */ 789 u32 kernel_ver; 790 791 /* 7:0 : major 792 * 15:8 : minor 793 * 23:16 : sub_minor 794 * 31:24 : module_type 795 */ 796 u32 driver_version; 797 798 /* features bitmap */ 799 u32 supported_network_features[2]; 800 801 /* ENA spec version of driver */ 802 u16 ena_spec_version; 803 804 /* ENA device's Bus, Device and Function 805 * 2:0 : function 806 * 7:3 : device 807 * 15:8 : bus 808 */ 809 u16 bdf; 810 811 /* Number of CPUs */ 812 u16 num_cpus; 813 814 u16 reserved; 815 816 /* 1 :0 : reserved 817 * 2 : interrupt_moderation 818 * 31:3 : reserved 819 */ 820 u32 driver_supported_features; 821 }; 822 823 struct ena_admin_rss_ind_table_entry { 824 u16 cq_idx; 825 826 u16 reserved; 827 }; 828 829 struct ena_admin_feature_rss_ind_table { 830 /* min supported table size (2^min_size) */ 831 u16 min_size; 832 833 /* max supported table size (2^max_size) */ 834 u16 max_size; 835 836 /* table size (2^size) */ 837 u16 size; 838 839 u16 reserved; 840 841 /* index of the inline entry. 0xFFFFFFFF means invalid */ 842 u32 inline_index; 843 844 /* used for updating single entry, ignored when setting the entire 845 * table through the control buffer. 846 */ 847 struct ena_admin_rss_ind_table_entry inline_entry; 848 }; 849 850 /* When hint value is 0, driver should use it's own predefined value */ 851 struct ena_admin_ena_hw_hints { 852 /* value in ms */ 853 u16 mmio_read_timeout; 854 855 /* value in ms */ 856 u16 driver_watchdog_timeout; 857 858 /* Per packet tx completion timeout. value in ms */ 859 u16 missing_tx_completion_timeout; 860 861 u16 missed_tx_completion_count_threshold_to_reset; 862 863 /* value in ms */ 864 u16 admin_completion_tx_timeout; 865 866 u16 netdev_wd_timeout; 867 868 u16 max_tx_sgl_size; 869 870 u16 max_rx_sgl_size; 871 872 u16 reserved[8]; 873 }; 874 875 struct ena_admin_get_feat_cmd { 876 struct ena_admin_aq_common_desc aq_common_descriptor; 877 878 struct ena_admin_ctrl_buff_info control_buffer; 879 880 struct ena_admin_get_set_feature_common_desc feat_common; 881 882 u32 raw[11]; 883 }; 884 885 struct ena_admin_queue_ext_feature_desc { 886 /* version */ 887 u8 version; 888 889 u8 reserved1[3]; 890 891 union { 892 struct ena_admin_queue_ext_feature_fields max_queue_ext; 893 894 u32 raw[10]; 895 }; 896 }; 897 898 struct ena_admin_get_feat_resp { 899 struct ena_admin_acq_common_desc acq_common_desc; 900 901 union { 902 u32 raw[14]; 903 904 struct ena_admin_device_attr_feature_desc dev_attr; 905 906 struct ena_admin_feature_llq_desc llq; 907 908 struct ena_admin_queue_feature_desc max_queue; 909 910 struct ena_admin_queue_ext_feature_desc max_queue_ext; 911 912 struct ena_admin_feature_aenq_desc aenq; 913 914 struct ena_admin_get_feature_link_desc link; 915 916 struct ena_admin_feature_offload_desc offload; 917 918 struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 919 920 struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 921 922 struct ena_admin_feature_rss_ind_table ind_table; 923 924 struct ena_admin_feature_intr_moder_desc intr_moderation; 925 926 struct ena_admin_ena_hw_hints hw_hints; 927 } u; 928 }; 929 930 struct ena_admin_set_feat_cmd { 931 struct ena_admin_aq_common_desc aq_common_descriptor; 932 933 struct ena_admin_ctrl_buff_info control_buffer; 934 935 struct ena_admin_get_set_feature_common_desc feat_common; 936 937 union { 938 u32 raw[11]; 939 940 /* mtu size */ 941 struct ena_admin_set_feature_mtu_desc mtu; 942 943 /* host attributes */ 944 struct ena_admin_set_feature_host_attr_desc host_attr; 945 946 /* AENQ configuration */ 947 struct ena_admin_feature_aenq_desc aenq; 948 949 /* rss flow hash function */ 950 struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 951 952 /* rss flow hash input */ 953 struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 954 955 /* rss indirection table */ 956 struct ena_admin_feature_rss_ind_table ind_table; 957 958 /* LLQ configuration */ 959 struct ena_admin_feature_llq_desc llq; 960 } u; 961 }; 962 963 struct ena_admin_set_feat_resp { 964 struct ena_admin_acq_common_desc acq_common_desc; 965 966 union { 967 u32 raw[14]; 968 } u; 969 }; 970 971 struct ena_admin_aenq_common_desc { 972 u16 group; 973 974 u16 syndrom; 975 976 /* 0 : phase 977 * 7:1 : reserved - MBZ 978 */ 979 u8 flags; 980 981 u8 reserved1[3]; 982 983 u32 timestamp_low; 984 985 u32 timestamp_high; 986 }; 987 988 /* asynchronous event notification groups */ 989 enum ena_admin_aenq_group { 990 ENA_ADMIN_LINK_CHANGE = 0, 991 ENA_ADMIN_FATAL_ERROR = 1, 992 ENA_ADMIN_WARNING = 2, 993 ENA_ADMIN_NOTIFICATION = 3, 994 ENA_ADMIN_KEEP_ALIVE = 4, 995 ENA_ADMIN_AENQ_GROUPS_NUM = 5, 996 }; 997 998 enum ena_admin_aenq_notification_syndrom { 999 ENA_ADMIN_SUSPEND = 0, 1000 ENA_ADMIN_RESUME = 1, 1001 ENA_ADMIN_UPDATE_HINTS = 2, 1002 }; 1003 1004 struct ena_admin_aenq_entry { 1005 struct ena_admin_aenq_common_desc aenq_common_desc; 1006 1007 /* command specific inline data */ 1008 u32 inline_data_w4[12]; 1009 }; 1010 1011 struct ena_admin_aenq_link_change_desc { 1012 struct ena_admin_aenq_common_desc aenq_common_desc; 1013 1014 /* 0 : link_status */ 1015 u32 flags; 1016 }; 1017 1018 struct ena_admin_aenq_keep_alive_desc { 1019 struct ena_admin_aenq_common_desc aenq_common_desc; 1020 1021 u32 rx_drops_low; 1022 1023 u32 rx_drops_high; 1024 1025 u32 tx_drops_low; 1026 1027 u32 tx_drops_high; 1028 }; 1029 1030 struct ena_admin_ena_mmio_req_read_less_resp { 1031 u16 req_id; 1032 1033 u16 reg_off; 1034 1035 /* value is valid when poll is cleared */ 1036 u32 reg_val; 1037 }; 1038 1039 /* aq_common_desc */ 1040 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 1041 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0) 1042 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1 1043 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1) 1044 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2 1045 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2) 1046 1047 /* sq */ 1048 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5 1049 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5) 1050 1051 /* acq_common_desc */ 1052 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 1053 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0) 1054 1055 /* aq_create_sq_cmd */ 1056 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5 1057 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5) 1058 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0) 1059 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4 1060 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4) 1061 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0) 1062 1063 /* aq_create_cq_cmd */ 1064 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5 1065 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5) 1066 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) 1067 1068 /* get_set_feature_common_desc */ 1069 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0) 1070 1071 /* get_feature_link_desc */ 1072 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0) 1073 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1 1074 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1) 1075 1076 /* feature_offload_desc */ 1077 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0) 1078 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1 1079 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1) 1080 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2 1081 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2) 1082 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3 1083 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3) 1084 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4 1085 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4) 1086 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5 1087 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5) 1088 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6 1089 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6) 1090 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7 1091 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7) 1092 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0) 1093 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1 1094 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1) 1095 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2 1096 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2) 1097 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3 1098 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3) 1099 1100 /* feature_rss_flow_hash_function */ 1101 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0) 1102 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0) 1103 1104 /* feature_rss_flow_hash_input */ 1105 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1 1106 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1) 1107 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2 1108 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2) 1109 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1 1110 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1) 1111 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2 1112 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2) 1113 1114 /* host_info */ 1115 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0) 1116 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8 1117 #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8) 1118 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16 1119 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16) 1120 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24 1121 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24) 1122 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0) 1123 #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3 1124 #define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3) 1125 #define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8 1126 #define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8) 1127 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2 1128 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2) 1129 1130 /* aenq_common_desc */ 1131 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0) 1132 1133 /* aenq_link_change_desc */ 1134 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0) 1135 1136 #endif /*_ENA_ADMIN_H_ */ 1137