1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* 3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved. 4 */ 5 #ifndef _ENA_ADMIN_H_ 6 #define _ENA_ADMIN_H_ 7 8 #define ENA_ADMIN_RSS_KEY_PARTS 10 9 10 enum ena_admin_aq_opcode { 11 ENA_ADMIN_CREATE_SQ = 1, 12 ENA_ADMIN_DESTROY_SQ = 2, 13 ENA_ADMIN_CREATE_CQ = 3, 14 ENA_ADMIN_DESTROY_CQ = 4, 15 ENA_ADMIN_GET_FEATURE = 8, 16 ENA_ADMIN_SET_FEATURE = 9, 17 ENA_ADMIN_GET_STATS = 11, 18 }; 19 20 enum ena_admin_aq_completion_status { 21 ENA_ADMIN_SUCCESS = 0, 22 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1, 23 ENA_ADMIN_BAD_OPCODE = 2, 24 ENA_ADMIN_UNSUPPORTED_OPCODE = 3, 25 ENA_ADMIN_MALFORMED_REQUEST = 4, 26 /* Additional status is provided in ACQ entry extended_status */ 27 ENA_ADMIN_ILLEGAL_PARAMETER = 5, 28 ENA_ADMIN_UNKNOWN_ERROR = 6, 29 ENA_ADMIN_RESOURCE_BUSY = 7, 30 }; 31 32 /* subcommands for the set/get feature admin commands */ 33 enum ena_admin_aq_feature_id { 34 ENA_ADMIN_DEVICE_ATTRIBUTES = 1, 35 ENA_ADMIN_MAX_QUEUES_NUM = 2, 36 ENA_ADMIN_HW_HINTS = 3, 37 ENA_ADMIN_LLQ = 4, 38 ENA_ADMIN_MAX_QUEUES_EXT = 7, 39 ENA_ADMIN_RSS_HASH_FUNCTION = 10, 40 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11, 41 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG = 12, 42 ENA_ADMIN_MTU = 14, 43 ENA_ADMIN_RSS_HASH_INPUT = 18, 44 ENA_ADMIN_INTERRUPT_MODERATION = 20, 45 ENA_ADMIN_AENQ_CONFIG = 26, 46 ENA_ADMIN_LINK_CONFIG = 27, 47 ENA_ADMIN_HOST_ATTR_CONFIG = 28, 48 ENA_ADMIN_FEATURES_OPCODE_NUM = 32, 49 }; 50 51 /* device capabilities */ 52 enum ena_admin_aq_caps_id { 53 ENA_ADMIN_ENI_STATS = 0, 54 /* ENA SRD customer metrics */ 55 ENA_ADMIN_ENA_SRD_INFO = 1, 56 }; 57 58 enum ena_admin_placement_policy_type { 59 /* descriptors and headers are in host memory */ 60 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1, 61 /* descriptors and headers are in device memory (a.k.a Low Latency 62 * Queue) 63 */ 64 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3, 65 }; 66 67 enum ena_admin_link_types { 68 ENA_ADMIN_LINK_SPEED_1G = 0x1, 69 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2, 70 ENA_ADMIN_LINK_SPEED_5G = 0x4, 71 ENA_ADMIN_LINK_SPEED_10G = 0x8, 72 ENA_ADMIN_LINK_SPEED_25G = 0x10, 73 ENA_ADMIN_LINK_SPEED_40G = 0x20, 74 ENA_ADMIN_LINK_SPEED_50G = 0x40, 75 ENA_ADMIN_LINK_SPEED_100G = 0x80, 76 ENA_ADMIN_LINK_SPEED_200G = 0x100, 77 ENA_ADMIN_LINK_SPEED_400G = 0x200, 78 }; 79 80 enum ena_admin_completion_policy_type { 81 /* completion queue entry for each sq descriptor */ 82 ENA_ADMIN_COMPLETION_POLICY_DESC = 0, 83 /* completion queue entry upon request in sq descriptor */ 84 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1, 85 /* current queue head pointer is updated in OS memory upon sq 86 * descriptor request 87 */ 88 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2, 89 /* current queue head pointer is updated in OS memory for each sq 90 * descriptor 91 */ 92 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3, 93 }; 94 95 /* basic stats return ena_admin_basic_stats while extanded stats return a 96 * buffer (string format) with additional statistics per queue and per 97 * device id 98 */ 99 enum ena_admin_get_stats_type { 100 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0, 101 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1, 102 /* extra HW stats for specific network interface */ 103 ENA_ADMIN_GET_STATS_TYPE_ENI = 2, 104 /* extra HW stats for ENA SRD */ 105 ENA_ADMIN_GET_STATS_TYPE_ENA_SRD = 3, 106 }; 107 108 enum ena_admin_get_stats_scope { 109 ENA_ADMIN_SPECIFIC_QUEUE = 0, 110 ENA_ADMIN_ETH_TRAFFIC = 1, 111 }; 112 113 /* ENA SRD configuration for ENI */ 114 enum ena_admin_ena_srd_flags { 115 /* Feature enabled */ 116 ENA_ADMIN_ENA_SRD_ENABLED = BIT(0), 117 /* UDP support enabled */ 118 ENA_ADMIN_ENA_SRD_UDP_ENABLED = BIT(1), 119 /* Bypass Rx UDP ordering */ 120 ENA_ADMIN_ENA_SRD_UDP_ORDERING_BYPASS_ENABLED = BIT(2), 121 }; 122 123 struct ena_admin_aq_common_desc { 124 /* 11:0 : command_id 125 * 15:12 : reserved12 126 */ 127 u16 command_id; 128 129 /* as appears in ena_admin_aq_opcode */ 130 u8 opcode; 131 132 /* 0 : phase 133 * 1 : ctrl_data - control buffer address valid 134 * 2 : ctrl_data_indirect - control buffer address 135 * points to list of pages with addresses of control 136 * buffers 137 * 7:3 : reserved3 138 */ 139 u8 flags; 140 }; 141 142 /* used in ena_admin_aq_entry. Can point directly to control data, or to a 143 * page list chunk. Used also at the end of indirect mode page list chunks, 144 * for chaining. 145 */ 146 struct ena_admin_ctrl_buff_info { 147 u32 length; 148 149 struct ena_common_mem_addr address; 150 }; 151 152 struct ena_admin_sq { 153 u16 sq_idx; 154 155 /* 4:0 : reserved 156 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx 157 */ 158 u8 sq_identity; 159 160 u8 reserved1; 161 }; 162 163 struct ena_admin_aq_entry { 164 struct ena_admin_aq_common_desc aq_common_descriptor; 165 166 union { 167 u32 inline_data_w1[3]; 168 169 struct ena_admin_ctrl_buff_info control_buffer; 170 } u; 171 172 u32 inline_data_w4[12]; 173 }; 174 175 struct ena_admin_acq_common_desc { 176 /* command identifier to associate it with the aq descriptor 177 * 11:0 : command_id 178 * 15:12 : reserved12 179 */ 180 u16 command; 181 182 u8 status; 183 184 /* 0 : phase 185 * 7:1 : reserved1 186 */ 187 u8 flags; 188 189 u16 extended_status; 190 191 /* indicates to the driver which AQ entry has been consumed by the 192 * device and could be reused 193 */ 194 u16 sq_head_indx; 195 }; 196 197 struct ena_admin_acq_entry { 198 struct ena_admin_acq_common_desc acq_common_descriptor; 199 200 u32 response_specific_data[14]; 201 }; 202 203 struct ena_admin_aq_create_sq_cmd { 204 struct ena_admin_aq_common_desc aq_common_descriptor; 205 206 /* 4:0 : reserved0_w1 207 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx 208 */ 209 u8 sq_identity; 210 211 u8 reserved8_w1; 212 213 /* 3:0 : placement_policy - Describing where the SQ 214 * descriptor ring and the SQ packet headers reside: 215 * 0x1 - descriptors and headers are in OS memory, 216 * 0x3 - descriptors and headers in device memory 217 * (a.k.a Low Latency Queue) 218 * 6:4 : completion_policy - Describing what policy 219 * to use for generation completion entry (cqe) in 220 * the CQ associated with this SQ: 0x0 - cqe for each 221 * sq descriptor, 0x1 - cqe upon request in sq 222 * descriptor, 0x2 - current queue head pointer is 223 * updated in OS memory upon sq descriptor request 224 * 0x3 - current queue head pointer is updated in OS 225 * memory for each sq descriptor 226 * 7 : reserved15_w1 227 */ 228 u8 sq_caps_2; 229 230 /* 0 : is_physically_contiguous - Described if the 231 * queue ring memory is allocated in physical 232 * contiguous pages or split. 233 * 7:1 : reserved17_w1 234 */ 235 u8 sq_caps_3; 236 237 /* associated completion queue id. This CQ must be created prior to SQ 238 * creation 239 */ 240 u16 cq_idx; 241 242 /* submission queue depth in entries */ 243 u16 sq_depth; 244 245 /* SQ physical base address in OS memory. This field should not be 246 * used for Low Latency queues. Has to be page aligned. 247 */ 248 struct ena_common_mem_addr sq_ba; 249 250 /* specifies queue head writeback location in OS memory. Valid if 251 * completion_policy is set to completion_policy_head_on_demand or 252 * completion_policy_head. Has to be cache aligned 253 */ 254 struct ena_common_mem_addr sq_head_writeback; 255 256 u32 reserved0_w7; 257 258 u32 reserved0_w8; 259 }; 260 261 enum ena_admin_sq_direction { 262 ENA_ADMIN_SQ_DIRECTION_TX = 1, 263 ENA_ADMIN_SQ_DIRECTION_RX = 2, 264 }; 265 266 struct ena_admin_acq_create_sq_resp_desc { 267 struct ena_admin_acq_common_desc acq_common_desc; 268 269 u16 sq_idx; 270 271 u16 reserved; 272 273 /* queue doorbell address as an offset to PCIe MMIO REG BAR */ 274 u32 sq_doorbell_offset; 275 276 /* low latency queue ring base address as an offset to PCIe MMIO 277 * LLQ_MEM BAR 278 */ 279 u32 llq_descriptors_offset; 280 281 /* low latency queue headers' memory as an offset to PCIe MMIO 282 * LLQ_MEM BAR 283 */ 284 u32 llq_headers_offset; 285 }; 286 287 struct ena_admin_aq_destroy_sq_cmd { 288 struct ena_admin_aq_common_desc aq_common_descriptor; 289 290 struct ena_admin_sq sq; 291 }; 292 293 struct ena_admin_acq_destroy_sq_resp_desc { 294 struct ena_admin_acq_common_desc acq_common_desc; 295 }; 296 297 struct ena_admin_aq_create_cq_cmd { 298 struct ena_admin_aq_common_desc aq_common_descriptor; 299 300 /* 4:0 : reserved5 301 * 5 : interrupt_mode_enabled - if set, cq operates 302 * in interrupt mode, otherwise - polling 303 * 7:6 : reserved6 304 */ 305 u8 cq_caps_1; 306 307 /* 4:0 : cq_entry_size_words - size of CQ entry in 308 * 32-bit words, valid values: 4, 8. 309 * 7:5 : reserved7 310 */ 311 u8 cq_caps_2; 312 313 /* completion queue depth in # of entries. must be power of 2 */ 314 u16 cq_depth; 315 316 /* msix vector assigned to this cq */ 317 u32 msix_vector; 318 319 /* cq physical base address in OS memory. CQ must be physically 320 * contiguous 321 */ 322 struct ena_common_mem_addr cq_ba; 323 }; 324 325 struct ena_admin_acq_create_cq_resp_desc { 326 struct ena_admin_acq_common_desc acq_common_desc; 327 328 u16 cq_idx; 329 330 /* actual cq depth in number of entries */ 331 u16 cq_actual_depth; 332 333 u32 numa_node_register_offset; 334 335 u32 cq_head_db_register_offset; 336 337 u32 cq_interrupt_unmask_register_offset; 338 }; 339 340 struct ena_admin_aq_destroy_cq_cmd { 341 struct ena_admin_aq_common_desc aq_common_descriptor; 342 343 u16 cq_idx; 344 345 u16 reserved1; 346 }; 347 348 struct ena_admin_acq_destroy_cq_resp_desc { 349 struct ena_admin_acq_common_desc acq_common_desc; 350 }; 351 352 /* ENA AQ Get Statistics command. Extended statistics are placed in control 353 * buffer pointed by AQ entry 354 */ 355 struct ena_admin_aq_get_stats_cmd { 356 struct ena_admin_aq_common_desc aq_common_descriptor; 357 358 union { 359 /* command specific inline data */ 360 u32 inline_data_w1[3]; 361 362 struct ena_admin_ctrl_buff_info control_buffer; 363 } u; 364 365 /* stats type as defined in enum ena_admin_get_stats_type */ 366 u8 type; 367 368 /* stats scope defined in enum ena_admin_get_stats_scope */ 369 u8 scope; 370 371 u16 reserved3; 372 373 /* queue id. used when scope is specific_queue */ 374 u16 queue_idx; 375 376 /* device id, value 0xFFFF means mine. only privileged device can get 377 * stats of other device 378 */ 379 u16 device_id; 380 }; 381 382 /* Basic Statistics Command. */ 383 struct ena_admin_basic_stats { 384 u32 tx_bytes_low; 385 386 u32 tx_bytes_high; 387 388 u32 tx_pkts_low; 389 390 u32 tx_pkts_high; 391 392 u32 rx_bytes_low; 393 394 u32 rx_bytes_high; 395 396 u32 rx_pkts_low; 397 398 u32 rx_pkts_high; 399 400 u32 rx_drops_low; 401 402 u32 rx_drops_high; 403 404 u32 tx_drops_low; 405 406 u32 tx_drops_high; 407 }; 408 409 /* ENI Statistics Command. */ 410 struct ena_admin_eni_stats { 411 /* The number of packets shaped due to inbound aggregate BW 412 * allowance being exceeded 413 */ 414 u64 bw_in_allowance_exceeded; 415 416 /* The number of packets shaped due to outbound aggregate BW 417 * allowance being exceeded 418 */ 419 u64 bw_out_allowance_exceeded; 420 421 /* The number of packets shaped due to PPS allowance being exceeded */ 422 u64 pps_allowance_exceeded; 423 424 /* The number of packets shaped due to connection tracking 425 * allowance being exceeded and leading to failure in establishment 426 * of new connections 427 */ 428 u64 conntrack_allowance_exceeded; 429 430 /* The number of packets shaped due to linklocal packet rate 431 * allowance being exceeded 432 */ 433 u64 linklocal_allowance_exceeded; 434 }; 435 436 struct ena_admin_ena_srd_stats { 437 /* Number of packets transmitted over ENA SRD */ 438 u64 ena_srd_tx_pkts; 439 440 /* Number of packets transmitted or could have been 441 * transmitted over ENA SRD 442 */ 443 u64 ena_srd_eligible_tx_pkts; 444 445 /* Number of packets received over ENA SRD */ 446 u64 ena_srd_rx_pkts; 447 448 /* Percentage of the ENA SRD resources that is in use */ 449 u64 ena_srd_resource_utilization; 450 }; 451 452 /* ENA SRD Statistics Command */ 453 struct ena_admin_ena_srd_info { 454 /* ENA SRD configuration bitmap. See ena_admin_ena_srd_flags for 455 * details 456 */ 457 u64 flags; 458 459 struct ena_admin_ena_srd_stats ena_srd_stats; 460 }; 461 462 struct ena_admin_acq_get_stats_resp { 463 struct ena_admin_acq_common_desc acq_common_desc; 464 465 union { 466 u64 raw[7]; 467 468 struct ena_admin_basic_stats basic_stats; 469 470 struct ena_admin_eni_stats eni_stats; 471 472 struct ena_admin_ena_srd_info ena_srd_info; 473 } u; 474 }; 475 476 struct ena_admin_get_set_feature_common_desc { 477 /* 1:0 : select - 0x1 - current value; 0x3 - default 478 * value 479 * 7:3 : reserved3 480 */ 481 u8 flags; 482 483 /* as appears in ena_admin_aq_feature_id */ 484 u8 feature_id; 485 486 /* The driver specifies the max feature version it supports and the 487 * device responds with the currently supported feature version. The 488 * field is zero based 489 */ 490 u8 feature_version; 491 492 u8 reserved8; 493 }; 494 495 struct ena_admin_device_attr_feature_desc { 496 u32 impl_id; 497 498 u32 device_version; 499 500 /* bitmap of ena_admin_aq_feature_id, which represents supported 501 * subcommands for the set/get feature admin commands. 502 */ 503 u32 supported_features; 504 505 /* bitmap of ena_admin_aq_caps_id, which represents device 506 * capabilities. 507 */ 508 u32 capabilities; 509 510 /* Indicates how many bits are used physical address access. */ 511 u32 phys_addr_width; 512 513 /* Indicates how many bits are used virtual address access. */ 514 u32 virt_addr_width; 515 516 /* unicast MAC address (in Network byte order) */ 517 u8 mac_addr[6]; 518 519 u8 reserved7[2]; 520 521 u32 max_mtu; 522 }; 523 524 enum ena_admin_llq_header_location { 525 /* header is in descriptor list */ 526 ENA_ADMIN_INLINE_HEADER = 1, 527 /* header in a separate ring, implies 16B descriptor list entry */ 528 ENA_ADMIN_HEADER_RING = 2, 529 }; 530 531 enum ena_admin_llq_ring_entry_size { 532 ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1, 533 ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2, 534 ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4, 535 }; 536 537 enum ena_admin_llq_num_descs_before_header { 538 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0, 539 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1, 540 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2, 541 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4, 542 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8, 543 }; 544 545 /* packet descriptor list entry always starts with one or more descriptors, 546 * followed by a header. The rest of the descriptors are located in the 547 * beginning of the subsequent entry. Stride refers to how the rest of the 548 * descriptors are placed. This field is relevant only for inline header 549 * mode 550 */ 551 enum ena_admin_llq_stride_ctrl { 552 ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1, 553 ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2, 554 }; 555 556 enum ena_admin_accel_mode_feat { 557 ENA_ADMIN_DISABLE_META_CACHING = 0, 558 ENA_ADMIN_LIMIT_TX_BURST = 1, 559 }; 560 561 struct ena_admin_accel_mode_get { 562 /* bit field of enum ena_admin_accel_mode_feat */ 563 u16 supported_flags; 564 565 /* maximum burst size between two doorbells. The size is in bytes */ 566 u16 max_tx_burst_size; 567 }; 568 569 struct ena_admin_accel_mode_set { 570 /* bit field of enum ena_admin_accel_mode_feat */ 571 u16 enabled_flags; 572 573 u16 reserved; 574 }; 575 576 struct ena_admin_accel_mode_req { 577 union { 578 u32 raw[2]; 579 580 struct ena_admin_accel_mode_get get; 581 582 struct ena_admin_accel_mode_set set; 583 } u; 584 }; 585 586 struct ena_admin_feature_llq_desc { 587 u32 max_llq_num; 588 589 u32 max_llq_depth; 590 591 /* specify the header locations the device supports. bitfield of enum 592 * ena_admin_llq_header_location. 593 */ 594 u16 header_location_ctrl_supported; 595 596 /* the header location the driver selected to use. */ 597 u16 header_location_ctrl_enabled; 598 599 /* if inline header is specified - this is the size of descriptor list 600 * entry. If header in a separate ring is specified - this is the size 601 * of header ring entry. bitfield of enum ena_admin_llq_ring_entry_size. 602 * specify the entry sizes the device supports 603 */ 604 u16 entry_size_ctrl_supported; 605 606 /* the entry size the driver selected to use. */ 607 u16 entry_size_ctrl_enabled; 608 609 /* valid only if inline header is specified. First entry associated with 610 * the packet includes descriptors and header. Rest of the entries 611 * occupied by descriptors. This parameter defines the max number of 612 * descriptors precedding the header in the first entry. The field is 613 * bitfield of enum ena_admin_llq_num_descs_before_header and specify 614 * the values the device supports 615 */ 616 u16 desc_num_before_header_supported; 617 618 /* the desire field the driver selected to use */ 619 u16 desc_num_before_header_enabled; 620 621 /* valid only if inline was chosen. bitfield of enum 622 * ena_admin_llq_stride_ctrl 623 */ 624 u16 descriptors_stride_ctrl_supported; 625 626 /* the stride control the driver selected to use */ 627 u16 descriptors_stride_ctrl_enabled; 628 629 /* reserved */ 630 u32 reserved1; 631 632 /* accelerated low latency queues requirement. driver needs to 633 * support those requirements in order to use accelerated llq 634 */ 635 struct ena_admin_accel_mode_req accel_mode; 636 }; 637 638 struct ena_admin_queue_ext_feature_fields { 639 u32 max_tx_sq_num; 640 641 u32 max_tx_cq_num; 642 643 u32 max_rx_sq_num; 644 645 u32 max_rx_cq_num; 646 647 u32 max_tx_sq_depth; 648 649 u32 max_tx_cq_depth; 650 651 u32 max_rx_sq_depth; 652 653 u32 max_rx_cq_depth; 654 655 u32 max_tx_header_size; 656 657 /* Maximum Descriptors number, including meta descriptor, allowed for a 658 * single Tx packet 659 */ 660 u16 max_per_packet_tx_descs; 661 662 /* Maximum Descriptors number allowed for a single Rx packet */ 663 u16 max_per_packet_rx_descs; 664 }; 665 666 struct ena_admin_queue_feature_desc { 667 u32 max_sq_num; 668 669 u32 max_sq_depth; 670 671 u32 max_cq_num; 672 673 u32 max_cq_depth; 674 675 u32 max_legacy_llq_num; 676 677 u32 max_legacy_llq_depth; 678 679 u32 max_header_size; 680 681 /* Maximum Descriptors number, including meta descriptor, allowed for a 682 * single Tx packet 683 */ 684 u16 max_packet_tx_descs; 685 686 /* Maximum Descriptors number allowed for a single Rx packet */ 687 u16 max_packet_rx_descs; 688 }; 689 690 struct ena_admin_set_feature_mtu_desc { 691 /* exclude L2 */ 692 u32 mtu; 693 }; 694 695 struct ena_admin_set_feature_host_attr_desc { 696 /* host OS info base address in OS memory. host info is 4KB of 697 * physically contiguous 698 */ 699 struct ena_common_mem_addr os_info_ba; 700 701 /* host debug area base address in OS memory. debug area must be 702 * physically contiguous 703 */ 704 struct ena_common_mem_addr debug_ba; 705 706 /* debug area size */ 707 u32 debug_area_size; 708 }; 709 710 struct ena_admin_feature_intr_moder_desc { 711 /* interrupt delay granularity in usec */ 712 u16 intr_delay_resolution; 713 714 u16 reserved; 715 }; 716 717 struct ena_admin_get_feature_link_desc { 718 /* Link speed in Mb */ 719 u32 speed; 720 721 /* bit field of enum ena_admin_link types */ 722 u32 supported; 723 724 /* 0 : autoneg 725 * 1 : duplex - Full Duplex 726 * 31:2 : reserved2 727 */ 728 u32 flags; 729 }; 730 731 struct ena_admin_feature_aenq_desc { 732 /* bitmask for AENQ groups the device can report */ 733 u32 supported_groups; 734 735 /* bitmask for AENQ groups to report */ 736 u32 enabled_groups; 737 }; 738 739 struct ena_admin_feature_offload_desc { 740 /* 0 : TX_L3_csum_ipv4 741 * 1 : TX_L4_ipv4_csum_part - The checksum field 742 * should be initialized with pseudo header checksum 743 * 2 : TX_L4_ipv4_csum_full 744 * 3 : TX_L4_ipv6_csum_part - The checksum field 745 * should be initialized with pseudo header checksum 746 * 4 : TX_L4_ipv6_csum_full 747 * 5 : tso_ipv4 748 * 6 : tso_ipv6 749 * 7 : tso_ecn 750 */ 751 u32 tx; 752 753 /* Receive side supported stateless offload 754 * 0 : RX_L3_csum_ipv4 - IPv4 checksum 755 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum 756 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum 757 * 3 : RX_hash - Hash calculation 758 */ 759 u32 rx_supported; 760 761 u32 rx_enabled; 762 }; 763 764 enum ena_admin_hash_functions { 765 ENA_ADMIN_TOEPLITZ = 1, 766 ENA_ADMIN_CRC32 = 2, 767 }; 768 769 struct ena_admin_feature_rss_flow_hash_control { 770 u32 key_parts; 771 772 u32 reserved; 773 774 u32 key[ENA_ADMIN_RSS_KEY_PARTS]; 775 }; 776 777 struct ena_admin_feature_rss_flow_hash_function { 778 /* 7:0 : funcs - bitmask of ena_admin_hash_functions */ 779 u32 supported_func; 780 781 /* 7:0 : selected_func - bitmask of 782 * ena_admin_hash_functions 783 */ 784 u32 selected_func; 785 786 /* initial value */ 787 u32 init_val; 788 }; 789 790 /* RSS flow hash protocols */ 791 enum ena_admin_flow_hash_proto { 792 ENA_ADMIN_RSS_TCP4 = 0, 793 ENA_ADMIN_RSS_UDP4 = 1, 794 ENA_ADMIN_RSS_TCP6 = 2, 795 ENA_ADMIN_RSS_UDP6 = 3, 796 ENA_ADMIN_RSS_IP4 = 4, 797 ENA_ADMIN_RSS_IP6 = 5, 798 ENA_ADMIN_RSS_IP4_FRAG = 6, 799 ENA_ADMIN_RSS_NOT_IP = 7, 800 /* TCPv6 with extension header */ 801 ENA_ADMIN_RSS_TCP6_EX = 8, 802 /* IPv6 with extension header */ 803 ENA_ADMIN_RSS_IP6_EX = 9, 804 ENA_ADMIN_RSS_PROTO_NUM = 16, 805 }; 806 807 /* RSS flow hash fields */ 808 enum ena_admin_flow_hash_fields { 809 /* Ethernet Dest Addr */ 810 ENA_ADMIN_RSS_L2_DA = BIT(0), 811 /* Ethernet Src Addr */ 812 ENA_ADMIN_RSS_L2_SA = BIT(1), 813 /* ipv4/6 Dest Addr */ 814 ENA_ADMIN_RSS_L3_DA = BIT(2), 815 /* ipv4/6 Src Addr */ 816 ENA_ADMIN_RSS_L3_SA = BIT(3), 817 /* tcp/udp Dest Port */ 818 ENA_ADMIN_RSS_L4_DP = BIT(4), 819 /* tcp/udp Src Port */ 820 ENA_ADMIN_RSS_L4_SP = BIT(5), 821 }; 822 823 struct ena_admin_proto_input { 824 /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */ 825 u16 fields; 826 827 u16 reserved2; 828 }; 829 830 struct ena_admin_feature_rss_hash_control { 831 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM]; 832 833 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM]; 834 835 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM]; 836 837 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM]; 838 }; 839 840 struct ena_admin_feature_rss_flow_hash_input { 841 /* supported hash input sorting 842 * 1 : L3_sort - support swap L3 addresses if DA is 843 * smaller than SA 844 * 2 : L4_sort - support swap L4 ports if DP smaller 845 * SP 846 */ 847 u16 supported_input_sort; 848 849 /* enabled hash input sorting 850 * 1 : enable_L3_sort - enable swap L3 addresses if 851 * DA smaller than SA 852 * 2 : enable_L4_sort - enable swap L4 ports if DP 853 * smaller than SP 854 */ 855 u16 enabled_input_sort; 856 }; 857 858 enum ena_admin_os_type { 859 ENA_ADMIN_OS_LINUX = 1, 860 ENA_ADMIN_OS_WIN = 2, 861 ENA_ADMIN_OS_DPDK = 3, 862 ENA_ADMIN_OS_FREEBSD = 4, 863 ENA_ADMIN_OS_IPXE = 5, 864 ENA_ADMIN_OS_ESXI = 6, 865 ENA_ADMIN_OS_GROUPS_NUM = 6, 866 }; 867 868 struct ena_admin_host_info { 869 /* defined in enum ena_admin_os_type */ 870 u32 os_type; 871 872 /* os distribution string format */ 873 u8 os_dist_str[128]; 874 875 /* OS distribution numeric format */ 876 u32 os_dist; 877 878 /* kernel version string format */ 879 u8 kernel_ver_str[32]; 880 881 /* Kernel version numeric format */ 882 u32 kernel_ver; 883 884 /* 7:0 : major 885 * 15:8 : minor 886 * 23:16 : sub_minor 887 * 31:24 : module_type 888 */ 889 u32 driver_version; 890 891 /* features bitmap */ 892 u32 supported_network_features[2]; 893 894 /* ENA spec version of driver */ 895 u16 ena_spec_version; 896 897 /* ENA device's Bus, Device and Function 898 * 2:0 : function 899 * 7:3 : device 900 * 15:8 : bus 901 */ 902 u16 bdf; 903 904 /* Number of CPUs */ 905 u16 num_cpus; 906 907 u16 reserved; 908 909 /* 0 : reserved 910 * 1 : rx_offset 911 * 2 : interrupt_moderation 912 * 3 : rx_buf_mirroring 913 * 4 : rss_configurable_function_key 914 * 5 : reserved 915 * 6 : rx_page_reuse 916 * 31:7 : reserved 917 */ 918 u32 driver_supported_features; 919 }; 920 921 struct ena_admin_rss_ind_table_entry { 922 u16 cq_idx; 923 924 u16 reserved; 925 }; 926 927 struct ena_admin_feature_rss_ind_table { 928 /* min supported table size (2^min_size) */ 929 u16 min_size; 930 931 /* max supported table size (2^max_size) */ 932 u16 max_size; 933 934 /* table size (2^size) */ 935 u16 size; 936 937 u16 reserved; 938 939 /* index of the inline entry. 0xFFFFFFFF means invalid */ 940 u32 inline_index; 941 942 /* used for updating single entry, ignored when setting the entire 943 * table through the control buffer. 944 */ 945 struct ena_admin_rss_ind_table_entry inline_entry; 946 }; 947 948 /* When hint value is 0, driver should use it's own predefined value */ 949 struct ena_admin_ena_hw_hints { 950 /* value in ms */ 951 u16 mmio_read_timeout; 952 953 /* value in ms */ 954 u16 driver_watchdog_timeout; 955 956 /* Per packet tx completion timeout. value in ms */ 957 u16 missing_tx_completion_timeout; 958 959 u16 missed_tx_completion_count_threshold_to_reset; 960 961 /* value in ms */ 962 u16 admin_completion_tx_timeout; 963 964 u16 netdev_wd_timeout; 965 966 u16 max_tx_sgl_size; 967 968 u16 max_rx_sgl_size; 969 970 u16 reserved[8]; 971 }; 972 973 struct ena_admin_get_feat_cmd { 974 struct ena_admin_aq_common_desc aq_common_descriptor; 975 976 struct ena_admin_ctrl_buff_info control_buffer; 977 978 struct ena_admin_get_set_feature_common_desc feat_common; 979 980 u32 raw[11]; 981 }; 982 983 struct ena_admin_queue_ext_feature_desc { 984 /* version */ 985 u8 version; 986 987 u8 reserved1[3]; 988 989 union { 990 struct ena_admin_queue_ext_feature_fields max_queue_ext; 991 992 u32 raw[10]; 993 }; 994 }; 995 996 struct ena_admin_get_feat_resp { 997 struct ena_admin_acq_common_desc acq_common_desc; 998 999 union { 1000 u32 raw[14]; 1001 1002 struct ena_admin_device_attr_feature_desc dev_attr; 1003 1004 struct ena_admin_feature_llq_desc llq; 1005 1006 struct ena_admin_queue_feature_desc max_queue; 1007 1008 struct ena_admin_queue_ext_feature_desc max_queue_ext; 1009 1010 struct ena_admin_feature_aenq_desc aenq; 1011 1012 struct ena_admin_get_feature_link_desc link; 1013 1014 struct ena_admin_feature_offload_desc offload; 1015 1016 struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 1017 1018 struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 1019 1020 struct ena_admin_feature_rss_ind_table ind_table; 1021 1022 struct ena_admin_feature_intr_moder_desc intr_moderation; 1023 1024 struct ena_admin_ena_hw_hints hw_hints; 1025 } u; 1026 }; 1027 1028 struct ena_admin_set_feat_cmd { 1029 struct ena_admin_aq_common_desc aq_common_descriptor; 1030 1031 struct ena_admin_ctrl_buff_info control_buffer; 1032 1033 struct ena_admin_get_set_feature_common_desc feat_common; 1034 1035 union { 1036 u32 raw[11]; 1037 1038 /* mtu size */ 1039 struct ena_admin_set_feature_mtu_desc mtu; 1040 1041 /* host attributes */ 1042 struct ena_admin_set_feature_host_attr_desc host_attr; 1043 1044 /* AENQ configuration */ 1045 struct ena_admin_feature_aenq_desc aenq; 1046 1047 /* rss flow hash function */ 1048 struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 1049 1050 /* rss flow hash input */ 1051 struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 1052 1053 /* rss indirection table */ 1054 struct ena_admin_feature_rss_ind_table ind_table; 1055 1056 /* LLQ configuration */ 1057 struct ena_admin_feature_llq_desc llq; 1058 } u; 1059 }; 1060 1061 struct ena_admin_set_feat_resp { 1062 struct ena_admin_acq_common_desc acq_common_desc; 1063 1064 union { 1065 u32 raw[14]; 1066 } u; 1067 }; 1068 1069 struct ena_admin_aenq_common_desc { 1070 u16 group; 1071 1072 u16 syndrome; 1073 1074 /* 0 : phase 1075 * 7:1 : reserved - MBZ 1076 */ 1077 u8 flags; 1078 1079 u8 reserved1[3]; 1080 1081 u32 timestamp_low; 1082 1083 u32 timestamp_high; 1084 }; 1085 1086 /* asynchronous event notification groups */ 1087 enum ena_admin_aenq_group { 1088 ENA_ADMIN_LINK_CHANGE = 0, 1089 ENA_ADMIN_FATAL_ERROR = 1, 1090 ENA_ADMIN_WARNING = 2, 1091 ENA_ADMIN_NOTIFICATION = 3, 1092 ENA_ADMIN_KEEP_ALIVE = 4, 1093 ENA_ADMIN_AENQ_GROUPS_NUM = 5, 1094 }; 1095 1096 enum ena_admin_aenq_notification_syndrome { 1097 ENA_ADMIN_UPDATE_HINTS = 2, 1098 }; 1099 1100 struct ena_admin_aenq_entry { 1101 struct ena_admin_aenq_common_desc aenq_common_desc; 1102 1103 /* command specific inline data */ 1104 u32 inline_data_w4[12]; 1105 }; 1106 1107 struct ena_admin_aenq_link_change_desc { 1108 struct ena_admin_aenq_common_desc aenq_common_desc; 1109 1110 /* 0 : link_status */ 1111 u32 flags; 1112 }; 1113 1114 struct ena_admin_aenq_keep_alive_desc { 1115 struct ena_admin_aenq_common_desc aenq_common_desc; 1116 1117 u32 rx_drops_low; 1118 1119 u32 rx_drops_high; 1120 1121 u32 tx_drops_low; 1122 1123 u32 tx_drops_high; 1124 }; 1125 1126 struct ena_admin_ena_mmio_req_read_less_resp { 1127 u16 req_id; 1128 1129 u16 reg_off; 1130 1131 /* value is valid when poll is cleared */ 1132 u32 reg_val; 1133 }; 1134 1135 /* aq_common_desc */ 1136 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 1137 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0) 1138 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1 1139 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1) 1140 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2 1141 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2) 1142 1143 /* sq */ 1144 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5 1145 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5) 1146 1147 /* acq_common_desc */ 1148 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 1149 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0) 1150 1151 /* aq_create_sq_cmd */ 1152 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5 1153 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5) 1154 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0) 1155 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4 1156 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4) 1157 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0) 1158 1159 /* aq_create_cq_cmd */ 1160 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5 1161 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5) 1162 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) 1163 1164 /* get_set_feature_common_desc */ 1165 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0) 1166 1167 /* get_feature_link_desc */ 1168 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0) 1169 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1 1170 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1) 1171 1172 /* feature_offload_desc */ 1173 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0) 1174 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1 1175 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1) 1176 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2 1177 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2) 1178 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3 1179 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3) 1180 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4 1181 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4) 1182 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5 1183 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5) 1184 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6 1185 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6) 1186 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7 1187 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7) 1188 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0) 1189 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1 1190 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1) 1191 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2 1192 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2) 1193 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3 1194 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3) 1195 1196 /* feature_rss_flow_hash_function */ 1197 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0) 1198 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0) 1199 1200 /* feature_rss_flow_hash_input */ 1201 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1 1202 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1) 1203 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2 1204 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2) 1205 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1 1206 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1) 1207 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2 1208 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2) 1209 1210 /* host_info */ 1211 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0) 1212 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8 1213 #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8) 1214 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16 1215 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16) 1216 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24 1217 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24) 1218 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0) 1219 #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3 1220 #define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3) 1221 #define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8 1222 #define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8) 1223 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 1 1224 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1) 1225 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2 1226 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2) 1227 #define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT 3 1228 #define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3) 1229 #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 4 1230 #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4) 1231 #define ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_SHIFT 6 1232 #define ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_MASK BIT(6) 1233 1234 /* aenq_common_desc */ 1235 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0) 1236 1237 /* aenq_link_change_desc */ 1238 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0) 1239 1240 #endif /* _ENA_ADMIN_H_ */ 1241