1 /* 2 * Copyright 2015 - 2016 Amazon.com, Inc. or its affiliates. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef _ENA_ADMIN_H_ 33 #define _ENA_ADMIN_H_ 34 35 #define ENA_ADMIN_EXTRA_PROPERTIES_STRING_LEN 32 36 #define ENA_ADMIN_EXTRA_PROPERTIES_COUNT 32 37 38 enum ena_admin_aq_opcode { 39 ENA_ADMIN_CREATE_SQ = 1, 40 ENA_ADMIN_DESTROY_SQ = 2, 41 ENA_ADMIN_CREATE_CQ = 3, 42 ENA_ADMIN_DESTROY_CQ = 4, 43 ENA_ADMIN_GET_FEATURE = 8, 44 ENA_ADMIN_SET_FEATURE = 9, 45 ENA_ADMIN_GET_STATS = 11, 46 }; 47 48 enum ena_admin_aq_completion_status { 49 ENA_ADMIN_SUCCESS = 0, 50 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1, 51 ENA_ADMIN_BAD_OPCODE = 2, 52 ENA_ADMIN_UNSUPPORTED_OPCODE = 3, 53 ENA_ADMIN_MALFORMED_REQUEST = 4, 54 /* Additional status is provided in ACQ entry extended_status */ 55 ENA_ADMIN_ILLEGAL_PARAMETER = 5, 56 ENA_ADMIN_UNKNOWN_ERROR = 6, 57 ENA_ADMIN_RESOURCE_BUSY = 7, 58 }; 59 60 enum ena_admin_aq_feature_id { 61 ENA_ADMIN_DEVICE_ATTRIBUTES = 1, 62 ENA_ADMIN_MAX_QUEUES_NUM = 2, 63 ENA_ADMIN_HW_HINTS = 3, 64 ENA_ADMIN_LLQ = 4, 65 ENA_ADMIN_EXTRA_PROPERTIES_STRINGS = 5, 66 ENA_ADMIN_EXTRA_PROPERTIES_FLAGS = 6, 67 ENA_ADMIN_MAX_QUEUES_EXT = 7, 68 ENA_ADMIN_RSS_HASH_FUNCTION = 10, 69 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11, 70 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12, 71 ENA_ADMIN_MTU = 14, 72 ENA_ADMIN_RSS_HASH_INPUT = 18, 73 ENA_ADMIN_INTERRUPT_MODERATION = 20, 74 ENA_ADMIN_AENQ_CONFIG = 26, 75 ENA_ADMIN_LINK_CONFIG = 27, 76 ENA_ADMIN_HOST_ATTR_CONFIG = 28, 77 ENA_ADMIN_FEATURES_OPCODE_NUM = 32, 78 }; 79 80 enum ena_admin_placement_policy_type { 81 /* descriptors and headers are in host memory */ 82 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1, 83 /* descriptors and headers are in device memory (a.k.a Low Latency 84 * Queue) 85 */ 86 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3, 87 }; 88 89 enum ena_admin_link_types { 90 ENA_ADMIN_LINK_SPEED_1G = 0x1, 91 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2, 92 ENA_ADMIN_LINK_SPEED_5G = 0x4, 93 ENA_ADMIN_LINK_SPEED_10G = 0x8, 94 ENA_ADMIN_LINK_SPEED_25G = 0x10, 95 ENA_ADMIN_LINK_SPEED_40G = 0x20, 96 ENA_ADMIN_LINK_SPEED_50G = 0x40, 97 ENA_ADMIN_LINK_SPEED_100G = 0x80, 98 ENA_ADMIN_LINK_SPEED_200G = 0x100, 99 ENA_ADMIN_LINK_SPEED_400G = 0x200, 100 }; 101 102 enum ena_admin_completion_policy_type { 103 /* completion queue entry for each sq descriptor */ 104 ENA_ADMIN_COMPLETION_POLICY_DESC = 0, 105 /* completion queue entry upon request in sq descriptor */ 106 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1, 107 /* current queue head pointer is updated in OS memory upon sq 108 * descriptor request 109 */ 110 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2, 111 /* current queue head pointer is updated in OS memory for each sq 112 * descriptor 113 */ 114 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3, 115 }; 116 117 /* basic stats return ena_admin_basic_stats while extanded stats return a 118 * buffer (string format) with additional statistics per queue and per 119 * device id 120 */ 121 enum ena_admin_get_stats_type { 122 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0, 123 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1, 124 }; 125 126 enum ena_admin_get_stats_scope { 127 ENA_ADMIN_SPECIFIC_QUEUE = 0, 128 ENA_ADMIN_ETH_TRAFFIC = 1, 129 }; 130 131 struct ena_admin_aq_common_desc { 132 /* 11:0 : command_id 133 * 15:12 : reserved12 134 */ 135 u16 command_id; 136 137 /* as appears in ena_admin_aq_opcode */ 138 u8 opcode; 139 140 /* 0 : phase 141 * 1 : ctrl_data - control buffer address valid 142 * 2 : ctrl_data_indirect - control buffer address 143 * points to list of pages with addresses of control 144 * buffers 145 * 7:3 : reserved3 146 */ 147 u8 flags; 148 }; 149 150 /* used in ena_admin_aq_entry. Can point directly to control data, or to a 151 * page list chunk. Used also at the end of indirect mode page list chunks, 152 * for chaining. 153 */ 154 struct ena_admin_ctrl_buff_info { 155 u32 length; 156 157 struct ena_common_mem_addr address; 158 }; 159 160 struct ena_admin_sq { 161 u16 sq_idx; 162 163 /* 4:0 : reserved 164 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx 165 */ 166 u8 sq_identity; 167 168 u8 reserved1; 169 }; 170 171 struct ena_admin_aq_entry { 172 struct ena_admin_aq_common_desc aq_common_descriptor; 173 174 union { 175 u32 inline_data_w1[3]; 176 177 struct ena_admin_ctrl_buff_info control_buffer; 178 } u; 179 180 u32 inline_data_w4[12]; 181 }; 182 183 struct ena_admin_acq_common_desc { 184 /* command identifier to associate it with the aq descriptor 185 * 11:0 : command_id 186 * 15:12 : reserved12 187 */ 188 u16 command; 189 190 u8 status; 191 192 /* 0 : phase 193 * 7:1 : reserved1 194 */ 195 u8 flags; 196 197 u16 extended_status; 198 199 /* indicates to the driver which AQ entry has been consumed by the 200 * device and could be reused 201 */ 202 u16 sq_head_indx; 203 }; 204 205 struct ena_admin_acq_entry { 206 struct ena_admin_acq_common_desc acq_common_descriptor; 207 208 u32 response_specific_data[14]; 209 }; 210 211 struct ena_admin_aq_create_sq_cmd { 212 struct ena_admin_aq_common_desc aq_common_descriptor; 213 214 /* 4:0 : reserved0_w1 215 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx 216 */ 217 u8 sq_identity; 218 219 u8 reserved8_w1; 220 221 /* 3:0 : placement_policy - Describing where the SQ 222 * descriptor ring and the SQ packet headers reside: 223 * 0x1 - descriptors and headers are in OS memory, 224 * 0x3 - descriptors and headers in device memory 225 * (a.k.a Low Latency Queue) 226 * 6:4 : completion_policy - Describing what policy 227 * to use for generation completion entry (cqe) in 228 * the CQ associated with this SQ: 0x0 - cqe for each 229 * sq descriptor, 0x1 - cqe upon request in sq 230 * descriptor, 0x2 - current queue head pointer is 231 * updated in OS memory upon sq descriptor request 232 * 0x3 - current queue head pointer is updated in OS 233 * memory for each sq descriptor 234 * 7 : reserved15_w1 235 */ 236 u8 sq_caps_2; 237 238 /* 0 : is_physically_contiguous - Described if the 239 * queue ring memory is allocated in physical 240 * contiguous pages or split. 241 * 7:1 : reserved17_w1 242 */ 243 u8 sq_caps_3; 244 245 /* associated completion queue id. This CQ must be created prior to 246 * SQ creation 247 */ 248 u16 cq_idx; 249 250 /* submission queue depth in entries */ 251 u16 sq_depth; 252 253 /* SQ physical base address in OS memory. This field should not be 254 * used for Low Latency queues. Has to be page aligned. 255 */ 256 struct ena_common_mem_addr sq_ba; 257 258 /* specifies queue head writeback location in OS memory. Valid if 259 * completion_policy is set to completion_policy_head_on_demand or 260 * completion_policy_head. Has to be cache aligned 261 */ 262 struct ena_common_mem_addr sq_head_writeback; 263 264 u32 reserved0_w7; 265 266 u32 reserved0_w8; 267 }; 268 269 enum ena_admin_sq_direction { 270 ENA_ADMIN_SQ_DIRECTION_TX = 1, 271 ENA_ADMIN_SQ_DIRECTION_RX = 2, 272 }; 273 274 struct ena_admin_acq_create_sq_resp_desc { 275 struct ena_admin_acq_common_desc acq_common_desc; 276 277 u16 sq_idx; 278 279 u16 reserved; 280 281 /* queue doorbell address as an offset to PCIe MMIO REG BAR */ 282 u32 sq_doorbell_offset; 283 284 /* low latency queue ring base address as an offset to PCIe MMIO 285 * LLQ_MEM BAR 286 */ 287 u32 llq_descriptors_offset; 288 289 /* low latency queue headers' memory as an offset to PCIe MMIO 290 * LLQ_MEM BAR 291 */ 292 u32 llq_headers_offset; 293 }; 294 295 struct ena_admin_aq_destroy_sq_cmd { 296 struct ena_admin_aq_common_desc aq_common_descriptor; 297 298 struct ena_admin_sq sq; 299 }; 300 301 struct ena_admin_acq_destroy_sq_resp_desc { 302 struct ena_admin_acq_common_desc acq_common_desc; 303 }; 304 305 struct ena_admin_aq_create_cq_cmd { 306 struct ena_admin_aq_common_desc aq_common_descriptor; 307 308 /* 4:0 : reserved5 309 * 5 : interrupt_mode_enabled - if set, cq operates 310 * in interrupt mode, otherwise - polling 311 * 7:6 : reserved6 312 */ 313 u8 cq_caps_1; 314 315 /* 4:0 : cq_entry_size_words - size of CQ entry in 316 * 32-bit words, valid values: 4, 8. 317 * 7:5 : reserved7 318 */ 319 u8 cq_caps_2; 320 321 /* completion queue depth in # of entries. must be power of 2 */ 322 u16 cq_depth; 323 324 /* msix vector assigned to this cq */ 325 u32 msix_vector; 326 327 /* cq physical base address in OS memory. CQ must be physically 328 * contiguous 329 */ 330 struct ena_common_mem_addr cq_ba; 331 }; 332 333 struct ena_admin_acq_create_cq_resp_desc { 334 struct ena_admin_acq_common_desc acq_common_desc; 335 336 u16 cq_idx; 337 338 /* actual cq depth in number of entries */ 339 u16 cq_actual_depth; 340 341 u32 numa_node_register_offset; 342 343 u32 cq_head_db_register_offset; 344 345 u32 cq_interrupt_unmask_register_offset; 346 }; 347 348 struct ena_admin_aq_destroy_cq_cmd { 349 struct ena_admin_aq_common_desc aq_common_descriptor; 350 351 u16 cq_idx; 352 353 u16 reserved1; 354 }; 355 356 struct ena_admin_acq_destroy_cq_resp_desc { 357 struct ena_admin_acq_common_desc acq_common_desc; 358 }; 359 360 /* ENA AQ Get Statistics command. Extended statistics are placed in control 361 * buffer pointed by AQ entry 362 */ 363 struct ena_admin_aq_get_stats_cmd { 364 struct ena_admin_aq_common_desc aq_common_descriptor; 365 366 union { 367 /* command specific inline data */ 368 u32 inline_data_w1[3]; 369 370 struct ena_admin_ctrl_buff_info control_buffer; 371 } u; 372 373 /* stats type as defined in enum ena_admin_get_stats_type */ 374 u8 type; 375 376 /* stats scope defined in enum ena_admin_get_stats_scope */ 377 u8 scope; 378 379 u16 reserved3; 380 381 /* queue id. used when scope is specific_queue */ 382 u16 queue_idx; 383 384 /* device id, value 0xFFFF means mine. only privileged device can get 385 * stats of other device 386 */ 387 u16 device_id; 388 }; 389 390 /* Basic Statistics Command. */ 391 struct ena_admin_basic_stats { 392 u32 tx_bytes_low; 393 394 u32 tx_bytes_high; 395 396 u32 tx_pkts_low; 397 398 u32 tx_pkts_high; 399 400 u32 rx_bytes_low; 401 402 u32 rx_bytes_high; 403 404 u32 rx_pkts_low; 405 406 u32 rx_pkts_high; 407 408 u32 rx_drops_low; 409 410 u32 rx_drops_high; 411 }; 412 413 struct ena_admin_acq_get_stats_resp { 414 struct ena_admin_acq_common_desc acq_common_desc; 415 416 struct ena_admin_basic_stats basic_stats; 417 }; 418 419 struct ena_admin_get_set_feature_common_desc { 420 /* 1:0 : select - 0x1 - current value; 0x3 - default 421 * value 422 * 7:3 : reserved3 423 */ 424 u8 flags; 425 426 /* as appears in ena_admin_aq_feature_id */ 427 u8 feature_id; 428 429 /* The driver specifies the max feature version it supports and the 430 * device responds with the currently supported feature version. The 431 * field is zero based 432 */ 433 u8 feature_version; 434 435 u8 reserved8; 436 }; 437 438 struct ena_admin_device_attr_feature_desc { 439 u32 impl_id; 440 441 u32 device_version; 442 443 /* bitmap of ena_admin_aq_feature_id */ 444 u32 supported_features; 445 446 u32 reserved3; 447 448 /* Indicates how many bits are used physical address access. */ 449 u32 phys_addr_width; 450 451 /* Indicates how many bits are used virtual address access. */ 452 u32 virt_addr_width; 453 454 /* unicast MAC address (in Network byte order) */ 455 u8 mac_addr[6]; 456 457 u8 reserved7[2]; 458 459 u32 max_mtu; 460 }; 461 462 enum ena_admin_llq_header_location { 463 /* header is in descriptor list */ 464 ENA_ADMIN_INLINE_HEADER = 1, 465 /* header in a separate ring, implies 16B descriptor list entry */ 466 ENA_ADMIN_HEADER_RING = 2, 467 }; 468 469 enum ena_admin_llq_ring_entry_size { 470 ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1, 471 ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2, 472 ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4, 473 }; 474 475 enum ena_admin_llq_num_descs_before_header { 476 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0, 477 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1, 478 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2, 479 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4, 480 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8, 481 }; 482 483 /* packet descriptor list entry always starts with one or more descriptors, 484 * followed by a header. The rest of the descriptors are located in the 485 * beginning of the subsequent entry. Stride refers to how the rest of the 486 * descriptors are placed. This field is relevant only for inline header 487 * mode 488 */ 489 enum ena_admin_llq_stride_ctrl { 490 ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1, 491 ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2, 492 }; 493 494 struct ena_admin_feature_llq_desc { 495 u32 max_llq_num; 496 497 u32 max_llq_depth; 498 499 /* specify the header locations the device supports. bitfield of 500 * enum ena_admin_llq_header_location. 501 */ 502 u16 header_location_ctrl_supported; 503 504 /* the header location the driver selected to use. */ 505 u16 header_location_ctrl_enabled; 506 507 /* if inline header is specified - this is the size of descriptor 508 * list entry. If header in a separate ring is specified - this is 509 * the size of header ring entry. bitfield of enum 510 * ena_admin_llq_ring_entry_size. specify the entry sizes the device 511 * supports 512 */ 513 u16 entry_size_ctrl_supported; 514 515 /* the entry size the driver selected to use. */ 516 u16 entry_size_ctrl_enabled; 517 518 /* valid only if inline header is specified. First entry associated 519 * with the packet includes descriptors and header. Rest of the 520 * entries occupied by descriptors. This parameter defines the max 521 * number of descriptors precedding the header in the first entry. 522 * The field is bitfield of enum 523 * ena_admin_llq_num_descs_before_header and specify the values the 524 * device supports 525 */ 526 u16 desc_num_before_header_supported; 527 528 /* the desire field the driver selected to use */ 529 u16 desc_num_before_header_enabled; 530 531 /* valid only if inline was chosen. bitfield of enum 532 * ena_admin_llq_stride_ctrl 533 */ 534 u16 descriptors_stride_ctrl_supported; 535 536 /* the stride control the driver selected to use */ 537 u16 descriptors_stride_ctrl_enabled; 538 539 /* Maximum size in bytes taken by llq entries in a single tx burst. 540 * Set to 0 when there is no such limit. 541 */ 542 u32 max_tx_burst_size; 543 }; 544 545 struct ena_admin_queue_ext_feature_fields { 546 u32 max_tx_sq_num; 547 548 u32 max_tx_cq_num; 549 550 u32 max_rx_sq_num; 551 552 u32 max_rx_cq_num; 553 554 u32 max_tx_sq_depth; 555 556 u32 max_tx_cq_depth; 557 558 u32 max_rx_sq_depth; 559 560 u32 max_rx_cq_depth; 561 562 u32 max_tx_header_size; 563 564 /* Maximum Descriptors number, including meta descriptor, allowed for 565 * a single Tx packet 566 */ 567 u16 max_per_packet_tx_descs; 568 569 /* Maximum Descriptors number allowed for a single Rx packet */ 570 u16 max_per_packet_rx_descs; 571 }; 572 573 struct ena_admin_queue_feature_desc { 574 u32 max_sq_num; 575 576 u32 max_sq_depth; 577 578 u32 max_cq_num; 579 580 u32 max_cq_depth; 581 582 u32 max_legacy_llq_num; 583 584 u32 max_legacy_llq_depth; 585 586 u32 max_header_size; 587 588 /* Maximum Descriptors number, including meta descriptor, allowed for 589 * a single Tx packet 590 */ 591 u16 max_packet_tx_descs; 592 593 /* Maximum Descriptors number allowed for a single Rx packet */ 594 u16 max_packet_rx_descs; 595 }; 596 597 struct ena_admin_set_feature_mtu_desc { 598 /* exclude L2 */ 599 u32 mtu; 600 }; 601 602 struct ena_admin_get_extra_properties_strings_desc { 603 u32 count; 604 }; 605 606 struct ena_admin_get_extra_properties_flags_desc { 607 u32 flags; 608 }; 609 610 struct ena_admin_set_feature_host_attr_desc { 611 /* host OS info base address in OS memory. host info is 4KB of 612 * physically contiguous 613 */ 614 struct ena_common_mem_addr os_info_ba; 615 616 /* host debug area base address in OS memory. debug area must be 617 * physically contiguous 618 */ 619 struct ena_common_mem_addr debug_ba; 620 621 /* debug area size */ 622 u32 debug_area_size; 623 }; 624 625 struct ena_admin_feature_intr_moder_desc { 626 /* interrupt delay granularity in usec */ 627 u16 intr_delay_resolution; 628 629 u16 reserved; 630 }; 631 632 struct ena_admin_get_feature_link_desc { 633 /* Link speed in Mb */ 634 u32 speed; 635 636 /* bit field of enum ena_admin_link types */ 637 u32 supported; 638 639 /* 0 : autoneg 640 * 1 : duplex - Full Duplex 641 * 31:2 : reserved2 642 */ 643 u32 flags; 644 }; 645 646 struct ena_admin_feature_aenq_desc { 647 /* bitmask for AENQ groups the device can report */ 648 u32 supported_groups; 649 650 /* bitmask for AENQ groups to report */ 651 u32 enabled_groups; 652 }; 653 654 struct ena_admin_feature_offload_desc { 655 /* 0 : TX_L3_csum_ipv4 656 * 1 : TX_L4_ipv4_csum_part - The checksum field 657 * should be initialized with pseudo header checksum 658 * 2 : TX_L4_ipv4_csum_full 659 * 3 : TX_L4_ipv6_csum_part - The checksum field 660 * should be initialized with pseudo header checksum 661 * 4 : TX_L4_ipv6_csum_full 662 * 5 : tso_ipv4 663 * 6 : tso_ipv6 664 * 7 : tso_ecn 665 */ 666 u32 tx; 667 668 /* Receive side supported stateless offload 669 * 0 : RX_L3_csum_ipv4 - IPv4 checksum 670 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum 671 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum 672 * 3 : RX_hash - Hash calculation 673 */ 674 u32 rx_supported; 675 676 u32 rx_enabled; 677 }; 678 679 enum ena_admin_hash_functions { 680 ENA_ADMIN_TOEPLITZ = 1, 681 ENA_ADMIN_CRC32 = 2, 682 }; 683 684 struct ena_admin_feature_rss_flow_hash_control { 685 u32 keys_num; 686 687 u32 reserved; 688 689 u32 key[10]; 690 }; 691 692 struct ena_admin_feature_rss_flow_hash_function { 693 /* 7:0 : funcs - bitmask of ena_admin_hash_functions */ 694 u32 supported_func; 695 696 /* 7:0 : selected_func - bitmask of 697 * ena_admin_hash_functions 698 */ 699 u32 selected_func; 700 701 /* initial value */ 702 u32 init_val; 703 }; 704 705 /* RSS flow hash protocols */ 706 enum ena_admin_flow_hash_proto { 707 ENA_ADMIN_RSS_TCP4 = 0, 708 ENA_ADMIN_RSS_UDP4 = 1, 709 ENA_ADMIN_RSS_TCP6 = 2, 710 ENA_ADMIN_RSS_UDP6 = 3, 711 ENA_ADMIN_RSS_IP4 = 4, 712 ENA_ADMIN_RSS_IP6 = 5, 713 ENA_ADMIN_RSS_IP4_FRAG = 6, 714 ENA_ADMIN_RSS_NOT_IP = 7, 715 /* TCPv6 with extension header */ 716 ENA_ADMIN_RSS_TCP6_EX = 8, 717 /* IPv6 with extension header */ 718 ENA_ADMIN_RSS_IP6_EX = 9, 719 ENA_ADMIN_RSS_PROTO_NUM = 16, 720 }; 721 722 /* RSS flow hash fields */ 723 enum ena_admin_flow_hash_fields { 724 /* Ethernet Dest Addr */ 725 ENA_ADMIN_RSS_L2_DA = BIT(0), 726 /* Ethernet Src Addr */ 727 ENA_ADMIN_RSS_L2_SA = BIT(1), 728 /* ipv4/6 Dest Addr */ 729 ENA_ADMIN_RSS_L3_DA = BIT(2), 730 /* ipv4/6 Src Addr */ 731 ENA_ADMIN_RSS_L3_SA = BIT(3), 732 /* tcp/udp Dest Port */ 733 ENA_ADMIN_RSS_L4_DP = BIT(4), 734 /* tcp/udp Src Port */ 735 ENA_ADMIN_RSS_L4_SP = BIT(5), 736 }; 737 738 struct ena_admin_proto_input { 739 /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */ 740 u16 fields; 741 742 u16 reserved2; 743 }; 744 745 struct ena_admin_feature_rss_hash_control { 746 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM]; 747 748 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM]; 749 750 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM]; 751 752 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM]; 753 }; 754 755 struct ena_admin_feature_rss_flow_hash_input { 756 /* supported hash input sorting 757 * 1 : L3_sort - support swap L3 addresses if DA is 758 * smaller than SA 759 * 2 : L4_sort - support swap L4 ports if DP smaller 760 * SP 761 */ 762 u16 supported_input_sort; 763 764 /* enabled hash input sorting 765 * 1 : enable_L3_sort - enable swap L3 addresses if 766 * DA smaller than SA 767 * 2 : enable_L4_sort - enable swap L4 ports if DP 768 * smaller than SP 769 */ 770 u16 enabled_input_sort; 771 }; 772 773 enum ena_admin_os_type { 774 ENA_ADMIN_OS_LINUX = 1, 775 ENA_ADMIN_OS_WIN = 2, 776 ENA_ADMIN_OS_DPDK = 3, 777 ENA_ADMIN_OS_FREEBSD = 4, 778 ENA_ADMIN_OS_IPXE = 5, 779 ENA_ADMIN_OS_ESXI = 6, 780 ENA_ADMIN_OS_GROUPS_NUM = 6, 781 }; 782 783 struct ena_admin_host_info { 784 /* defined in enum ena_admin_os_type */ 785 u32 os_type; 786 787 /* os distribution string format */ 788 u8 os_dist_str[128]; 789 790 /* OS distribution numeric format */ 791 u32 os_dist; 792 793 /* kernel version string format */ 794 u8 kernel_ver_str[32]; 795 796 /* Kernel version numeric format */ 797 u32 kernel_ver; 798 799 /* 7:0 : major 800 * 15:8 : minor 801 * 23:16 : sub_minor 802 * 31:24 : module_type 803 */ 804 u32 driver_version; 805 806 /* features bitmap */ 807 u32 supported_network_features[2]; 808 809 /* ENA spec version of driver */ 810 u16 ena_spec_version; 811 812 /* ENA device's Bus, Device and Function 813 * 2:0 : function 814 * 7:3 : device 815 * 15:8 : bus 816 */ 817 u16 bdf; 818 819 /* Number of CPUs */ 820 u16 num_cpus; 821 822 u16 reserved; 823 }; 824 825 struct ena_admin_rss_ind_table_entry { 826 u16 cq_idx; 827 828 u16 reserved; 829 }; 830 831 struct ena_admin_feature_rss_ind_table { 832 /* min supported table size (2^min_size) */ 833 u16 min_size; 834 835 /* max supported table size (2^max_size) */ 836 u16 max_size; 837 838 /* table size (2^size) */ 839 u16 size; 840 841 u16 reserved; 842 843 /* index of the inline entry. 0xFFFFFFFF means invalid */ 844 u32 inline_index; 845 846 /* used for updating single entry, ignored when setting the entire 847 * table through the control buffer. 848 */ 849 struct ena_admin_rss_ind_table_entry inline_entry; 850 }; 851 852 /* When hint value is 0, driver should use it's own predefined value */ 853 struct ena_admin_ena_hw_hints { 854 /* value in ms */ 855 u16 mmio_read_timeout; 856 857 /* value in ms */ 858 u16 driver_watchdog_timeout; 859 860 /* Per packet tx completion timeout. value in ms */ 861 u16 missing_tx_completion_timeout; 862 863 u16 missed_tx_completion_count_threshold_to_reset; 864 865 /* value in ms */ 866 u16 admin_completion_tx_timeout; 867 868 u16 netdev_wd_timeout; 869 870 u16 max_tx_sgl_size; 871 872 u16 max_rx_sgl_size; 873 874 u16 reserved[8]; 875 }; 876 877 struct ena_admin_get_feat_cmd { 878 struct ena_admin_aq_common_desc aq_common_descriptor; 879 880 struct ena_admin_ctrl_buff_info control_buffer; 881 882 struct ena_admin_get_set_feature_common_desc feat_common; 883 884 u32 raw[11]; 885 }; 886 887 struct ena_admin_queue_ext_feature_desc { 888 /* version */ 889 u8 version; 890 891 u8 reserved1[3]; 892 893 union { 894 struct ena_admin_queue_ext_feature_fields max_queue_ext; 895 896 u32 raw[10]; 897 }; 898 }; 899 900 struct ena_admin_get_feat_resp { 901 struct ena_admin_acq_common_desc acq_common_desc; 902 903 union { 904 u32 raw[14]; 905 906 struct ena_admin_device_attr_feature_desc dev_attr; 907 908 struct ena_admin_feature_llq_desc llq; 909 910 struct ena_admin_queue_feature_desc max_queue; 911 912 struct ena_admin_queue_ext_feature_desc max_queue_ext; 913 914 struct ena_admin_feature_aenq_desc aenq; 915 916 struct ena_admin_get_feature_link_desc link; 917 918 struct ena_admin_feature_offload_desc offload; 919 920 struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 921 922 struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 923 924 struct ena_admin_feature_rss_ind_table ind_table; 925 926 struct ena_admin_feature_intr_moder_desc intr_moderation; 927 928 struct ena_admin_ena_hw_hints hw_hints; 929 930 struct ena_admin_get_extra_properties_strings_desc extra_properties_strings; 931 932 struct ena_admin_get_extra_properties_flags_desc extra_properties_flags; 933 } u; 934 }; 935 936 struct ena_admin_set_feat_cmd { 937 struct ena_admin_aq_common_desc aq_common_descriptor; 938 939 struct ena_admin_ctrl_buff_info control_buffer; 940 941 struct ena_admin_get_set_feature_common_desc feat_common; 942 943 union { 944 u32 raw[11]; 945 946 /* mtu size */ 947 struct ena_admin_set_feature_mtu_desc mtu; 948 949 /* host attributes */ 950 struct ena_admin_set_feature_host_attr_desc host_attr; 951 952 /* AENQ configuration */ 953 struct ena_admin_feature_aenq_desc aenq; 954 955 /* rss flow hash function */ 956 struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 957 958 /* rss flow hash input */ 959 struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 960 961 /* rss indirection table */ 962 struct ena_admin_feature_rss_ind_table ind_table; 963 964 /* LLQ configuration */ 965 struct ena_admin_feature_llq_desc llq; 966 } u; 967 }; 968 969 struct ena_admin_set_feat_resp { 970 struct ena_admin_acq_common_desc acq_common_desc; 971 972 union { 973 u32 raw[14]; 974 } u; 975 }; 976 977 struct ena_admin_aenq_common_desc { 978 u16 group; 979 980 u16 syndrom; 981 982 /* 0 : phase 983 * 7:1 : reserved - MBZ 984 */ 985 u8 flags; 986 987 u8 reserved1[3]; 988 989 u32 timestamp_low; 990 991 u32 timestamp_high; 992 }; 993 994 /* asynchronous event notification groups */ 995 enum ena_admin_aenq_group { 996 ENA_ADMIN_LINK_CHANGE = 0, 997 ENA_ADMIN_FATAL_ERROR = 1, 998 ENA_ADMIN_WARNING = 2, 999 ENA_ADMIN_NOTIFICATION = 3, 1000 ENA_ADMIN_KEEP_ALIVE = 4, 1001 ENA_ADMIN_AENQ_GROUPS_NUM = 5, 1002 }; 1003 1004 enum ena_admin_aenq_notification_syndrom { 1005 ENA_ADMIN_SUSPEND = 0, 1006 ENA_ADMIN_RESUME = 1, 1007 ENA_ADMIN_UPDATE_HINTS = 2, 1008 }; 1009 1010 struct ena_admin_aenq_entry { 1011 struct ena_admin_aenq_common_desc aenq_common_desc; 1012 1013 /* command specific inline data */ 1014 u32 inline_data_w4[12]; 1015 }; 1016 1017 struct ena_admin_aenq_link_change_desc { 1018 struct ena_admin_aenq_common_desc aenq_common_desc; 1019 1020 /* 0 : link_status */ 1021 u32 flags; 1022 }; 1023 1024 struct ena_admin_aenq_keep_alive_desc { 1025 struct ena_admin_aenq_common_desc aenq_common_desc; 1026 1027 u32 rx_drops_low; 1028 1029 u32 rx_drops_high; 1030 }; 1031 1032 struct ena_admin_ena_mmio_req_read_less_resp { 1033 u16 req_id; 1034 1035 u16 reg_off; 1036 1037 /* value is valid when poll is cleared */ 1038 u32 reg_val; 1039 }; 1040 1041 /* aq_common_desc */ 1042 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 1043 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0) 1044 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1 1045 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1) 1046 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2 1047 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2) 1048 1049 /* sq */ 1050 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5 1051 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5) 1052 1053 /* acq_common_desc */ 1054 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 1055 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0) 1056 1057 /* aq_create_sq_cmd */ 1058 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5 1059 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5) 1060 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0) 1061 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4 1062 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4) 1063 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0) 1064 1065 /* aq_create_cq_cmd */ 1066 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5 1067 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5) 1068 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) 1069 1070 /* get_set_feature_common_desc */ 1071 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0) 1072 1073 /* get_feature_link_desc */ 1074 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0) 1075 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1 1076 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1) 1077 1078 /* feature_offload_desc */ 1079 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0) 1080 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1 1081 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1) 1082 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2 1083 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2) 1084 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3 1085 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3) 1086 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4 1087 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4) 1088 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5 1089 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5) 1090 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6 1091 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6) 1092 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7 1093 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7) 1094 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0) 1095 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1 1096 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1) 1097 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2 1098 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2) 1099 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3 1100 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3) 1101 1102 /* feature_rss_flow_hash_function */ 1103 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0) 1104 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0) 1105 1106 /* feature_rss_flow_hash_input */ 1107 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1 1108 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1) 1109 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2 1110 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2) 1111 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1 1112 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1) 1113 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2 1114 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2) 1115 1116 /* host_info */ 1117 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0) 1118 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8 1119 #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8) 1120 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16 1121 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16) 1122 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24 1123 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24) 1124 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0) 1125 #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3 1126 #define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3) 1127 #define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8 1128 #define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8) 1129 1130 /* aenq_common_desc */ 1131 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0) 1132 1133 /* aenq_link_change_desc */ 1134 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0) 1135 1136 #endif /*_ENA_ADMIN_H_ */ 1137