1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Altera Triple-Speed Ethernet MAC driver 3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved 4 * 5 * Contributors: 6 * Dalon Westergreen 7 * Thomas Chou 8 * Ian Abbott 9 * Yuriy Kozlov 10 * Tobias Klauser 11 * Andriy Smolskyy 12 * Roman Bulgakov 13 * Dmytro Mytarchuk 14 * Matthew Gerlach 15 * 16 * Original driver contributed by SLS. 17 * Major updates contributed by GlobalLogic 18 */ 19 20 #include <linux/atomic.h> 21 #include <linux/delay.h> 22 #include <linux/etherdevice.h> 23 #include <linux/if_vlan.h> 24 #include <linux/init.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/kernel.h> 28 #include <linux/module.h> 29 #include <linux/mii.h> 30 #include <linux/mdio/mdio-regmap.h> 31 #include <linux/netdevice.h> 32 #include <linux/of.h> 33 #include <linux/of_mdio.h> 34 #include <linux/of_net.h> 35 #include <linux/pcs-lynx.h> 36 #include <linux/phy.h> 37 #include <linux/platform_device.h> 38 #include <linux/property.h> 39 #include <linux/regmap.h> 40 #include <linux/skbuff.h> 41 #include <asm/cacheflush.h> 42 43 #include "altera_utils.h" 44 #include "altera_tse.h" 45 #include "altera_sgdma.h" 46 #include "altera_msgdma.h" 47 48 static atomic_t instance_count = ATOMIC_INIT(~0); 49 /* Module parameters */ 50 static int debug = -1; 51 module_param(debug, int, 0644); 52 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 53 54 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 55 NETIF_MSG_LINK | NETIF_MSG_IFUP | 56 NETIF_MSG_IFDOWN); 57 58 #define RX_DESCRIPTORS 64 59 static int dma_rx_num = RX_DESCRIPTORS; 60 module_param(dma_rx_num, int, 0644); 61 MODULE_PARM_DESC(dma_rx_num, "Number of descriptors in the RX list"); 62 63 #define TX_DESCRIPTORS 64 64 static int dma_tx_num = TX_DESCRIPTORS; 65 module_param(dma_tx_num, int, 0644); 66 MODULE_PARM_DESC(dma_tx_num, "Number of descriptors in the TX list"); 67 68 69 #define POLL_PHY (-1) 70 71 /* Make sure DMA buffer size is larger than the max frame size 72 * plus some alignment offset and a VLAN header. If the max frame size is 73 * 1518, a VLAN header would be additional 4 bytes and additional 74 * headroom for alignment is 2 bytes, 2048 is just fine. 75 */ 76 #define ALTERA_RXDMABUFFER_SIZE 2048 77 78 /* Allow network stack to resume queuing packets after we've 79 * finished transmitting at least 1/4 of the packets in the queue. 80 */ 81 #define TSE_TX_THRESH(x) (x->tx_ring_size / 4) 82 83 #define TXQUEUESTOP_THRESHHOLD 2 84 85 static inline u32 tse_tx_avail(struct altera_tse_private *priv) 86 { 87 return priv->tx_cons + priv->tx_ring_size - priv->tx_prod - 1; 88 } 89 90 /* MDIO specific functions 91 */ 92 static int altera_tse_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 93 { 94 struct net_device *ndev = bus->priv; 95 struct altera_tse_private *priv = netdev_priv(ndev); 96 97 /* set MDIO address */ 98 csrwr32((mii_id & 0x1f), priv->mac_dev, 99 tse_csroffs(mdio_phy1_addr)); 100 101 /* get the data */ 102 return csrrd32(priv->mac_dev, 103 tse_csroffs(mdio_phy1) + regnum * 4) & 0xffff; 104 } 105 106 static int altera_tse_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 107 u16 value) 108 { 109 struct net_device *ndev = bus->priv; 110 struct altera_tse_private *priv = netdev_priv(ndev); 111 112 /* set MDIO address */ 113 csrwr32((mii_id & 0x1f), priv->mac_dev, 114 tse_csroffs(mdio_phy1_addr)); 115 116 /* write the data */ 117 csrwr32(value, priv->mac_dev, tse_csroffs(mdio_phy1) + regnum * 4); 118 return 0; 119 } 120 121 static int altera_tse_mdio_create(struct net_device *dev, unsigned int id) 122 { 123 struct altera_tse_private *priv = netdev_priv(dev); 124 struct device_node *mdio_node = NULL; 125 struct device_node *child_node = NULL; 126 struct mii_bus *mdio = NULL; 127 int ret; 128 129 for_each_child_of_node(priv->device->of_node, child_node) { 130 if (of_device_is_compatible(child_node, "altr,tse-mdio")) { 131 mdio_node = child_node; 132 break; 133 } 134 } 135 136 if (mdio_node) { 137 netdev_dbg(dev, "FOUND MDIO subnode\n"); 138 } else { 139 netdev_dbg(dev, "NO MDIO subnode\n"); 140 return 0; 141 } 142 143 mdio = mdiobus_alloc(); 144 if (mdio == NULL) { 145 netdev_err(dev, "Error allocating MDIO bus\n"); 146 ret = -ENOMEM; 147 goto put_node; 148 } 149 150 mdio->name = ALTERA_TSE_RESOURCE_NAME; 151 mdio->read = &altera_tse_mdio_read; 152 mdio->write = &altera_tse_mdio_write; 153 snprintf(mdio->id, MII_BUS_ID_SIZE, "%s-%u", mdio->name, id); 154 155 mdio->priv = dev; 156 mdio->parent = priv->device; 157 158 ret = of_mdiobus_register(mdio, mdio_node); 159 if (ret != 0) { 160 netdev_err(dev, "Cannot register MDIO bus %s\n", 161 mdio->id); 162 goto out_free_mdio; 163 } 164 of_node_put(mdio_node); 165 166 if (netif_msg_drv(priv)) 167 netdev_info(dev, "MDIO bus %s: created\n", mdio->id); 168 169 priv->mdio = mdio; 170 return 0; 171 out_free_mdio: 172 mdiobus_free(mdio); 173 mdio = NULL; 174 put_node: 175 of_node_put(mdio_node); 176 return ret; 177 } 178 179 static void altera_tse_mdio_destroy(struct net_device *dev) 180 { 181 struct altera_tse_private *priv = netdev_priv(dev); 182 183 if (priv->mdio == NULL) 184 return; 185 186 if (netif_msg_drv(priv)) 187 netdev_info(dev, "MDIO bus %s: removed\n", 188 priv->mdio->id); 189 190 mdiobus_unregister(priv->mdio); 191 mdiobus_free(priv->mdio); 192 priv->mdio = NULL; 193 } 194 195 static int tse_init_rx_buffer(struct altera_tse_private *priv, 196 struct tse_buffer *rxbuffer, int len) 197 { 198 rxbuffer->skb = netdev_alloc_skb_ip_align(priv->dev, len); 199 if (!rxbuffer->skb) 200 return -ENOMEM; 201 202 rxbuffer->dma_addr = dma_map_single(priv->device, rxbuffer->skb->data, 203 len, 204 DMA_FROM_DEVICE); 205 206 if (dma_mapping_error(priv->device, rxbuffer->dma_addr)) { 207 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__); 208 dev_kfree_skb_any(rxbuffer->skb); 209 return -EINVAL; 210 } 211 rxbuffer->dma_addr &= (dma_addr_t)~3; 212 rxbuffer->len = len; 213 return 0; 214 } 215 216 static void tse_free_rx_buffer(struct altera_tse_private *priv, 217 struct tse_buffer *rxbuffer) 218 { 219 dma_addr_t dma_addr = rxbuffer->dma_addr; 220 struct sk_buff *skb = rxbuffer->skb; 221 222 if (skb != NULL) { 223 if (dma_addr) 224 dma_unmap_single(priv->device, dma_addr, 225 rxbuffer->len, 226 DMA_FROM_DEVICE); 227 dev_kfree_skb_any(skb); 228 rxbuffer->skb = NULL; 229 rxbuffer->dma_addr = 0; 230 } 231 } 232 233 /* Unmap and free Tx buffer resources 234 */ 235 static void tse_free_tx_buffer(struct altera_tse_private *priv, 236 struct tse_buffer *buffer) 237 { 238 if (buffer->dma_addr) { 239 if (buffer->mapped_as_page) 240 dma_unmap_page(priv->device, buffer->dma_addr, 241 buffer->len, DMA_TO_DEVICE); 242 else 243 dma_unmap_single(priv->device, buffer->dma_addr, 244 buffer->len, DMA_TO_DEVICE); 245 buffer->dma_addr = 0; 246 } 247 if (buffer->skb) { 248 dev_kfree_skb_any(buffer->skb); 249 buffer->skb = NULL; 250 } 251 } 252 253 static int alloc_init_skbufs(struct altera_tse_private *priv) 254 { 255 unsigned int rx_descs = priv->rx_ring_size; 256 unsigned int tx_descs = priv->tx_ring_size; 257 int ret = -ENOMEM; 258 int i; 259 260 /* Create Rx ring buffer */ 261 priv->rx_ring = kzalloc_objs(struct tse_buffer, rx_descs); 262 if (!priv->rx_ring) 263 goto err_rx_ring; 264 265 /* Create Tx ring buffer */ 266 priv->tx_ring = kzalloc_objs(struct tse_buffer, tx_descs); 267 if (!priv->tx_ring) 268 goto err_tx_ring; 269 270 priv->tx_cons = 0; 271 priv->tx_prod = 0; 272 273 /* Init Rx ring */ 274 for (i = 0; i < rx_descs; i++) { 275 ret = tse_init_rx_buffer(priv, &priv->rx_ring[i], 276 priv->rx_dma_buf_sz); 277 if (ret) 278 goto err_init_rx_buffers; 279 } 280 281 priv->rx_cons = 0; 282 priv->rx_prod = 0; 283 284 return 0; 285 err_init_rx_buffers: 286 while (--i >= 0) 287 tse_free_rx_buffer(priv, &priv->rx_ring[i]); 288 kfree(priv->tx_ring); 289 err_tx_ring: 290 kfree(priv->rx_ring); 291 err_rx_ring: 292 return ret; 293 } 294 295 static void free_skbufs(struct net_device *dev) 296 { 297 struct altera_tse_private *priv = netdev_priv(dev); 298 unsigned int rx_descs = priv->rx_ring_size; 299 unsigned int tx_descs = priv->tx_ring_size; 300 int i; 301 302 /* Release the DMA TX/RX socket buffers */ 303 for (i = 0; i < rx_descs; i++) 304 tse_free_rx_buffer(priv, &priv->rx_ring[i]); 305 for (i = 0; i < tx_descs; i++) 306 tse_free_tx_buffer(priv, &priv->tx_ring[i]); 307 308 309 kfree(priv->tx_ring); 310 } 311 312 /* Reallocate the skb for the reception process 313 */ 314 static inline void tse_rx_refill(struct altera_tse_private *priv) 315 { 316 unsigned int rxsize = priv->rx_ring_size; 317 unsigned int entry; 318 int ret; 319 320 for (; priv->rx_cons - priv->rx_prod > 0; 321 priv->rx_prod++) { 322 entry = priv->rx_prod % rxsize; 323 if (likely(priv->rx_ring[entry].skb == NULL)) { 324 ret = tse_init_rx_buffer(priv, &priv->rx_ring[entry], 325 priv->rx_dma_buf_sz); 326 if (unlikely(ret != 0)) 327 break; 328 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[entry]); 329 } 330 } 331 } 332 333 /* Pull out the VLAN tag and fix up the packet 334 */ 335 static inline void tse_rx_vlan(struct net_device *dev, struct sk_buff *skb) 336 { 337 struct ethhdr *eth_hdr; 338 u16 vid; 339 340 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 341 !__vlan_get_tag(skb, &vid)) { 342 eth_hdr = (struct ethhdr *)skb->data; 343 memmove(skb->data + VLAN_HLEN, eth_hdr, ETH_ALEN * 2); 344 skb_pull(skb, VLAN_HLEN); 345 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 346 } 347 } 348 349 /* Receive a packet: retrieve and pass over to upper levels 350 */ 351 static int tse_rx(struct altera_tse_private *priv, int limit) 352 { 353 unsigned int entry = priv->rx_cons % priv->rx_ring_size; 354 unsigned int next_entry; 355 unsigned int count = 0; 356 struct sk_buff *skb; 357 u32 rxstatus; 358 u16 pktlength; 359 u16 pktstatus; 360 361 /* Check for count < limit first as get_rx_status is changing 362 * the response-fifo so we must process the next packet 363 * after calling get_rx_status if a response is pending. 364 * (reading the last byte of the response pops the value from the fifo.) 365 */ 366 while ((count < limit) && 367 ((rxstatus = priv->dmaops->get_rx_status(priv)) != 0)) { 368 pktstatus = rxstatus >> 16; 369 pktlength = rxstatus & 0xffff; 370 371 if ((pktstatus & 0xFF) || (pktlength == 0)) 372 netdev_err(priv->dev, 373 "RCV pktstatus %08X pktlength %08X\n", 374 pktstatus, pktlength); 375 376 /* DMA transfer from TSE starts with 2 additional bytes for 377 * IP payload alignment. Status returned by get_rx_status() 378 * contains DMA transfer length. Packet is 2 bytes shorter. 379 */ 380 pktlength -= 2; 381 382 count++; 383 next_entry = (++priv->rx_cons) % priv->rx_ring_size; 384 385 skb = priv->rx_ring[entry].skb; 386 if (unlikely(!skb)) { 387 netdev_err(priv->dev, 388 "%s: Inconsistent Rx descriptor chain\n", 389 __func__); 390 priv->dev->stats.rx_dropped++; 391 break; 392 } 393 priv->rx_ring[entry].skb = NULL; 394 395 skb_put(skb, pktlength); 396 397 dma_unmap_single(priv->device, priv->rx_ring[entry].dma_addr, 398 priv->rx_ring[entry].len, DMA_FROM_DEVICE); 399 400 if (netif_msg_pktdata(priv)) { 401 netdev_info(priv->dev, "frame received %d bytes\n", 402 pktlength); 403 print_hex_dump(KERN_ERR, "data: ", DUMP_PREFIX_OFFSET, 404 16, 1, skb->data, pktlength, true); 405 } 406 407 tse_rx_vlan(priv->dev, skb); 408 409 skb->protocol = eth_type_trans(skb, priv->dev); 410 skb_checksum_none_assert(skb); 411 412 napi_gro_receive(&priv->napi, skb); 413 414 priv->dev->stats.rx_packets++; 415 priv->dev->stats.rx_bytes += pktlength; 416 417 entry = next_entry; 418 419 tse_rx_refill(priv); 420 } 421 422 return count; 423 } 424 425 /* Reclaim resources after transmission completes 426 */ 427 static int tse_tx_complete(struct altera_tse_private *priv) 428 { 429 unsigned int txsize = priv->tx_ring_size; 430 struct tse_buffer *tx_buff; 431 unsigned int entry; 432 int txcomplete = 0; 433 u32 ready; 434 435 spin_lock(&priv->tx_lock); 436 437 ready = priv->dmaops->tx_completions(priv); 438 439 /* Free sent buffers */ 440 while (ready && (priv->tx_cons != priv->tx_prod)) { 441 entry = priv->tx_cons % txsize; 442 tx_buff = &priv->tx_ring[entry]; 443 444 if (netif_msg_tx_done(priv)) 445 netdev_dbg(priv->dev, "%s: curr %d, dirty %d\n", 446 __func__, priv->tx_prod, priv->tx_cons); 447 448 if (likely(tx_buff->skb)) 449 priv->dev->stats.tx_packets++; 450 451 tse_free_tx_buffer(priv, tx_buff); 452 priv->tx_cons++; 453 454 txcomplete++; 455 ready--; 456 } 457 458 if (unlikely(netif_queue_stopped(priv->dev) && 459 tse_tx_avail(priv) > TSE_TX_THRESH(priv))) { 460 if (netif_queue_stopped(priv->dev) && 461 tse_tx_avail(priv) > TSE_TX_THRESH(priv)) { 462 if (netif_msg_tx_done(priv)) 463 netdev_dbg(priv->dev, "%s: restart transmit\n", 464 __func__); 465 netif_wake_queue(priv->dev); 466 } 467 } 468 469 spin_unlock(&priv->tx_lock); 470 return txcomplete; 471 } 472 473 /* NAPI polling function 474 */ 475 static int tse_poll(struct napi_struct *napi, int budget) 476 { 477 struct altera_tse_private *priv = 478 container_of(napi, struct altera_tse_private, napi); 479 unsigned long int flags; 480 int rxcomplete = 0; 481 482 tse_tx_complete(priv); 483 484 rxcomplete = tse_rx(priv, budget); 485 486 if (rxcomplete < budget) { 487 488 napi_complete_done(napi, rxcomplete); 489 490 netdev_dbg(priv->dev, 491 "NAPI Complete, did %d packets with budget %d\n", 492 rxcomplete, budget); 493 494 spin_lock_irqsave(&priv->rxdma_irq_lock, flags); 495 priv->dmaops->enable_rxirq(priv); 496 priv->dmaops->enable_txirq(priv); 497 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags); 498 } 499 return rxcomplete; 500 } 501 502 /* DMA TX & RX FIFO interrupt routing 503 */ 504 static irqreturn_t altera_isr(int irq, void *dev_id) 505 { 506 struct net_device *dev = dev_id; 507 struct altera_tse_private *priv; 508 509 if (unlikely(!dev)) { 510 pr_err("%s: invalid dev pointer\n", __func__); 511 return IRQ_NONE; 512 } 513 priv = netdev_priv(dev); 514 515 spin_lock(&priv->rxdma_irq_lock); 516 /* reset IRQs */ 517 priv->dmaops->clear_rxirq(priv); 518 priv->dmaops->clear_txirq(priv); 519 spin_unlock(&priv->rxdma_irq_lock); 520 521 if (likely(napi_schedule_prep(&priv->napi))) { 522 spin_lock(&priv->rxdma_irq_lock); 523 priv->dmaops->disable_rxirq(priv); 524 priv->dmaops->disable_txirq(priv); 525 spin_unlock(&priv->rxdma_irq_lock); 526 __napi_schedule(&priv->napi); 527 } 528 529 530 return IRQ_HANDLED; 531 } 532 533 /* Transmit a packet (called by the kernel). Dispatches 534 * either the SGDMA method for transmitting or the 535 * MSGDMA method, assumes no scatter/gather support, 536 * implying an assumption that there's only one 537 * physically contiguous fragment starting at 538 * skb->data, for length of skb_headlen(skb). 539 */ 540 static netdev_tx_t tse_start_xmit(struct sk_buff *skb, struct net_device *dev) 541 { 542 struct altera_tse_private *priv = netdev_priv(dev); 543 unsigned int nopaged_len = skb_headlen(skb); 544 unsigned int txsize = priv->tx_ring_size; 545 int nfrags = skb_shinfo(skb)->nr_frags; 546 struct tse_buffer *buffer = NULL; 547 netdev_tx_t ret = NETDEV_TX_OK; 548 dma_addr_t dma_addr; 549 unsigned int entry; 550 551 spin_lock_bh(&priv->tx_lock); 552 553 if (unlikely(tse_tx_avail(priv) < nfrags + 1)) { 554 if (!netif_queue_stopped(dev)) { 555 netif_stop_queue(dev); 556 /* This is a hard error, log it. */ 557 netdev_err(priv->dev, 558 "%s: Tx list full when queue awake\n", 559 __func__); 560 } 561 ret = NETDEV_TX_BUSY; 562 goto out; 563 } 564 565 /* Map the first skb fragment */ 566 entry = priv->tx_prod % txsize; 567 buffer = &priv->tx_ring[entry]; 568 569 dma_addr = dma_map_single(priv->device, skb->data, nopaged_len, 570 DMA_TO_DEVICE); 571 if (dma_mapping_error(priv->device, dma_addr)) { 572 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__); 573 ret = NETDEV_TX_OK; 574 goto out; 575 } 576 577 buffer->skb = skb; 578 buffer->dma_addr = dma_addr; 579 buffer->len = nopaged_len; 580 581 priv->dmaops->tx_buffer(priv, buffer); 582 583 skb_tx_timestamp(skb); 584 585 priv->tx_prod++; 586 dev->stats.tx_bytes += skb->len; 587 588 if (unlikely(tse_tx_avail(priv) <= TXQUEUESTOP_THRESHHOLD)) { 589 if (netif_msg_hw(priv)) 590 netdev_dbg(priv->dev, "%s: stop transmitted packets\n", 591 __func__); 592 netif_stop_queue(dev); 593 } 594 595 out: 596 spin_unlock_bh(&priv->tx_lock); 597 598 return ret; 599 } 600 601 static int altera_tse_phy_get_addr_mdio_create(struct net_device *dev) 602 { 603 struct altera_tse_private *priv = netdev_priv(dev); 604 struct device_node *np = priv->device->of_node; 605 int ret; 606 607 ret = of_get_phy_mode(np, &priv->phy_iface); 608 609 /* Avoid get phy addr and create mdio if no phy is present */ 610 if (ret) 611 return 0; 612 613 /* try to get PHY address from device tree, use PHY autodetection if 614 * no valid address is given 615 */ 616 617 if (of_property_read_u32(priv->device->of_node, "phy-addr", 618 &priv->phy_addr)) { 619 priv->phy_addr = POLL_PHY; 620 } 621 622 if (!((priv->phy_addr == POLL_PHY) || 623 ((priv->phy_addr >= 0) && (priv->phy_addr < PHY_MAX_ADDR)))) { 624 netdev_err(dev, "invalid phy-addr specified %d\n", 625 priv->phy_addr); 626 return -ENODEV; 627 } 628 629 /* Create/attach to MDIO bus */ 630 ret = altera_tse_mdio_create(dev, 631 atomic_add_return(1, &instance_count)); 632 633 if (ret) 634 return -ENODEV; 635 636 return 0; 637 } 638 639 static void tse_update_mac_addr(struct altera_tse_private *priv, const u8 *addr) 640 { 641 u32 msb; 642 u32 lsb; 643 644 msb = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; 645 lsb = ((addr[5] << 8) | addr[4]) & 0xffff; 646 647 /* Set primary MAC address */ 648 csrwr32(msb, priv->mac_dev, tse_csroffs(mac_addr_0)); 649 csrwr32(lsb, priv->mac_dev, tse_csroffs(mac_addr_1)); 650 } 651 652 /* MAC software reset. 653 * When reset is triggered, the MAC function completes the current 654 * transmission or reception, and subsequently disables the transmit and 655 * receive logic, flushes the receive FIFO buffer, and resets the statistics 656 * counters. 657 */ 658 static int reset_mac(struct altera_tse_private *priv) 659 { 660 int counter; 661 u32 dat; 662 663 dat = csrrd32(priv->mac_dev, tse_csroffs(command_config)); 664 dat &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA); 665 dat |= MAC_CMDCFG_SW_RESET | MAC_CMDCFG_CNT_RESET; 666 csrwr32(dat, priv->mac_dev, tse_csroffs(command_config)); 667 668 counter = 0; 669 while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) { 670 if (tse_bit_is_clear(priv->mac_dev, tse_csroffs(command_config), 671 MAC_CMDCFG_SW_RESET)) 672 break; 673 udelay(1); 674 } 675 676 if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) { 677 dat = csrrd32(priv->mac_dev, tse_csroffs(command_config)); 678 dat &= ~MAC_CMDCFG_SW_RESET; 679 csrwr32(dat, priv->mac_dev, tse_csroffs(command_config)); 680 return -1; 681 } 682 return 0; 683 } 684 685 /* Initialize MAC core registers 686 */ 687 static int init_mac(struct altera_tse_private *priv) 688 { 689 unsigned int cmd = 0; 690 u32 frm_length; 691 692 /* Setup Rx FIFO */ 693 csrwr32(priv->rx_fifo_depth - ALTERA_TSE_RX_SECTION_EMPTY, 694 priv->mac_dev, tse_csroffs(rx_section_empty)); 695 696 csrwr32(ALTERA_TSE_RX_SECTION_FULL, priv->mac_dev, 697 tse_csroffs(rx_section_full)); 698 699 csrwr32(ALTERA_TSE_RX_ALMOST_EMPTY, priv->mac_dev, 700 tse_csroffs(rx_almost_empty)); 701 702 csrwr32(ALTERA_TSE_RX_ALMOST_FULL, priv->mac_dev, 703 tse_csroffs(rx_almost_full)); 704 705 /* Setup Tx FIFO */ 706 csrwr32(priv->tx_fifo_depth - ALTERA_TSE_TX_SECTION_EMPTY, 707 priv->mac_dev, tse_csroffs(tx_section_empty)); 708 709 csrwr32(ALTERA_TSE_TX_SECTION_FULL, priv->mac_dev, 710 tse_csroffs(tx_section_full)); 711 712 csrwr32(ALTERA_TSE_TX_ALMOST_EMPTY, priv->mac_dev, 713 tse_csroffs(tx_almost_empty)); 714 715 csrwr32(ALTERA_TSE_TX_ALMOST_FULL, priv->mac_dev, 716 tse_csroffs(tx_almost_full)); 717 718 /* MAC Address Configuration */ 719 tse_update_mac_addr(priv, priv->dev->dev_addr); 720 721 /* MAC Function Configuration */ 722 frm_length = ETH_HLEN + priv->dev->mtu + ETH_FCS_LEN; 723 csrwr32(frm_length, priv->mac_dev, tse_csroffs(frm_length)); 724 725 csrwr32(ALTERA_TSE_TX_IPG_LENGTH, priv->mac_dev, 726 tse_csroffs(tx_ipg_length)); 727 728 /* Disable RX/TX shift 16 for alignment of all received frames on 16-bit 729 * start address 730 */ 731 tse_set_bit(priv->mac_dev, tse_csroffs(rx_cmd_stat), 732 ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16); 733 734 tse_clear_bit(priv->mac_dev, tse_csroffs(tx_cmd_stat), 735 ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 | 736 ALTERA_TSE_TX_CMD_STAT_OMIT_CRC); 737 738 /* Set the MAC options */ 739 cmd = csrrd32(priv->mac_dev, tse_csroffs(command_config)); 740 cmd &= ~MAC_CMDCFG_PAD_EN; /* No padding Removal on Receive */ 741 cmd &= ~MAC_CMDCFG_CRC_FWD; /* CRC Removal */ 742 cmd |= MAC_CMDCFG_RX_ERR_DISC; /* Automatically discard frames 743 * with CRC errors 744 */ 745 cmd |= MAC_CMDCFG_CNTL_FRM_ENA; 746 cmd &= ~MAC_CMDCFG_TX_ENA; 747 cmd &= ~MAC_CMDCFG_RX_ENA; 748 749 /* Default speed and duplex setting, full/100 */ 750 cmd &= ~MAC_CMDCFG_HD_ENA; 751 cmd &= ~MAC_CMDCFG_ETH_SPEED; 752 cmd &= ~MAC_CMDCFG_ENA_10; 753 754 csrwr32(cmd, priv->mac_dev, tse_csroffs(command_config)); 755 756 csrwr32(ALTERA_TSE_PAUSE_QUANTA, priv->mac_dev, 757 tse_csroffs(pause_quanta)); 758 759 if (netif_msg_hw(priv)) 760 dev_dbg(priv->device, 761 "MAC post-initialization: CMD_CONFIG = 0x%08x\n", cmd); 762 763 return 0; 764 } 765 766 /* Start/stop MAC transmission logic 767 */ 768 static void tse_set_mac(struct altera_tse_private *priv, bool enable) 769 { 770 u32 value = csrrd32(priv->mac_dev, tse_csroffs(command_config)); 771 772 if (enable) 773 value |= MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA; 774 else 775 value &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA); 776 777 csrwr32(value, priv->mac_dev, tse_csroffs(command_config)); 778 } 779 780 /* Change the MTU 781 */ 782 static int tse_change_mtu(struct net_device *dev, int new_mtu) 783 { 784 if (netif_running(dev)) { 785 netdev_err(dev, "must be stopped to change its MTU\n"); 786 return -EBUSY; 787 } 788 789 WRITE_ONCE(dev->mtu, new_mtu); 790 netdev_update_features(dev); 791 792 return 0; 793 } 794 795 static void altera_tse_set_mcfilter(struct net_device *dev) 796 { 797 struct altera_tse_private *priv = netdev_priv(dev); 798 struct netdev_hw_addr *ha; 799 int i; 800 801 /* clear the hash filter */ 802 for (i = 0; i < 64; i++) 803 csrwr32(0, priv->mac_dev, tse_csroffs(hash_table) + i * 4); 804 805 netdev_for_each_mc_addr(ha, dev) { 806 unsigned int hash = 0; 807 int mac_octet; 808 809 for (mac_octet = 5; mac_octet >= 0; mac_octet--) { 810 unsigned char xor_bit = 0; 811 unsigned char octet = ha->addr[mac_octet]; 812 unsigned int bitshift; 813 814 for (bitshift = 0; bitshift < 8; bitshift++) 815 xor_bit ^= ((octet >> bitshift) & 0x01); 816 817 hash = (hash << 1) | xor_bit; 818 } 819 csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + hash * 4); 820 } 821 } 822 823 824 static void altera_tse_set_mcfilterall(struct net_device *dev) 825 { 826 struct altera_tse_private *priv = netdev_priv(dev); 827 int i; 828 829 /* set the hash filter */ 830 for (i = 0; i < 64; i++) 831 csrwr32(1, priv->mac_dev, tse_csroffs(hash_table) + i * 4); 832 } 833 834 /* Set or clear the multicast filter for this adapter 835 */ 836 static void tse_set_rx_mode_hashfilter(struct net_device *dev) 837 { 838 struct altera_tse_private *priv = netdev_priv(dev); 839 840 spin_lock(&priv->mac_cfg_lock); 841 842 if (dev->flags & IFF_PROMISC) 843 tse_set_bit(priv->mac_dev, tse_csroffs(command_config), 844 MAC_CMDCFG_PROMIS_EN); 845 846 if (dev->flags & IFF_ALLMULTI) 847 altera_tse_set_mcfilterall(dev); 848 else 849 altera_tse_set_mcfilter(dev); 850 851 spin_unlock(&priv->mac_cfg_lock); 852 } 853 854 /* Set or clear the multicast filter for this adapter 855 */ 856 static void tse_set_rx_mode(struct net_device *dev) 857 { 858 struct altera_tse_private *priv = netdev_priv(dev); 859 860 spin_lock(&priv->mac_cfg_lock); 861 862 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI) || 863 !netdev_mc_empty(dev) || !netdev_uc_empty(dev)) 864 tse_set_bit(priv->mac_dev, tse_csroffs(command_config), 865 MAC_CMDCFG_PROMIS_EN); 866 else 867 tse_clear_bit(priv->mac_dev, tse_csroffs(command_config), 868 MAC_CMDCFG_PROMIS_EN); 869 870 spin_unlock(&priv->mac_cfg_lock); 871 } 872 873 /* Open and initialize the interface 874 */ 875 static int tse_open(struct net_device *dev) 876 { 877 struct altera_tse_private *priv = netdev_priv(dev); 878 unsigned long flags; 879 int ret = 0; 880 int i; 881 882 /* Reset and configure TSE MAC and probe associated PHY */ 883 ret = priv->dmaops->init_dma(priv); 884 if (ret != 0) { 885 netdev_err(dev, "Cannot initialize DMA\n"); 886 goto phy_error; 887 } 888 889 if (netif_msg_ifup(priv)) 890 netdev_warn(dev, "device MAC address %pM\n", 891 dev->dev_addr); 892 893 spin_lock(&priv->mac_cfg_lock); 894 895 ret = reset_mac(priv); 896 /* Note that reset_mac will fail if the clocks are gated by the PHY 897 * due to the PHY being put into isolation or power down mode. 898 * This is not an error if reset fails due to no clock. 899 */ 900 if (ret) 901 netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret); 902 903 ret = init_mac(priv); 904 spin_unlock(&priv->mac_cfg_lock); 905 if (ret) { 906 netdev_err(dev, "Cannot init MAC core (error: %d)\n", ret); 907 goto alloc_skbuf_error; 908 } 909 910 priv->dmaops->reset_dma(priv); 911 912 /* Create and initialize the TX/RX descriptors chains. */ 913 priv->rx_ring_size = dma_rx_num; 914 priv->tx_ring_size = dma_tx_num; 915 ret = alloc_init_skbufs(priv); 916 if (ret) { 917 netdev_err(dev, "DMA descriptors initialization failed\n"); 918 goto alloc_skbuf_error; 919 } 920 921 922 /* Register RX interrupt */ 923 ret = request_irq(priv->rx_irq, altera_isr, IRQF_SHARED, 924 dev->name, dev); 925 if (ret) { 926 netdev_err(dev, "Unable to register RX interrupt %d\n", 927 priv->rx_irq); 928 goto init_error; 929 } 930 931 /* Register TX interrupt */ 932 ret = request_irq(priv->tx_irq, altera_isr, IRQF_SHARED, 933 dev->name, dev); 934 if (ret) { 935 netdev_err(dev, "Unable to register TX interrupt %d\n", 936 priv->tx_irq); 937 goto tx_request_irq_error; 938 } 939 940 /* Enable DMA interrupts */ 941 spin_lock_irqsave(&priv->rxdma_irq_lock, flags); 942 priv->dmaops->enable_rxirq(priv); 943 priv->dmaops->enable_txirq(priv); 944 945 /* Setup RX descriptor chain */ 946 for (i = 0; i < priv->rx_ring_size; i++) 947 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[i]); 948 949 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags); 950 951 ret = phylink_of_phy_connect(priv->phylink, priv->device->of_node, 0); 952 if (ret) { 953 netdev_err(dev, "could not connect phylink (%d)\n", ret); 954 goto tx_request_irq_error; 955 } 956 phylink_start(priv->phylink); 957 958 napi_enable(&priv->napi); 959 netif_start_queue(dev); 960 961 priv->dmaops->start_rxdma(priv); 962 963 /* Start MAC Rx/Tx */ 964 spin_lock(&priv->mac_cfg_lock); 965 tse_set_mac(priv, true); 966 spin_unlock(&priv->mac_cfg_lock); 967 968 return 0; 969 970 tx_request_irq_error: 971 free_irq(priv->rx_irq, dev); 972 init_error: 973 free_skbufs(dev); 974 alloc_skbuf_error: 975 phy_error: 976 return ret; 977 } 978 979 /* Stop TSE MAC interface and put the device in an inactive state 980 */ 981 static int tse_shutdown(struct net_device *dev) 982 { 983 struct altera_tse_private *priv = netdev_priv(dev); 984 unsigned long int flags; 985 int ret; 986 987 phylink_stop(priv->phylink); 988 phylink_disconnect_phy(priv->phylink); 989 netif_stop_queue(dev); 990 napi_disable(&priv->napi); 991 992 /* Disable DMA interrupts */ 993 spin_lock_irqsave(&priv->rxdma_irq_lock, flags); 994 priv->dmaops->disable_rxirq(priv); 995 priv->dmaops->disable_txirq(priv); 996 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags); 997 998 /* Free the IRQ lines */ 999 free_irq(priv->rx_irq, dev); 1000 free_irq(priv->tx_irq, dev); 1001 1002 /* disable and reset the MAC, empties fifo */ 1003 spin_lock(&priv->mac_cfg_lock); 1004 spin_lock(&priv->tx_lock); 1005 1006 ret = reset_mac(priv); 1007 /* Note that reset_mac will fail if the clocks are gated by the PHY 1008 * due to the PHY being put into isolation or power down mode. 1009 * This is not an error if reset fails due to no clock. 1010 */ 1011 if (ret) 1012 netdev_dbg(dev, "Cannot reset MAC core (error: %d)\n", ret); 1013 priv->dmaops->reset_dma(priv); 1014 free_skbufs(dev); 1015 1016 spin_unlock(&priv->tx_lock); 1017 spin_unlock(&priv->mac_cfg_lock); 1018 1019 priv->dmaops->uninit_dma(priv); 1020 1021 return 0; 1022 } 1023 1024 static struct net_device_ops altera_tse_netdev_ops = { 1025 .ndo_open = tse_open, 1026 .ndo_stop = tse_shutdown, 1027 .ndo_start_xmit = tse_start_xmit, 1028 .ndo_set_mac_address = eth_mac_addr, 1029 .ndo_set_rx_mode = tse_set_rx_mode, 1030 .ndo_change_mtu = tse_change_mtu, 1031 .ndo_validate_addr = eth_validate_addr, 1032 }; 1033 1034 static void alt_tse_mac_config(struct phylink_config *config, unsigned int mode, 1035 const struct phylink_link_state *state) 1036 { 1037 struct net_device *ndev = to_net_dev(config->dev); 1038 struct altera_tse_private *priv = netdev_priv(ndev); 1039 1040 spin_lock(&priv->mac_cfg_lock); 1041 reset_mac(priv); 1042 tse_set_mac(priv, true); 1043 spin_unlock(&priv->mac_cfg_lock); 1044 } 1045 1046 static void alt_tse_mac_link_down(struct phylink_config *config, 1047 unsigned int mode, phy_interface_t interface) 1048 { 1049 } 1050 1051 static void alt_tse_mac_link_up(struct phylink_config *config, 1052 struct phy_device *phy, unsigned int mode, 1053 phy_interface_t interface, int speed, 1054 int duplex, bool tx_pause, bool rx_pause) 1055 { 1056 struct net_device *ndev = to_net_dev(config->dev); 1057 struct altera_tse_private *priv = netdev_priv(ndev); 1058 u32 ctrl; 1059 1060 ctrl = csrrd32(priv->mac_dev, tse_csroffs(command_config)); 1061 ctrl &= ~(MAC_CMDCFG_ENA_10 | MAC_CMDCFG_ETH_SPEED | MAC_CMDCFG_HD_ENA); 1062 1063 if (duplex == DUPLEX_HALF) 1064 ctrl |= MAC_CMDCFG_HD_ENA; 1065 1066 if (speed == SPEED_1000) 1067 ctrl |= MAC_CMDCFG_ETH_SPEED; 1068 else if (speed == SPEED_10) 1069 ctrl |= MAC_CMDCFG_ENA_10; 1070 1071 spin_lock(&priv->mac_cfg_lock); 1072 csrwr32(ctrl, priv->mac_dev, tse_csroffs(command_config)); 1073 spin_unlock(&priv->mac_cfg_lock); 1074 } 1075 1076 static struct phylink_pcs *alt_tse_select_pcs(struct phylink_config *config, 1077 phy_interface_t interface) 1078 { 1079 struct net_device *ndev = to_net_dev(config->dev); 1080 struct altera_tse_private *priv = netdev_priv(ndev); 1081 1082 if (interface == PHY_INTERFACE_MODE_SGMII || 1083 interface == PHY_INTERFACE_MODE_1000BASEX) 1084 return priv->pcs; 1085 else 1086 return NULL; 1087 } 1088 1089 static const struct phylink_mac_ops alt_tse_phylink_ops = { 1090 .mac_config = alt_tse_mac_config, 1091 .mac_link_down = alt_tse_mac_link_down, 1092 .mac_link_up = alt_tse_mac_link_up, 1093 .mac_select_pcs = alt_tse_select_pcs, 1094 }; 1095 1096 static int request_and_map(struct platform_device *pdev, const char *name, 1097 struct resource **res, void __iomem **ptr) 1098 { 1099 struct device *device = &pdev->dev; 1100 struct resource *region; 1101 1102 *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 1103 if (*res == NULL) { 1104 dev_err(device, "resource %s not defined\n", name); 1105 return -ENODEV; 1106 } 1107 1108 region = devm_request_mem_region(device, (*res)->start, 1109 resource_size(*res), dev_name(device)); 1110 if (region == NULL) { 1111 dev_err(device, "unable to request %s\n", name); 1112 return -EBUSY; 1113 } 1114 1115 *ptr = devm_ioremap(device, region->start, 1116 resource_size(region)); 1117 if (*ptr == NULL) { 1118 dev_err(device, "ioremap of %s failed!", name); 1119 return -ENOMEM; 1120 } 1121 1122 return 0; 1123 } 1124 1125 /* Probe Altera TSE MAC device 1126 */ 1127 static int altera_tse_probe(struct platform_device *pdev) 1128 { 1129 struct regmap_config pcs_regmap_cfg; 1130 struct altera_tse_private *priv; 1131 struct mdio_regmap_config mrc; 1132 struct resource *control_port; 1133 struct regmap *pcs_regmap; 1134 struct resource *dma_res; 1135 struct resource *pcs_res; 1136 struct mii_bus *pcs_bus; 1137 struct net_device *ndev; 1138 void __iomem *descmap; 1139 int ret = -ENODEV; 1140 u32 revision; 1141 1142 ndev = alloc_etherdev(sizeof(struct altera_tse_private)); 1143 if (!ndev) { 1144 dev_err(&pdev->dev, "Could not allocate network device\n"); 1145 return -ENODEV; 1146 } 1147 1148 SET_NETDEV_DEV(ndev, &pdev->dev); 1149 platform_set_drvdata(pdev, ndev); 1150 1151 priv = netdev_priv(ndev); 1152 priv->device = &pdev->dev; 1153 priv->dev = ndev; 1154 priv->msg_enable = netif_msg_init(debug, default_msg_level); 1155 1156 priv->dmaops = device_get_match_data(&pdev->dev); 1157 1158 if (priv->dmaops && 1159 priv->dmaops->altera_dtype == ALTERA_DTYPE_SGDMA) { 1160 /* Get the mapped address to the SGDMA descriptor memory */ 1161 ret = request_and_map(pdev, "s1", &dma_res, &descmap); 1162 if (ret) 1163 goto err_free_netdev; 1164 1165 /* Start of that memory is for transmit descriptors */ 1166 priv->tx_dma_desc = descmap; 1167 1168 /* First half is for tx descriptors, other half for tx */ 1169 priv->txdescmem = resource_size(dma_res)/2; 1170 1171 priv->txdescmem_busaddr = (dma_addr_t)dma_res->start; 1172 1173 priv->rx_dma_desc = (void __iomem *)((uintptr_t)(descmap + 1174 priv->txdescmem)); 1175 priv->rxdescmem = resource_size(dma_res)/2; 1176 priv->rxdescmem_busaddr = dma_res->start; 1177 priv->rxdescmem_busaddr += priv->txdescmem; 1178 1179 if (upper_32_bits(priv->rxdescmem_busaddr)) { 1180 dev_dbg(priv->device, 1181 "SGDMA bus addresses greater than 32-bits\n"); 1182 ret = -EINVAL; 1183 goto err_free_netdev; 1184 } 1185 if (upper_32_bits(priv->txdescmem_busaddr)) { 1186 dev_dbg(priv->device, 1187 "SGDMA bus addresses greater than 32-bits\n"); 1188 ret = -EINVAL; 1189 goto err_free_netdev; 1190 } 1191 } else if (priv->dmaops && 1192 priv->dmaops->altera_dtype == ALTERA_DTYPE_MSGDMA) { 1193 ret = request_and_map(pdev, "rx_resp", &dma_res, 1194 &priv->rx_dma_resp); 1195 if (ret) 1196 goto err_free_netdev; 1197 1198 ret = request_and_map(pdev, "tx_desc", &dma_res, 1199 &priv->tx_dma_desc); 1200 if (ret) 1201 goto err_free_netdev; 1202 1203 priv->txdescmem = resource_size(dma_res); 1204 priv->txdescmem_busaddr = dma_res->start; 1205 1206 ret = request_and_map(pdev, "rx_desc", &dma_res, 1207 &priv->rx_dma_desc); 1208 if (ret) 1209 goto err_free_netdev; 1210 1211 priv->rxdescmem = resource_size(dma_res); 1212 priv->rxdescmem_busaddr = dma_res->start; 1213 1214 } else { 1215 ret = -ENODEV; 1216 goto err_free_netdev; 1217 } 1218 1219 if (!dma_set_mask(priv->device, DMA_BIT_MASK(priv->dmaops->dmamask))) { 1220 dma_set_coherent_mask(priv->device, 1221 DMA_BIT_MASK(priv->dmaops->dmamask)); 1222 } else if (!dma_set_mask(priv->device, DMA_BIT_MASK(32))) { 1223 dma_set_coherent_mask(priv->device, DMA_BIT_MASK(32)); 1224 } else { 1225 ret = -EIO; 1226 goto err_free_netdev; 1227 } 1228 1229 /* MAC address space */ 1230 ret = request_and_map(pdev, "control_port", &control_port, 1231 (void __iomem **)&priv->mac_dev); 1232 if (ret) 1233 goto err_free_netdev; 1234 1235 /* xSGDMA Rx Dispatcher address space */ 1236 ret = request_and_map(pdev, "rx_csr", &dma_res, 1237 &priv->rx_dma_csr); 1238 if (ret) 1239 goto err_free_netdev; 1240 1241 1242 /* xSGDMA Tx Dispatcher address space */ 1243 ret = request_and_map(pdev, "tx_csr", &dma_res, 1244 &priv->tx_dma_csr); 1245 if (ret) 1246 goto err_free_netdev; 1247 1248 memset(&pcs_regmap_cfg, 0, sizeof(pcs_regmap_cfg)); 1249 memset(&mrc, 0, sizeof(mrc)); 1250 /* SGMII PCS address space. The location can vary depending on how the 1251 * IP is integrated. We can have a resource dedicated to it at a specific 1252 * address space, but if it's not the case, we fallback to the mdiophy0 1253 * from the MAC's address space 1254 */ 1255 ret = request_and_map(pdev, "pcs", &pcs_res, &priv->pcs_base); 1256 if (ret) { 1257 /* If we can't find a dedicated resource for the PCS, fallback 1258 * to the internal PCS, that has a different address stride 1259 */ 1260 priv->pcs_base = priv->mac_dev + tse_csroffs(mdio_phy0); 1261 pcs_regmap_cfg.reg_bits = 32; 1262 /* Values are MDIO-like values, on 16 bits */ 1263 pcs_regmap_cfg.val_bits = 16; 1264 pcs_regmap_cfg.reg_shift = REGMAP_UPSHIFT(2); 1265 } else { 1266 pcs_regmap_cfg.reg_bits = 16; 1267 pcs_regmap_cfg.val_bits = 16; 1268 pcs_regmap_cfg.reg_shift = REGMAP_UPSHIFT(1); 1269 } 1270 1271 /* Create a regmap for the PCS so that it can be used by the PCS driver */ 1272 pcs_regmap = devm_regmap_init_mmio(&pdev->dev, priv->pcs_base, 1273 &pcs_regmap_cfg); 1274 if (IS_ERR(pcs_regmap)) { 1275 ret = PTR_ERR(pcs_regmap); 1276 goto err_free_netdev; 1277 } 1278 mrc.regmap = pcs_regmap; 1279 mrc.parent = &pdev->dev; 1280 mrc.valid_addr = 0x0; 1281 mrc.autoscan = false; 1282 1283 /* Rx IRQ */ 1284 priv->rx_irq = platform_get_irq_byname(pdev, "rx_irq"); 1285 if (priv->rx_irq == -ENXIO) { 1286 dev_err(&pdev->dev, "cannot obtain Rx IRQ\n"); 1287 ret = -ENXIO; 1288 goto err_free_netdev; 1289 } 1290 1291 /* Tx IRQ */ 1292 priv->tx_irq = platform_get_irq_byname(pdev, "tx_irq"); 1293 if (priv->tx_irq == -ENXIO) { 1294 dev_err(&pdev->dev, "cannot obtain Tx IRQ\n"); 1295 ret = -ENXIO; 1296 goto err_free_netdev; 1297 } 1298 1299 /* get FIFO depths from device tree */ 1300 if (of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth", 1301 &priv->rx_fifo_depth)) { 1302 dev_err(&pdev->dev, "cannot obtain rx-fifo-depth\n"); 1303 ret = -ENXIO; 1304 goto err_free_netdev; 1305 } 1306 1307 if (of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth", 1308 &priv->tx_fifo_depth)) { 1309 dev_err(&pdev->dev, "cannot obtain tx-fifo-depth\n"); 1310 ret = -ENXIO; 1311 goto err_free_netdev; 1312 } 1313 1314 /* get hash filter settings for this instance */ 1315 priv->hash_filter = 1316 of_property_read_bool(pdev->dev.of_node, 1317 "altr,has-hash-multicast-filter"); 1318 1319 /* Set hash filter to not set for now until the 1320 * multicast filter receive issue is debugged 1321 */ 1322 priv->hash_filter = 0; 1323 1324 /* get supplemental address settings for this instance */ 1325 priv->added_unicast = 1326 of_property_read_bool(pdev->dev.of_node, 1327 "altr,has-supplementary-unicast"); 1328 1329 priv->dev->min_mtu = ETH_ZLEN + ETH_FCS_LEN; 1330 /* Max MTU is 1500, ETH_DATA_LEN */ 1331 priv->dev->max_mtu = ETH_DATA_LEN; 1332 1333 /* Get the max mtu from the device tree. Note that the 1334 * "max-frame-size" parameter is actually max mtu. Definition 1335 * in the ePAPR v1.1 spec and usage differ, so go with usage. 1336 */ 1337 of_property_read_u32(pdev->dev.of_node, "max-frame-size", 1338 &priv->dev->max_mtu); 1339 1340 /* The DMA buffer size already accounts for an alignment bias 1341 * to avoid unaligned access exceptions for the NIOS processor, 1342 */ 1343 priv->rx_dma_buf_sz = ALTERA_RXDMABUFFER_SIZE; 1344 1345 /* get default MAC address from device tree */ 1346 ret = of_get_ethdev_address(pdev->dev.of_node, ndev); 1347 if (ret) 1348 eth_hw_addr_random(ndev); 1349 1350 /* get phy addr and create mdio */ 1351 ret = altera_tse_phy_get_addr_mdio_create(ndev); 1352 1353 if (ret) 1354 goto err_free_netdev; 1355 1356 /* initialize netdev */ 1357 ndev->mem_start = control_port->start; 1358 ndev->mem_end = control_port->end; 1359 ndev->netdev_ops = &altera_tse_netdev_ops; 1360 altera_tse_set_ethtool_ops(ndev); 1361 1362 altera_tse_netdev_ops.ndo_set_rx_mode = tse_set_rx_mode; 1363 1364 if (priv->hash_filter) 1365 altera_tse_netdev_ops.ndo_set_rx_mode = 1366 tse_set_rx_mode_hashfilter; 1367 1368 /* Scatter/gather IO is not supported, 1369 * so it is turned off 1370 */ 1371 ndev->hw_features &= ~NETIF_F_SG; 1372 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 1373 1374 /* VLAN offloading of tagging, stripping and filtering is not 1375 * supported by hardware, but driver will accommodate the 1376 * extra 4-byte VLAN tag for processing by upper layers 1377 */ 1378 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 1379 1380 /* setup NAPI interface */ 1381 netif_napi_add(ndev, &priv->napi, tse_poll); 1382 1383 spin_lock_init(&priv->mac_cfg_lock); 1384 spin_lock_init(&priv->tx_lock); 1385 spin_lock_init(&priv->rxdma_irq_lock); 1386 1387 snprintf(mrc.name, MII_BUS_ID_SIZE, "%s-pcs-mii", dev_name(&pdev->dev)); 1388 pcs_bus = devm_mdio_regmap_register(&pdev->dev, &mrc); 1389 if (IS_ERR(pcs_bus)) { 1390 ret = PTR_ERR(pcs_bus); 1391 goto err_init_pcs; 1392 } 1393 1394 priv->pcs = lynx_pcs_create_mdiodev(pcs_bus, 0); 1395 if (IS_ERR(priv->pcs)) { 1396 ret = PTR_ERR(priv->pcs); 1397 goto err_init_pcs; 1398 } 1399 1400 priv->phylink_config.dev = &ndev->dev; 1401 priv->phylink_config.type = PHYLINK_NETDEV; 1402 priv->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | 1403 MAC_100 | MAC_1000FD; 1404 1405 phy_interface_set_rgmii(priv->phylink_config.supported_interfaces); 1406 __set_bit(PHY_INTERFACE_MODE_MII, 1407 priv->phylink_config.supported_interfaces); 1408 __set_bit(PHY_INTERFACE_MODE_GMII, 1409 priv->phylink_config.supported_interfaces); 1410 __set_bit(PHY_INTERFACE_MODE_SGMII, 1411 priv->phylink_config.supported_interfaces); 1412 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 1413 priv->phylink_config.supported_interfaces); 1414 1415 priv->phylink = phylink_create(&priv->phylink_config, 1416 of_fwnode_handle(priv->device->of_node), 1417 priv->phy_iface, &alt_tse_phylink_ops); 1418 if (IS_ERR(priv->phylink)) { 1419 dev_err(&pdev->dev, "failed to create phylink\n"); 1420 ret = PTR_ERR(priv->phylink); 1421 goto err_init_phylink; 1422 } 1423 1424 ret = register_netdev(ndev); 1425 if (ret) { 1426 dev_err(&pdev->dev, "failed to register TSE net device\n"); 1427 goto err_register_netdev; 1428 } 1429 1430 revision = ioread32(&priv->mac_dev->megacore_revision); 1431 1432 if (revision < 0xd00 || revision > 0xe00) 1433 netdev_warn(ndev, "TSE revision %x\n", revision); 1434 1435 if (netif_msg_probe(priv)) 1436 dev_info(&pdev->dev, "Altera TSE MAC version %d.%d at 0x%08lx irq %d/%d\n", 1437 (revision >> 8) & 0xff, revision & 0xff, 1438 (unsigned long)control_port->start, priv->rx_irq, 1439 priv->tx_irq); 1440 1441 return 0; 1442 1443 err_register_netdev: 1444 phylink_destroy(priv->phylink); 1445 err_init_phylink: 1446 lynx_pcs_destroy(priv->pcs); 1447 err_init_pcs: 1448 netif_napi_del(&priv->napi); 1449 altera_tse_mdio_destroy(ndev); 1450 err_free_netdev: 1451 free_netdev(ndev); 1452 return ret; 1453 } 1454 1455 /* Remove Altera TSE MAC device 1456 */ 1457 static void altera_tse_remove(struct platform_device *pdev) 1458 { 1459 struct net_device *ndev = platform_get_drvdata(pdev); 1460 struct altera_tse_private *priv = netdev_priv(ndev); 1461 1462 platform_set_drvdata(pdev, NULL); 1463 altera_tse_mdio_destroy(ndev); 1464 unregister_netdev(ndev); 1465 phylink_destroy(priv->phylink); 1466 lynx_pcs_destroy(priv->pcs); 1467 1468 free_netdev(ndev); 1469 } 1470 1471 static const struct altera_dmaops altera_dtype_sgdma = { 1472 .altera_dtype = ALTERA_DTYPE_SGDMA, 1473 .dmamask = 32, 1474 .reset_dma = sgdma_reset, 1475 .enable_txirq = sgdma_enable_txirq, 1476 .enable_rxirq = sgdma_enable_rxirq, 1477 .disable_txirq = sgdma_disable_txirq, 1478 .disable_rxirq = sgdma_disable_rxirq, 1479 .clear_txirq = sgdma_clear_txirq, 1480 .clear_rxirq = sgdma_clear_rxirq, 1481 .tx_buffer = sgdma_tx_buffer, 1482 .tx_completions = sgdma_tx_completions, 1483 .add_rx_desc = sgdma_add_rx_desc, 1484 .get_rx_status = sgdma_rx_status, 1485 .init_dma = sgdma_initialize, 1486 .uninit_dma = sgdma_uninitialize, 1487 .start_rxdma = sgdma_start_rxdma, 1488 }; 1489 1490 static const struct altera_dmaops altera_dtype_msgdma = { 1491 .altera_dtype = ALTERA_DTYPE_MSGDMA, 1492 .dmamask = 64, 1493 .reset_dma = msgdma_reset, 1494 .enable_txirq = msgdma_enable_txirq, 1495 .enable_rxirq = msgdma_enable_rxirq, 1496 .disable_txirq = msgdma_disable_txirq, 1497 .disable_rxirq = msgdma_disable_rxirq, 1498 .clear_txirq = msgdma_clear_txirq, 1499 .clear_rxirq = msgdma_clear_rxirq, 1500 .tx_buffer = msgdma_tx_buffer, 1501 .tx_completions = msgdma_tx_completions, 1502 .add_rx_desc = msgdma_add_rx_desc, 1503 .get_rx_status = msgdma_rx_status, 1504 .init_dma = msgdma_initialize, 1505 .uninit_dma = msgdma_uninitialize, 1506 .start_rxdma = msgdma_start_rxdma, 1507 }; 1508 1509 static const struct of_device_id altera_tse_ids[] = { 1510 { .compatible = "altr,tse-msgdma-1.0", .data = &altera_dtype_msgdma, }, 1511 { .compatible = "altr,tse-1.0", .data = &altera_dtype_sgdma, }, 1512 { .compatible = "ALTR,tse-1.0", .data = &altera_dtype_sgdma, }, 1513 {}, 1514 }; 1515 MODULE_DEVICE_TABLE(of, altera_tse_ids); 1516 1517 static struct platform_driver altera_tse_driver = { 1518 .probe = altera_tse_probe, 1519 .remove = altera_tse_remove, 1520 .suspend = NULL, 1521 .resume = NULL, 1522 .driver = { 1523 .name = ALTERA_TSE_RESOURCE_NAME, 1524 .of_match_table = altera_tse_ids, 1525 }, 1526 }; 1527 1528 module_platform_driver(altera_tse_driver); 1529 1530 MODULE_AUTHOR("Altera Corporation"); 1531 MODULE_DESCRIPTION("Altera Triple Speed Ethernet MAC driver"); 1532 MODULE_LICENSE("GPL v2"); 1533