1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 #ifndef _SLIC_H 4 #define _SLIC_H 5 6 #include <linux/types.h> 7 #include <linux/netdevice.h> 8 #include <linux/spinlock_types.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/pci.h> 11 #include <linux/list.h> 12 #include <linux/u64_stats_sync.h> 13 14 #define SLIC_VGBSTAT_XPERR 0x40000000 15 #define SLIC_VGBSTAT_XERRSHFT 25 16 #define SLIC_VGBSTAT_XCSERR 0x23 17 #define SLIC_VGBSTAT_XUFLOW 0x22 18 #define SLIC_VGBSTAT_XHLEN 0x20 19 #define SLIC_VGBSTAT_NETERR 0x01000000 20 #define SLIC_VGBSTAT_NERRSHFT 16 21 #define SLIC_VGBSTAT_NERRMSK 0x1ff 22 #define SLIC_VGBSTAT_NCSERR 0x103 23 #define SLIC_VGBSTAT_NUFLOW 0x102 24 #define SLIC_VGBSTAT_NHLEN 0x100 25 #define SLIC_VGBSTAT_LNKERR 0x00000080 26 #define SLIC_VGBSTAT_LERRMSK 0xff 27 #define SLIC_VGBSTAT_LDEARLY 0x86 28 #define SLIC_VGBSTAT_LBOFLO 0x85 29 #define SLIC_VGBSTAT_LCODERR 0x84 30 #define SLIC_VGBSTAT_LDBLNBL 0x83 31 #define SLIC_VGBSTAT_LCRCERR 0x82 32 #define SLIC_VGBSTAT_LOFLO 0x81 33 #define SLIC_VGBSTAT_LUFLO 0x80 34 35 #define SLIC_IRHDDR_FLEN_MSK 0x0000ffff 36 #define SLIC_IRHDDR_SVALID 0x80000000 37 #define SLIC_IRHDDR_ERR 0x10000000 38 39 #define SLIC_VRHSTAT_802OE 0x80000000 40 #define SLIC_VRHSTAT_TPOFLO 0x10000000 41 #define SLIC_VRHSTATB_802UE 0x80000000 42 #define SLIC_VRHSTATB_RCVE 0x40000000 43 #define SLIC_VRHSTATB_BUFF 0x20000000 44 #define SLIC_VRHSTATB_CARRE 0x08000000 45 #define SLIC_VRHSTATB_LONGE 0x02000000 46 #define SLIC_VRHSTATB_PREA 0x01000000 47 #define SLIC_VRHSTATB_CRC 0x00800000 48 #define SLIC_VRHSTATB_DRBL 0x00400000 49 #define SLIC_VRHSTATB_CODE 0x00200000 50 #define SLIC_VRHSTATB_TPCSUM 0x00100000 51 #define SLIC_VRHSTATB_TPHLEN 0x00080000 52 #define SLIC_VRHSTATB_IPCSUM 0x00040000 53 #define SLIC_VRHSTATB_IPLERR 0x00020000 54 #define SLIC_VRHSTATB_IPHERR 0x00010000 55 56 #define SLIC_CMD_XMT_REQ 0x01 57 #define SLIC_CMD_TYPE_DUMB 3 58 59 #define SLIC_RESET_MAGIC 0xDEAD 60 #define SLIC_ICR_INT_OFF 0 61 #define SLIC_ICR_INT_ON 1 62 #define SLIC_ICR_INT_MASK 2 63 64 #define SLIC_ISR_ERR 0x80000000 65 #define SLIC_ISR_RCV 0x40000000 66 #define SLIC_ISR_CMD 0x20000000 67 #define SLIC_ISR_IO 0x60000000 68 #define SLIC_ISR_UPC 0x10000000 69 #define SLIC_ISR_LEVENT 0x08000000 70 #define SLIC_ISR_RMISS 0x02000000 71 #define SLIC_ISR_UPCERR 0x01000000 72 #define SLIC_ISR_XDROP 0x00800000 73 #define SLIC_ISR_UPCBSY 0x00020000 74 75 #define SLIC_ISR_PING_MASK 0x00700000 76 #define SLIC_ISR_UPCERR_MASK (SLIC_ISR_UPCERR | SLIC_ISR_UPCBSY) 77 #define SLIC_ISR_UPC_MASK (SLIC_ISR_UPC | SLIC_ISR_UPCERR_MASK) 78 #define SLIC_WCS_START 0x80000000 79 #define SLIC_WCS_COMPARE 0x40000000 80 #define SLIC_RCVWCS_BEGIN 0x40000000 81 #define SLIC_RCVWCS_FINISH 0x80000000 82 83 #define SLIC_MIICR_REG_16 0x00100000 84 #define SLIC_MRV_REG16_XOVERON 0x0068 85 86 #define SLIC_GIG_LINKUP 0x0001 87 #define SLIC_GIG_FULLDUPLEX 0x0002 88 #define SLIC_GIG_SPEED_MASK 0x000C 89 #define SLIC_GIG_SPEED_1000 0x0008 90 #define SLIC_GIG_SPEED_100 0x0004 91 #define SLIC_GIG_SPEED_10 0x0000 92 93 #define SLIC_GMCR_RESET 0x80000000 94 #define SLIC_GMCR_GBIT 0x20000000 95 #define SLIC_GMCR_FULLD 0x10000000 96 #define SLIC_GMCR_GAPBB_SHIFT 14 97 #define SLIC_GMCR_GAPR1_SHIFT 7 98 #define SLIC_GMCR_GAPR2_SHIFT 0 99 #define SLIC_GMCR_GAPBB_1000 0x60 100 #define SLIC_GMCR_GAPR1_1000 0x2C 101 #define SLIC_GMCR_GAPR2_1000 0x40 102 #define SLIC_GMCR_GAPBB_100 0x70 103 #define SLIC_GMCR_GAPR1_100 0x2C 104 #define SLIC_GMCR_GAPR2_100 0x40 105 106 #define SLIC_XCR_RESET 0x80000000 107 #define SLIC_XCR_XMTEN 0x40000000 108 #define SLIC_XCR_PAUSEEN 0x20000000 109 #define SLIC_XCR_LOADRNG 0x10000000 110 111 #define SLIC_GXCR_RESET 0x80000000 112 #define SLIC_GXCR_XMTEN 0x40000000 113 #define SLIC_GXCR_PAUSEEN 0x20000000 114 115 #define SLIC_GRCR_RESET 0x80000000 116 #define SLIC_GRCR_RCVEN 0x40000000 117 #define SLIC_GRCR_RCVALL 0x20000000 118 #define SLIC_GRCR_RCVBAD 0x10000000 119 #define SLIC_GRCR_CTLEN 0x08000000 120 #define SLIC_GRCR_ADDRAEN 0x02000000 121 #define SLIC_GRCR_HASHSIZE_SHIFT 17 122 #define SLIC_GRCR_HASHSIZE 14 123 124 /* Reset Register */ 125 #define SLIC_REG_RESET 0x0000 126 /* Interrupt Control Register */ 127 #define SLIC_REG_ICR 0x0008 128 /* Interrupt status pointer */ 129 #define SLIC_REG_ISP 0x0010 130 /* Interrupt status */ 131 #define SLIC_REG_ISR 0x0018 132 /* Header buffer address reg 133 * 31-8 - phy addr of set of contiguous hdr buffers 134 * 7-0 - number of buffers passed 135 * Buffers are 256 bytes long on 256-byte boundaries. 136 */ 137 #define SLIC_REG_HBAR 0x0020 138 /* Data buffer handle & address reg 139 * 4 sets of registers; Buffers are 2K bytes long 2 per 4K page. 140 */ 141 #define SLIC_REG_DBAR 0x0028 142 /* Xmt Cmd buf addr regs. 143 * 1 per XMT interface 144 * 31-5 - phy addr of host command buffer 145 * 4-0 - length of cmd in multiples of 32 bytes 146 * Buffers are 32 bytes up to 512 bytes long 147 */ 148 #define SLIC_REG_CBAR 0x0030 149 /* Write control store */ 150 #define SLIC_REG_WCS 0x0034 151 /*Response buffer address reg. 152 * 31-8 - phy addr of set of contiguous response buffers 153 * 7-0 - number of buffers passed 154 * Buffers are 32 bytes long on 32-byte boundaries. 155 */ 156 #define SLIC_REG_RBAR 0x0038 157 /* Read statistics (UPR) */ 158 #define SLIC_REG_RSTAT 0x0040 159 /* Read link status */ 160 #define SLIC_REG_LSTAT 0x0048 161 /* Write Mac Config */ 162 #define SLIC_REG_WMCFG 0x0050 163 /* Write phy register */ 164 #define SLIC_REG_WPHY 0x0058 165 /* Rcv Cmd buf addr reg */ 166 #define SLIC_REG_RCBAR 0x0060 167 /* Read SLIC Config*/ 168 #define SLIC_REG_RCONFIG 0x0068 169 /* Interrupt aggregation time */ 170 #define SLIC_REG_INTAGG 0x0070 171 /* Write XMIT config reg */ 172 #define SLIC_REG_WXCFG 0x0078 173 /* Write RCV config reg */ 174 #define SLIC_REG_WRCFG 0x0080 175 /* Write rcv addr a low */ 176 #define SLIC_REG_WRADDRAL 0x0088 177 /* Write rcv addr a high */ 178 #define SLIC_REG_WRADDRAH 0x0090 179 /* Write rcv addr b low */ 180 #define SLIC_REG_WRADDRBL 0x0098 181 /* Write rcv addr b high */ 182 #define SLIC_REG_WRADDRBH 0x00a0 183 /* Low bits of mcast mask */ 184 #define SLIC_REG_MCASTLOW 0x00a8 185 /* High bits of mcast mask */ 186 #define SLIC_REG_MCASTHIGH 0x00b0 187 /* Ping the card */ 188 #define SLIC_REG_PING 0x00b8 189 /* Dump command */ 190 #define SLIC_REG_DUMP_CMD 0x00c0 191 /* Dump data pointer */ 192 #define SLIC_REG_DUMP_DATA 0x00c8 193 /* Read card's pci_status register */ 194 #define SLIC_REG_PCISTATUS 0x00d0 195 /* Write hostid field */ 196 #define SLIC_REG_WRHOSTID 0x00d8 197 /* Put card in a low power state */ 198 #define SLIC_REG_LOW_POWER 0x00e0 199 /* Force slic into quiescent state before soft reset */ 200 #define SLIC_REG_QUIESCE 0x00e8 201 /* Reset interface queues */ 202 #define SLIC_REG_RESET_IFACE 0x00f0 203 /* Register is only written when it has changed. 204 * Bits 63-32 for host i/f addrs. 205 */ 206 #define SLIC_REG_ADDR_UPPER 0x00f8 207 /* 64 bit Header buffer address reg */ 208 #define SLIC_REG_HBAR64 0x0100 209 /* 64 bit Data buffer handle & address reg */ 210 #define SLIC_REG_DBAR64 0x0108 211 /* 64 bit Xmt Cmd buf addr regs. */ 212 #define SLIC_REG_CBAR64 0x0110 213 /* 64 bit Response buffer address reg.*/ 214 #define SLIC_REG_RBAR64 0x0118 215 /* 64 bit Rcv Cmd buf addr reg*/ 216 #define SLIC_REG_RCBAR64 0x0120 217 /* Read statistics (64 bit UPR) */ 218 #define SLIC_REG_RSTAT64 0x0128 219 /* Download Gigabit RCV sequencer ucode */ 220 #define SLIC_REG_RCV_WCS 0x0130 221 /* Write VlanId field */ 222 #define SLIC_REG_WRVLANID 0x0138 223 /* Read Transformer info */ 224 #define SLIC_REG_READ_XF_INFO 0x0140 225 /* Write Transformer info */ 226 #define SLIC_REG_WRITE_XF_INFO 0x0148 227 /* Write card ticks per second */ 228 #define SLIC_REG_TICKS_PER_SEC 0x0170 229 #define SLIC_REG_HOSTID 0x1554 230 231 #define PCI_VENDOR_ID_ALACRITECH 0x139A 232 #define PCI_DEVICE_ID_ALACRITECH_MOJAVE 0x0005 233 #define PCI_SUBDEVICE_ID_ALACRITECH_1000X1 0x0005 234 #define PCI_SUBDEVICE_ID_ALACRITECH_1000X1_2 0x0006 235 #define PCI_SUBDEVICE_ID_ALACRITECH_1000X1F 0x0007 236 #define PCI_SUBDEVICE_ID_ALACRITECH_CICADA 0x0008 237 #define PCI_SUBDEVICE_ID_ALACRITECH_SES1001T 0x2006 238 #define PCI_SUBDEVICE_ID_ALACRITECH_SES1001F 0x2007 239 #define PCI_DEVICE_ID_ALACRITECH_OASIS 0x0007 240 #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2002XT 0x000B 241 #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2002XF 0x000C 242 #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2001XT 0x000D 243 #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2001XF 0x000E 244 #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2104EF 0x000F 245 #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2104ET 0x0010 246 #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2102EF 0x0011 247 #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2102ET 0x0012 248 249 /* Note: power of two required for number descriptors */ 250 #define SLIC_NUM_RX_LES 256 251 #define SLIC_RX_BUFF_SIZE 2048 252 #define SLIC_RX_BUFF_ALIGN 256 253 #define SLIC_RX_BUFF_HDR_SIZE 34 254 #define SLIC_MAX_REQ_RX_DESCS 1 255 256 #define SLIC_NUM_TX_DESCS 256 257 #define SLIC_TX_DESC_ALIGN 32 258 #define SLIC_MIN_TX_WAKEUP_DESCS 10 259 #define SLIC_MAX_REQ_TX_DESCS 1 260 #define SLIC_MAX_TX_COMPLETIONS 100 261 262 #define SLIC_NUM_STAT_DESCS 128 263 #define SLIC_STATS_DESC_ALIGN 256 264 265 #define SLIC_NUM_STAT_DESC_ARRAYS 4 266 #define SLIC_INVALID_STAT_DESC_IDX 0xffffffff 267 268 #define SLIC_NAPI_WEIGHT 64 269 270 #define SLIC_UPR_LSTAT 0 271 #define SLIC_UPR_CONFIG 1 272 273 #define SLIC_EEPROM_SIZE 128 274 #define SLIC_EEPROM_MAGIC 0xa5a5 275 276 #define SLIC_FIRMWARE_MOJAVE "slicoss/gbdownload.sys" 277 #define SLIC_FIRMWARE_OASIS "slicoss/oasisdownload.sys" 278 #define SLIC_RCV_FIRMWARE_MOJAVE "slicoss/gbrcvucode.sys" 279 #define SLIC_RCV_FIRMWARE_OASIS "slicoss/oasisrcvucode.sys" 280 #define SLIC_FIRMWARE_MIN_SIZE 64 281 #define SLIC_FIRMWARE_MAX_SECTIONS 3 282 283 #define SLIC_MODEL_MOJAVE 0 284 #define SLIC_MODEL_OASIS 1 285 286 #define SLIC_INC_STATS_COUNTER(st, counter) \ 287 do { \ 288 u64_stats_update_begin(&(st)->syncp); \ 289 (st)->counter++; \ 290 u64_stats_update_end(&(st)->syncp); \ 291 } while (0) 292 293 #define SLIC_GET_STATS_COUNTER(newst, st, counter) \ 294 { \ 295 unsigned int start; \ 296 do { \ 297 start = u64_stats_fetch_begin_irq(&(st)->syncp); \ 298 newst = (st)->counter; \ 299 } while (u64_stats_fetch_retry_irq(&(st)->syncp, start)); \ 300 } 301 302 struct slic_upr { 303 dma_addr_t paddr; 304 unsigned int type; 305 struct list_head list; 306 }; 307 308 struct slic_upr_list { 309 bool pending; 310 struct list_head list; 311 /* upr list lock */ 312 spinlock_t lock; 313 }; 314 315 /* SLIC EEPROM structure for Mojave */ 316 struct slic_mojave_eeprom { 317 __le16 id; /* 00 EEPROM/FLASH Magic code 'A5A5'*/ 318 __le16 eeprom_code_size;/* 01 Size of EEPROM Codes (bytes * 4)*/ 319 __le16 flash_size; /* 02 Flash size */ 320 __le16 eeprom_size; /* 03 EEPROM Size */ 321 __le16 vendor_id; /* 04 Vendor ID */ 322 __le16 dev_id; /* 05 Device ID */ 323 u8 rev_id; /* 06 Revision ID */ 324 u8 class_code[3]; /* 07 Class Code */ 325 u8 irqpin_dbg; /* 08 Debug Interrupt pin */ 326 u8 irqpin; /* Network Interrupt Pin */ 327 u8 min_grant; /* 09 Minimum grant */ 328 u8 max_lat; /* Maximum Latency */ 329 __le16 pci_stat; /* 10 PCI Status */ 330 __le16 sub_vendor_id; /* 11 Subsystem Vendor Id */ 331 __le16 sub_id; /* 12 Subsystem ID */ 332 __le16 dev_id_dbg; /* 13 Debug Device Id */ 333 __le16 ramrom; /* 14 Dram/Rom function */ 334 __le16 dram_size2pci; /* 15 DRAM size to PCI (bytes * 64K) */ 335 __le16 rom_size2pci; /* 16 ROM extension size to PCI (bytes * 4k) */ 336 u8 pad[2]; /* 17 Padding */ 337 u8 freetime; /* 18 FreeTime setting */ 338 u8 ifctrl; /* 10-bit interface control (Mojave only) */ 339 __le16 dram_size; /* 19 DRAM size (bytes * 64k) */ 340 u8 mac[ETH_ALEN]; /* 20 MAC addresses */ 341 u8 mac2[ETH_ALEN]; 342 u8 pad2[6]; 343 u16 dev_id2; /* Device ID for 2nd PCI function */ 344 u8 irqpin2; /* Interrupt pin for 2nd PCI function */ 345 u8 class_code2[3]; /* Class Code for 2nd PCI function */ 346 u16 cfg_byte6; /* Config Byte 6 */ 347 u16 pme_cap; /* Power Mgment capabilities */ 348 u16 nwclk_ctrl; /* NetworkClockControls */ 349 u8 fru_format; /* Alacritech FRU format type */ 350 u8 fru_assembly[6]; /* Alacritech FRU information */ 351 u8 fru_rev[2]; 352 u8 fru_serial[14]; 353 u8 fru_pad[3]; 354 u8 oem_fru[28]; /* optional OEM FRU format type */ 355 u8 pad3[4]; /* Pad to 128 bytes - includes 2 cksum bytes 356 * (if OEM FRU info exists) and two unusable 357 * bytes at the end 358 */ 359 }; 360 361 /* SLIC EEPROM structure for Oasis */ 362 struct slic_oasis_eeprom { 363 __le16 id; /* 00 EEPROM/FLASH Magic code 'A5A5' */ 364 __le16 eeprom_code_size;/* 01 Size of EEPROM Codes (bytes * 4)*/ 365 __le16 spidev0_cfg; /* 02 Flash Config for SPI device 0 */ 366 __le16 spidev1_cfg; /* 03 Flash Config for SPI device 1 */ 367 __le16 vendor_id; /* 04 Vendor ID */ 368 __le16 dev_id; /* 05 Device ID (function 0) */ 369 u8 rev_id; /* 06 Revision ID */ 370 u8 class_code0[3]; /* 07 Class Code for PCI function 0 */ 371 u8 irqpin1; /* 08 Interrupt pin for PCI function 1*/ 372 u8 class_code1[3]; /* 09 Class Code for PCI function 1 */ 373 u8 irqpin2; /* 10 Interrupt pin for PCI function 2*/ 374 u8 irqpin0; /* Interrupt pin for PCI function 0*/ 375 u8 min_grant; /* 11 Minimum grant */ 376 u8 max_lat; /* Maximum Latency */ 377 __le16 sub_vendor_id; /* 12 Subsystem Vendor Id */ 378 __le16 sub_id; /* 13 Subsystem ID */ 379 __le16 flash_size; /* 14 Flash size (bytes / 4K) */ 380 __le16 dram_size2pci; /* 15 DRAM size to PCI (bytes / 64K) */ 381 __le16 rom_size2pci; /* 16 Flash (ROM extension) size to PCI 382 * (bytes / 4K) 383 */ 384 __le16 dev_id1; /* 17 Device Id (function 1) */ 385 __le16 dev_id2; /* 18 Device Id (function 2) */ 386 __le16 dev_stat_cfg; /* 19 Device Status Config Bytes 6-7 */ 387 __le16 pme_cap; /* 20 Power Mgment capabilities */ 388 u8 msi_cap; /* 21 MSI capabilities */ 389 u8 clock_div; /* Clock divider */ 390 __le16 pci_stat_lo; /* 22 PCI Status bits 15:0 */ 391 __le16 pci_stat_hi; /* 23 PCI Status bits 31:16 */ 392 __le16 dram_cfg_lo; /* 24 DRAM Configuration bits 15:0 */ 393 __le16 dram_cfg_hi; /* 25 DRAM Configuration bits 31:16 */ 394 __le16 dram_size; /* 26 DRAM size (bytes / 64K) */ 395 __le16 gpio_tbi_ctrl; /* 27 GPIO/TBI controls for functions 1/0 */ 396 __le16 eeprom_size; /* 28 EEPROM Size */ 397 u8 mac[ETH_ALEN]; /* 29 MAC addresses (2 ports) */ 398 u8 mac2[ETH_ALEN]; 399 u8 fru_format; /* 35 Alacritech FRU format type */ 400 u8 fru_assembly[6]; /* Alacritech FRU information */ 401 u8 fru_rev[2]; 402 u8 fru_serial[14]; 403 u8 fru_pad[3]; 404 u8 oem_fru[28]; /* optional OEM FRU information */ 405 u8 pad[4]; /* Pad to 128 bytes - includes 2 checksum bytes 406 * (if OEM FRU info exists) and two unusable 407 * bytes at the end 408 */ 409 }; 410 411 struct slic_stats { 412 u64 rx_packets; 413 u64 rx_bytes; 414 u64 rx_mcasts; 415 u64 rx_errors; 416 u64 tx_packets; 417 u64 tx_bytes; 418 /* HW STATS */ 419 u64 rx_buff_miss; 420 u64 tx_dropped; 421 u64 irq_errs; 422 /* transport layer */ 423 u64 rx_tpcsum; 424 u64 rx_tpoflow; 425 u64 rx_tphlen; 426 /* ip layer */ 427 u64 rx_ipcsum; 428 u64 rx_iplen; 429 u64 rx_iphlen; 430 /* link layer */ 431 u64 rx_early; 432 u64 rx_buffoflow; 433 u64 rx_lcode; 434 u64 rx_drbl; 435 u64 rx_crc; 436 u64 rx_oflow802; 437 u64 rx_uflow802; 438 /* oasis only */ 439 u64 tx_carrier; 440 struct u64_stats_sync syncp; 441 }; 442 443 struct slic_shmem_data { 444 __le32 isr; 445 __le32 link; 446 }; 447 448 struct slic_shmem { 449 dma_addr_t isr_paddr; 450 dma_addr_t link_paddr; 451 struct slic_shmem_data *shmem_data; 452 }; 453 454 struct slic_rx_info_oasis { 455 __le32 frame_status; 456 __le32 frame_status_b; 457 __le32 time_stamp; 458 __le32 checksum; 459 }; 460 461 struct slic_rx_info_mojave { 462 __le32 frame_status; 463 __le16 byte_cnt; 464 __le16 tp_chksum; 465 __le16 ctx_hash; 466 __le16 mac_hash; 467 __le16 buff_lnk; 468 }; 469 470 struct slic_stat_desc { 471 __le32 hnd; 472 __u8 pad[8]; 473 __le32 status; 474 __u8 pad2[16]; 475 }; 476 477 struct slic_stat_queue { 478 struct slic_stat_desc *descs[SLIC_NUM_STAT_DESC_ARRAYS]; 479 dma_addr_t paddr[SLIC_NUM_STAT_DESC_ARRAYS]; 480 unsigned int addr_offset[SLIC_NUM_STAT_DESC_ARRAYS]; 481 unsigned int active_array; 482 unsigned int len; 483 unsigned int done_idx; 484 size_t mem_size; 485 }; 486 487 struct slic_tx_desc { 488 __le32 hnd; 489 __le32 rsvd; 490 u8 cmd; 491 u8 flags; 492 __le16 rsvd2; 493 __le32 totlen; 494 __le32 paddrl; 495 __le32 paddrh; 496 __le32 len; 497 __le32 type; 498 }; 499 500 struct slic_tx_buffer { 501 struct sk_buff *skb; 502 DEFINE_DMA_UNMAP_ADDR(map_addr); 503 DEFINE_DMA_UNMAP_LEN(map_len); 504 struct slic_tx_desc *desc; 505 dma_addr_t desc_paddr; 506 }; 507 508 struct slic_tx_queue { 509 struct dma_pool *dma_pool; 510 struct slic_tx_buffer *txbuffs; 511 unsigned int len; 512 unsigned int put_idx; 513 unsigned int done_idx; 514 }; 515 516 struct slic_rx_desc { 517 u8 pad[16]; 518 __le32 buffer; 519 __le32 length; 520 __le32 status; 521 }; 522 523 struct slic_rx_buffer { 524 struct sk_buff *skb; 525 DEFINE_DMA_UNMAP_ADDR(map_addr); 526 DEFINE_DMA_UNMAP_LEN(map_len); 527 unsigned int addr_offset; 528 }; 529 530 struct slic_rx_queue { 531 struct slic_rx_buffer *rxbuffs; 532 unsigned int len; 533 unsigned int done_idx; 534 unsigned int put_idx; 535 }; 536 537 struct slic_device { 538 struct pci_dev *pdev; 539 struct net_device *netdev; 540 void __iomem *regs; 541 /* upper address setting lock */ 542 spinlock_t upper_lock; 543 struct slic_shmem shmem; 544 struct napi_struct napi; 545 struct slic_rx_queue rxq; 546 struct slic_tx_queue txq; 547 struct slic_stat_queue stq; 548 struct slic_stats stats; 549 struct slic_upr_list upr_list; 550 /* link configuration lock */ 551 spinlock_t link_lock; 552 bool promisc; 553 int speed; 554 unsigned int duplex; 555 bool is_fiber; 556 unsigned char model; 557 }; 558 559 static inline u32 slic_read(struct slic_device *sdev, unsigned int reg) 560 { 561 return ioread32(sdev->regs + reg); 562 } 563 564 static inline void slic_write(struct slic_device *sdev, unsigned int reg, 565 u32 val) 566 { 567 iowrite32(val, sdev->regs + reg); 568 } 569 570 static inline void slic_flush_write(struct slic_device *sdev) 571 { 572 (void)ioread32(sdev->regs + SLIC_REG_HOSTID); 573 } 574 575 #endif /* _SLIC_H */ 576