1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2025 AIROHA Inc 4 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 5 */ 6 7 #include <linux/devcoredump.h> 8 #include <linux/firmware.h> 9 #include <linux/platform_device.h> 10 #include <linux/of_net.h> 11 #include <linux/of_platform.h> 12 #include <linux/of_reserved_mem.h> 13 #include <linux/regmap.h> 14 15 #include "airoha_eth.h" 16 17 #define NPU_EN7581_FIRMWARE_DATA "airoha/en7581_npu_data.bin" 18 #define NPU_EN7581_FIRMWARE_RV32 "airoha/en7581_npu_rv32.bin" 19 #define NPU_EN7581_7996_FIRMWARE_DATA "airoha/en7581_MT7996_npu_data.bin" 20 #define NPU_EN7581_7996_FIRMWARE_RV32 "airoha/en7581_MT7996_npu_rv32.bin" 21 #define NPU_AN7583_FIRMWARE_DATA "airoha/an7583_npu_data.bin" 22 #define NPU_AN7583_FIRMWARE_RV32 "airoha/an7583_npu_rv32.bin" 23 #define NPU_EN7581_FIRMWARE_RV32_MAX_SIZE 0x200000 24 #define NPU_EN7581_FIRMWARE_DATA_MAX_SIZE 0x10000 25 #define NPU_DUMP_SIZE 512 26 27 #define REG_NPU_LOCAL_SRAM 0x0 28 29 #define NPU_PC_BASE_ADDR 0x305000 30 #define REG_PC_DBG(_n) (0x305000 + ((_n) * 0x100)) 31 32 #define NPU_CLUSTER_BASE_ADDR 0x306000 33 34 #define REG_CR_BOOT_TRIGGER (NPU_CLUSTER_BASE_ADDR + 0x000) 35 #define REG_CR_BOOT_CONFIG (NPU_CLUSTER_BASE_ADDR + 0x004) 36 #define REG_CR_BOOT_BASE(_n) (NPU_CLUSTER_BASE_ADDR + 0x020 + ((_n) << 2)) 37 38 #define NPU_MBOX_BASE_ADDR 0x30c000 39 40 #define REG_CR_MBOX_INT_STATUS (NPU_MBOX_BASE_ADDR + 0x000) 41 #define MBOX_INT_STATUS_MASK BIT(8) 42 43 #define REG_CR_MBOX_INT_MASK(_n) (NPU_MBOX_BASE_ADDR + 0x004 + ((_n) << 2)) 44 #define REG_CR_MBQ0_CTRL(_n) (NPU_MBOX_BASE_ADDR + 0x030 + ((_n) << 2)) 45 #define REG_CR_MBQ8_CTRL(_n) (NPU_MBOX_BASE_ADDR + 0x0b0 + ((_n) << 2)) 46 #define REG_CR_NPU_MIB(_n) (NPU_MBOX_BASE_ADDR + 0x140 + ((_n) << 2)) 47 48 #define NPU_WLAN_BASE_ADDR 0x30d000 49 50 #define REG_IRQ_STATUS (NPU_WLAN_BASE_ADDR + 0x030) 51 #define REG_IRQ_RXDONE(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 2) + 0x034) 52 #define NPU_IRQ_RX_MASK(_n) ((_n) == 1 ? BIT(17) : BIT(16)) 53 54 #define REG_TX_BASE(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x080) 55 #define REG_TX_DSCP_NUM(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x084) 56 #define REG_TX_CPU_IDX(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x088) 57 #define REG_TX_DMA_IDX(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x08c) 58 59 #define REG_RX_BASE(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x180) 60 #define REG_RX_DSCP_NUM(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x184) 61 #define REG_RX_CPU_IDX(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x188) 62 #define REG_RX_DMA_IDX(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x18c) 63 64 #define NPU_TIMER_BASE_ADDR 0x310100 65 #define REG_WDT_TIMER_CTRL(_n) (NPU_TIMER_BASE_ADDR + ((_n) * 0x100)) 66 #define WDT_EN_MASK BIT(25) 67 #define WDT_INTR_MASK BIT(21) 68 69 enum { 70 NPU_OP_SET = 1, 71 NPU_OP_SET_NO_WAIT, 72 NPU_OP_GET, 73 NPU_OP_GET_NO_WAIT, 74 }; 75 76 enum { 77 NPU_FUNC_WIFI, 78 NPU_FUNC_TUNNEL, 79 NPU_FUNC_NOTIFY, 80 NPU_FUNC_DBA, 81 NPU_FUNC_TR471, 82 NPU_FUNC_PPE, 83 }; 84 85 enum { 86 NPU_MBOX_ERROR, 87 NPU_MBOX_SUCCESS, 88 }; 89 90 enum { 91 PPE_FUNC_SET_WAIT, 92 PPE_FUNC_SET_WAIT_HWNAT_INIT, 93 PPE_FUNC_SET_WAIT_HWNAT_DEINIT, 94 PPE_FUNC_SET_WAIT_API, 95 PPE_FUNC_SET_WAIT_FLOW_STATS_SETUP, 96 }; 97 98 enum { 99 PPE2_SRAM_SET_ENTRY, 100 PPE_SRAM_SET_ENTRY, 101 PPE_SRAM_SET_VAL, 102 PPE_SRAM_RESET_VAL, 103 }; 104 105 enum { 106 QDMA_WAN_ETHER = 1, 107 QDMA_WAN_PON_XDSL, 108 }; 109 110 struct airoha_npu_fw { 111 const char *name; 112 int max_size; 113 }; 114 115 struct airoha_npu_soc_data { 116 struct airoha_npu_fw fw_rv32; 117 struct airoha_npu_fw fw_data; 118 }; 119 120 #define MBOX_MSG_FUNC_ID GENMASK(14, 11) 121 #define MBOX_MSG_STATIC_BUF BIT(5) 122 #define MBOX_MSG_STATUS GENMASK(4, 2) 123 #define MBOX_MSG_DONE BIT(1) 124 #define MBOX_MSG_WAIT_RSP BIT(0) 125 126 #define PPE_TYPE_L2B_IPV4 2 127 #define PPE_TYPE_L2B_IPV4_IPV6 3 128 129 struct ppe_mbox_data { 130 u32 func_type; 131 u32 func_id; 132 union { 133 struct { 134 u8 cds; 135 u8 xpon_hal_api; 136 u8 wan_xsi; 137 u8 ct_joyme4; 138 u8 max_packet; 139 u8 rsv[3]; 140 u32 ppe_type; 141 u32 wan_mode; 142 u32 wan_sel; 143 } init_info; 144 struct { 145 u32 func_id; 146 u32 size; 147 u32 data; 148 } set_info; 149 struct { 150 u32 npu_stats_addr; 151 u32 foe_stats_addr; 152 } stats_info; 153 }; 154 }; 155 156 struct wlan_mbox_data { 157 u32 ifindex:4; 158 u32 func_type:4; 159 u32 func_id; 160 DECLARE_FLEX_ARRAY(u8, d); 161 }; 162 163 static int airoha_npu_send_msg(struct airoha_npu *npu, int func_id, 164 void *p, int size) 165 { 166 u16 core = 0; /* FIXME */ 167 u32 val, offset = core << 4; 168 dma_addr_t dma_addr; 169 int ret; 170 171 dma_addr = dma_map_single(npu->dev, p, size, DMA_TO_DEVICE); 172 ret = dma_mapping_error(npu->dev, dma_addr); 173 if (ret) 174 return ret; 175 176 spin_lock_bh(&npu->cores[core].lock); 177 178 regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(0) + offset, dma_addr); 179 regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(1) + offset, size); 180 regmap_read(npu->regmap, REG_CR_MBQ0_CTRL(2) + offset, &val); 181 regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(2) + offset, val + 1); 182 val = FIELD_PREP(MBOX_MSG_FUNC_ID, func_id) | MBOX_MSG_WAIT_RSP; 183 regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(3) + offset, val); 184 185 ret = regmap_read_poll_timeout_atomic(npu->regmap, 186 REG_CR_MBQ0_CTRL(3) + offset, 187 val, (val & MBOX_MSG_DONE), 188 100, 100 * MSEC_PER_SEC); 189 if (!ret && FIELD_GET(MBOX_MSG_STATUS, val) != NPU_MBOX_SUCCESS) 190 ret = -EINVAL; 191 192 spin_unlock_bh(&npu->cores[core].lock); 193 194 dma_unmap_single(npu->dev, dma_addr, size, DMA_TO_DEVICE); 195 196 return ret; 197 } 198 199 static int airoha_npu_load_firmware(struct device *dev, void __iomem *addr, 200 const char *fw_name, int fw_max_size) 201 { 202 const struct firmware *fw; 203 int ret; 204 205 ret = request_firmware(&fw, fw_name, dev); 206 if (ret) 207 return ret == -ENOENT ? -EPROBE_DEFER : ret; 208 209 if (fw->size > fw_max_size) { 210 dev_err(dev, "%s: fw size too overlimit (%zu)\n", 211 fw_name, fw->size); 212 ret = -E2BIG; 213 goto out; 214 } 215 216 memcpy_toio(addr, fw->data, fw->size); 217 out: 218 release_firmware(fw); 219 220 return ret; 221 } 222 223 static int 224 airoha_npu_load_firmware_from_dts(struct device *dev, void __iomem *addr, 225 void __iomem *base) 226 { 227 const char *fw_names[2]; 228 int ret; 229 230 ret = of_property_read_string_array(dev->of_node, "firmware-name", 231 fw_names, ARRAY_SIZE(fw_names)); 232 if (ret != ARRAY_SIZE(fw_names)) 233 return -EINVAL; 234 235 ret = airoha_npu_load_firmware(dev, addr, fw_names[0], 236 NPU_EN7581_FIRMWARE_RV32_MAX_SIZE); 237 if (ret) 238 return ret; 239 240 return airoha_npu_load_firmware(dev, base + REG_NPU_LOCAL_SRAM, 241 fw_names[1], 242 NPU_EN7581_FIRMWARE_DATA_MAX_SIZE); 243 } 244 245 static int airoha_npu_run_firmware(struct device *dev, void __iomem *base, 246 struct resource *res) 247 { 248 const struct airoha_npu_soc_data *soc; 249 void __iomem *addr; 250 int ret; 251 252 soc = of_device_get_match_data(dev); 253 if (!soc) 254 return -EINVAL; 255 256 addr = devm_ioremap_resource(dev, res); 257 if (IS_ERR(addr)) 258 return PTR_ERR(addr); 259 260 /* Try to load firmware images using the firmware names provided via 261 * dts if available. 262 */ 263 if (of_find_property(dev->of_node, "firmware-name", NULL)) 264 return airoha_npu_load_firmware_from_dts(dev, addr, base); 265 266 /* Load rv32 npu firmware */ 267 ret = airoha_npu_load_firmware(dev, addr, soc->fw_rv32.name, 268 soc->fw_rv32.max_size); 269 if (ret) 270 return ret; 271 272 /* Load data npu firmware */ 273 return airoha_npu_load_firmware(dev, base + REG_NPU_LOCAL_SRAM, 274 soc->fw_data.name, 275 soc->fw_data.max_size); 276 } 277 278 static irqreturn_t airoha_npu_mbox_handler(int irq, void *npu_instance) 279 { 280 struct airoha_npu *npu = npu_instance; 281 282 /* clear mbox interrupt status */ 283 regmap_write(npu->regmap, REG_CR_MBOX_INT_STATUS, 284 MBOX_INT_STATUS_MASK); 285 286 /* acknowledge npu */ 287 regmap_update_bits(npu->regmap, REG_CR_MBQ8_CTRL(3), 288 MBOX_MSG_STATUS | MBOX_MSG_DONE, MBOX_MSG_DONE); 289 290 return IRQ_HANDLED; 291 } 292 293 static void airoha_npu_wdt_work(struct work_struct *work) 294 { 295 struct airoha_npu_core *core; 296 struct airoha_npu *npu; 297 void *dump; 298 u32 val[3]; 299 int c; 300 301 core = container_of(work, struct airoha_npu_core, wdt_work); 302 npu = core->npu; 303 304 dump = vzalloc(NPU_DUMP_SIZE); 305 if (!dump) 306 return; 307 308 c = core - &npu->cores[0]; 309 regmap_bulk_read(npu->regmap, REG_PC_DBG(c), val, ARRAY_SIZE(val)); 310 snprintf(dump, NPU_DUMP_SIZE, "PC: %08x SP: %08x LR: %08x\n", 311 val[0], val[1], val[2]); 312 313 dev_coredumpv(npu->dev, dump, NPU_DUMP_SIZE, GFP_KERNEL); 314 } 315 316 static irqreturn_t airoha_npu_wdt_handler(int irq, void *core_instance) 317 { 318 struct airoha_npu_core *core = core_instance; 319 struct airoha_npu *npu = core->npu; 320 int c = core - &npu->cores[0]; 321 u32 val; 322 323 regmap_set_bits(npu->regmap, REG_WDT_TIMER_CTRL(c), WDT_INTR_MASK); 324 if (!regmap_read(npu->regmap, REG_WDT_TIMER_CTRL(c), &val) && 325 FIELD_GET(WDT_EN_MASK, val)) 326 schedule_work(&core->wdt_work); 327 328 return IRQ_HANDLED; 329 } 330 331 static int airoha_npu_ppe_init(struct airoha_npu *npu) 332 { 333 struct ppe_mbox_data *ppe_data; 334 int err; 335 336 ppe_data = kzalloc(sizeof(*ppe_data), GFP_KERNEL); 337 if (!ppe_data) 338 return -ENOMEM; 339 340 ppe_data->func_type = NPU_OP_SET; 341 ppe_data->func_id = PPE_FUNC_SET_WAIT_HWNAT_INIT; 342 ppe_data->init_info.ppe_type = PPE_TYPE_L2B_IPV4_IPV6; 343 ppe_data->init_info.wan_mode = QDMA_WAN_ETHER; 344 345 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data, 346 sizeof(*ppe_data)); 347 kfree(ppe_data); 348 349 return err; 350 } 351 352 static int airoha_npu_ppe_deinit(struct airoha_npu *npu) 353 { 354 struct ppe_mbox_data *ppe_data; 355 int err; 356 357 ppe_data = kzalloc(sizeof(*ppe_data), GFP_KERNEL); 358 if (!ppe_data) 359 return -ENOMEM; 360 361 ppe_data->func_type = NPU_OP_SET; 362 ppe_data->func_id = PPE_FUNC_SET_WAIT_HWNAT_DEINIT; 363 364 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data, 365 sizeof(*ppe_data)); 366 kfree(ppe_data); 367 368 return err; 369 } 370 371 static int airoha_npu_ppe_flush_sram_entries(struct airoha_npu *npu, 372 dma_addr_t foe_addr, 373 int sram_num_entries) 374 { 375 struct ppe_mbox_data *ppe_data; 376 int err; 377 378 ppe_data = kzalloc(sizeof(*ppe_data), GFP_KERNEL); 379 if (!ppe_data) 380 return -ENOMEM; 381 382 ppe_data->func_type = NPU_OP_SET; 383 ppe_data->func_id = PPE_FUNC_SET_WAIT_API; 384 ppe_data->set_info.func_id = PPE_SRAM_RESET_VAL; 385 ppe_data->set_info.data = foe_addr; 386 ppe_data->set_info.size = sram_num_entries; 387 388 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data, 389 sizeof(*ppe_data)); 390 kfree(ppe_data); 391 392 return err; 393 } 394 395 static int airoha_npu_foe_commit_entry(struct airoha_npu *npu, 396 dma_addr_t foe_addr, 397 u32 entry_size, u32 hash, bool ppe2) 398 { 399 struct ppe_mbox_data *ppe_data; 400 int err; 401 402 ppe_data = kzalloc(sizeof(*ppe_data), GFP_ATOMIC); 403 if (!ppe_data) 404 return -ENOMEM; 405 406 ppe_data->func_type = NPU_OP_SET; 407 ppe_data->func_id = PPE_FUNC_SET_WAIT_API; 408 ppe_data->set_info.data = foe_addr; 409 ppe_data->set_info.size = entry_size; 410 ppe_data->set_info.func_id = ppe2 ? PPE2_SRAM_SET_ENTRY 411 : PPE_SRAM_SET_ENTRY; 412 413 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data, 414 sizeof(*ppe_data)); 415 if (err) 416 goto out; 417 418 ppe_data->set_info.func_id = PPE_SRAM_SET_VAL; 419 ppe_data->set_info.data = hash; 420 ppe_data->set_info.size = sizeof(u32); 421 422 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data, 423 sizeof(*ppe_data)); 424 out: 425 kfree(ppe_data); 426 427 return err; 428 } 429 430 static int airoha_npu_ppe_stats_setup(struct airoha_npu *npu, 431 dma_addr_t foe_stats_addr, 432 u32 num_stats_entries) 433 { 434 int err, size = num_stats_entries * sizeof(*npu->stats); 435 struct ppe_mbox_data *ppe_data; 436 437 ppe_data = kzalloc(sizeof(*ppe_data), GFP_ATOMIC); 438 if (!ppe_data) 439 return -ENOMEM; 440 441 ppe_data->func_type = NPU_OP_SET; 442 ppe_data->func_id = PPE_FUNC_SET_WAIT_FLOW_STATS_SETUP; 443 ppe_data->stats_info.foe_stats_addr = foe_stats_addr; 444 445 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data, 446 sizeof(*ppe_data)); 447 if (err) 448 goto out; 449 450 npu->stats = devm_ioremap(npu->dev, 451 ppe_data->stats_info.npu_stats_addr, 452 size); 453 if (!npu->stats) 454 err = -ENOMEM; 455 out: 456 kfree(ppe_data); 457 458 return err; 459 } 460 461 static int airoha_npu_wlan_msg_send(struct airoha_npu *npu, int ifindex, 462 enum airoha_npu_wlan_set_cmd func_id, 463 void *data, int data_len, gfp_t gfp) 464 { 465 struct wlan_mbox_data *wlan_data; 466 int err, len; 467 468 len = sizeof(*wlan_data) + data_len; 469 wlan_data = kzalloc(len, gfp); 470 if (!wlan_data) 471 return -ENOMEM; 472 473 wlan_data->ifindex = ifindex; 474 wlan_data->func_type = NPU_OP_SET; 475 wlan_data->func_id = func_id; 476 memcpy(wlan_data->d, data, data_len); 477 478 err = airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len); 479 kfree(wlan_data); 480 481 return err; 482 } 483 484 static int airoha_npu_wlan_msg_get(struct airoha_npu *npu, int ifindex, 485 enum airoha_npu_wlan_get_cmd func_id, 486 void *data, int data_len, gfp_t gfp) 487 { 488 struct wlan_mbox_data *wlan_data; 489 int err, len; 490 491 len = sizeof(*wlan_data) + data_len; 492 wlan_data = kzalloc(len, gfp); 493 if (!wlan_data) 494 return -ENOMEM; 495 496 wlan_data->ifindex = ifindex; 497 wlan_data->func_type = NPU_OP_GET; 498 wlan_data->func_id = func_id; 499 500 err = airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len); 501 if (!err) 502 memcpy(data, wlan_data->d, data_len); 503 kfree(wlan_data); 504 505 return err; 506 } 507 508 static int 509 airoha_npu_wlan_set_reserved_memory(struct airoha_npu *npu, 510 int ifindex, const char *name, 511 enum airoha_npu_wlan_set_cmd func_id) 512 { 513 struct device *dev = npu->dev; 514 struct resource res; 515 int err; 516 u32 val; 517 518 err = of_reserved_mem_region_to_resource_byname(dev->of_node, name, 519 &res); 520 if (err) 521 return err; 522 523 val = res.start; 524 return airoha_npu_wlan_msg_send(npu, ifindex, func_id, &val, 525 sizeof(val), GFP_KERNEL); 526 } 527 528 static int airoha_npu_wlan_init_memory(struct airoha_npu *npu) 529 { 530 enum airoha_npu_wlan_set_cmd cmd = WLAN_FUNC_SET_WAIT_NPU_BAND0_ONCPU; 531 u32 val = 0; 532 int err; 533 534 err = airoha_npu_wlan_msg_send(npu, 1, cmd, &val, sizeof(val), 535 GFP_KERNEL); 536 if (err) 537 return err; 538 539 cmd = WLAN_FUNC_SET_WAIT_TX_BUF_CHECK_ADDR; 540 err = airoha_npu_wlan_set_reserved_memory(npu, 0, "tx-bufid", cmd); 541 if (err) 542 return err; 543 544 cmd = WLAN_FUNC_SET_WAIT_PKT_BUF_ADDR; 545 err = airoha_npu_wlan_set_reserved_memory(npu, 0, "pkt", cmd); 546 if (err) 547 return err; 548 549 cmd = WLAN_FUNC_SET_WAIT_TX_PKT_BUF_ADDR; 550 err = airoha_npu_wlan_set_reserved_memory(npu, 0, "tx-pkt", cmd); 551 if (err) 552 return err; 553 554 if (of_property_match_string(npu->dev->of_node, "memory-region-names", 555 "ba") >= 0) { 556 cmd = WLAN_FUNC_SET_WAIT_DRAM_BA_NODE_ADDR; 557 err = airoha_npu_wlan_set_reserved_memory(npu, 0, "ba", cmd); 558 if (err) 559 return err; 560 } 561 562 cmd = WLAN_FUNC_SET_WAIT_IS_FORCE_TO_CPU; 563 return airoha_npu_wlan_msg_send(npu, 0, cmd, &val, sizeof(val), 564 GFP_KERNEL); 565 } 566 567 static u32 airoha_npu_wlan_queue_addr_get(struct airoha_npu *npu, int qid, 568 bool xmit) 569 { 570 if (xmit) 571 return REG_TX_BASE(qid + 2); 572 573 return REG_RX_BASE(qid); 574 } 575 576 static void airoha_npu_wlan_irq_status_set(struct airoha_npu *npu, u32 val) 577 { 578 regmap_write(npu->regmap, REG_IRQ_STATUS, val); 579 } 580 581 static u32 airoha_npu_wlan_irq_status_get(struct airoha_npu *npu, int q) 582 { 583 u32 val; 584 585 regmap_read(npu->regmap, REG_IRQ_STATUS, &val); 586 return val; 587 } 588 589 static void airoha_npu_wlan_irq_enable(struct airoha_npu *npu, int q) 590 { 591 regmap_set_bits(npu->regmap, REG_IRQ_RXDONE(q), NPU_IRQ_RX_MASK(q)); 592 } 593 594 static void airoha_npu_wlan_irq_disable(struct airoha_npu *npu, int q) 595 { 596 regmap_clear_bits(npu->regmap, REG_IRQ_RXDONE(q), NPU_IRQ_RX_MASK(q)); 597 } 598 599 struct airoha_npu *airoha_npu_get(struct device *dev) 600 { 601 struct platform_device *pdev; 602 struct device_node *np; 603 struct airoha_npu *npu; 604 605 np = of_parse_phandle(dev->of_node, "airoha,npu", 0); 606 if (!np) 607 return ERR_PTR(-ENODEV); 608 609 pdev = of_find_device_by_node(np); 610 611 if (!pdev) { 612 dev_err(dev, "cannot find device node %s\n", np->name); 613 of_node_put(np); 614 return ERR_PTR(-ENODEV); 615 } 616 of_node_put(np); 617 618 if (!try_module_get(THIS_MODULE)) { 619 dev_err(dev, "failed to get the device driver module\n"); 620 npu = ERR_PTR(-ENODEV); 621 goto error_pdev_put; 622 } 623 624 npu = platform_get_drvdata(pdev); 625 if (!npu) { 626 npu = ERR_PTR(-ENODEV); 627 goto error_module_put; 628 } 629 630 if (!device_link_add(dev, &pdev->dev, DL_FLAG_AUTOREMOVE_SUPPLIER)) { 631 dev_err(&pdev->dev, 632 "failed to create device link to consumer %s\n", 633 dev_name(dev)); 634 npu = ERR_PTR(-EINVAL); 635 goto error_module_put; 636 } 637 638 return npu; 639 640 error_module_put: 641 module_put(THIS_MODULE); 642 error_pdev_put: 643 platform_device_put(pdev); 644 645 return npu; 646 } 647 EXPORT_SYMBOL_GPL(airoha_npu_get); 648 649 void airoha_npu_put(struct airoha_npu *npu) 650 { 651 module_put(THIS_MODULE); 652 put_device(npu->dev); 653 } 654 EXPORT_SYMBOL_GPL(airoha_npu_put); 655 656 static const struct airoha_npu_soc_data en7581_npu_soc_data = { 657 .fw_rv32 = { 658 .name = NPU_EN7581_FIRMWARE_RV32, 659 .max_size = NPU_EN7581_FIRMWARE_RV32_MAX_SIZE, 660 }, 661 .fw_data = { 662 .name = NPU_EN7581_FIRMWARE_DATA, 663 .max_size = NPU_EN7581_FIRMWARE_DATA_MAX_SIZE, 664 }, 665 }; 666 667 static const struct airoha_npu_soc_data an7583_npu_soc_data = { 668 .fw_rv32 = { 669 .name = NPU_AN7583_FIRMWARE_RV32, 670 .max_size = NPU_EN7581_FIRMWARE_RV32_MAX_SIZE, 671 }, 672 .fw_data = { 673 .name = NPU_AN7583_FIRMWARE_DATA, 674 .max_size = NPU_EN7581_FIRMWARE_DATA_MAX_SIZE, 675 }, 676 }; 677 678 static const struct of_device_id of_airoha_npu_match[] = { 679 { .compatible = "airoha,en7581-npu", .data = &en7581_npu_soc_data }, 680 { .compatible = "airoha,an7583-npu", .data = &an7583_npu_soc_data }, 681 { /* sentinel */ } 682 }; 683 MODULE_DEVICE_TABLE(of, of_airoha_npu_match); 684 685 static const struct regmap_config regmap_config = { 686 .name = "npu", 687 .reg_bits = 32, 688 .val_bits = 32, 689 .reg_stride = 4, 690 .disable_locking = true, 691 }; 692 693 static int airoha_npu_probe(struct platform_device *pdev) 694 { 695 struct device *dev = &pdev->dev; 696 struct airoha_npu *npu; 697 struct resource res; 698 void __iomem *base; 699 int i, irq, err; 700 u32 val; 701 702 base = devm_platform_ioremap_resource(pdev, 0); 703 if (IS_ERR(base)) 704 return PTR_ERR(base); 705 706 npu = devm_kzalloc(dev, sizeof(*npu), GFP_KERNEL); 707 if (!npu) 708 return -ENOMEM; 709 710 npu->dev = dev; 711 npu->ops.ppe_init = airoha_npu_ppe_init; 712 npu->ops.ppe_deinit = airoha_npu_ppe_deinit; 713 npu->ops.ppe_init_stats = airoha_npu_ppe_stats_setup; 714 npu->ops.ppe_flush_sram_entries = airoha_npu_ppe_flush_sram_entries; 715 npu->ops.ppe_foe_commit_entry = airoha_npu_foe_commit_entry; 716 npu->ops.wlan_init_reserved_memory = airoha_npu_wlan_init_memory; 717 npu->ops.wlan_send_msg = airoha_npu_wlan_msg_send; 718 npu->ops.wlan_get_msg = airoha_npu_wlan_msg_get; 719 npu->ops.wlan_get_queue_addr = airoha_npu_wlan_queue_addr_get; 720 npu->ops.wlan_set_irq_status = airoha_npu_wlan_irq_status_set; 721 npu->ops.wlan_get_irq_status = airoha_npu_wlan_irq_status_get; 722 npu->ops.wlan_enable_irq = airoha_npu_wlan_irq_enable; 723 npu->ops.wlan_disable_irq = airoha_npu_wlan_irq_disable; 724 725 npu->regmap = devm_regmap_init_mmio(dev, base, ®map_config); 726 if (IS_ERR(npu->regmap)) 727 return PTR_ERR(npu->regmap); 728 729 err = of_reserved_mem_region_to_resource(dev->of_node, 0, &res); 730 if (err) 731 return err; 732 733 irq = platform_get_irq(pdev, 0); 734 if (irq < 0) 735 return irq; 736 737 err = devm_request_irq(dev, irq, airoha_npu_mbox_handler, 738 IRQF_SHARED, "airoha-npu-mbox", npu); 739 if (err) 740 return err; 741 742 for (i = 0; i < ARRAY_SIZE(npu->cores); i++) { 743 struct airoha_npu_core *core = &npu->cores[i]; 744 745 spin_lock_init(&core->lock); 746 core->npu = npu; 747 748 irq = platform_get_irq(pdev, i + 1); 749 if (irq < 0) 750 return irq; 751 752 err = devm_request_irq(dev, irq, airoha_npu_wdt_handler, 753 IRQF_SHARED, "airoha-npu-wdt", core); 754 if (err) 755 return err; 756 757 INIT_WORK(&core->wdt_work, airoha_npu_wdt_work); 758 } 759 760 /* wlan IRQ lines */ 761 for (i = 0; i < ARRAY_SIZE(npu->irqs); i++) { 762 irq = platform_get_irq(pdev, i + ARRAY_SIZE(npu->cores) + 1); 763 if (irq < 0) 764 return irq; 765 766 npu->irqs[i] = irq; 767 } 768 769 err = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); 770 if (err) 771 return err; 772 773 err = airoha_npu_run_firmware(dev, base, &res); 774 if (err) 775 return dev_err_probe(dev, err, "failed to run npu firmware\n"); 776 777 regmap_write(npu->regmap, REG_CR_NPU_MIB(10), 778 res.start + NPU_EN7581_FIRMWARE_RV32_MAX_SIZE); 779 regmap_write(npu->regmap, REG_CR_NPU_MIB(11), 0x40000); /* SRAM 256K */ 780 regmap_write(npu->regmap, REG_CR_NPU_MIB(12), 0); 781 regmap_write(npu->regmap, REG_CR_NPU_MIB(21), 1); 782 msleep(100); 783 784 /* setting booting address */ 785 for (i = 0; i < NPU_NUM_CORES; i++) 786 regmap_write(npu->regmap, REG_CR_BOOT_BASE(i), res.start); 787 usleep_range(1000, 2000); 788 789 /* enable NPU cores */ 790 regmap_write(npu->regmap, REG_CR_BOOT_CONFIG, 0xff); 791 regmap_write(npu->regmap, REG_CR_BOOT_TRIGGER, 0x1); 792 msleep(100); 793 794 if (!airoha_npu_wlan_msg_get(npu, 0, WLAN_FUNC_GET_WAIT_NPU_VERSION, 795 &val, sizeof(val), GFP_KERNEL)) 796 dev_info(dev, "NPU fw version: %0d.%d\n", 797 (val >> 16) & 0xffff, val & 0xffff); 798 799 platform_set_drvdata(pdev, npu); 800 801 return 0; 802 } 803 804 static void airoha_npu_remove(struct platform_device *pdev) 805 { 806 struct airoha_npu *npu = platform_get_drvdata(pdev); 807 int i; 808 809 for (i = 0; i < ARRAY_SIZE(npu->cores); i++) 810 cancel_work_sync(&npu->cores[i].wdt_work); 811 } 812 813 static struct platform_driver airoha_npu_driver = { 814 .probe = airoha_npu_probe, 815 .remove = airoha_npu_remove, 816 .driver = { 817 .name = "airoha-npu", 818 .of_match_table = of_airoha_npu_match, 819 }, 820 }; 821 module_platform_driver(airoha_npu_driver); 822 823 MODULE_FIRMWARE(NPU_EN7581_FIRMWARE_DATA); 824 MODULE_FIRMWARE(NPU_EN7581_FIRMWARE_RV32); 825 MODULE_FIRMWARE(NPU_EN7581_7996_FIRMWARE_DATA); 826 MODULE_FIRMWARE(NPU_EN7581_7996_FIRMWARE_RV32); 827 MODULE_FIRMWARE(NPU_AN7583_FIRMWARE_DATA); 828 MODULE_FIRMWARE(NPU_AN7583_FIRMWARE_RV32); 829 MODULE_LICENSE("GPL"); 830 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 831 MODULE_DESCRIPTION("Airoha Network Processor Unit driver"); 832