1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2025 AIROHA Inc 4 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 5 */ 6 7 #include <linux/devcoredump.h> 8 #include <linux/firmware.h> 9 #include <linux/platform_device.h> 10 #include <linux/of_net.h> 11 #include <linux/of_platform.h> 12 #include <linux/of_reserved_mem.h> 13 #include <linux/regmap.h> 14 #include <linux/soc/airoha/airoha_offload.h> 15 16 #include "airoha_eth.h" 17 18 #define NPU_EN7581_FIRMWARE_DATA "airoha/en7581_npu_data.bin" 19 #define NPU_EN7581_FIRMWARE_RV32 "airoha/en7581_npu_rv32.bin" 20 #define NPU_EN7581_FIRMWARE_RV32_MAX_SIZE 0x200000 21 #define NPU_EN7581_FIRMWARE_DATA_MAX_SIZE 0x10000 22 #define NPU_DUMP_SIZE 512 23 24 #define REG_NPU_LOCAL_SRAM 0x0 25 26 #define NPU_PC_BASE_ADDR 0x305000 27 #define REG_PC_DBG(_n) (0x305000 + ((_n) * 0x100)) 28 29 #define NPU_CLUSTER_BASE_ADDR 0x306000 30 31 #define REG_CR_BOOT_TRIGGER (NPU_CLUSTER_BASE_ADDR + 0x000) 32 #define REG_CR_BOOT_CONFIG (NPU_CLUSTER_BASE_ADDR + 0x004) 33 #define REG_CR_BOOT_BASE(_n) (NPU_CLUSTER_BASE_ADDR + 0x020 + ((_n) << 2)) 34 35 #define NPU_MBOX_BASE_ADDR 0x30c000 36 37 #define REG_CR_MBOX_INT_STATUS (NPU_MBOX_BASE_ADDR + 0x000) 38 #define MBOX_INT_STATUS_MASK BIT(8) 39 40 #define REG_CR_MBOX_INT_MASK(_n) (NPU_MBOX_BASE_ADDR + 0x004 + ((_n) << 2)) 41 #define REG_CR_MBQ0_CTRL(_n) (NPU_MBOX_BASE_ADDR + 0x030 + ((_n) << 2)) 42 #define REG_CR_MBQ8_CTRL(_n) (NPU_MBOX_BASE_ADDR + 0x0b0 + ((_n) << 2)) 43 #define REG_CR_NPU_MIB(_n) (NPU_MBOX_BASE_ADDR + 0x140 + ((_n) << 2)) 44 45 #define NPU_WLAN_BASE_ADDR 0x30d000 46 47 #define REG_IRQ_STATUS (NPU_WLAN_BASE_ADDR + 0x030) 48 #define REG_IRQ_RXDONE(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 2) + 0x034) 49 #define NPU_IRQ_RX_MASK(_n) ((_n) == 1 ? BIT(17) : BIT(16)) 50 51 #define REG_TX_BASE(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x080) 52 #define REG_TX_DSCP_NUM(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x084) 53 #define REG_TX_CPU_IDX(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x088) 54 #define REG_TX_DMA_IDX(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x08c) 55 56 #define REG_RX_BASE(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x180) 57 #define REG_RX_DSCP_NUM(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x184) 58 #define REG_RX_CPU_IDX(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x188) 59 #define REG_RX_DMA_IDX(_n) (NPU_WLAN_BASE_ADDR + ((_n) << 4) + 0x18c) 60 61 #define NPU_TIMER_BASE_ADDR 0x310100 62 #define REG_WDT_TIMER_CTRL(_n) (NPU_TIMER_BASE_ADDR + ((_n) * 0x100)) 63 #define WDT_EN_MASK BIT(25) 64 #define WDT_INTR_MASK BIT(21) 65 66 enum { 67 NPU_OP_SET = 1, 68 NPU_OP_SET_NO_WAIT, 69 NPU_OP_GET, 70 NPU_OP_GET_NO_WAIT, 71 }; 72 73 enum { 74 NPU_FUNC_WIFI, 75 NPU_FUNC_TUNNEL, 76 NPU_FUNC_NOTIFY, 77 NPU_FUNC_DBA, 78 NPU_FUNC_TR471, 79 NPU_FUNC_PPE, 80 }; 81 82 enum { 83 NPU_MBOX_ERROR, 84 NPU_MBOX_SUCCESS, 85 }; 86 87 enum { 88 PPE_FUNC_SET_WAIT, 89 PPE_FUNC_SET_WAIT_HWNAT_INIT, 90 PPE_FUNC_SET_WAIT_HWNAT_DEINIT, 91 PPE_FUNC_SET_WAIT_API, 92 PPE_FUNC_SET_WAIT_FLOW_STATS_SETUP, 93 }; 94 95 enum { 96 PPE2_SRAM_SET_ENTRY, 97 PPE_SRAM_SET_ENTRY, 98 PPE_SRAM_SET_VAL, 99 PPE_SRAM_RESET_VAL, 100 }; 101 102 enum { 103 QDMA_WAN_ETHER = 1, 104 QDMA_WAN_PON_XDSL, 105 }; 106 107 #define MBOX_MSG_FUNC_ID GENMASK(14, 11) 108 #define MBOX_MSG_STATIC_BUF BIT(5) 109 #define MBOX_MSG_STATUS GENMASK(4, 2) 110 #define MBOX_MSG_DONE BIT(1) 111 #define MBOX_MSG_WAIT_RSP BIT(0) 112 113 #define PPE_TYPE_L2B_IPV4 2 114 #define PPE_TYPE_L2B_IPV4_IPV6 3 115 116 struct ppe_mbox_data { 117 u32 func_type; 118 u32 func_id; 119 union { 120 struct { 121 u8 cds; 122 u8 xpon_hal_api; 123 u8 wan_xsi; 124 u8 ct_joyme4; 125 u8 max_packet; 126 u8 rsv[3]; 127 u32 ppe_type; 128 u32 wan_mode; 129 u32 wan_sel; 130 } init_info; 131 struct { 132 u32 func_id; 133 u32 size; 134 u32 data; 135 } set_info; 136 struct { 137 u32 npu_stats_addr; 138 u32 foe_stats_addr; 139 } stats_info; 140 }; 141 }; 142 143 struct wlan_mbox_data { 144 u32 ifindex:4; 145 u32 func_type:4; 146 u32 func_id; 147 DECLARE_FLEX_ARRAY(u8, d); 148 }; 149 150 static int airoha_npu_send_msg(struct airoha_npu *npu, int func_id, 151 void *p, int size) 152 { 153 u16 core = 0; /* FIXME */ 154 u32 val, offset = core << 4; 155 dma_addr_t dma_addr; 156 int ret; 157 158 dma_addr = dma_map_single(npu->dev, p, size, DMA_TO_DEVICE); 159 ret = dma_mapping_error(npu->dev, dma_addr); 160 if (ret) 161 return ret; 162 163 spin_lock_bh(&npu->cores[core].lock); 164 165 regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(0) + offset, dma_addr); 166 regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(1) + offset, size); 167 regmap_read(npu->regmap, REG_CR_MBQ0_CTRL(2) + offset, &val); 168 regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(2) + offset, val + 1); 169 val = FIELD_PREP(MBOX_MSG_FUNC_ID, func_id) | MBOX_MSG_WAIT_RSP; 170 regmap_write(npu->regmap, REG_CR_MBQ0_CTRL(3) + offset, val); 171 172 ret = regmap_read_poll_timeout_atomic(npu->regmap, 173 REG_CR_MBQ0_CTRL(3) + offset, 174 val, (val & MBOX_MSG_DONE), 175 100, 100 * MSEC_PER_SEC); 176 if (!ret && FIELD_GET(MBOX_MSG_STATUS, val) != NPU_MBOX_SUCCESS) 177 ret = -EINVAL; 178 179 spin_unlock_bh(&npu->cores[core].lock); 180 181 dma_unmap_single(npu->dev, dma_addr, size, DMA_TO_DEVICE); 182 183 return ret; 184 } 185 186 static int airoha_npu_run_firmware(struct device *dev, void __iomem *base, 187 struct resource *res) 188 { 189 const struct firmware *fw; 190 void __iomem *addr; 191 int ret; 192 193 ret = request_firmware(&fw, NPU_EN7581_FIRMWARE_RV32, dev); 194 if (ret) 195 return ret == -ENOENT ? -EPROBE_DEFER : ret; 196 197 if (fw->size > NPU_EN7581_FIRMWARE_RV32_MAX_SIZE) { 198 dev_err(dev, "%s: fw size too overlimit (%zu)\n", 199 NPU_EN7581_FIRMWARE_RV32, fw->size); 200 ret = -E2BIG; 201 goto out; 202 } 203 204 addr = devm_ioremap_resource(dev, res); 205 if (IS_ERR(addr)) { 206 ret = PTR_ERR(addr); 207 goto out; 208 } 209 210 memcpy_toio(addr, fw->data, fw->size); 211 release_firmware(fw); 212 213 ret = request_firmware(&fw, NPU_EN7581_FIRMWARE_DATA, dev); 214 if (ret) 215 return ret == -ENOENT ? -EPROBE_DEFER : ret; 216 217 if (fw->size > NPU_EN7581_FIRMWARE_DATA_MAX_SIZE) { 218 dev_err(dev, "%s: fw size too overlimit (%zu)\n", 219 NPU_EN7581_FIRMWARE_DATA, fw->size); 220 ret = -E2BIG; 221 goto out; 222 } 223 224 memcpy_toio(base + REG_NPU_LOCAL_SRAM, fw->data, fw->size); 225 out: 226 release_firmware(fw); 227 228 return ret; 229 } 230 231 static irqreturn_t airoha_npu_mbox_handler(int irq, void *npu_instance) 232 { 233 struct airoha_npu *npu = npu_instance; 234 235 /* clear mbox interrupt status */ 236 regmap_write(npu->regmap, REG_CR_MBOX_INT_STATUS, 237 MBOX_INT_STATUS_MASK); 238 239 /* acknowledge npu */ 240 regmap_update_bits(npu->regmap, REG_CR_MBQ8_CTRL(3), 241 MBOX_MSG_STATUS | MBOX_MSG_DONE, MBOX_MSG_DONE); 242 243 return IRQ_HANDLED; 244 } 245 246 static void airoha_npu_wdt_work(struct work_struct *work) 247 { 248 struct airoha_npu_core *core; 249 struct airoha_npu *npu; 250 void *dump; 251 u32 val[3]; 252 int c; 253 254 core = container_of(work, struct airoha_npu_core, wdt_work); 255 npu = core->npu; 256 257 dump = vzalloc(NPU_DUMP_SIZE); 258 if (!dump) 259 return; 260 261 c = core - &npu->cores[0]; 262 regmap_bulk_read(npu->regmap, REG_PC_DBG(c), val, ARRAY_SIZE(val)); 263 snprintf(dump, NPU_DUMP_SIZE, "PC: %08x SP: %08x LR: %08x\n", 264 val[0], val[1], val[2]); 265 266 dev_coredumpv(npu->dev, dump, NPU_DUMP_SIZE, GFP_KERNEL); 267 } 268 269 static irqreturn_t airoha_npu_wdt_handler(int irq, void *core_instance) 270 { 271 struct airoha_npu_core *core = core_instance; 272 struct airoha_npu *npu = core->npu; 273 int c = core - &npu->cores[0]; 274 u32 val; 275 276 regmap_set_bits(npu->regmap, REG_WDT_TIMER_CTRL(c), WDT_INTR_MASK); 277 if (!regmap_read(npu->regmap, REG_WDT_TIMER_CTRL(c), &val) && 278 FIELD_GET(WDT_EN_MASK, val)) 279 schedule_work(&core->wdt_work); 280 281 return IRQ_HANDLED; 282 } 283 284 static int airoha_npu_ppe_init(struct airoha_npu *npu) 285 { 286 struct ppe_mbox_data *ppe_data; 287 int err; 288 289 ppe_data = kzalloc(sizeof(*ppe_data), GFP_KERNEL); 290 if (!ppe_data) 291 return -ENOMEM; 292 293 ppe_data->func_type = NPU_OP_SET; 294 ppe_data->func_id = PPE_FUNC_SET_WAIT_HWNAT_INIT; 295 ppe_data->init_info.ppe_type = PPE_TYPE_L2B_IPV4_IPV6; 296 ppe_data->init_info.wan_mode = QDMA_WAN_ETHER; 297 298 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data, 299 sizeof(*ppe_data)); 300 kfree(ppe_data); 301 302 return err; 303 } 304 305 static int airoha_npu_ppe_deinit(struct airoha_npu *npu) 306 { 307 struct ppe_mbox_data *ppe_data; 308 int err; 309 310 ppe_data = kzalloc(sizeof(*ppe_data), GFP_KERNEL); 311 if (!ppe_data) 312 return -ENOMEM; 313 314 ppe_data->func_type = NPU_OP_SET; 315 ppe_data->func_id = PPE_FUNC_SET_WAIT_HWNAT_DEINIT; 316 317 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data, 318 sizeof(*ppe_data)); 319 kfree(ppe_data); 320 321 return err; 322 } 323 324 static int airoha_npu_ppe_flush_sram_entries(struct airoha_npu *npu, 325 dma_addr_t foe_addr, 326 int sram_num_entries) 327 { 328 struct ppe_mbox_data *ppe_data; 329 int err; 330 331 ppe_data = kzalloc(sizeof(*ppe_data), GFP_KERNEL); 332 if (!ppe_data) 333 return -ENOMEM; 334 335 ppe_data->func_type = NPU_OP_SET; 336 ppe_data->func_id = PPE_FUNC_SET_WAIT_API; 337 ppe_data->set_info.func_id = PPE_SRAM_RESET_VAL; 338 ppe_data->set_info.data = foe_addr; 339 ppe_data->set_info.size = sram_num_entries; 340 341 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data, 342 sizeof(*ppe_data)); 343 kfree(ppe_data); 344 345 return err; 346 } 347 348 static int airoha_npu_foe_commit_entry(struct airoha_npu *npu, 349 dma_addr_t foe_addr, 350 u32 entry_size, u32 hash, bool ppe2) 351 { 352 struct ppe_mbox_data *ppe_data; 353 int err; 354 355 ppe_data = kzalloc(sizeof(*ppe_data), GFP_ATOMIC); 356 if (!ppe_data) 357 return -ENOMEM; 358 359 ppe_data->func_type = NPU_OP_SET; 360 ppe_data->func_id = PPE_FUNC_SET_WAIT_API; 361 ppe_data->set_info.data = foe_addr; 362 ppe_data->set_info.size = entry_size; 363 ppe_data->set_info.func_id = ppe2 ? PPE2_SRAM_SET_ENTRY 364 : PPE_SRAM_SET_ENTRY; 365 366 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data, 367 sizeof(*ppe_data)); 368 if (err) 369 goto out; 370 371 ppe_data->set_info.func_id = PPE_SRAM_SET_VAL; 372 ppe_data->set_info.data = hash; 373 ppe_data->set_info.size = sizeof(u32); 374 375 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data, 376 sizeof(*ppe_data)); 377 out: 378 kfree(ppe_data); 379 380 return err; 381 } 382 383 static int airoha_npu_stats_setup(struct airoha_npu *npu, 384 dma_addr_t foe_stats_addr) 385 { 386 int err, size = PPE_STATS_NUM_ENTRIES * sizeof(*npu->stats); 387 struct ppe_mbox_data *ppe_data; 388 389 if (!size) /* flow stats are disabled */ 390 return 0; 391 392 ppe_data = kzalloc(sizeof(*ppe_data), GFP_ATOMIC); 393 if (!ppe_data) 394 return -ENOMEM; 395 396 ppe_data->func_type = NPU_OP_SET; 397 ppe_data->func_id = PPE_FUNC_SET_WAIT_FLOW_STATS_SETUP; 398 ppe_data->stats_info.foe_stats_addr = foe_stats_addr; 399 400 err = airoha_npu_send_msg(npu, NPU_FUNC_PPE, ppe_data, 401 sizeof(*ppe_data)); 402 if (err) 403 goto out; 404 405 npu->stats = devm_ioremap(npu->dev, 406 ppe_data->stats_info.npu_stats_addr, 407 size); 408 if (!npu->stats) 409 err = -ENOMEM; 410 out: 411 kfree(ppe_data); 412 413 return err; 414 } 415 416 static int airoha_npu_wlan_msg_send(struct airoha_npu *npu, int ifindex, 417 enum airoha_npu_wlan_set_cmd func_id, 418 void *data, int data_len, gfp_t gfp) 419 { 420 struct wlan_mbox_data *wlan_data; 421 int err, len; 422 423 len = sizeof(*wlan_data) + data_len; 424 wlan_data = kzalloc(len, gfp); 425 if (!wlan_data) 426 return -ENOMEM; 427 428 wlan_data->ifindex = ifindex; 429 wlan_data->func_type = NPU_OP_SET; 430 wlan_data->func_id = func_id; 431 memcpy(wlan_data->d, data, data_len); 432 433 err = airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len); 434 kfree(wlan_data); 435 436 return err; 437 } 438 439 static int airoha_npu_wlan_msg_get(struct airoha_npu *npu, int ifindex, 440 enum airoha_npu_wlan_get_cmd func_id, 441 void *data, int data_len, gfp_t gfp) 442 { 443 struct wlan_mbox_data *wlan_data; 444 int err, len; 445 446 len = sizeof(*wlan_data) + data_len; 447 wlan_data = kzalloc(len, gfp); 448 if (!wlan_data) 449 return -ENOMEM; 450 451 wlan_data->ifindex = ifindex; 452 wlan_data->func_type = NPU_OP_GET; 453 wlan_data->func_id = func_id; 454 455 err = airoha_npu_send_msg(npu, NPU_FUNC_WIFI, wlan_data, len); 456 if (!err) 457 memcpy(data, wlan_data->d, data_len); 458 kfree(wlan_data); 459 460 return err; 461 } 462 463 static int 464 airoha_npu_wlan_set_reserved_memory(struct airoha_npu *npu, 465 int ifindex, const char *name, 466 enum airoha_npu_wlan_set_cmd func_id) 467 { 468 struct device *dev = npu->dev; 469 struct resource res; 470 int err; 471 u32 val; 472 473 err = of_reserved_mem_region_to_resource_byname(dev->of_node, name, 474 &res); 475 if (err) 476 return err; 477 478 val = res.start; 479 return airoha_npu_wlan_msg_send(npu, ifindex, func_id, &val, 480 sizeof(val), GFP_KERNEL); 481 } 482 483 static int airoha_npu_wlan_init_memory(struct airoha_npu *npu) 484 { 485 enum airoha_npu_wlan_set_cmd cmd = WLAN_FUNC_SET_WAIT_NPU_BAND0_ONCPU; 486 u32 val = 0; 487 int err; 488 489 err = airoha_npu_wlan_msg_send(npu, 1, cmd, &val, sizeof(val), 490 GFP_KERNEL); 491 if (err) 492 return err; 493 494 cmd = WLAN_FUNC_SET_WAIT_TX_BUF_CHECK_ADDR; 495 err = airoha_npu_wlan_set_reserved_memory(npu, 0, "tx-bufid", cmd); 496 if (err) 497 return err; 498 499 cmd = WLAN_FUNC_SET_WAIT_PKT_BUF_ADDR; 500 err = airoha_npu_wlan_set_reserved_memory(npu, 0, "pkt", cmd); 501 if (err) 502 return err; 503 504 cmd = WLAN_FUNC_SET_WAIT_TX_PKT_BUF_ADDR; 505 err = airoha_npu_wlan_set_reserved_memory(npu, 0, "tx-pkt", cmd); 506 if (err) 507 return err; 508 509 cmd = WLAN_FUNC_SET_WAIT_IS_FORCE_TO_CPU; 510 return airoha_npu_wlan_msg_send(npu, 0, cmd, &val, sizeof(val), 511 GFP_KERNEL); 512 } 513 514 static u32 airoha_npu_wlan_queue_addr_get(struct airoha_npu *npu, int qid, 515 bool xmit) 516 { 517 if (xmit) 518 return REG_TX_BASE(qid + 2); 519 520 return REG_RX_BASE(qid); 521 } 522 523 static void airoha_npu_wlan_irq_status_set(struct airoha_npu *npu, u32 val) 524 { 525 regmap_write(npu->regmap, REG_IRQ_STATUS, val); 526 } 527 528 static u32 airoha_npu_wlan_irq_status_get(struct airoha_npu *npu, int q) 529 { 530 u32 val; 531 532 regmap_read(npu->regmap, REG_IRQ_STATUS, &val); 533 return val; 534 } 535 536 static void airoha_npu_wlan_irq_enable(struct airoha_npu *npu, int q) 537 { 538 regmap_set_bits(npu->regmap, REG_IRQ_RXDONE(q), NPU_IRQ_RX_MASK(q)); 539 } 540 541 static void airoha_npu_wlan_irq_disable(struct airoha_npu *npu, int q) 542 { 543 regmap_clear_bits(npu->regmap, REG_IRQ_RXDONE(q), NPU_IRQ_RX_MASK(q)); 544 } 545 546 struct airoha_npu *airoha_npu_get(struct device *dev, dma_addr_t *stats_addr) 547 { 548 struct platform_device *pdev; 549 struct device_node *np; 550 struct airoha_npu *npu; 551 552 np = of_parse_phandle(dev->of_node, "airoha,npu", 0); 553 if (!np) 554 return ERR_PTR(-ENODEV); 555 556 pdev = of_find_device_by_node(np); 557 558 if (!pdev) { 559 dev_err(dev, "cannot find device node %s\n", np->name); 560 of_node_put(np); 561 return ERR_PTR(-ENODEV); 562 } 563 of_node_put(np); 564 565 if (!try_module_get(THIS_MODULE)) { 566 dev_err(dev, "failed to get the device driver module\n"); 567 npu = ERR_PTR(-ENODEV); 568 goto error_pdev_put; 569 } 570 571 npu = platform_get_drvdata(pdev); 572 if (!npu) { 573 npu = ERR_PTR(-ENODEV); 574 goto error_module_put; 575 } 576 577 if (!device_link_add(dev, &pdev->dev, DL_FLAG_AUTOREMOVE_SUPPLIER)) { 578 dev_err(&pdev->dev, 579 "failed to create device link to consumer %s\n", 580 dev_name(dev)); 581 npu = ERR_PTR(-EINVAL); 582 goto error_module_put; 583 } 584 585 if (stats_addr) { 586 int err; 587 588 err = airoha_npu_stats_setup(npu, *stats_addr); 589 if (err) { 590 dev_err(dev, "failed to allocate npu stats buffer\n"); 591 npu = ERR_PTR(err); 592 goto error_module_put; 593 } 594 } 595 596 return npu; 597 598 error_module_put: 599 module_put(THIS_MODULE); 600 error_pdev_put: 601 platform_device_put(pdev); 602 603 return npu; 604 } 605 EXPORT_SYMBOL_GPL(airoha_npu_get); 606 607 void airoha_npu_put(struct airoha_npu *npu) 608 { 609 module_put(THIS_MODULE); 610 put_device(npu->dev); 611 } 612 EXPORT_SYMBOL_GPL(airoha_npu_put); 613 614 static const struct of_device_id of_airoha_npu_match[] = { 615 { .compatible = "airoha,en7581-npu" }, 616 { /* sentinel */ } 617 }; 618 MODULE_DEVICE_TABLE(of, of_airoha_npu_match); 619 620 static const struct regmap_config regmap_config = { 621 .name = "npu", 622 .reg_bits = 32, 623 .val_bits = 32, 624 .reg_stride = 4, 625 .disable_locking = true, 626 }; 627 628 static int airoha_npu_probe(struct platform_device *pdev) 629 { 630 struct device *dev = &pdev->dev; 631 struct airoha_npu *npu; 632 struct resource res; 633 void __iomem *base; 634 int i, irq, err; 635 636 base = devm_platform_ioremap_resource(pdev, 0); 637 if (IS_ERR(base)) 638 return PTR_ERR(base); 639 640 npu = devm_kzalloc(dev, sizeof(*npu), GFP_KERNEL); 641 if (!npu) 642 return -ENOMEM; 643 644 npu->dev = dev; 645 npu->ops.ppe_init = airoha_npu_ppe_init; 646 npu->ops.ppe_deinit = airoha_npu_ppe_deinit; 647 npu->ops.ppe_flush_sram_entries = airoha_npu_ppe_flush_sram_entries; 648 npu->ops.ppe_foe_commit_entry = airoha_npu_foe_commit_entry; 649 npu->ops.wlan_init_reserved_memory = airoha_npu_wlan_init_memory; 650 npu->ops.wlan_send_msg = airoha_npu_wlan_msg_send; 651 npu->ops.wlan_get_msg = airoha_npu_wlan_msg_get; 652 npu->ops.wlan_get_queue_addr = airoha_npu_wlan_queue_addr_get; 653 npu->ops.wlan_set_irq_status = airoha_npu_wlan_irq_status_set; 654 npu->ops.wlan_get_irq_status = airoha_npu_wlan_irq_status_get; 655 npu->ops.wlan_enable_irq = airoha_npu_wlan_irq_enable; 656 npu->ops.wlan_disable_irq = airoha_npu_wlan_irq_disable; 657 658 npu->regmap = devm_regmap_init_mmio(dev, base, ®map_config); 659 if (IS_ERR(npu->regmap)) 660 return PTR_ERR(npu->regmap); 661 662 err = of_reserved_mem_region_to_resource(dev->of_node, 0, &res); 663 if (err) 664 return err; 665 666 irq = platform_get_irq(pdev, 0); 667 if (irq < 0) 668 return irq; 669 670 err = devm_request_irq(dev, irq, airoha_npu_mbox_handler, 671 IRQF_SHARED, "airoha-npu-mbox", npu); 672 if (err) 673 return err; 674 675 for (i = 0; i < ARRAY_SIZE(npu->cores); i++) { 676 struct airoha_npu_core *core = &npu->cores[i]; 677 678 spin_lock_init(&core->lock); 679 core->npu = npu; 680 681 irq = platform_get_irq(pdev, i + 1); 682 if (irq < 0) 683 return irq; 684 685 err = devm_request_irq(dev, irq, airoha_npu_wdt_handler, 686 IRQF_SHARED, "airoha-npu-wdt", core); 687 if (err) 688 return err; 689 690 INIT_WORK(&core->wdt_work, airoha_npu_wdt_work); 691 } 692 693 /* wlan IRQ lines */ 694 for (i = 0; i < ARRAY_SIZE(npu->irqs); i++) { 695 irq = platform_get_irq(pdev, i + ARRAY_SIZE(npu->cores) + 1); 696 if (irq < 0) 697 return irq; 698 699 npu->irqs[i] = irq; 700 } 701 702 err = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); 703 if (err) 704 return err; 705 706 err = airoha_npu_run_firmware(dev, base, &res); 707 if (err) 708 return dev_err_probe(dev, err, "failed to run npu firmware\n"); 709 710 regmap_write(npu->regmap, REG_CR_NPU_MIB(10), 711 res.start + NPU_EN7581_FIRMWARE_RV32_MAX_SIZE); 712 regmap_write(npu->regmap, REG_CR_NPU_MIB(11), 0x40000); /* SRAM 256K */ 713 regmap_write(npu->regmap, REG_CR_NPU_MIB(12), 0); 714 regmap_write(npu->regmap, REG_CR_NPU_MIB(21), 1); 715 msleep(100); 716 717 /* setting booting address */ 718 for (i = 0; i < NPU_NUM_CORES; i++) 719 regmap_write(npu->regmap, REG_CR_BOOT_BASE(i), res.start); 720 usleep_range(1000, 2000); 721 722 /* enable NPU cores */ 723 regmap_write(npu->regmap, REG_CR_BOOT_CONFIG, 0xff); 724 regmap_write(npu->regmap, REG_CR_BOOT_TRIGGER, 0x1); 725 msleep(100); 726 727 platform_set_drvdata(pdev, npu); 728 729 return 0; 730 } 731 732 static void airoha_npu_remove(struct platform_device *pdev) 733 { 734 struct airoha_npu *npu = platform_get_drvdata(pdev); 735 int i; 736 737 for (i = 0; i < ARRAY_SIZE(npu->cores); i++) 738 cancel_work_sync(&npu->cores[i].wdt_work); 739 } 740 741 static struct platform_driver airoha_npu_driver = { 742 .probe = airoha_npu_probe, 743 .remove = airoha_npu_remove, 744 .driver = { 745 .name = "airoha-npu", 746 .of_match_table = of_airoha_npu_match, 747 }, 748 }; 749 module_platform_driver(airoha_npu_driver); 750 751 MODULE_FIRMWARE(NPU_EN7581_FIRMWARE_DATA); 752 MODULE_FIRMWARE(NPU_EN7581_FIRMWARE_RV32); 753 MODULE_LICENSE("GPL"); 754 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 755 MODULE_DESCRIPTION("Airoha Network Processor Unit driver"); 756