1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2024 AIROHA Inc 4 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 5 */ 6 7 #ifndef AIROHA_ETH_H 8 #define AIROHA_ETH_H 9 10 #include <linux/debugfs.h> 11 #include <linux/etherdevice.h> 12 #include <linux/iopoll.h> 13 #include <linux/kernel.h> 14 #include <linux/netdevice.h> 15 #include <linux/reset.h> 16 #include <net/dsa.h> 17 18 #define AIROHA_MAX_NUM_GDM_PORTS 4 19 #define AIROHA_MAX_NUM_QDMA 2 20 #define AIROHA_MAX_DSA_PORTS 7 21 #define AIROHA_MAX_NUM_RSTS 3 22 #define AIROHA_MAX_NUM_XSI_RSTS 5 23 #define AIROHA_MAX_MTU 9216 24 #define AIROHA_MAX_PACKET_SIZE 2048 25 #define AIROHA_NUM_QOS_CHANNELS 4 26 #define AIROHA_NUM_QOS_QUEUES 8 27 #define AIROHA_NUM_TX_RING 32 28 #define AIROHA_NUM_RX_RING 32 29 #define AIROHA_NUM_NETDEV_TX_RINGS (AIROHA_NUM_TX_RING + \ 30 AIROHA_NUM_QOS_CHANNELS) 31 #define AIROHA_FE_MC_MAX_VLAN_TABLE 64 32 #define AIROHA_FE_MC_MAX_VLAN_PORT 16 33 #define AIROHA_NUM_TX_IRQ 2 34 #define HW_DSCP_NUM 2048 35 #define IRQ_QUEUE_LEN(_n) ((_n) ? 1024 : 2048) 36 #define TX_DSCP_NUM 1024 37 #define RX_DSCP_NUM(_n) \ 38 ((_n) == 2 ? 128 : \ 39 (_n) == 11 ? 128 : \ 40 (_n) == 15 ? 128 : \ 41 (_n) == 0 ? 1024 : 16) 42 43 #define PSE_RSV_PAGES 128 44 #define PSE_QUEUE_RSV_PAGES 64 45 46 #define QDMA_METER_IDX(_n) ((_n) & 0xff) 47 #define QDMA_METER_GROUP(_n) (((_n) >> 8) & 0x3) 48 49 #define PPE_NUM 2 50 #define PPE1_SRAM_NUM_ENTRIES (8 * 1024) 51 #define PPE_SRAM_NUM_ENTRIES (2 * PPE1_SRAM_NUM_ENTRIES) 52 #define PPE_DRAM_NUM_ENTRIES (16 * 1024) 53 #define PPE_NUM_ENTRIES (PPE_SRAM_NUM_ENTRIES + PPE_DRAM_NUM_ENTRIES) 54 #define PPE_HASH_MASK (PPE_NUM_ENTRIES - 1) 55 #define PPE_ENTRY_SIZE 80 56 #define PPE_RAM_NUM_ENTRIES_SHIFT(_n) (__ffs((_n) >> 10)) 57 58 #define MTK_HDR_LEN 4 59 #define MTK_HDR_XMIT_TAGGED_TPID_8100 1 60 #define MTK_HDR_XMIT_TAGGED_TPID_88A8 2 61 62 enum { 63 QDMA_INT_REG_IDX0, 64 QDMA_INT_REG_IDX1, 65 QDMA_INT_REG_IDX2, 66 QDMA_INT_REG_IDX3, 67 QDMA_INT_REG_IDX4, 68 QDMA_INT_REG_MAX 69 }; 70 71 enum { 72 HSGMII_LAN_PCIE0_SRCPORT = 0x16, 73 HSGMII_LAN_PCIE1_SRCPORT, 74 HSGMII_LAN_ETH_SRCPORT, 75 HSGMII_LAN_USB_SRCPORT, 76 }; 77 78 enum { 79 XSI_PCIE0_VIP_PORT_MASK = BIT(22), 80 XSI_PCIE1_VIP_PORT_MASK = BIT(23), 81 XSI_USB_VIP_PORT_MASK = BIT(25), 82 XSI_ETH_VIP_PORT_MASK = BIT(24), 83 }; 84 85 enum { 86 DEV_STATE_INITIALIZED, 87 }; 88 89 enum { 90 CDM_CRSN_QSEL_Q1 = 1, 91 CDM_CRSN_QSEL_Q5 = 5, 92 CDM_CRSN_QSEL_Q6 = 6, 93 CDM_CRSN_QSEL_Q15 = 15, 94 }; 95 96 enum { 97 CRSN_08 = 0x8, 98 CRSN_21 = 0x15, /* KA */ 99 CRSN_22 = 0x16, /* hit bind and force route to CPU */ 100 CRSN_24 = 0x18, 101 CRSN_25 = 0x19, 102 }; 103 104 enum { 105 FE_PSE_PORT_CDM1, 106 FE_PSE_PORT_GDM1, 107 FE_PSE_PORT_GDM2, 108 FE_PSE_PORT_GDM3, 109 FE_PSE_PORT_PPE1, 110 FE_PSE_PORT_CDM2, 111 FE_PSE_PORT_CDM3, 112 FE_PSE_PORT_CDM4, 113 FE_PSE_PORT_PPE2, 114 FE_PSE_PORT_GDM4, 115 FE_PSE_PORT_CDM5, 116 FE_PSE_PORT_DROP = 0xf, 117 }; 118 119 enum tx_sched_mode { 120 TC_SCH_WRR8, 121 TC_SCH_SP, 122 TC_SCH_WRR7, 123 TC_SCH_WRR6, 124 TC_SCH_WRR5, 125 TC_SCH_WRR4, 126 TC_SCH_WRR3, 127 TC_SCH_WRR2, 128 }; 129 130 enum trtcm_param_type { 131 TRTCM_MISC_MODE, /* meter_en, pps_mode, tick_sel */ 132 TRTCM_TOKEN_RATE_MODE, 133 TRTCM_BUCKETSIZE_SHIFT_MODE, 134 TRTCM_BUCKET_COUNTER_MODE, 135 }; 136 137 enum trtcm_mode_type { 138 TRTCM_COMMIT_MODE, 139 TRTCM_PEAK_MODE, 140 }; 141 142 enum trtcm_param { 143 TRTCM_TICK_SEL = BIT(0), 144 TRTCM_PKT_MODE = BIT(1), 145 TRTCM_METER_MODE = BIT(2), 146 }; 147 148 #define MIN_TOKEN_SIZE 4096 149 #define MAX_TOKEN_SIZE_OFFSET 17 150 #define TRTCM_TOKEN_RATE_MASK GENMASK(23, 6) 151 #define TRTCM_TOKEN_RATE_FRACTION_MASK GENMASK(5, 0) 152 153 struct airoha_queue_entry { 154 union { 155 void *buf; 156 struct sk_buff *skb; 157 }; 158 dma_addr_t dma_addr; 159 u16 dma_len; 160 }; 161 162 struct airoha_queue { 163 struct airoha_qdma *qdma; 164 165 /* protect concurrent queue accesses */ 166 spinlock_t lock; 167 struct airoha_queue_entry *entry; 168 struct airoha_qdma_desc *desc; 169 u16 head; 170 u16 tail; 171 172 int queued; 173 int ndesc; 174 int free_thr; 175 int buf_size; 176 177 struct napi_struct napi; 178 struct page_pool *page_pool; 179 struct sk_buff *skb; 180 }; 181 182 struct airoha_tx_irq_queue { 183 struct airoha_qdma *qdma; 184 185 struct napi_struct napi; 186 187 int size; 188 u32 *q; 189 }; 190 191 struct airoha_hw_stats { 192 /* protect concurrent hw_stats accesses */ 193 spinlock_t lock; 194 struct u64_stats_sync syncp; 195 196 /* get_stats64 */ 197 u64 rx_ok_pkts; 198 u64 tx_ok_pkts; 199 u64 rx_ok_bytes; 200 u64 tx_ok_bytes; 201 u64 rx_multicast; 202 u64 rx_errors; 203 u64 rx_drops; 204 u64 tx_drops; 205 u64 rx_crc_error; 206 u64 rx_over_errors; 207 /* ethtool stats */ 208 u64 tx_broadcast; 209 u64 tx_multicast; 210 u64 tx_len[7]; 211 u64 rx_broadcast; 212 u64 rx_fragment; 213 u64 rx_jabber; 214 u64 rx_len[7]; 215 }; 216 217 enum { 218 PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED = 0x0f, 219 }; 220 221 enum { 222 AIROHA_FOE_STATE_INVALID, 223 AIROHA_FOE_STATE_UNBIND, 224 AIROHA_FOE_STATE_BIND, 225 AIROHA_FOE_STATE_FIN 226 }; 227 228 enum { 229 PPE_PKT_TYPE_IPV4_HNAPT = 0, 230 PPE_PKT_TYPE_IPV4_ROUTE = 1, 231 PPE_PKT_TYPE_BRIDGE = 2, 232 PPE_PKT_TYPE_IPV4_DSLITE = 3, 233 PPE_PKT_TYPE_IPV6_ROUTE_3T = 4, 234 PPE_PKT_TYPE_IPV6_ROUTE_5T = 5, 235 PPE_PKT_TYPE_IPV6_6RD = 7, 236 }; 237 238 #define AIROHA_FOE_MAC_SMAC_ID GENMASK(20, 16) 239 #define AIROHA_FOE_MAC_PPPOE_ID GENMASK(15, 0) 240 241 struct airoha_foe_mac_info_common { 242 u16 vlan1; 243 u16 etype; 244 245 u32 dest_mac_hi; 246 247 u16 vlan2; 248 u16 dest_mac_lo; 249 250 u32 src_mac_hi; 251 }; 252 253 struct airoha_foe_mac_info { 254 struct airoha_foe_mac_info_common common; 255 256 u16 pppoe_id; 257 u16 src_mac_lo; 258 }; 259 260 #define AIROHA_FOE_IB1_UNBIND_PREBIND BIT(24) 261 #define AIROHA_FOE_IB1_UNBIND_PACKETS GENMASK(23, 8) 262 #define AIROHA_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0) 263 264 #define AIROHA_FOE_IB1_BIND_STATIC BIT(31) 265 #define AIROHA_FOE_IB1_BIND_UDP BIT(30) 266 #define AIROHA_FOE_IB1_BIND_STATE GENMASK(29, 28) 267 #define AIROHA_FOE_IB1_BIND_PACKET_TYPE GENMASK(27, 25) 268 #define AIROHA_FOE_IB1_BIND_TTL BIT(24) 269 #define AIROHA_FOE_IB1_BIND_TUNNEL_DECAP BIT(23) 270 #define AIROHA_FOE_IB1_BIND_PPPOE BIT(22) 271 #define AIROHA_FOE_IB1_BIND_VPM GENMASK(21, 20) 272 #define AIROHA_FOE_IB1_BIND_VLAN_LAYER GENMASK(19, 16) 273 #define AIROHA_FOE_IB1_BIND_KEEPALIVE BIT(15) 274 #define AIROHA_FOE_IB1_BIND_TIMESTAMP GENMASK(14, 0) 275 276 #define AIROHA_FOE_IB2_DSCP GENMASK(31, 24) 277 #define AIROHA_FOE_IB2_PORT_AG GENMASK(23, 13) 278 #define AIROHA_FOE_IB2_PCP BIT(12) 279 #define AIROHA_FOE_IB2_MULTICAST BIT(11) 280 #define AIROHA_FOE_IB2_FAST_PATH BIT(10) 281 #define AIROHA_FOE_IB2_PSE_QOS BIT(9) 282 #define AIROHA_FOE_IB2_PSE_PORT GENMASK(8, 5) 283 #define AIROHA_FOE_IB2_NBQ GENMASK(4, 0) 284 285 #define AIROHA_FOE_ACTDP GENMASK(31, 24) 286 #define AIROHA_FOE_SHAPER_ID GENMASK(23, 16) 287 #define AIROHA_FOE_CHANNEL GENMASK(15, 11) 288 #define AIROHA_FOE_QID GENMASK(10, 8) 289 #define AIROHA_FOE_DPI BIT(7) 290 #define AIROHA_FOE_TUNNEL BIT(6) 291 #define AIROHA_FOE_TUNNEL_ID GENMASK(5, 0) 292 293 struct airoha_foe_bridge { 294 u32 dest_mac_hi; 295 296 u16 src_mac_hi; 297 u16 dest_mac_lo; 298 299 u32 src_mac_lo; 300 301 u32 ib2; 302 303 u32 rsv[5]; 304 305 u32 data; 306 307 struct airoha_foe_mac_info l2; 308 }; 309 310 struct airoha_foe_ipv4_tuple { 311 u32 src_ip; 312 u32 dest_ip; 313 union { 314 struct { 315 u16 dest_port; 316 u16 src_port; 317 }; 318 struct { 319 u8 protocol; 320 u8 _pad[3]; /* fill with 0xa5a5a5 */ 321 }; 322 u32 ports; 323 }; 324 }; 325 326 struct airoha_foe_ipv4 { 327 struct airoha_foe_ipv4_tuple orig_tuple; 328 329 u32 ib2; 330 331 struct airoha_foe_ipv4_tuple new_tuple; 332 333 u32 rsv[2]; 334 335 u32 data; 336 337 struct airoha_foe_mac_info l2; 338 }; 339 340 struct airoha_foe_ipv4_dslite { 341 struct airoha_foe_ipv4_tuple ip4; 342 343 u32 ib2; 344 345 u8 flow_label[3]; 346 u8 priority; 347 348 u32 rsv[4]; 349 350 u32 data; 351 352 struct airoha_foe_mac_info l2; 353 }; 354 355 struct airoha_foe_ipv6 { 356 u32 src_ip[4]; 357 u32 dest_ip[4]; 358 359 union { 360 struct { 361 u16 dest_port; 362 u16 src_port; 363 }; 364 struct { 365 u8 protocol; 366 u8 pad[3]; 367 }; 368 u32 ports; 369 }; 370 371 u32 data; 372 373 u32 ib2; 374 375 struct airoha_foe_mac_info_common l2; 376 }; 377 378 struct airoha_foe_entry { 379 union { 380 struct { 381 u32 ib1; 382 union { 383 struct airoha_foe_bridge bridge; 384 struct airoha_foe_ipv4 ipv4; 385 struct airoha_foe_ipv4_dslite dslite; 386 struct airoha_foe_ipv6 ipv6; 387 DECLARE_FLEX_ARRAY(u32, d); 388 }; 389 }; 390 u8 data[PPE_ENTRY_SIZE]; 391 }; 392 }; 393 394 struct airoha_flow_data { 395 struct ethhdr eth; 396 397 union { 398 struct { 399 __be32 src_addr; 400 __be32 dst_addr; 401 } v4; 402 403 struct { 404 struct in6_addr src_addr; 405 struct in6_addr dst_addr; 406 } v6; 407 }; 408 409 __be16 src_port; 410 __be16 dst_port; 411 412 struct { 413 struct { 414 u16 id; 415 __be16 proto; 416 } hdr[2]; 417 u8 num; 418 } vlan; 419 struct { 420 u16 sid; 421 u8 num; 422 } pppoe; 423 }; 424 425 struct airoha_flow_table_entry { 426 struct hlist_node list; 427 428 struct airoha_foe_entry data; 429 u32 hash; 430 431 struct rhash_head node; 432 unsigned long cookie; 433 }; 434 435 struct airoha_qdma { 436 struct airoha_eth *eth; 437 void __iomem *regs; 438 439 /* protect concurrent irqmask accesses */ 440 spinlock_t irq_lock; 441 u32 irqmask[QDMA_INT_REG_MAX]; 442 int irq; 443 444 atomic_t users; 445 446 struct airoha_tx_irq_queue q_tx_irq[AIROHA_NUM_TX_IRQ]; 447 448 struct airoha_queue q_tx[AIROHA_NUM_TX_RING]; 449 struct airoha_queue q_rx[AIROHA_NUM_RX_RING]; 450 451 /* descriptor and packet buffers for qdma hw forward */ 452 struct { 453 void *desc; 454 void *q; 455 } hfwd; 456 }; 457 458 struct airoha_gdm_port { 459 struct airoha_qdma *qdma; 460 struct net_device *dev; 461 int id; 462 463 struct airoha_hw_stats stats; 464 465 DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS); 466 467 /* qos stats counters */ 468 u64 cpu_tx_packets; 469 u64 fwd_tx_packets; 470 471 struct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS]; 472 }; 473 474 #define AIROHA_RXD4_PPE_CPU_REASON GENMASK(20, 16) 475 #define AIROHA_RXD4_FOE_ENTRY GENMASK(15, 0) 476 477 struct airoha_ppe { 478 struct airoha_eth *eth; 479 480 void *foe; 481 dma_addr_t foe_dma; 482 483 struct hlist_head *foe_flow; 484 u16 foe_check_time[PPE_NUM_ENTRIES]; 485 486 struct dentry *debugfs_dir; 487 }; 488 489 struct airoha_eth { 490 struct device *dev; 491 492 unsigned long state; 493 void __iomem *fe_regs; 494 495 struct airoha_npu __rcu *npu; 496 497 struct airoha_ppe *ppe; 498 struct rhashtable flow_table; 499 500 struct reset_control_bulk_data rsts[AIROHA_MAX_NUM_RSTS]; 501 struct reset_control_bulk_data xsi_rsts[AIROHA_MAX_NUM_XSI_RSTS]; 502 503 struct net_device *napi_dev; 504 505 struct airoha_qdma qdma[AIROHA_MAX_NUM_QDMA]; 506 struct airoha_gdm_port *ports[AIROHA_MAX_NUM_GDM_PORTS]; 507 }; 508 509 u32 airoha_rr(void __iomem *base, u32 offset); 510 void airoha_wr(void __iomem *base, u32 offset, u32 val); 511 u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val); 512 513 #define airoha_fe_rr(eth, offset) \ 514 airoha_rr((eth)->fe_regs, (offset)) 515 #define airoha_fe_wr(eth, offset, val) \ 516 airoha_wr((eth)->fe_regs, (offset), (val)) 517 #define airoha_fe_rmw(eth, offset, mask, val) \ 518 airoha_rmw((eth)->fe_regs, (offset), (mask), (val)) 519 #define airoha_fe_set(eth, offset, val) \ 520 airoha_rmw((eth)->fe_regs, (offset), 0, (val)) 521 #define airoha_fe_clear(eth, offset, val) \ 522 airoha_rmw((eth)->fe_regs, (offset), (val), 0) 523 524 #define airoha_qdma_rr(qdma, offset) \ 525 airoha_rr((qdma)->regs, (offset)) 526 #define airoha_qdma_wr(qdma, offset, val) \ 527 airoha_wr((qdma)->regs, (offset), (val)) 528 #define airoha_qdma_rmw(qdma, offset, mask, val) \ 529 airoha_rmw((qdma)->regs, (offset), (mask), (val)) 530 #define airoha_qdma_set(qdma, offset, val) \ 531 airoha_rmw((qdma)->regs, (offset), 0, (val)) 532 #define airoha_qdma_clear(qdma, offset, val) \ 533 airoha_rmw((qdma)->regs, (offset), (val), 0) 534 535 bool airoha_is_valid_gdm_port(struct airoha_eth *eth, 536 struct airoha_gdm_port *port); 537 538 void airoha_ppe_check_skb(struct airoha_ppe *ppe, u16 hash); 539 int airoha_ppe_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 540 void *cb_priv); 541 int airoha_ppe_init(struct airoha_eth *eth); 542 void airoha_ppe_deinit(struct airoha_eth *eth); 543 struct airoha_foe_entry *airoha_ppe_foe_get_entry(struct airoha_ppe *ppe, 544 u32 hash); 545 546 #ifdef CONFIG_DEBUG_FS 547 int airoha_ppe_debugfs_init(struct airoha_ppe *ppe); 548 #else 549 static inline int airoha_ppe_debugfs_init(struct airoha_ppe *ppe) 550 { 551 return 0; 552 } 553 #endif 554 555 #endif /* AIROHA_ETH_H */ 556