1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2024 AIROHA Inc 4 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 5 */ 6 7 #ifndef AIROHA_ETH_H 8 #define AIROHA_ETH_H 9 10 #include <linux/debugfs.h> 11 #include <linux/etherdevice.h> 12 #include <linux/iopoll.h> 13 #include <linux/kernel.h> 14 #include <linux/netdevice.h> 15 #include <linux/reset.h> 16 #include <linux/soc/airoha/airoha_offload.h> 17 #include <net/dsa.h> 18 19 #define AIROHA_MAX_NUM_GDM_PORTS 4 20 #define AIROHA_MAX_NUM_QDMA 2 21 #define AIROHA_MAX_NUM_IRQ_BANKS 4 22 #define AIROHA_MAX_DSA_PORTS 7 23 #define AIROHA_MAX_NUM_RSTS 3 24 #define AIROHA_MAX_NUM_XSI_RSTS 5 25 #define AIROHA_MAX_MTU 9216 26 #define AIROHA_MAX_PACKET_SIZE 2048 27 #define AIROHA_NUM_QOS_CHANNELS 4 28 #define AIROHA_NUM_QOS_QUEUES 8 29 #define AIROHA_NUM_TX_RING 32 30 #define AIROHA_NUM_RX_RING 32 31 #define AIROHA_NUM_NETDEV_TX_RINGS (AIROHA_NUM_TX_RING + \ 32 AIROHA_NUM_QOS_CHANNELS) 33 #define AIROHA_FE_MC_MAX_VLAN_TABLE 64 34 #define AIROHA_FE_MC_MAX_VLAN_PORT 16 35 #define AIROHA_NUM_TX_IRQ 2 36 #define HW_DSCP_NUM 2048 37 #define IRQ_QUEUE_LEN(_n) ((_n) ? 1024 : 2048) 38 #define TX_DSCP_NUM 1024 39 #define RX_DSCP_NUM(_n) \ 40 ((_n) == 2 ? 128 : \ 41 (_n) == 11 ? 128 : \ 42 (_n) == 15 ? 128 : \ 43 (_n) == 0 ? 1024 : 16) 44 45 #define PSE_RSV_PAGES 128 46 #define PSE_QUEUE_RSV_PAGES 64 47 48 #define QDMA_METER_IDX(_n) ((_n) & 0xff) 49 #define QDMA_METER_GROUP(_n) (((_n) >> 8) & 0x3) 50 51 #define PPE_NUM 2 52 #define PPE1_SRAM_NUM_ENTRIES (8 * 1024) 53 #define PPE_SRAM_NUM_ENTRIES (2 * PPE1_SRAM_NUM_ENTRIES) 54 #ifdef CONFIG_NET_AIROHA_FLOW_STATS 55 #define PPE1_STATS_NUM_ENTRIES (4 * 1024) 56 #else 57 #define PPE1_STATS_NUM_ENTRIES 0 58 #endif /* CONFIG_NET_AIROHA_FLOW_STATS */ 59 #define PPE_STATS_NUM_ENTRIES (2 * PPE1_STATS_NUM_ENTRIES) 60 #define PPE1_SRAM_NUM_DATA_ENTRIES (PPE1_SRAM_NUM_ENTRIES - PPE1_STATS_NUM_ENTRIES) 61 #define PPE_SRAM_NUM_DATA_ENTRIES (2 * PPE1_SRAM_NUM_DATA_ENTRIES) 62 #define PPE_DRAM_NUM_ENTRIES (16 * 1024) 63 #define PPE_NUM_ENTRIES (PPE_SRAM_NUM_ENTRIES + PPE_DRAM_NUM_ENTRIES) 64 #define PPE_HASH_MASK (PPE_NUM_ENTRIES - 1) 65 #define PPE_ENTRY_SIZE 80 66 #define PPE_RAM_NUM_ENTRIES_SHIFT(_n) (__ffs((_n) >> 10)) 67 68 #define MTK_HDR_LEN 4 69 #define MTK_HDR_XMIT_TAGGED_TPID_8100 1 70 #define MTK_HDR_XMIT_TAGGED_TPID_88A8 2 71 72 enum { 73 QDMA_INT_REG_IDX0, 74 QDMA_INT_REG_IDX1, 75 QDMA_INT_REG_IDX2, 76 QDMA_INT_REG_IDX3, 77 QDMA_INT_REG_IDX4, 78 QDMA_INT_REG_MAX 79 }; 80 81 enum { 82 HSGMII_LAN_PCIE0_SRCPORT = 0x16, 83 HSGMII_LAN_PCIE1_SRCPORT, 84 HSGMII_LAN_ETH_SRCPORT, 85 HSGMII_LAN_USB_SRCPORT, 86 }; 87 88 enum { 89 XSI_PCIE0_VIP_PORT_MASK = BIT(22), 90 XSI_PCIE1_VIP_PORT_MASK = BIT(23), 91 XSI_USB_VIP_PORT_MASK = BIT(25), 92 XSI_ETH_VIP_PORT_MASK = BIT(24), 93 }; 94 95 enum { 96 DEV_STATE_INITIALIZED, 97 }; 98 99 enum { 100 CDM_CRSN_QSEL_Q1 = 1, 101 CDM_CRSN_QSEL_Q5 = 5, 102 CDM_CRSN_QSEL_Q6 = 6, 103 CDM_CRSN_QSEL_Q15 = 15, 104 }; 105 106 enum { 107 CRSN_08 = 0x8, 108 CRSN_21 = 0x15, /* KA */ 109 CRSN_22 = 0x16, /* hit bind and force route to CPU */ 110 CRSN_24 = 0x18, 111 CRSN_25 = 0x19, 112 }; 113 114 enum { 115 FE_PSE_PORT_CDM1, 116 FE_PSE_PORT_GDM1, 117 FE_PSE_PORT_GDM2, 118 FE_PSE_PORT_GDM3, 119 FE_PSE_PORT_PPE1, 120 FE_PSE_PORT_CDM2, 121 FE_PSE_PORT_CDM3, 122 FE_PSE_PORT_CDM4, 123 FE_PSE_PORT_PPE2, 124 FE_PSE_PORT_GDM4, 125 FE_PSE_PORT_CDM5, 126 FE_PSE_PORT_DROP = 0xf, 127 }; 128 129 enum tx_sched_mode { 130 TC_SCH_WRR8, 131 TC_SCH_SP, 132 TC_SCH_WRR7, 133 TC_SCH_WRR6, 134 TC_SCH_WRR5, 135 TC_SCH_WRR4, 136 TC_SCH_WRR3, 137 TC_SCH_WRR2, 138 }; 139 140 enum trtcm_unit_type { 141 TRTCM_BYTE_UNIT, 142 TRTCM_PACKET_UNIT, 143 }; 144 145 enum trtcm_param_type { 146 TRTCM_MISC_MODE, /* meter_en, pps_mode, tick_sel */ 147 TRTCM_TOKEN_RATE_MODE, 148 TRTCM_BUCKETSIZE_SHIFT_MODE, 149 TRTCM_BUCKET_COUNTER_MODE, 150 }; 151 152 enum trtcm_mode_type { 153 TRTCM_COMMIT_MODE, 154 TRTCM_PEAK_MODE, 155 }; 156 157 enum trtcm_param { 158 TRTCM_TICK_SEL = BIT(0), 159 TRTCM_PKT_MODE = BIT(1), 160 TRTCM_METER_MODE = BIT(2), 161 }; 162 163 #define MIN_TOKEN_SIZE 4096 164 #define MAX_TOKEN_SIZE_OFFSET 17 165 #define TRTCM_TOKEN_RATE_MASK GENMASK(23, 6) 166 #define TRTCM_TOKEN_RATE_FRACTION_MASK GENMASK(5, 0) 167 168 struct airoha_queue_entry { 169 union { 170 void *buf; 171 struct sk_buff *skb; 172 }; 173 dma_addr_t dma_addr; 174 u16 dma_len; 175 }; 176 177 struct airoha_queue { 178 struct airoha_qdma *qdma; 179 180 /* protect concurrent queue accesses */ 181 spinlock_t lock; 182 struct airoha_queue_entry *entry; 183 struct airoha_qdma_desc *desc; 184 u16 head; 185 u16 tail; 186 187 int queued; 188 int ndesc; 189 int free_thr; 190 int buf_size; 191 192 struct napi_struct napi; 193 struct page_pool *page_pool; 194 struct sk_buff *skb; 195 }; 196 197 struct airoha_tx_irq_queue { 198 struct airoha_qdma *qdma; 199 200 struct napi_struct napi; 201 202 int size; 203 u32 *q; 204 }; 205 206 struct airoha_hw_stats { 207 /* protect concurrent hw_stats accesses */ 208 spinlock_t lock; 209 struct u64_stats_sync syncp; 210 211 /* get_stats64 */ 212 u64 rx_ok_pkts; 213 u64 tx_ok_pkts; 214 u64 rx_ok_bytes; 215 u64 tx_ok_bytes; 216 u64 rx_multicast; 217 u64 rx_errors; 218 u64 rx_drops; 219 u64 tx_drops; 220 u64 rx_crc_error; 221 u64 rx_over_errors; 222 /* ethtool stats */ 223 u64 tx_broadcast; 224 u64 tx_multicast; 225 u64 tx_len[7]; 226 u64 rx_broadcast; 227 u64 rx_fragment; 228 u64 rx_jabber; 229 u64 rx_len[7]; 230 }; 231 232 enum { 233 AIROHA_FOE_STATE_INVALID, 234 AIROHA_FOE_STATE_UNBIND, 235 AIROHA_FOE_STATE_BIND, 236 AIROHA_FOE_STATE_FIN 237 }; 238 239 enum { 240 PPE_PKT_TYPE_IPV4_HNAPT = 0, 241 PPE_PKT_TYPE_IPV4_ROUTE = 1, 242 PPE_PKT_TYPE_BRIDGE = 2, 243 PPE_PKT_TYPE_IPV4_DSLITE = 3, 244 PPE_PKT_TYPE_IPV6_ROUTE_3T = 4, 245 PPE_PKT_TYPE_IPV6_ROUTE_5T = 5, 246 PPE_PKT_TYPE_IPV6_6RD = 7, 247 }; 248 249 #define AIROHA_FOE_MAC_SMAC_ID GENMASK(20, 16) 250 #define AIROHA_FOE_MAC_PPPOE_ID GENMASK(15, 0) 251 252 #define AIROHA_FOE_MAC_WDMA_QOS GENMASK(15, 12) 253 #define AIROHA_FOE_MAC_WDMA_BAND BIT(11) 254 #define AIROHA_FOE_MAC_WDMA_WCID GENMASK(10, 0) 255 256 struct airoha_foe_mac_info_common { 257 u16 vlan1; 258 u16 etype; 259 260 u32 dest_mac_hi; 261 262 u16 vlan2; 263 u16 dest_mac_lo; 264 265 u32 src_mac_hi; 266 }; 267 268 struct airoha_foe_mac_info { 269 struct airoha_foe_mac_info_common common; 270 271 u16 pppoe_id; 272 u16 src_mac_lo; 273 274 u32 meter; 275 }; 276 277 #define AIROHA_FOE_IB1_UNBIND_PREBIND BIT(24) 278 #define AIROHA_FOE_IB1_UNBIND_PACKETS GENMASK(23, 8) 279 #define AIROHA_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0) 280 281 #define AIROHA_FOE_IB1_BIND_STATIC BIT(31) 282 #define AIROHA_FOE_IB1_BIND_UDP BIT(30) 283 #define AIROHA_FOE_IB1_BIND_STATE GENMASK(29, 28) 284 #define AIROHA_FOE_IB1_BIND_PACKET_TYPE GENMASK(27, 25) 285 #define AIROHA_FOE_IB1_BIND_TTL BIT(24) 286 #define AIROHA_FOE_IB1_BIND_TUNNEL_DECAP BIT(23) 287 #define AIROHA_FOE_IB1_BIND_PPPOE BIT(22) 288 #define AIROHA_FOE_IB1_BIND_VPM GENMASK(21, 20) 289 #define AIROHA_FOE_IB1_BIND_VLAN_LAYER GENMASK(19, 16) 290 #define AIROHA_FOE_IB1_BIND_KEEPALIVE BIT(15) 291 #define AIROHA_FOE_IB1_BIND_TIMESTAMP GENMASK(14, 0) 292 293 #define AIROHA_FOE_IB2_DSCP GENMASK(31, 24) 294 #define AIROHA_FOE_IB2_PORT_AG GENMASK(23, 13) 295 #define AIROHA_FOE_IB2_PCP BIT(12) 296 #define AIROHA_FOE_IB2_MULTICAST BIT(11) 297 #define AIROHA_FOE_IB2_FAST_PATH BIT(10) 298 #define AIROHA_FOE_IB2_PSE_QOS BIT(9) 299 #define AIROHA_FOE_IB2_PSE_PORT GENMASK(8, 5) 300 #define AIROHA_FOE_IB2_NBQ GENMASK(4, 0) 301 302 #define AIROHA_FOE_ACTDP GENMASK(31, 24) 303 #define AIROHA_FOE_SHAPER_ID GENMASK(23, 16) 304 #define AIROHA_FOE_CHANNEL GENMASK(15, 11) 305 #define AIROHA_FOE_QID GENMASK(10, 8) 306 #define AIROHA_FOE_DPI BIT(7) 307 #define AIROHA_FOE_TUNNEL BIT(6) 308 #define AIROHA_FOE_TUNNEL_ID GENMASK(5, 0) 309 310 #define AIROHA_FOE_TUNNEL_MTU GENMASK(31, 16) 311 #define AIROHA_FOE_ACNT_GRP3 GENMASK(15, 9) 312 #define AIROHA_FOE_METER_GRP3 GENMASK(8, 5) 313 #define AIROHA_FOE_METER_GRP2 GENMASK(4, 0) 314 315 struct airoha_foe_bridge { 316 u32 dest_mac_hi; 317 318 u16 src_mac_hi; 319 u16 dest_mac_lo; 320 321 u32 src_mac_lo; 322 323 u32 ib2; 324 325 u32 rsv[5]; 326 327 u32 data; 328 329 struct airoha_foe_mac_info l2; 330 }; 331 332 struct airoha_foe_ipv4_tuple { 333 u32 src_ip; 334 u32 dest_ip; 335 union { 336 struct { 337 u16 dest_port; 338 u16 src_port; 339 }; 340 struct { 341 u8 protocol; 342 u8 _pad[3]; /* fill with 0xa5a5a5 */ 343 }; 344 u32 ports; 345 }; 346 }; 347 348 struct airoha_foe_ipv4 { 349 struct airoha_foe_ipv4_tuple orig_tuple; 350 351 u32 ib2; 352 353 struct airoha_foe_ipv4_tuple new_tuple; 354 355 u32 rsv[2]; 356 357 u32 data; 358 359 struct airoha_foe_mac_info l2; 360 }; 361 362 struct airoha_foe_ipv4_dslite { 363 struct airoha_foe_ipv4_tuple ip4; 364 365 u32 ib2; 366 367 u8 flow_label[3]; 368 u8 priority; 369 370 u32 rsv[4]; 371 372 u32 data; 373 374 struct airoha_foe_mac_info l2; 375 }; 376 377 struct airoha_foe_ipv6 { 378 u32 src_ip[4]; 379 u32 dest_ip[4]; 380 381 union { 382 struct { 383 u16 dest_port; 384 u16 src_port; 385 }; 386 struct { 387 u8 protocol; 388 u8 pad[3]; 389 }; 390 u32 ports; 391 }; 392 393 u32 data; 394 395 u32 ib2; 396 397 struct airoha_foe_mac_info_common l2; 398 399 u32 meter; 400 }; 401 402 struct airoha_foe_entry { 403 union { 404 struct { 405 u32 ib1; 406 union { 407 struct airoha_foe_bridge bridge; 408 struct airoha_foe_ipv4 ipv4; 409 struct airoha_foe_ipv4_dslite dslite; 410 struct airoha_foe_ipv6 ipv6; 411 DECLARE_FLEX_ARRAY(u32, d); 412 }; 413 }; 414 u8 data[PPE_ENTRY_SIZE]; 415 }; 416 }; 417 418 struct airoha_foe_stats { 419 u32 bytes; 420 u32 packets; 421 }; 422 423 struct airoha_foe_stats64 { 424 u64 bytes; 425 u64 packets; 426 }; 427 428 struct airoha_flow_data { 429 struct ethhdr eth; 430 431 union { 432 struct { 433 __be32 src_addr; 434 __be32 dst_addr; 435 } v4; 436 437 struct { 438 struct in6_addr src_addr; 439 struct in6_addr dst_addr; 440 } v6; 441 }; 442 443 __be16 src_port; 444 __be16 dst_port; 445 446 struct { 447 struct { 448 u16 id; 449 __be16 proto; 450 } hdr[2]; 451 u8 num; 452 } vlan; 453 struct { 454 u16 sid; 455 u8 num; 456 } pppoe; 457 }; 458 459 enum airoha_flow_entry_type { 460 FLOW_TYPE_L4, 461 FLOW_TYPE_L2, 462 FLOW_TYPE_L2_SUBFLOW, 463 }; 464 465 struct airoha_flow_table_entry { 466 union { 467 struct hlist_node list; /* PPE L3 flow entry */ 468 struct { 469 struct rhash_head l2_node; /* L2 flow entry */ 470 struct hlist_head l2_flows; /* PPE L2 subflows list */ 471 }; 472 }; 473 474 struct hlist_node l2_subflow_node; /* PPE L2 subflow entry */ 475 u32 hash; 476 477 struct airoha_foe_stats64 stats; 478 enum airoha_flow_entry_type type; 479 480 struct rhash_head node; 481 unsigned long cookie; 482 483 /* Must be last --ends in a flexible-array member. */ 484 struct airoha_foe_entry data; 485 }; 486 487 struct airoha_wdma_info { 488 u8 idx; 489 u8 queue; 490 u16 wcid; 491 u8 bss; 492 }; 493 494 /* RX queue to IRQ mapping: BIT(q) in IRQ(n) */ 495 #define RX_IRQ0_BANK_PIN_MASK 0x839f 496 #define RX_IRQ1_BANK_PIN_MASK 0x7fe00000 497 #define RX_IRQ2_BANK_PIN_MASK 0x20 498 #define RX_IRQ3_BANK_PIN_MASK 0x40 499 #define RX_IRQ_BANK_PIN_MASK(_n) \ 500 (((_n) == 3) ? RX_IRQ3_BANK_PIN_MASK : \ 501 ((_n) == 2) ? RX_IRQ2_BANK_PIN_MASK : \ 502 ((_n) == 1) ? RX_IRQ1_BANK_PIN_MASK : \ 503 RX_IRQ0_BANK_PIN_MASK) 504 505 struct airoha_irq_bank { 506 struct airoha_qdma *qdma; 507 508 /* protect concurrent irqmask accesses */ 509 spinlock_t irq_lock; 510 u32 irqmask[QDMA_INT_REG_MAX]; 511 int irq; 512 }; 513 514 struct airoha_qdma { 515 struct airoha_eth *eth; 516 void __iomem *regs; 517 518 atomic_t users; 519 520 struct airoha_irq_bank irq_banks[AIROHA_MAX_NUM_IRQ_BANKS]; 521 522 struct airoha_tx_irq_queue q_tx_irq[AIROHA_NUM_TX_IRQ]; 523 524 struct airoha_queue q_tx[AIROHA_NUM_TX_RING]; 525 struct airoha_queue q_rx[AIROHA_NUM_RX_RING]; 526 }; 527 528 struct airoha_gdm_port { 529 struct airoha_qdma *qdma; 530 struct net_device *dev; 531 int id; 532 533 struct airoha_hw_stats stats; 534 535 DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS); 536 537 /* qos stats counters */ 538 u64 cpu_tx_packets; 539 u64 fwd_tx_packets; 540 541 struct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS]; 542 }; 543 544 #define AIROHA_RXD4_PPE_CPU_REASON GENMASK(20, 16) 545 #define AIROHA_RXD4_FOE_ENTRY GENMASK(15, 0) 546 547 struct airoha_ppe { 548 struct airoha_ppe_dev dev; 549 struct airoha_eth *eth; 550 551 void *foe; 552 dma_addr_t foe_dma; 553 554 struct rhashtable l2_flows; 555 556 struct hlist_head *foe_flow; 557 u16 foe_check_time[PPE_NUM_ENTRIES]; 558 559 struct airoha_foe_stats *foe_stats; 560 dma_addr_t foe_stats_dma; 561 562 struct dentry *debugfs_dir; 563 }; 564 565 struct airoha_eth { 566 struct device *dev; 567 568 unsigned long state; 569 void __iomem *fe_regs; 570 571 struct airoha_npu __rcu *npu; 572 573 struct airoha_ppe *ppe; 574 struct rhashtable flow_table; 575 576 struct reset_control_bulk_data rsts[AIROHA_MAX_NUM_RSTS]; 577 struct reset_control_bulk_data xsi_rsts[AIROHA_MAX_NUM_XSI_RSTS]; 578 579 struct net_device *napi_dev; 580 581 struct airoha_qdma qdma[AIROHA_MAX_NUM_QDMA]; 582 struct airoha_gdm_port *ports[AIROHA_MAX_NUM_GDM_PORTS]; 583 }; 584 585 u32 airoha_rr(void __iomem *base, u32 offset); 586 void airoha_wr(void __iomem *base, u32 offset, u32 val); 587 u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val); 588 589 #define airoha_fe_rr(eth, offset) \ 590 airoha_rr((eth)->fe_regs, (offset)) 591 #define airoha_fe_wr(eth, offset, val) \ 592 airoha_wr((eth)->fe_regs, (offset), (val)) 593 #define airoha_fe_rmw(eth, offset, mask, val) \ 594 airoha_rmw((eth)->fe_regs, (offset), (mask), (val)) 595 #define airoha_fe_set(eth, offset, val) \ 596 airoha_rmw((eth)->fe_regs, (offset), 0, (val)) 597 #define airoha_fe_clear(eth, offset, val) \ 598 airoha_rmw((eth)->fe_regs, (offset), (val), 0) 599 600 #define airoha_qdma_rr(qdma, offset) \ 601 airoha_rr((qdma)->regs, (offset)) 602 #define airoha_qdma_wr(qdma, offset, val) \ 603 airoha_wr((qdma)->regs, (offset), (val)) 604 #define airoha_qdma_rmw(qdma, offset, mask, val) \ 605 airoha_rmw((qdma)->regs, (offset), (mask), (val)) 606 #define airoha_qdma_set(qdma, offset, val) \ 607 airoha_rmw((qdma)->regs, (offset), 0, (val)) 608 #define airoha_qdma_clear(qdma, offset, val) \ 609 airoha_rmw((qdma)->regs, (offset), (val), 0) 610 611 static inline bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port) 612 { 613 /* GDM1 port on EN7581 SoC is connected to the lan dsa switch. 614 * GDM{2,3,4} can be used as wan port connected to an external 615 * phy module. 616 */ 617 return port->id == 1; 618 } 619 620 bool airoha_is_valid_gdm_port(struct airoha_eth *eth, 621 struct airoha_gdm_port *port); 622 623 void airoha_ppe_check_skb(struct airoha_ppe_dev *dev, struct sk_buff *skb, 624 u16 hash, bool rx_wlan); 625 int airoha_ppe_setup_tc_block_cb(struct airoha_ppe_dev *dev, void *type_data); 626 int airoha_ppe_init(struct airoha_eth *eth); 627 void airoha_ppe_deinit(struct airoha_eth *eth); 628 void airoha_ppe_init_upd_mem(struct airoha_gdm_port *port); 629 struct airoha_foe_entry *airoha_ppe_foe_get_entry(struct airoha_ppe *ppe, 630 u32 hash); 631 void airoha_ppe_foe_entry_get_stats(struct airoha_ppe *ppe, u32 hash, 632 struct airoha_foe_stats64 *stats); 633 634 #ifdef CONFIG_DEBUG_FS 635 int airoha_ppe_debugfs_init(struct airoha_ppe *ppe); 636 #else 637 static inline int airoha_ppe_debugfs_init(struct airoha_ppe *ppe) 638 { 639 return 0; 640 } 641 #endif 642 643 #endif /* AIROHA_ETH_H */ 644