1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2024 AIROHA Inc 4 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 5 */ 6 7 #ifndef AIROHA_ETH_H 8 #define AIROHA_ETH_H 9 10 #include <linux/debugfs.h> 11 #include <linux/etherdevice.h> 12 #include <linux/iopoll.h> 13 #include <linux/kernel.h> 14 #include <linux/netdevice.h> 15 #include <linux/reset.h> 16 #include <linux/soc/airoha/airoha_offload.h> 17 #include <net/dsa.h> 18 19 #define AIROHA_MAX_NUM_GDM_PORTS 4 20 #define AIROHA_MAX_NUM_QDMA 2 21 #define AIROHA_MAX_NUM_IRQ_BANKS 4 22 #define AIROHA_MAX_DSA_PORTS 7 23 #define AIROHA_MAX_NUM_RSTS 3 24 #define AIROHA_MAX_MTU 9216 25 #define AIROHA_MAX_PACKET_SIZE 2048 26 #define AIROHA_NUM_QOS_CHANNELS 4 27 #define AIROHA_NUM_QOS_QUEUES 8 28 #define AIROHA_NUM_TX_RING 32 29 #define AIROHA_NUM_RX_RING 32 30 #define AIROHA_NUM_NETDEV_TX_RINGS (AIROHA_NUM_TX_RING + \ 31 AIROHA_NUM_QOS_CHANNELS) 32 #define AIROHA_FE_MC_MAX_VLAN_TABLE 64 33 #define AIROHA_FE_MC_MAX_VLAN_PORT 16 34 #define AIROHA_NUM_TX_IRQ 2 35 #define HW_DSCP_NUM 2048 36 #define IRQ_QUEUE_LEN(_n) ((_n) ? 1024 : 2048) 37 #define TX_DSCP_NUM 1024 38 #define RX_DSCP_NUM(_n) \ 39 ((_n) == 2 ? 128 : \ 40 (_n) == 11 ? 128 : \ 41 (_n) == 15 ? 128 : \ 42 (_n) == 0 ? 1024 : 16) 43 44 #define PSE_RSV_PAGES 128 45 #define PSE_QUEUE_RSV_PAGES 64 46 47 #define QDMA_METER_IDX(_n) ((_n) & 0xff) 48 #define QDMA_METER_GROUP(_n) (((_n) >> 8) & 0x3) 49 50 #define PPE_SRAM_NUM_ENTRIES (8 * 1024) 51 #define PPE_STATS_NUM_ENTRIES (4 * 1024) 52 #define PPE_DRAM_NUM_ENTRIES (16 * 1024) 53 #define PPE_ENTRY_SIZE 80 54 #define PPE_RAM_NUM_ENTRIES_SHIFT(_n) (__ffs((_n) >> 10)) 55 56 #define MTK_HDR_LEN 4 57 #define MTK_HDR_XMIT_TAGGED_TPID_8100 1 58 #define MTK_HDR_XMIT_TAGGED_TPID_88A8 2 59 60 enum { 61 QDMA_INT_REG_IDX0, 62 QDMA_INT_REG_IDX1, 63 QDMA_INT_REG_IDX2, 64 QDMA_INT_REG_IDX3, 65 QDMA_INT_REG_IDX4, 66 QDMA_INT_REG_MAX 67 }; 68 69 enum { 70 HSGMII_LAN_7581_PCIE0_SRCPORT = 0x16, 71 HSGMII_LAN_7581_PCIE1_SRCPORT, 72 HSGMII_LAN_7581_ETH_SRCPORT, 73 HSGMII_LAN_7581_USB_SRCPORT, 74 }; 75 76 enum { 77 HSGMII_LAN_7583_ETH_SRCPORT = 0x16, 78 HSGMII_LAN_7583_PCIE_SRCPORT = 0x18, 79 HSGMII_LAN_7583_USB_SRCPORT, 80 }; 81 82 enum { 83 XSI_PCIE0_VIP_PORT_MASK = BIT(22), 84 XSI_PCIE1_VIP_PORT_MASK = BIT(23), 85 XSI_USB_VIP_PORT_MASK = BIT(25), 86 XSI_ETH_VIP_PORT_MASK = BIT(24), 87 }; 88 89 enum { 90 DEV_STATE_INITIALIZED, 91 }; 92 93 enum { 94 CDM_CRSN_QSEL_Q1 = 1, 95 CDM_CRSN_QSEL_Q5 = 5, 96 CDM_CRSN_QSEL_Q6 = 6, 97 CDM_CRSN_QSEL_Q15 = 15, 98 }; 99 100 enum { 101 CRSN_08 = 0x8, 102 CRSN_21 = 0x15, /* KA */ 103 CRSN_22 = 0x16, /* hit bind and force route to CPU */ 104 CRSN_24 = 0x18, 105 CRSN_25 = 0x19, 106 }; 107 108 enum airoha_gdm_index { 109 AIROHA_GDM1_IDX = 1, 110 AIROHA_GDM2_IDX = 2, 111 AIROHA_GDM3_IDX = 3, 112 AIROHA_GDM4_IDX = 4, 113 }; 114 115 enum { 116 FE_PSE_PORT_CDM1, 117 FE_PSE_PORT_GDM1, 118 FE_PSE_PORT_GDM2, 119 FE_PSE_PORT_GDM3, 120 FE_PSE_PORT_PPE1, 121 FE_PSE_PORT_CDM2, 122 FE_PSE_PORT_CDM3, 123 FE_PSE_PORT_CDM4, 124 FE_PSE_PORT_PPE2, 125 FE_PSE_PORT_GDM4, 126 FE_PSE_PORT_CDM5, 127 FE_PSE_PORT_DROP = 0xf, 128 }; 129 130 enum tx_sched_mode { 131 TC_SCH_WRR8, 132 TC_SCH_SP, 133 TC_SCH_WRR7, 134 TC_SCH_WRR6, 135 TC_SCH_WRR5, 136 TC_SCH_WRR4, 137 TC_SCH_WRR3, 138 TC_SCH_WRR2, 139 }; 140 141 enum trtcm_unit_type { 142 TRTCM_BYTE_UNIT, 143 TRTCM_PACKET_UNIT, 144 }; 145 146 enum trtcm_param_type { 147 TRTCM_MISC_MODE, /* meter_en, pps_mode, tick_sel */ 148 TRTCM_TOKEN_RATE_MODE, 149 TRTCM_BUCKETSIZE_SHIFT_MODE, 150 TRTCM_BUCKET_COUNTER_MODE, 151 }; 152 153 enum trtcm_mode_type { 154 TRTCM_COMMIT_MODE, 155 TRTCM_PEAK_MODE, 156 }; 157 158 enum trtcm_param { 159 TRTCM_TICK_SEL = BIT(0), 160 TRTCM_PKT_MODE = BIT(1), 161 TRTCM_METER_MODE = BIT(2), 162 }; 163 164 #define MIN_TOKEN_SIZE 4096 165 #define MAX_TOKEN_SIZE_OFFSET 17 166 #define TRTCM_TOKEN_RATE_MASK GENMASK(23, 6) 167 #define TRTCM_TOKEN_RATE_FRACTION_MASK GENMASK(5, 0) 168 169 struct airoha_queue_entry { 170 union { 171 void *buf; 172 struct sk_buff *skb; 173 }; 174 dma_addr_t dma_addr; 175 u16 dma_len; 176 }; 177 178 struct airoha_queue { 179 struct airoha_qdma *qdma; 180 181 /* protect concurrent queue accesses */ 182 spinlock_t lock; 183 struct airoha_queue_entry *entry; 184 struct airoha_qdma_desc *desc; 185 u16 head; 186 u16 tail; 187 188 int queued; 189 int ndesc; 190 int free_thr; 191 int buf_size; 192 193 struct napi_struct napi; 194 struct page_pool *page_pool; 195 struct sk_buff *skb; 196 }; 197 198 struct airoha_tx_irq_queue { 199 struct airoha_qdma *qdma; 200 201 struct napi_struct napi; 202 203 int size; 204 u32 *q; 205 }; 206 207 struct airoha_hw_stats { 208 /* protect concurrent hw_stats accesses */ 209 spinlock_t lock; 210 struct u64_stats_sync syncp; 211 212 /* get_stats64 */ 213 u64 rx_ok_pkts; 214 u64 tx_ok_pkts; 215 u64 rx_ok_bytes; 216 u64 tx_ok_bytes; 217 u64 rx_multicast; 218 u64 rx_errors; 219 u64 rx_drops; 220 u64 tx_drops; 221 u64 rx_crc_error; 222 u64 rx_over_errors; 223 /* ethtool stats */ 224 u64 tx_broadcast; 225 u64 tx_multicast; 226 u64 tx_len[7]; 227 u64 rx_broadcast; 228 u64 rx_fragment; 229 u64 rx_jabber; 230 u64 rx_len[7]; 231 }; 232 233 enum { 234 AIROHA_FOE_STATE_INVALID, 235 AIROHA_FOE_STATE_UNBIND, 236 AIROHA_FOE_STATE_BIND, 237 AIROHA_FOE_STATE_FIN 238 }; 239 240 enum { 241 PPE_PKT_TYPE_IPV4_HNAPT = 0, 242 PPE_PKT_TYPE_IPV4_ROUTE = 1, 243 PPE_PKT_TYPE_BRIDGE = 2, 244 PPE_PKT_TYPE_IPV4_DSLITE = 3, 245 PPE_PKT_TYPE_IPV6_ROUTE_3T = 4, 246 PPE_PKT_TYPE_IPV6_ROUTE_5T = 5, 247 PPE_PKT_TYPE_IPV6_6RD = 7, 248 }; 249 250 #define AIROHA_FOE_MAC_SMAC_ID GENMASK(20, 16) 251 #define AIROHA_FOE_MAC_PPPOE_ID GENMASK(15, 0) 252 253 #define AIROHA_FOE_MAC_WDMA_QOS GENMASK(15, 12) 254 #define AIROHA_FOE_MAC_WDMA_BAND BIT(11) 255 #define AIROHA_FOE_MAC_WDMA_WCID GENMASK(10, 0) 256 257 struct airoha_foe_mac_info_common { 258 u16 vlan1; 259 u16 etype; 260 261 u32 dest_mac_hi; 262 263 u16 vlan2; 264 u16 dest_mac_lo; 265 266 u32 src_mac_hi; 267 }; 268 269 struct airoha_foe_mac_info { 270 struct airoha_foe_mac_info_common common; 271 272 u16 pppoe_id; 273 u16 src_mac_lo; 274 275 u32 meter; 276 }; 277 278 #define AIROHA_FOE_IB1_UNBIND_PREBIND BIT(24) 279 #define AIROHA_FOE_IB1_UNBIND_PACKETS GENMASK(23, 8) 280 #define AIROHA_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0) 281 282 #define AIROHA_FOE_IB1_BIND_STATIC BIT(31) 283 #define AIROHA_FOE_IB1_BIND_UDP BIT(30) 284 #define AIROHA_FOE_IB1_BIND_STATE GENMASK(29, 28) 285 #define AIROHA_FOE_IB1_BIND_PACKET_TYPE GENMASK(27, 25) 286 #define AIROHA_FOE_IB1_BIND_TTL BIT(24) 287 #define AIROHA_FOE_IB1_BIND_TUNNEL_DECAP BIT(23) 288 #define AIROHA_FOE_IB1_BIND_PPPOE BIT(22) 289 #define AIROHA_FOE_IB1_BIND_VPM GENMASK(21, 20) 290 #define AIROHA_FOE_IB1_BIND_VLAN_LAYER GENMASK(19, 16) 291 #define AIROHA_FOE_IB1_BIND_KEEPALIVE BIT(15) 292 #define AIROHA_FOE_IB1_BIND_TIMESTAMP GENMASK(14, 0) 293 294 #define AIROHA_FOE_IB2_DSCP GENMASK(31, 24) 295 #define AIROHA_FOE_IB2_PORT_AG GENMASK(23, 13) 296 #define AIROHA_FOE_IB2_PCP BIT(12) 297 #define AIROHA_FOE_IB2_MULTICAST BIT(11) 298 #define AIROHA_FOE_IB2_FAST_PATH BIT(10) 299 #define AIROHA_FOE_IB2_PSE_QOS BIT(9) 300 #define AIROHA_FOE_IB2_PSE_PORT GENMASK(8, 5) 301 #define AIROHA_FOE_IB2_NBQ GENMASK(4, 0) 302 303 #define AIROHA_FOE_ACTDP GENMASK(31, 24) 304 #define AIROHA_FOE_SHAPER_ID GENMASK(23, 16) 305 #define AIROHA_FOE_CHANNEL GENMASK(15, 11) 306 #define AIROHA_FOE_QID GENMASK(10, 8) 307 #define AIROHA_FOE_DPI BIT(7) 308 #define AIROHA_FOE_TUNNEL BIT(6) 309 #define AIROHA_FOE_TUNNEL_ID GENMASK(5, 0) 310 311 #define AIROHA_FOE_TUNNEL_MTU GENMASK(31, 16) 312 #define AIROHA_FOE_ACNT_GRP3 GENMASK(15, 9) 313 #define AIROHA_FOE_METER_GRP3 GENMASK(8, 5) 314 #define AIROHA_FOE_METER_GRP2 GENMASK(4, 0) 315 316 struct airoha_foe_bridge { 317 u32 dest_mac_hi; 318 319 u16 src_mac_hi; 320 u16 dest_mac_lo; 321 322 u32 src_mac_lo; 323 324 u32 ib2; 325 326 u32 rsv[5]; 327 328 u32 data; 329 330 struct airoha_foe_mac_info l2; 331 }; 332 333 struct airoha_foe_ipv4_tuple { 334 u32 src_ip; 335 u32 dest_ip; 336 union { 337 struct { 338 u16 dest_port; 339 u16 src_port; 340 }; 341 struct { 342 u8 protocol; 343 u8 _pad[3]; /* fill with 0xa5a5a5 */ 344 }; 345 u32 ports; 346 }; 347 }; 348 349 struct airoha_foe_ipv4 { 350 struct airoha_foe_ipv4_tuple orig_tuple; 351 352 u32 ib2; 353 354 struct airoha_foe_ipv4_tuple new_tuple; 355 356 u32 rsv[2]; 357 358 u32 data; 359 360 struct airoha_foe_mac_info l2; 361 }; 362 363 struct airoha_foe_ipv4_dslite { 364 struct airoha_foe_ipv4_tuple ip4; 365 366 u32 ib2; 367 368 u8 flow_label[3]; 369 u8 priority; 370 371 u32 rsv[4]; 372 373 u32 data; 374 375 struct airoha_foe_mac_info l2; 376 }; 377 378 struct airoha_foe_ipv6 { 379 u32 src_ip[4]; 380 u32 dest_ip[4]; 381 382 union { 383 struct { 384 u16 dest_port; 385 u16 src_port; 386 }; 387 struct { 388 u8 protocol; 389 u8 pad[3]; 390 }; 391 u32 ports; 392 }; 393 394 u32 data; 395 396 u32 ib2; 397 398 struct airoha_foe_mac_info_common l2; 399 400 u32 meter; 401 }; 402 403 struct airoha_foe_entry { 404 union { 405 struct { 406 u32 ib1; 407 union { 408 struct airoha_foe_bridge bridge; 409 struct airoha_foe_ipv4 ipv4; 410 struct airoha_foe_ipv4_dslite dslite; 411 struct airoha_foe_ipv6 ipv6; 412 DECLARE_FLEX_ARRAY(u32, d); 413 }; 414 }; 415 u8 data[PPE_ENTRY_SIZE]; 416 }; 417 }; 418 419 struct airoha_foe_stats { 420 u32 bytes; 421 u32 packets; 422 }; 423 424 struct airoha_foe_stats64 { 425 u64 bytes; 426 u64 packets; 427 }; 428 429 struct airoha_flow_data { 430 struct ethhdr eth; 431 432 union { 433 struct { 434 __be32 src_addr; 435 __be32 dst_addr; 436 } v4; 437 438 struct { 439 struct in6_addr src_addr; 440 struct in6_addr dst_addr; 441 } v6; 442 }; 443 444 __be16 src_port; 445 __be16 dst_port; 446 447 struct { 448 struct { 449 u16 id; 450 __be16 proto; 451 } hdr[2]; 452 u8 num; 453 } vlan; 454 struct { 455 u16 sid; 456 u8 num; 457 } pppoe; 458 }; 459 460 enum airoha_flow_entry_type { 461 FLOW_TYPE_L4, 462 FLOW_TYPE_L2, 463 FLOW_TYPE_L2_SUBFLOW, 464 }; 465 466 struct airoha_flow_table_entry { 467 union { 468 struct hlist_node list; /* PPE L3 flow entry */ 469 struct { 470 struct rhash_head l2_node; /* L2 flow entry */ 471 struct hlist_head l2_flows; /* PPE L2 subflows list */ 472 }; 473 }; 474 475 struct hlist_node l2_subflow_node; /* PPE L2 subflow entry */ 476 u32 hash; 477 478 struct airoha_foe_stats64 stats; 479 enum airoha_flow_entry_type type; 480 481 struct rhash_head node; 482 unsigned long cookie; 483 484 /* Must be last --ends in a flexible-array member. */ 485 struct airoha_foe_entry data; 486 }; 487 488 struct airoha_wdma_info { 489 u8 idx; 490 u8 queue; 491 u16 wcid; 492 u8 bss; 493 }; 494 495 /* RX queue to IRQ mapping: BIT(q) in IRQ(n) */ 496 #define RX_IRQ0_BANK_PIN_MASK 0x839f 497 #define RX_IRQ1_BANK_PIN_MASK 0x7fe00000 498 #define RX_IRQ2_BANK_PIN_MASK 0x20 499 #define RX_IRQ3_BANK_PIN_MASK 0x40 500 #define RX_IRQ_BANK_PIN_MASK(_n) \ 501 (((_n) == 3) ? RX_IRQ3_BANK_PIN_MASK : \ 502 ((_n) == 2) ? RX_IRQ2_BANK_PIN_MASK : \ 503 ((_n) == 1) ? RX_IRQ1_BANK_PIN_MASK : \ 504 RX_IRQ0_BANK_PIN_MASK) 505 506 struct airoha_irq_bank { 507 struct airoha_qdma *qdma; 508 509 /* protect concurrent irqmask accesses */ 510 spinlock_t irq_lock; 511 u32 irqmask[QDMA_INT_REG_MAX]; 512 int irq; 513 }; 514 515 struct airoha_qdma { 516 struct airoha_eth *eth; 517 void __iomem *regs; 518 519 atomic_t users; 520 521 struct airoha_irq_bank irq_banks[AIROHA_MAX_NUM_IRQ_BANKS]; 522 523 struct airoha_tx_irq_queue q_tx_irq[AIROHA_NUM_TX_IRQ]; 524 525 struct airoha_queue q_tx[AIROHA_NUM_TX_RING]; 526 struct airoha_queue q_rx[AIROHA_NUM_RX_RING]; 527 }; 528 529 struct airoha_gdm_port { 530 struct airoha_qdma *qdma; 531 struct net_device *dev; 532 int id; 533 534 struct airoha_hw_stats stats; 535 536 DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS); 537 538 /* qos stats counters */ 539 u64 cpu_tx_packets; 540 u64 fwd_tx_packets; 541 542 struct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS]; 543 }; 544 545 #define AIROHA_RXD4_PPE_CPU_REASON GENMASK(20, 16) 546 #define AIROHA_RXD4_FOE_ENTRY GENMASK(15, 0) 547 548 struct airoha_ppe { 549 struct airoha_ppe_dev dev; 550 struct airoha_eth *eth; 551 552 void *foe; 553 dma_addr_t foe_dma; 554 555 struct rhashtable l2_flows; 556 557 struct hlist_head *foe_flow; 558 u16 *foe_check_time; 559 560 struct airoha_foe_stats *foe_stats; 561 dma_addr_t foe_stats_dma; 562 563 struct dentry *debugfs_dir; 564 }; 565 566 struct airoha_eth_soc_data { 567 u16 version; 568 const char * const *xsi_rsts_names; 569 int num_xsi_rsts; 570 int num_ppe; 571 struct { 572 int (*get_src_port_id)(struct airoha_gdm_port *port, int nbq); 573 } ops; 574 }; 575 576 struct airoha_eth { 577 struct device *dev; 578 579 const struct airoha_eth_soc_data *soc; 580 581 unsigned long state; 582 void __iomem *fe_regs; 583 584 struct airoha_npu __rcu *npu; 585 586 struct airoha_ppe *ppe; 587 struct rhashtable flow_table; 588 589 struct reset_control_bulk_data rsts[AIROHA_MAX_NUM_RSTS]; 590 struct reset_control_bulk_data *xsi_rsts; 591 592 struct net_device *napi_dev; 593 594 struct airoha_qdma qdma[AIROHA_MAX_NUM_QDMA]; 595 struct airoha_gdm_port *ports[AIROHA_MAX_NUM_GDM_PORTS]; 596 }; 597 598 u32 airoha_rr(void __iomem *base, u32 offset); 599 void airoha_wr(void __iomem *base, u32 offset, u32 val); 600 u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val); 601 602 #define airoha_fe_rr(eth, offset) \ 603 airoha_rr((eth)->fe_regs, (offset)) 604 #define airoha_fe_wr(eth, offset, val) \ 605 airoha_wr((eth)->fe_regs, (offset), (val)) 606 #define airoha_fe_rmw(eth, offset, mask, val) \ 607 airoha_rmw((eth)->fe_regs, (offset), (mask), (val)) 608 #define airoha_fe_set(eth, offset, val) \ 609 airoha_rmw((eth)->fe_regs, (offset), 0, (val)) 610 #define airoha_fe_clear(eth, offset, val) \ 611 airoha_rmw((eth)->fe_regs, (offset), (val), 0) 612 613 #define airoha_qdma_rr(qdma, offset) \ 614 airoha_rr((qdma)->regs, (offset)) 615 #define airoha_qdma_wr(qdma, offset, val) \ 616 airoha_wr((qdma)->regs, (offset), (val)) 617 #define airoha_qdma_rmw(qdma, offset, mask, val) \ 618 airoha_rmw((qdma)->regs, (offset), (mask), (val)) 619 #define airoha_qdma_set(qdma, offset, val) \ 620 airoha_rmw((qdma)->regs, (offset), 0, (val)) 621 #define airoha_qdma_clear(qdma, offset, val) \ 622 airoha_rmw((qdma)->regs, (offset), (val), 0) 623 624 static inline bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port) 625 { 626 /* GDM1 port on EN7581 SoC is connected to the lan dsa switch. 627 * GDM{2,3,4} can be used as wan port connected to an external 628 * phy module. 629 */ 630 return port->id == 1; 631 } 632 633 static inline bool airoha_is_7581(struct airoha_eth *eth) 634 { 635 return eth->soc->version == 0x7581; 636 } 637 638 static inline bool airoha_is_7583(struct airoha_eth *eth) 639 { 640 return eth->soc->version == 0x7583; 641 } 642 643 bool airoha_is_valid_gdm_port(struct airoha_eth *eth, 644 struct airoha_gdm_port *port); 645 646 bool airoha_ppe_is_enabled(struct airoha_eth *eth, int index); 647 void airoha_ppe_check_skb(struct airoha_ppe_dev *dev, struct sk_buff *skb, 648 u16 hash, bool rx_wlan); 649 int airoha_ppe_setup_tc_block_cb(struct airoha_ppe_dev *dev, void *type_data); 650 int airoha_ppe_init(struct airoha_eth *eth); 651 void airoha_ppe_deinit(struct airoha_eth *eth); 652 void airoha_ppe_init_upd_mem(struct airoha_gdm_port *port); 653 u32 airoha_ppe_get_total_num_entries(struct airoha_ppe *ppe); 654 struct airoha_foe_entry *airoha_ppe_foe_get_entry(struct airoha_ppe *ppe, 655 u32 hash); 656 void airoha_ppe_foe_entry_get_stats(struct airoha_ppe *ppe, u32 hash, 657 struct airoha_foe_stats64 *stats); 658 659 #ifdef CONFIG_DEBUG_FS 660 int airoha_ppe_debugfs_init(struct airoha_ppe *ppe); 661 #else 662 static inline int airoha_ppe_debugfs_init(struct airoha_ppe *ppe) 663 { 664 return 0; 665 } 666 #endif 667 668 #endif /* AIROHA_ETH_H */ 669