1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2024 AIROHA Inc 4 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 5 */ 6 7 #ifndef AIROHA_ETH_H 8 #define AIROHA_ETH_H 9 10 #include <linux/debugfs.h> 11 #include <linux/etherdevice.h> 12 #include <linux/iopoll.h> 13 #include <linux/kernel.h> 14 #include <linux/netdevice.h> 15 #include <linux/reset.h> 16 #include <net/dsa.h> 17 18 #define AIROHA_MAX_NUM_GDM_PORTS 4 19 #define AIROHA_MAX_NUM_QDMA 2 20 #define AIROHA_MAX_NUM_IRQ_BANKS 4 21 #define AIROHA_MAX_DSA_PORTS 7 22 #define AIROHA_MAX_NUM_RSTS 3 23 #define AIROHA_MAX_NUM_XSI_RSTS 5 24 #define AIROHA_MAX_MTU 9216 25 #define AIROHA_MAX_PACKET_SIZE 2048 26 #define AIROHA_NUM_QOS_CHANNELS 4 27 #define AIROHA_NUM_QOS_QUEUES 8 28 #define AIROHA_NUM_TX_RING 32 29 #define AIROHA_NUM_RX_RING 32 30 #define AIROHA_NUM_NETDEV_TX_RINGS (AIROHA_NUM_TX_RING + \ 31 AIROHA_NUM_QOS_CHANNELS) 32 #define AIROHA_FE_MC_MAX_VLAN_TABLE 64 33 #define AIROHA_FE_MC_MAX_VLAN_PORT 16 34 #define AIROHA_NUM_TX_IRQ 2 35 #define HW_DSCP_NUM 2048 36 #define IRQ_QUEUE_LEN(_n) ((_n) ? 1024 : 2048) 37 #define TX_DSCP_NUM 1024 38 #define RX_DSCP_NUM(_n) \ 39 ((_n) == 2 ? 128 : \ 40 (_n) == 11 ? 128 : \ 41 (_n) == 15 ? 128 : \ 42 (_n) == 0 ? 1024 : 16) 43 44 #define PSE_RSV_PAGES 128 45 #define PSE_QUEUE_RSV_PAGES 64 46 47 #define QDMA_METER_IDX(_n) ((_n) & 0xff) 48 #define QDMA_METER_GROUP(_n) (((_n) >> 8) & 0x3) 49 50 #define PPE_NUM 2 51 #define PPE1_SRAM_NUM_ENTRIES (8 * 1024) 52 #define PPE_SRAM_NUM_ENTRIES (2 * PPE1_SRAM_NUM_ENTRIES) 53 #ifdef CONFIG_NET_AIROHA_FLOW_STATS 54 #define PPE1_STATS_NUM_ENTRIES (4 * 1024) 55 #else 56 #define PPE1_STATS_NUM_ENTRIES 0 57 #endif /* CONFIG_NET_AIROHA_FLOW_STATS */ 58 #define PPE_STATS_NUM_ENTRIES (2 * PPE1_STATS_NUM_ENTRIES) 59 #define PPE1_SRAM_NUM_DATA_ENTRIES (PPE1_SRAM_NUM_ENTRIES - PPE1_STATS_NUM_ENTRIES) 60 #define PPE_SRAM_NUM_DATA_ENTRIES (2 * PPE1_SRAM_NUM_DATA_ENTRIES) 61 #define PPE_DRAM_NUM_ENTRIES (16 * 1024) 62 #define PPE_NUM_ENTRIES (PPE_SRAM_NUM_ENTRIES + PPE_DRAM_NUM_ENTRIES) 63 #define PPE_HASH_MASK (PPE_NUM_ENTRIES - 1) 64 #define PPE_ENTRY_SIZE 80 65 #define PPE_RAM_NUM_ENTRIES_SHIFT(_n) (__ffs((_n) >> 10)) 66 67 #define MTK_HDR_LEN 4 68 #define MTK_HDR_XMIT_TAGGED_TPID_8100 1 69 #define MTK_HDR_XMIT_TAGGED_TPID_88A8 2 70 71 enum { 72 QDMA_INT_REG_IDX0, 73 QDMA_INT_REG_IDX1, 74 QDMA_INT_REG_IDX2, 75 QDMA_INT_REG_IDX3, 76 QDMA_INT_REG_IDX4, 77 QDMA_INT_REG_MAX 78 }; 79 80 enum { 81 HSGMII_LAN_PCIE0_SRCPORT = 0x16, 82 HSGMII_LAN_PCIE1_SRCPORT, 83 HSGMII_LAN_ETH_SRCPORT, 84 HSGMII_LAN_USB_SRCPORT, 85 }; 86 87 enum { 88 XSI_PCIE0_VIP_PORT_MASK = BIT(22), 89 XSI_PCIE1_VIP_PORT_MASK = BIT(23), 90 XSI_USB_VIP_PORT_MASK = BIT(25), 91 XSI_ETH_VIP_PORT_MASK = BIT(24), 92 }; 93 94 enum { 95 DEV_STATE_INITIALIZED, 96 }; 97 98 enum { 99 CDM_CRSN_QSEL_Q1 = 1, 100 CDM_CRSN_QSEL_Q5 = 5, 101 CDM_CRSN_QSEL_Q6 = 6, 102 CDM_CRSN_QSEL_Q15 = 15, 103 }; 104 105 enum { 106 CRSN_08 = 0x8, 107 CRSN_21 = 0x15, /* KA */ 108 CRSN_22 = 0x16, /* hit bind and force route to CPU */ 109 CRSN_24 = 0x18, 110 CRSN_25 = 0x19, 111 }; 112 113 enum { 114 FE_PSE_PORT_CDM1, 115 FE_PSE_PORT_GDM1, 116 FE_PSE_PORT_GDM2, 117 FE_PSE_PORT_GDM3, 118 FE_PSE_PORT_PPE1, 119 FE_PSE_PORT_CDM2, 120 FE_PSE_PORT_CDM3, 121 FE_PSE_PORT_CDM4, 122 FE_PSE_PORT_PPE2, 123 FE_PSE_PORT_GDM4, 124 FE_PSE_PORT_CDM5, 125 FE_PSE_PORT_DROP = 0xf, 126 }; 127 128 enum tx_sched_mode { 129 TC_SCH_WRR8, 130 TC_SCH_SP, 131 TC_SCH_WRR7, 132 TC_SCH_WRR6, 133 TC_SCH_WRR5, 134 TC_SCH_WRR4, 135 TC_SCH_WRR3, 136 TC_SCH_WRR2, 137 }; 138 139 enum trtcm_unit_type { 140 TRTCM_BYTE_UNIT, 141 TRTCM_PACKET_UNIT, 142 }; 143 144 enum trtcm_param_type { 145 TRTCM_MISC_MODE, /* meter_en, pps_mode, tick_sel */ 146 TRTCM_TOKEN_RATE_MODE, 147 TRTCM_BUCKETSIZE_SHIFT_MODE, 148 TRTCM_BUCKET_COUNTER_MODE, 149 }; 150 151 enum trtcm_mode_type { 152 TRTCM_COMMIT_MODE, 153 TRTCM_PEAK_MODE, 154 }; 155 156 enum trtcm_param { 157 TRTCM_TICK_SEL = BIT(0), 158 TRTCM_PKT_MODE = BIT(1), 159 TRTCM_METER_MODE = BIT(2), 160 }; 161 162 #define MIN_TOKEN_SIZE 4096 163 #define MAX_TOKEN_SIZE_OFFSET 17 164 #define TRTCM_TOKEN_RATE_MASK GENMASK(23, 6) 165 #define TRTCM_TOKEN_RATE_FRACTION_MASK GENMASK(5, 0) 166 167 struct airoha_queue_entry { 168 union { 169 void *buf; 170 struct sk_buff *skb; 171 }; 172 dma_addr_t dma_addr; 173 u16 dma_len; 174 }; 175 176 struct airoha_queue { 177 struct airoha_qdma *qdma; 178 179 /* protect concurrent queue accesses */ 180 spinlock_t lock; 181 struct airoha_queue_entry *entry; 182 struct airoha_qdma_desc *desc; 183 u16 head; 184 u16 tail; 185 186 int queued; 187 int ndesc; 188 int free_thr; 189 int buf_size; 190 191 struct napi_struct napi; 192 struct page_pool *page_pool; 193 struct sk_buff *skb; 194 }; 195 196 struct airoha_tx_irq_queue { 197 struct airoha_qdma *qdma; 198 199 struct napi_struct napi; 200 201 int size; 202 u32 *q; 203 }; 204 205 struct airoha_hw_stats { 206 /* protect concurrent hw_stats accesses */ 207 spinlock_t lock; 208 struct u64_stats_sync syncp; 209 210 /* get_stats64 */ 211 u64 rx_ok_pkts; 212 u64 tx_ok_pkts; 213 u64 rx_ok_bytes; 214 u64 tx_ok_bytes; 215 u64 rx_multicast; 216 u64 rx_errors; 217 u64 rx_drops; 218 u64 tx_drops; 219 u64 rx_crc_error; 220 u64 rx_over_errors; 221 /* ethtool stats */ 222 u64 tx_broadcast; 223 u64 tx_multicast; 224 u64 tx_len[7]; 225 u64 rx_broadcast; 226 u64 rx_fragment; 227 u64 rx_jabber; 228 u64 rx_len[7]; 229 }; 230 231 enum { 232 PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED = 0x0f, 233 }; 234 235 enum { 236 AIROHA_FOE_STATE_INVALID, 237 AIROHA_FOE_STATE_UNBIND, 238 AIROHA_FOE_STATE_BIND, 239 AIROHA_FOE_STATE_FIN 240 }; 241 242 enum { 243 PPE_PKT_TYPE_IPV4_HNAPT = 0, 244 PPE_PKT_TYPE_IPV4_ROUTE = 1, 245 PPE_PKT_TYPE_BRIDGE = 2, 246 PPE_PKT_TYPE_IPV4_DSLITE = 3, 247 PPE_PKT_TYPE_IPV6_ROUTE_3T = 4, 248 PPE_PKT_TYPE_IPV6_ROUTE_5T = 5, 249 PPE_PKT_TYPE_IPV6_6RD = 7, 250 }; 251 252 #define AIROHA_FOE_MAC_SMAC_ID GENMASK(20, 16) 253 #define AIROHA_FOE_MAC_PPPOE_ID GENMASK(15, 0) 254 255 #define AIROHA_FOE_MAC_WDMA_QOS GENMASK(15, 12) 256 #define AIROHA_FOE_MAC_WDMA_BAND BIT(11) 257 #define AIROHA_FOE_MAC_WDMA_WCID GENMASK(10, 0) 258 259 struct airoha_foe_mac_info_common { 260 u16 vlan1; 261 u16 etype; 262 263 u32 dest_mac_hi; 264 265 u16 vlan2; 266 u16 dest_mac_lo; 267 268 u32 src_mac_hi; 269 }; 270 271 struct airoha_foe_mac_info { 272 struct airoha_foe_mac_info_common common; 273 274 u16 pppoe_id; 275 u16 src_mac_lo; 276 277 u32 meter; 278 }; 279 280 #define AIROHA_FOE_IB1_UNBIND_PREBIND BIT(24) 281 #define AIROHA_FOE_IB1_UNBIND_PACKETS GENMASK(23, 8) 282 #define AIROHA_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0) 283 284 #define AIROHA_FOE_IB1_BIND_STATIC BIT(31) 285 #define AIROHA_FOE_IB1_BIND_UDP BIT(30) 286 #define AIROHA_FOE_IB1_BIND_STATE GENMASK(29, 28) 287 #define AIROHA_FOE_IB1_BIND_PACKET_TYPE GENMASK(27, 25) 288 #define AIROHA_FOE_IB1_BIND_TTL BIT(24) 289 #define AIROHA_FOE_IB1_BIND_TUNNEL_DECAP BIT(23) 290 #define AIROHA_FOE_IB1_BIND_PPPOE BIT(22) 291 #define AIROHA_FOE_IB1_BIND_VPM GENMASK(21, 20) 292 #define AIROHA_FOE_IB1_BIND_VLAN_LAYER GENMASK(19, 16) 293 #define AIROHA_FOE_IB1_BIND_KEEPALIVE BIT(15) 294 #define AIROHA_FOE_IB1_BIND_TIMESTAMP GENMASK(14, 0) 295 296 #define AIROHA_FOE_IB2_DSCP GENMASK(31, 24) 297 #define AIROHA_FOE_IB2_PORT_AG GENMASK(23, 13) 298 #define AIROHA_FOE_IB2_PCP BIT(12) 299 #define AIROHA_FOE_IB2_MULTICAST BIT(11) 300 #define AIROHA_FOE_IB2_FAST_PATH BIT(10) 301 #define AIROHA_FOE_IB2_PSE_QOS BIT(9) 302 #define AIROHA_FOE_IB2_PSE_PORT GENMASK(8, 5) 303 #define AIROHA_FOE_IB2_NBQ GENMASK(4, 0) 304 305 #define AIROHA_FOE_ACTDP GENMASK(31, 24) 306 #define AIROHA_FOE_SHAPER_ID GENMASK(23, 16) 307 #define AIROHA_FOE_CHANNEL GENMASK(15, 11) 308 #define AIROHA_FOE_QID GENMASK(10, 8) 309 #define AIROHA_FOE_DPI BIT(7) 310 #define AIROHA_FOE_TUNNEL BIT(6) 311 #define AIROHA_FOE_TUNNEL_ID GENMASK(5, 0) 312 313 #define AIROHA_FOE_TUNNEL_MTU GENMASK(31, 16) 314 #define AIROHA_FOE_ACNT_GRP3 GENMASK(15, 9) 315 #define AIROHA_FOE_METER_GRP3 GENMASK(8, 5) 316 #define AIROHA_FOE_METER_GRP2 GENMASK(4, 0) 317 318 struct airoha_foe_bridge { 319 u32 dest_mac_hi; 320 321 u16 src_mac_hi; 322 u16 dest_mac_lo; 323 324 u32 src_mac_lo; 325 326 u32 ib2; 327 328 u32 rsv[5]; 329 330 u32 data; 331 332 struct airoha_foe_mac_info l2; 333 }; 334 335 struct airoha_foe_ipv4_tuple { 336 u32 src_ip; 337 u32 dest_ip; 338 union { 339 struct { 340 u16 dest_port; 341 u16 src_port; 342 }; 343 struct { 344 u8 protocol; 345 u8 _pad[3]; /* fill with 0xa5a5a5 */ 346 }; 347 u32 ports; 348 }; 349 }; 350 351 struct airoha_foe_ipv4 { 352 struct airoha_foe_ipv4_tuple orig_tuple; 353 354 u32 ib2; 355 356 struct airoha_foe_ipv4_tuple new_tuple; 357 358 u32 rsv[2]; 359 360 u32 data; 361 362 struct airoha_foe_mac_info l2; 363 }; 364 365 struct airoha_foe_ipv4_dslite { 366 struct airoha_foe_ipv4_tuple ip4; 367 368 u32 ib2; 369 370 u8 flow_label[3]; 371 u8 priority; 372 373 u32 rsv[4]; 374 375 u32 data; 376 377 struct airoha_foe_mac_info l2; 378 }; 379 380 struct airoha_foe_ipv6 { 381 u32 src_ip[4]; 382 u32 dest_ip[4]; 383 384 union { 385 struct { 386 u16 dest_port; 387 u16 src_port; 388 }; 389 struct { 390 u8 protocol; 391 u8 pad[3]; 392 }; 393 u32 ports; 394 }; 395 396 u32 data; 397 398 u32 ib2; 399 400 struct airoha_foe_mac_info_common l2; 401 402 u32 meter; 403 }; 404 405 struct airoha_foe_entry { 406 union { 407 struct { 408 u32 ib1; 409 union { 410 struct airoha_foe_bridge bridge; 411 struct airoha_foe_ipv4 ipv4; 412 struct airoha_foe_ipv4_dslite dslite; 413 struct airoha_foe_ipv6 ipv6; 414 DECLARE_FLEX_ARRAY(u32, d); 415 }; 416 }; 417 u8 data[PPE_ENTRY_SIZE]; 418 }; 419 }; 420 421 struct airoha_foe_stats { 422 u32 bytes; 423 u32 packets; 424 }; 425 426 struct airoha_foe_stats64 { 427 u64 bytes; 428 u64 packets; 429 }; 430 431 struct airoha_flow_data { 432 struct ethhdr eth; 433 434 union { 435 struct { 436 __be32 src_addr; 437 __be32 dst_addr; 438 } v4; 439 440 struct { 441 struct in6_addr src_addr; 442 struct in6_addr dst_addr; 443 } v6; 444 }; 445 446 __be16 src_port; 447 __be16 dst_port; 448 449 struct { 450 struct { 451 u16 id; 452 __be16 proto; 453 } hdr[2]; 454 u8 num; 455 } vlan; 456 struct { 457 u16 sid; 458 u8 num; 459 } pppoe; 460 }; 461 462 enum airoha_flow_entry_type { 463 FLOW_TYPE_L4, 464 FLOW_TYPE_L2, 465 FLOW_TYPE_L2_SUBFLOW, 466 }; 467 468 struct airoha_flow_table_entry { 469 union { 470 struct hlist_node list; /* PPE L3 flow entry */ 471 struct { 472 struct rhash_head l2_node; /* L2 flow entry */ 473 struct hlist_head l2_flows; /* PPE L2 subflows list */ 474 }; 475 }; 476 477 struct airoha_foe_entry data; 478 struct hlist_node l2_subflow_node; /* PPE L2 subflow entry */ 479 u32 hash; 480 481 struct airoha_foe_stats64 stats; 482 enum airoha_flow_entry_type type; 483 484 struct rhash_head node; 485 unsigned long cookie; 486 }; 487 488 struct airoha_wdma_info { 489 u8 idx; 490 u8 queue; 491 u16 wcid; 492 u8 bss; 493 }; 494 495 /* RX queue to IRQ mapping: BIT(q) in IRQ(n) */ 496 #define RX_IRQ0_BANK_PIN_MASK 0x839f 497 #define RX_IRQ1_BANK_PIN_MASK 0x7fe00000 498 #define RX_IRQ2_BANK_PIN_MASK 0x20 499 #define RX_IRQ3_BANK_PIN_MASK 0x40 500 #define RX_IRQ_BANK_PIN_MASK(_n) \ 501 (((_n) == 3) ? RX_IRQ3_BANK_PIN_MASK : \ 502 ((_n) == 2) ? RX_IRQ2_BANK_PIN_MASK : \ 503 ((_n) == 1) ? RX_IRQ1_BANK_PIN_MASK : \ 504 RX_IRQ0_BANK_PIN_MASK) 505 506 struct airoha_irq_bank { 507 struct airoha_qdma *qdma; 508 509 /* protect concurrent irqmask accesses */ 510 spinlock_t irq_lock; 511 u32 irqmask[QDMA_INT_REG_MAX]; 512 int irq; 513 }; 514 515 struct airoha_qdma { 516 struct airoha_eth *eth; 517 void __iomem *regs; 518 519 atomic_t users; 520 521 struct airoha_irq_bank irq_banks[AIROHA_MAX_NUM_IRQ_BANKS]; 522 523 struct airoha_tx_irq_queue q_tx_irq[AIROHA_NUM_TX_IRQ]; 524 525 struct airoha_queue q_tx[AIROHA_NUM_TX_RING]; 526 struct airoha_queue q_rx[AIROHA_NUM_RX_RING]; 527 }; 528 529 struct airoha_gdm_port { 530 struct airoha_qdma *qdma; 531 struct net_device *dev; 532 int id; 533 534 struct airoha_hw_stats stats; 535 536 DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS); 537 538 /* qos stats counters */ 539 u64 cpu_tx_packets; 540 u64 fwd_tx_packets; 541 542 struct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS]; 543 }; 544 545 #define AIROHA_RXD4_PPE_CPU_REASON GENMASK(20, 16) 546 #define AIROHA_RXD4_FOE_ENTRY GENMASK(15, 0) 547 548 struct airoha_ppe { 549 struct airoha_eth *eth; 550 551 void *foe; 552 dma_addr_t foe_dma; 553 554 struct rhashtable l2_flows; 555 556 struct hlist_head *foe_flow; 557 u16 foe_check_time[PPE_NUM_ENTRIES]; 558 559 struct airoha_foe_stats *foe_stats; 560 dma_addr_t foe_stats_dma; 561 562 struct dentry *debugfs_dir; 563 }; 564 565 struct airoha_eth { 566 struct device *dev; 567 568 unsigned long state; 569 void __iomem *fe_regs; 570 571 struct airoha_npu __rcu *npu; 572 573 struct airoha_ppe *ppe; 574 struct rhashtable flow_table; 575 576 struct reset_control_bulk_data rsts[AIROHA_MAX_NUM_RSTS]; 577 struct reset_control_bulk_data xsi_rsts[AIROHA_MAX_NUM_XSI_RSTS]; 578 579 struct net_device *napi_dev; 580 581 struct airoha_qdma qdma[AIROHA_MAX_NUM_QDMA]; 582 struct airoha_gdm_port *ports[AIROHA_MAX_NUM_GDM_PORTS]; 583 }; 584 585 u32 airoha_rr(void __iomem *base, u32 offset); 586 void airoha_wr(void __iomem *base, u32 offset, u32 val); 587 u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val); 588 589 #define airoha_fe_rr(eth, offset) \ 590 airoha_rr((eth)->fe_regs, (offset)) 591 #define airoha_fe_wr(eth, offset, val) \ 592 airoha_wr((eth)->fe_regs, (offset), (val)) 593 #define airoha_fe_rmw(eth, offset, mask, val) \ 594 airoha_rmw((eth)->fe_regs, (offset), (mask), (val)) 595 #define airoha_fe_set(eth, offset, val) \ 596 airoha_rmw((eth)->fe_regs, (offset), 0, (val)) 597 #define airoha_fe_clear(eth, offset, val) \ 598 airoha_rmw((eth)->fe_regs, (offset), (val), 0) 599 600 #define airoha_qdma_rr(qdma, offset) \ 601 airoha_rr((qdma)->regs, (offset)) 602 #define airoha_qdma_wr(qdma, offset, val) \ 603 airoha_wr((qdma)->regs, (offset), (val)) 604 #define airoha_qdma_rmw(qdma, offset, mask, val) \ 605 airoha_rmw((qdma)->regs, (offset), (mask), (val)) 606 #define airoha_qdma_set(qdma, offset, val) \ 607 airoha_rmw((qdma)->regs, (offset), 0, (val)) 608 #define airoha_qdma_clear(qdma, offset, val) \ 609 airoha_rmw((qdma)->regs, (offset), (val), 0) 610 611 static inline bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port) 612 { 613 /* GDM1 port on EN7581 SoC is connected to the lan dsa switch. 614 * GDM{2,3,4} can be used as wan port connected to an external 615 * phy module. 616 */ 617 return port->id == 1; 618 } 619 620 bool airoha_is_valid_gdm_port(struct airoha_eth *eth, 621 struct airoha_gdm_port *port); 622 623 void airoha_ppe_check_skb(struct airoha_ppe *ppe, struct sk_buff *skb, 624 u16 hash); 625 int airoha_ppe_setup_tc_block_cb(struct net_device *dev, void *type_data); 626 int airoha_ppe_init(struct airoha_eth *eth); 627 void airoha_ppe_deinit(struct airoha_eth *eth); 628 void airoha_ppe_init_upd_mem(struct airoha_gdm_port *port); 629 struct airoha_foe_entry *airoha_ppe_foe_get_entry(struct airoha_ppe *ppe, 630 u32 hash); 631 void airoha_ppe_foe_entry_get_stats(struct airoha_ppe *ppe, u32 hash, 632 struct airoha_foe_stats64 *stats); 633 634 #ifdef CONFIG_DEBUG_FS 635 int airoha_ppe_debugfs_init(struct airoha_ppe *ppe); 636 #else 637 static inline int airoha_ppe_debugfs_init(struct airoha_ppe *ppe) 638 { 639 return 0; 640 } 641 #endif 642 643 #endif /* AIROHA_ETH_H */ 644