1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024 AIROHA Inc 4 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 5 */ 6 #include <linux/of.h> 7 #include <linux/of_net.h> 8 #include <linux/platform_device.h> 9 #include <linux/tcp.h> 10 #include <linux/u64_stats_sync.h> 11 #include <net/dst_metadata.h> 12 #include <net/page_pool/helpers.h> 13 #include <net/pkt_cls.h> 14 #include <uapi/linux/ppp_defs.h> 15 16 #include "airoha_regs.h" 17 #include "airoha_eth.h" 18 19 u32 airoha_rr(void __iomem *base, u32 offset) 20 { 21 return readl(base + offset); 22 } 23 24 void airoha_wr(void __iomem *base, u32 offset, u32 val) 25 { 26 writel(val, base + offset); 27 } 28 29 u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val) 30 { 31 val |= (airoha_rr(base, offset) & ~mask); 32 airoha_wr(base, offset, val); 33 34 return val; 35 } 36 37 static void airoha_qdma_set_irqmask(struct airoha_qdma *qdma, int index, 38 u32 clear, u32 set) 39 { 40 unsigned long flags; 41 42 if (WARN_ON_ONCE(index >= ARRAY_SIZE(qdma->irqmask))) 43 return; 44 45 spin_lock_irqsave(&qdma->irq_lock, flags); 46 47 qdma->irqmask[index] &= ~clear; 48 qdma->irqmask[index] |= set; 49 airoha_qdma_wr(qdma, REG_INT_ENABLE(index), qdma->irqmask[index]); 50 /* Read irq_enable register in order to guarantee the update above 51 * completes in the spinlock critical section. 52 */ 53 airoha_qdma_rr(qdma, REG_INT_ENABLE(index)); 54 55 spin_unlock_irqrestore(&qdma->irq_lock, flags); 56 } 57 58 static void airoha_qdma_irq_enable(struct airoha_qdma *qdma, int index, 59 u32 mask) 60 { 61 airoha_qdma_set_irqmask(qdma, index, 0, mask); 62 } 63 64 static void airoha_qdma_irq_disable(struct airoha_qdma *qdma, int index, 65 u32 mask) 66 { 67 airoha_qdma_set_irqmask(qdma, index, mask, 0); 68 } 69 70 static bool airhoa_is_lan_gdm_port(struct airoha_gdm_port *port) 71 { 72 /* GDM1 port on EN7581 SoC is connected to the lan dsa switch. 73 * GDM{2,3,4} can be used as wan port connected to an external 74 * phy module. 75 */ 76 return port->id == 1; 77 } 78 79 static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr) 80 { 81 struct airoha_eth *eth = port->qdma->eth; 82 u32 val, reg; 83 84 reg = airhoa_is_lan_gdm_port(port) ? REG_FE_LAN_MAC_H 85 : REG_FE_WAN_MAC_H; 86 val = (addr[0] << 16) | (addr[1] << 8) | addr[2]; 87 airoha_fe_wr(eth, reg, val); 88 89 val = (addr[3] << 16) | (addr[4] << 8) | addr[5]; 90 airoha_fe_wr(eth, REG_FE_MAC_LMIN(reg), val); 91 airoha_fe_wr(eth, REG_FE_MAC_LMAX(reg), val); 92 } 93 94 static void airoha_set_gdm_port_fwd_cfg(struct airoha_eth *eth, u32 addr, 95 u32 val) 96 { 97 airoha_fe_rmw(eth, addr, GDM_OCFQ_MASK, 98 FIELD_PREP(GDM_OCFQ_MASK, val)); 99 airoha_fe_rmw(eth, addr, GDM_MCFQ_MASK, 100 FIELD_PREP(GDM_MCFQ_MASK, val)); 101 airoha_fe_rmw(eth, addr, GDM_BCFQ_MASK, 102 FIELD_PREP(GDM_BCFQ_MASK, val)); 103 airoha_fe_rmw(eth, addr, GDM_UCFQ_MASK, 104 FIELD_PREP(GDM_UCFQ_MASK, val)); 105 } 106 107 static int airoha_set_vip_for_gdm_port(struct airoha_gdm_port *port, 108 bool enable) 109 { 110 struct airoha_eth *eth = port->qdma->eth; 111 u32 vip_port; 112 113 switch (port->id) { 114 case 3: 115 /* FIXME: handle XSI_PCIE1_PORT */ 116 vip_port = XSI_PCIE0_VIP_PORT_MASK; 117 break; 118 case 4: 119 /* FIXME: handle XSI_USB_PORT */ 120 vip_port = XSI_ETH_VIP_PORT_MASK; 121 break; 122 default: 123 return 0; 124 } 125 126 if (enable) { 127 airoha_fe_set(eth, REG_FE_VIP_PORT_EN, vip_port); 128 airoha_fe_set(eth, REG_FE_IFC_PORT_EN, vip_port); 129 } else { 130 airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, vip_port); 131 airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, vip_port); 132 } 133 134 return 0; 135 } 136 137 static void airoha_fe_maccr_init(struct airoha_eth *eth) 138 { 139 int p; 140 141 for (p = 1; p <= ARRAY_SIZE(eth->ports); p++) 142 airoha_fe_set(eth, REG_GDM_FWD_CFG(p), 143 GDM_TCP_CKSUM | GDM_UDP_CKSUM | GDM_IP4_CKSUM | 144 GDM_DROP_CRC_ERR); 145 146 airoha_fe_rmw(eth, REG_CDM1_VLAN_CTRL, CDM1_VLAN_MASK, 147 FIELD_PREP(CDM1_VLAN_MASK, 0x8100)); 148 149 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PAD); 150 } 151 152 static void airoha_fe_vip_setup(struct airoha_eth *eth) 153 { 154 airoha_fe_wr(eth, REG_FE_VIP_PATN(3), ETH_P_PPP_DISC); 155 airoha_fe_wr(eth, REG_FE_VIP_EN(3), PATN_FCPU_EN_MASK | PATN_EN_MASK); 156 157 airoha_fe_wr(eth, REG_FE_VIP_PATN(4), PPP_LCP); 158 airoha_fe_wr(eth, REG_FE_VIP_EN(4), 159 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 160 PATN_EN_MASK); 161 162 airoha_fe_wr(eth, REG_FE_VIP_PATN(6), PPP_IPCP); 163 airoha_fe_wr(eth, REG_FE_VIP_EN(6), 164 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 165 PATN_EN_MASK); 166 167 airoha_fe_wr(eth, REG_FE_VIP_PATN(7), PPP_CHAP); 168 airoha_fe_wr(eth, REG_FE_VIP_EN(7), 169 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 170 PATN_EN_MASK); 171 172 /* BOOTP (0x43) */ 173 airoha_fe_wr(eth, REG_FE_VIP_PATN(8), 0x43); 174 airoha_fe_wr(eth, REG_FE_VIP_EN(8), 175 PATN_FCPU_EN_MASK | PATN_SP_EN_MASK | 176 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 177 178 /* BOOTP (0x44) */ 179 airoha_fe_wr(eth, REG_FE_VIP_PATN(9), 0x44); 180 airoha_fe_wr(eth, REG_FE_VIP_EN(9), 181 PATN_FCPU_EN_MASK | PATN_SP_EN_MASK | 182 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 183 184 /* ISAKMP */ 185 airoha_fe_wr(eth, REG_FE_VIP_PATN(10), 0x1f401f4); 186 airoha_fe_wr(eth, REG_FE_VIP_EN(10), 187 PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK | 188 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 189 190 airoha_fe_wr(eth, REG_FE_VIP_PATN(11), PPP_IPV6CP); 191 airoha_fe_wr(eth, REG_FE_VIP_EN(11), 192 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 193 PATN_EN_MASK); 194 195 /* DHCPv6 */ 196 airoha_fe_wr(eth, REG_FE_VIP_PATN(12), 0x2220223); 197 airoha_fe_wr(eth, REG_FE_VIP_EN(12), 198 PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK | 199 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 200 201 airoha_fe_wr(eth, REG_FE_VIP_PATN(19), PPP_PAP); 202 airoha_fe_wr(eth, REG_FE_VIP_EN(19), 203 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 204 PATN_EN_MASK); 205 206 /* ETH->ETH_P_1905 (0x893a) */ 207 airoha_fe_wr(eth, REG_FE_VIP_PATN(20), 0x893a); 208 airoha_fe_wr(eth, REG_FE_VIP_EN(20), 209 PATN_FCPU_EN_MASK | PATN_EN_MASK); 210 211 airoha_fe_wr(eth, REG_FE_VIP_PATN(21), ETH_P_LLDP); 212 airoha_fe_wr(eth, REG_FE_VIP_EN(21), 213 PATN_FCPU_EN_MASK | PATN_EN_MASK); 214 } 215 216 static u32 airoha_fe_get_pse_queue_rsv_pages(struct airoha_eth *eth, 217 u32 port, u32 queue) 218 { 219 u32 val; 220 221 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR, 222 PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK, 223 FIELD_PREP(PSE_CFG_PORT_ID_MASK, port) | 224 FIELD_PREP(PSE_CFG_QUEUE_ID_MASK, queue)); 225 val = airoha_fe_rr(eth, REG_FE_PSE_QUEUE_CFG_VAL); 226 227 return FIELD_GET(PSE_CFG_OQ_RSV_MASK, val); 228 } 229 230 static void airoha_fe_set_pse_queue_rsv_pages(struct airoha_eth *eth, 231 u32 port, u32 queue, u32 val) 232 { 233 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_VAL, PSE_CFG_OQ_RSV_MASK, 234 FIELD_PREP(PSE_CFG_OQ_RSV_MASK, val)); 235 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR, 236 PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK | 237 PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK, 238 FIELD_PREP(PSE_CFG_PORT_ID_MASK, port) | 239 FIELD_PREP(PSE_CFG_QUEUE_ID_MASK, queue) | 240 PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK); 241 } 242 243 static u32 airoha_fe_get_pse_all_rsv(struct airoha_eth *eth) 244 { 245 u32 val = airoha_fe_rr(eth, REG_FE_PSE_BUF_SET); 246 247 return FIELD_GET(PSE_ALLRSV_MASK, val); 248 } 249 250 static int airoha_fe_set_pse_oq_rsv(struct airoha_eth *eth, 251 u32 port, u32 queue, u32 val) 252 { 253 u32 orig_val = airoha_fe_get_pse_queue_rsv_pages(eth, port, queue); 254 u32 tmp, all_rsv, fq_limit; 255 256 airoha_fe_set_pse_queue_rsv_pages(eth, port, queue, val); 257 258 /* modify all rsv */ 259 all_rsv = airoha_fe_get_pse_all_rsv(eth); 260 all_rsv += (val - orig_val); 261 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK, 262 FIELD_PREP(PSE_ALLRSV_MASK, all_rsv)); 263 264 /* modify hthd */ 265 tmp = airoha_fe_rr(eth, PSE_FQ_CFG); 266 fq_limit = FIELD_GET(PSE_FQ_LIMIT_MASK, tmp); 267 tmp = fq_limit - all_rsv - 0x20; 268 airoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD, 269 PSE_SHARE_USED_HTHD_MASK, 270 FIELD_PREP(PSE_SHARE_USED_HTHD_MASK, tmp)); 271 272 tmp = fq_limit - all_rsv - 0x100; 273 airoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD, 274 PSE_SHARE_USED_MTHD_MASK, 275 FIELD_PREP(PSE_SHARE_USED_MTHD_MASK, tmp)); 276 tmp = (3 * tmp) >> 2; 277 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, 278 PSE_SHARE_USED_LTHD_MASK, 279 FIELD_PREP(PSE_SHARE_USED_LTHD_MASK, tmp)); 280 281 return 0; 282 } 283 284 static void airoha_fe_pse_ports_init(struct airoha_eth *eth) 285 { 286 const u32 pse_port_num_queues[] = { 287 [FE_PSE_PORT_CDM1] = 6, 288 [FE_PSE_PORT_GDM1] = 6, 289 [FE_PSE_PORT_GDM2] = 32, 290 [FE_PSE_PORT_GDM3] = 6, 291 [FE_PSE_PORT_PPE1] = 4, 292 [FE_PSE_PORT_CDM2] = 6, 293 [FE_PSE_PORT_CDM3] = 8, 294 [FE_PSE_PORT_CDM4] = 10, 295 [FE_PSE_PORT_PPE2] = 4, 296 [FE_PSE_PORT_GDM4] = 2, 297 [FE_PSE_PORT_CDM5] = 2, 298 }; 299 u32 all_rsv; 300 int q; 301 302 all_rsv = airoha_fe_get_pse_all_rsv(eth); 303 /* hw misses PPE2 oq rsv */ 304 all_rsv += PSE_RSV_PAGES * pse_port_num_queues[FE_PSE_PORT_PPE2]; 305 airoha_fe_set(eth, REG_FE_PSE_BUF_SET, all_rsv); 306 307 /* CMD1 */ 308 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM1]; q++) 309 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM1, q, 310 PSE_QUEUE_RSV_PAGES); 311 /* GMD1 */ 312 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM1]; q++) 313 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM1, q, 314 PSE_QUEUE_RSV_PAGES); 315 /* GMD2 */ 316 for (q = 6; q < pse_port_num_queues[FE_PSE_PORT_GDM2]; q++) 317 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM2, q, 0); 318 /* GMD3 */ 319 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM3]; q++) 320 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM3, q, 321 PSE_QUEUE_RSV_PAGES); 322 /* PPE1 */ 323 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE1]; q++) { 324 if (q < pse_port_num_queues[FE_PSE_PORT_PPE1]) 325 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 326 PSE_QUEUE_RSV_PAGES); 327 else 328 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 0); 329 } 330 /* CDM2 */ 331 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM2]; q++) 332 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM2, q, 333 PSE_QUEUE_RSV_PAGES); 334 /* CDM3 */ 335 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM3] - 1; q++) 336 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM3, q, 0); 337 /* CDM4 */ 338 for (q = 4; q < pse_port_num_queues[FE_PSE_PORT_CDM4]; q++) 339 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM4, q, 340 PSE_QUEUE_RSV_PAGES); 341 /* PPE2 */ 342 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE2]; q++) { 343 if (q < pse_port_num_queues[FE_PSE_PORT_PPE2] / 2) 344 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, q, 345 PSE_QUEUE_RSV_PAGES); 346 else 347 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, q, 0); 348 } 349 /* GMD4 */ 350 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM4]; q++) 351 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM4, q, 352 PSE_QUEUE_RSV_PAGES); 353 /* CDM5 */ 354 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM5]; q++) 355 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM5, q, 356 PSE_QUEUE_RSV_PAGES); 357 } 358 359 static int airoha_fe_mc_vlan_clear(struct airoha_eth *eth) 360 { 361 int i; 362 363 for (i = 0; i < AIROHA_FE_MC_MAX_VLAN_TABLE; i++) { 364 int err, j; 365 u32 val; 366 367 airoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0); 368 369 val = FIELD_PREP(MC_VLAN_CFG_TABLE_ID_MASK, i) | 370 MC_VLAN_CFG_TABLE_SEL_MASK | MC_VLAN_CFG_RW_MASK; 371 airoha_fe_wr(eth, REG_MC_VLAN_CFG, val); 372 err = read_poll_timeout(airoha_fe_rr, val, 373 val & MC_VLAN_CFG_CMD_DONE_MASK, 374 USEC_PER_MSEC, 5 * USEC_PER_MSEC, 375 false, eth, REG_MC_VLAN_CFG); 376 if (err) 377 return err; 378 379 for (j = 0; j < AIROHA_FE_MC_MAX_VLAN_PORT; j++) { 380 airoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0); 381 382 val = FIELD_PREP(MC_VLAN_CFG_TABLE_ID_MASK, i) | 383 FIELD_PREP(MC_VLAN_CFG_PORT_ID_MASK, j) | 384 MC_VLAN_CFG_RW_MASK; 385 airoha_fe_wr(eth, REG_MC_VLAN_CFG, val); 386 err = read_poll_timeout(airoha_fe_rr, val, 387 val & MC_VLAN_CFG_CMD_DONE_MASK, 388 USEC_PER_MSEC, 389 5 * USEC_PER_MSEC, false, eth, 390 REG_MC_VLAN_CFG); 391 if (err) 392 return err; 393 } 394 } 395 396 return 0; 397 } 398 399 static void airoha_fe_crsn_qsel_init(struct airoha_eth *eth) 400 { 401 /* CDM1_CRSN_QSEL */ 402 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_22 >> 2), 403 CDM1_CRSN_QSEL_REASON_MASK(CRSN_22), 404 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_22), 405 CDM_CRSN_QSEL_Q1)); 406 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_08 >> 2), 407 CDM1_CRSN_QSEL_REASON_MASK(CRSN_08), 408 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_08), 409 CDM_CRSN_QSEL_Q1)); 410 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_21 >> 2), 411 CDM1_CRSN_QSEL_REASON_MASK(CRSN_21), 412 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_21), 413 CDM_CRSN_QSEL_Q1)); 414 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_24 >> 2), 415 CDM1_CRSN_QSEL_REASON_MASK(CRSN_24), 416 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_24), 417 CDM_CRSN_QSEL_Q6)); 418 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_25 >> 2), 419 CDM1_CRSN_QSEL_REASON_MASK(CRSN_25), 420 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_25), 421 CDM_CRSN_QSEL_Q1)); 422 /* CDM2_CRSN_QSEL */ 423 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_08 >> 2), 424 CDM2_CRSN_QSEL_REASON_MASK(CRSN_08), 425 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_08), 426 CDM_CRSN_QSEL_Q1)); 427 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_21 >> 2), 428 CDM2_CRSN_QSEL_REASON_MASK(CRSN_21), 429 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_21), 430 CDM_CRSN_QSEL_Q1)); 431 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_22 >> 2), 432 CDM2_CRSN_QSEL_REASON_MASK(CRSN_22), 433 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_22), 434 CDM_CRSN_QSEL_Q1)); 435 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_24 >> 2), 436 CDM2_CRSN_QSEL_REASON_MASK(CRSN_24), 437 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_24), 438 CDM_CRSN_QSEL_Q6)); 439 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_25 >> 2), 440 CDM2_CRSN_QSEL_REASON_MASK(CRSN_25), 441 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_25), 442 CDM_CRSN_QSEL_Q1)); 443 } 444 445 static int airoha_fe_init(struct airoha_eth *eth) 446 { 447 airoha_fe_maccr_init(eth); 448 449 /* PSE IQ reserve */ 450 airoha_fe_rmw(eth, REG_PSE_IQ_REV1, PSE_IQ_RES1_P2_MASK, 451 FIELD_PREP(PSE_IQ_RES1_P2_MASK, 0x10)); 452 airoha_fe_rmw(eth, REG_PSE_IQ_REV2, 453 PSE_IQ_RES2_P5_MASK | PSE_IQ_RES2_P4_MASK, 454 FIELD_PREP(PSE_IQ_RES2_P5_MASK, 0x40) | 455 FIELD_PREP(PSE_IQ_RES2_P4_MASK, 0x34)); 456 457 /* enable FE copy engine for MC/KA/DPI */ 458 airoha_fe_wr(eth, REG_FE_PCE_CFG, 459 PCE_DPI_EN_MASK | PCE_KA_EN_MASK | PCE_MC_EN_MASK); 460 /* set vip queue selection to ring 1 */ 461 airoha_fe_rmw(eth, REG_CDM1_FWD_CFG, CDM1_VIP_QSEL_MASK, 462 FIELD_PREP(CDM1_VIP_QSEL_MASK, 0x4)); 463 airoha_fe_rmw(eth, REG_CDM2_FWD_CFG, CDM2_VIP_QSEL_MASK, 464 FIELD_PREP(CDM2_VIP_QSEL_MASK, 0x4)); 465 /* set GDM4 source interface offset to 8 */ 466 airoha_fe_rmw(eth, REG_GDM4_SRC_PORT_SET, 467 GDM4_SPORT_OFF2_MASK | 468 GDM4_SPORT_OFF1_MASK | 469 GDM4_SPORT_OFF0_MASK, 470 FIELD_PREP(GDM4_SPORT_OFF2_MASK, 8) | 471 FIELD_PREP(GDM4_SPORT_OFF1_MASK, 8) | 472 FIELD_PREP(GDM4_SPORT_OFF0_MASK, 8)); 473 474 /* set PSE Page as 128B */ 475 airoha_fe_rmw(eth, REG_FE_DMA_GLO_CFG, 476 FE_DMA_GLO_L2_SPACE_MASK | FE_DMA_GLO_PG_SZ_MASK, 477 FIELD_PREP(FE_DMA_GLO_L2_SPACE_MASK, 2) | 478 FE_DMA_GLO_PG_SZ_MASK); 479 airoha_fe_wr(eth, REG_FE_RST_GLO_CFG, 480 FE_RST_CORE_MASK | FE_RST_GDM3_MBI_ARB_MASK | 481 FE_RST_GDM4_MBI_ARB_MASK); 482 usleep_range(1000, 2000); 483 484 /* connect RxRing1 and RxRing15 to PSE Port0 OQ-1 485 * connect other rings to PSE Port0 OQ-0 486 */ 487 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP0, BIT(4)); 488 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP1, BIT(28)); 489 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP2, BIT(4)); 490 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP3, BIT(28)); 491 492 airoha_fe_vip_setup(eth); 493 airoha_fe_pse_ports_init(eth); 494 495 airoha_fe_set(eth, REG_GDM_MISC_CFG, 496 GDM2_RDM_ACK_WAIT_PREF_MASK | 497 GDM2_CHN_VLD_MODE_MASK); 498 airoha_fe_rmw(eth, REG_CDM2_FWD_CFG, CDM2_OAM_QSEL_MASK, 499 FIELD_PREP(CDM2_OAM_QSEL_MASK, 15)); 500 501 /* init fragment and assemble Force Port */ 502 /* NPU Core-3, NPU Bridge Channel-3 */ 503 airoha_fe_rmw(eth, REG_IP_FRAG_FP, 504 IP_FRAGMENT_PORT_MASK | IP_FRAGMENT_NBQ_MASK, 505 FIELD_PREP(IP_FRAGMENT_PORT_MASK, 6) | 506 FIELD_PREP(IP_FRAGMENT_NBQ_MASK, 3)); 507 /* QDMA LAN, RX Ring-22 */ 508 airoha_fe_rmw(eth, REG_IP_FRAG_FP, 509 IP_ASSEMBLE_PORT_MASK | IP_ASSEMBLE_NBQ_MASK, 510 FIELD_PREP(IP_ASSEMBLE_PORT_MASK, 0) | 511 FIELD_PREP(IP_ASSEMBLE_NBQ_MASK, 22)); 512 513 airoha_fe_set(eth, REG_GDM3_FWD_CFG, GDM3_PAD_EN_MASK); 514 airoha_fe_set(eth, REG_GDM4_FWD_CFG, GDM4_PAD_EN_MASK); 515 516 airoha_fe_crsn_qsel_init(eth); 517 518 airoha_fe_clear(eth, REG_FE_CPORT_CFG, FE_CPORT_QUEUE_XFC_MASK); 519 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PORT_XFC_MASK); 520 521 /* default aging mode for mbi unlock issue */ 522 airoha_fe_rmw(eth, REG_GDM2_CHN_RLS, 523 MBI_RX_AGE_SEL_MASK | MBI_TX_AGE_SEL_MASK, 524 FIELD_PREP(MBI_RX_AGE_SEL_MASK, 3) | 525 FIELD_PREP(MBI_TX_AGE_SEL_MASK, 3)); 526 527 /* disable IFC by default */ 528 airoha_fe_clear(eth, REG_FE_CSR_IFC_CFG, FE_IFC_EN_MASK); 529 530 /* enable 1:N vlan action, init vlan table */ 531 airoha_fe_set(eth, REG_MC_VLAN_EN, MC_VLAN_EN_MASK); 532 533 return airoha_fe_mc_vlan_clear(eth); 534 } 535 536 static int airoha_qdma_fill_rx_queue(struct airoha_queue *q) 537 { 538 enum dma_data_direction dir = page_pool_get_dma_dir(q->page_pool); 539 struct airoha_qdma *qdma = q->qdma; 540 struct airoha_eth *eth = qdma->eth; 541 int qid = q - &qdma->q_rx[0]; 542 int nframes = 0; 543 544 while (q->queued < q->ndesc - 1) { 545 struct airoha_queue_entry *e = &q->entry[q->head]; 546 struct airoha_qdma_desc *desc = &q->desc[q->head]; 547 struct page *page; 548 int offset; 549 u32 val; 550 551 page = page_pool_dev_alloc_frag(q->page_pool, &offset, 552 q->buf_size); 553 if (!page) 554 break; 555 556 q->head = (q->head + 1) % q->ndesc; 557 q->queued++; 558 nframes++; 559 560 e->buf = page_address(page) + offset; 561 e->dma_addr = page_pool_get_dma_addr(page) + offset; 562 e->dma_len = SKB_WITH_OVERHEAD(q->buf_size); 563 564 dma_sync_single_for_device(eth->dev, e->dma_addr, e->dma_len, 565 dir); 566 567 val = FIELD_PREP(QDMA_DESC_LEN_MASK, e->dma_len); 568 WRITE_ONCE(desc->ctrl, cpu_to_le32(val)); 569 WRITE_ONCE(desc->addr, cpu_to_le32(e->dma_addr)); 570 val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, q->head); 571 WRITE_ONCE(desc->data, cpu_to_le32(val)); 572 WRITE_ONCE(desc->msg0, 0); 573 WRITE_ONCE(desc->msg1, 0); 574 WRITE_ONCE(desc->msg2, 0); 575 WRITE_ONCE(desc->msg3, 0); 576 577 airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), 578 RX_RING_CPU_IDX_MASK, 579 FIELD_PREP(RX_RING_CPU_IDX_MASK, q->head)); 580 } 581 582 return nframes; 583 } 584 585 static int airoha_qdma_get_gdm_port(struct airoha_eth *eth, 586 struct airoha_qdma_desc *desc) 587 { 588 u32 port, sport, msg1 = le32_to_cpu(desc->msg1); 589 590 sport = FIELD_GET(QDMA_ETH_RXMSG_SPORT_MASK, msg1); 591 switch (sport) { 592 case 0x10 ... 0x14: 593 port = 0; 594 break; 595 case 0x2 ... 0x4: 596 port = sport - 1; 597 break; 598 default: 599 return -EINVAL; 600 } 601 602 return port >= ARRAY_SIZE(eth->ports) ? -EINVAL : port; 603 } 604 605 static int airoha_qdma_rx_process(struct airoha_queue *q, int budget) 606 { 607 enum dma_data_direction dir = page_pool_get_dma_dir(q->page_pool); 608 struct airoha_qdma *qdma = q->qdma; 609 struct airoha_eth *eth = qdma->eth; 610 int qid = q - &qdma->q_rx[0]; 611 int done = 0; 612 613 while (done < budget) { 614 struct airoha_queue_entry *e = &q->entry[q->tail]; 615 struct airoha_qdma_desc *desc = &q->desc[q->tail]; 616 u32 hash, reason, msg1 = le32_to_cpu(desc->msg1); 617 dma_addr_t dma_addr = le32_to_cpu(desc->addr); 618 struct page *page = virt_to_head_page(e->buf); 619 u32 desc_ctrl = le32_to_cpu(desc->ctrl); 620 struct airoha_gdm_port *port; 621 int data_len, len, p; 622 623 if (!(desc_ctrl & QDMA_DESC_DONE_MASK)) 624 break; 625 626 if (!dma_addr) 627 break; 628 629 len = FIELD_GET(QDMA_DESC_LEN_MASK, desc_ctrl); 630 if (!len) 631 break; 632 633 q->tail = (q->tail + 1) % q->ndesc; 634 q->queued--; 635 636 dma_sync_single_for_cpu(eth->dev, dma_addr, 637 SKB_WITH_OVERHEAD(q->buf_size), dir); 638 639 data_len = q->skb ? q->buf_size 640 : SKB_WITH_OVERHEAD(q->buf_size); 641 if (data_len < len) 642 goto free_frag; 643 644 p = airoha_qdma_get_gdm_port(eth, desc); 645 if (p < 0 || !eth->ports[p]) 646 goto free_frag; 647 648 port = eth->ports[p]; 649 if (!q->skb) { /* first buffer */ 650 q->skb = napi_build_skb(e->buf, q->buf_size); 651 if (!q->skb) 652 goto free_frag; 653 654 __skb_put(q->skb, len); 655 skb_mark_for_recycle(q->skb); 656 q->skb->dev = port->dev; 657 q->skb->protocol = eth_type_trans(q->skb, port->dev); 658 q->skb->ip_summed = CHECKSUM_UNNECESSARY; 659 skb_record_rx_queue(q->skb, qid); 660 } else { /* scattered frame */ 661 struct skb_shared_info *shinfo = skb_shinfo(q->skb); 662 int nr_frags = shinfo->nr_frags; 663 664 if (nr_frags >= ARRAY_SIZE(shinfo->frags)) 665 goto free_frag; 666 667 skb_add_rx_frag(q->skb, nr_frags, page, 668 e->buf - page_address(page), len, 669 q->buf_size); 670 } 671 672 if (FIELD_GET(QDMA_DESC_MORE_MASK, desc_ctrl)) 673 continue; 674 675 if (netdev_uses_dsa(port->dev)) { 676 /* PPE module requires untagged packets to work 677 * properly and it provides DSA port index via the 678 * DMA descriptor. Report DSA tag to the DSA stack 679 * via skb dst info. 680 */ 681 u32 sptag = FIELD_GET(QDMA_ETH_RXMSG_SPTAG, 682 le32_to_cpu(desc->msg0)); 683 684 if (sptag < ARRAY_SIZE(port->dsa_meta) && 685 port->dsa_meta[sptag]) 686 skb_dst_set_noref(q->skb, 687 &port->dsa_meta[sptag]->dst); 688 } 689 690 hash = FIELD_GET(AIROHA_RXD4_FOE_ENTRY, msg1); 691 if (hash != AIROHA_RXD4_FOE_ENTRY) 692 skb_set_hash(q->skb, jhash_1word(hash, 0), 693 PKT_HASH_TYPE_L4); 694 695 reason = FIELD_GET(AIROHA_RXD4_PPE_CPU_REASON, msg1); 696 if (reason == PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 697 airoha_ppe_check_skb(eth->ppe, hash); 698 699 done++; 700 napi_gro_receive(&q->napi, q->skb); 701 q->skb = NULL; 702 continue; 703 free_frag: 704 page_pool_put_full_page(q->page_pool, page, true); 705 dev_kfree_skb(q->skb); 706 q->skb = NULL; 707 } 708 airoha_qdma_fill_rx_queue(q); 709 710 return done; 711 } 712 713 static int airoha_qdma_rx_napi_poll(struct napi_struct *napi, int budget) 714 { 715 struct airoha_queue *q = container_of(napi, struct airoha_queue, napi); 716 int cur, done = 0; 717 718 do { 719 cur = airoha_qdma_rx_process(q, budget - done); 720 done += cur; 721 } while (cur && done < budget); 722 723 if (done < budget && napi_complete(napi)) 724 airoha_qdma_irq_enable(q->qdma, QDMA_INT_REG_IDX1, 725 RX_DONE_INT_MASK); 726 727 return done; 728 } 729 730 static int airoha_qdma_init_rx_queue(struct airoha_queue *q, 731 struct airoha_qdma *qdma, int ndesc) 732 { 733 const struct page_pool_params pp_params = { 734 .order = 0, 735 .pool_size = 256, 736 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 737 .dma_dir = DMA_FROM_DEVICE, 738 .max_len = PAGE_SIZE, 739 .nid = NUMA_NO_NODE, 740 .dev = qdma->eth->dev, 741 .napi = &q->napi, 742 }; 743 struct airoha_eth *eth = qdma->eth; 744 int qid = q - &qdma->q_rx[0], thr; 745 dma_addr_t dma_addr; 746 747 q->buf_size = PAGE_SIZE / 2; 748 q->ndesc = ndesc; 749 q->qdma = qdma; 750 751 q->entry = devm_kzalloc(eth->dev, q->ndesc * sizeof(*q->entry), 752 GFP_KERNEL); 753 if (!q->entry) 754 return -ENOMEM; 755 756 q->page_pool = page_pool_create(&pp_params); 757 if (IS_ERR(q->page_pool)) { 758 int err = PTR_ERR(q->page_pool); 759 760 q->page_pool = NULL; 761 return err; 762 } 763 764 q->desc = dmam_alloc_coherent(eth->dev, q->ndesc * sizeof(*q->desc), 765 &dma_addr, GFP_KERNEL); 766 if (!q->desc) 767 return -ENOMEM; 768 769 netif_napi_add(eth->napi_dev, &q->napi, airoha_qdma_rx_napi_poll); 770 771 airoha_qdma_wr(qdma, REG_RX_RING_BASE(qid), dma_addr); 772 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), 773 RX_RING_SIZE_MASK, 774 FIELD_PREP(RX_RING_SIZE_MASK, ndesc)); 775 776 thr = clamp(ndesc >> 3, 1, 32); 777 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), RX_RING_THR_MASK, 778 FIELD_PREP(RX_RING_THR_MASK, thr)); 779 airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK, 780 FIELD_PREP(RX_RING_DMA_IDX_MASK, q->head)); 781 airoha_qdma_set(qdma, REG_RX_SCATTER_CFG(qid), RX_RING_SG_EN_MASK); 782 783 airoha_qdma_fill_rx_queue(q); 784 785 return 0; 786 } 787 788 static void airoha_qdma_cleanup_rx_queue(struct airoha_queue *q) 789 { 790 struct airoha_eth *eth = q->qdma->eth; 791 792 while (q->queued) { 793 struct airoha_queue_entry *e = &q->entry[q->tail]; 794 struct page *page = virt_to_head_page(e->buf); 795 796 dma_sync_single_for_cpu(eth->dev, e->dma_addr, e->dma_len, 797 page_pool_get_dma_dir(q->page_pool)); 798 page_pool_put_full_page(q->page_pool, page, false); 799 q->tail = (q->tail + 1) % q->ndesc; 800 q->queued--; 801 } 802 } 803 804 static int airoha_qdma_init_rx(struct airoha_qdma *qdma) 805 { 806 int i; 807 808 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 809 int err; 810 811 if (!(RX_DONE_INT_MASK & BIT(i))) { 812 /* rx-queue not binded to irq */ 813 continue; 814 } 815 816 err = airoha_qdma_init_rx_queue(&qdma->q_rx[i], qdma, 817 RX_DSCP_NUM(i)); 818 if (err) 819 return err; 820 } 821 822 return 0; 823 } 824 825 static int airoha_qdma_tx_napi_poll(struct napi_struct *napi, int budget) 826 { 827 struct airoha_tx_irq_queue *irq_q; 828 int id, done = 0, irq_queued; 829 struct airoha_qdma *qdma; 830 struct airoha_eth *eth; 831 u32 status, head; 832 833 irq_q = container_of(napi, struct airoha_tx_irq_queue, napi); 834 qdma = irq_q->qdma; 835 id = irq_q - &qdma->q_tx_irq[0]; 836 eth = qdma->eth; 837 838 status = airoha_qdma_rr(qdma, REG_IRQ_STATUS(id)); 839 head = FIELD_GET(IRQ_HEAD_IDX_MASK, status); 840 head = head % irq_q->size; 841 irq_queued = FIELD_GET(IRQ_ENTRY_LEN_MASK, status); 842 843 while (irq_queued > 0 && done < budget) { 844 u32 qid, val = irq_q->q[head]; 845 struct airoha_qdma_desc *desc; 846 struct airoha_queue_entry *e; 847 struct airoha_queue *q; 848 u32 index, desc_ctrl; 849 struct sk_buff *skb; 850 851 if (val == 0xff) 852 break; 853 854 irq_q->q[head] = 0xff; /* mark as done */ 855 head = (head + 1) % irq_q->size; 856 irq_queued--; 857 done++; 858 859 qid = FIELD_GET(IRQ_RING_IDX_MASK, val); 860 if (qid >= ARRAY_SIZE(qdma->q_tx)) 861 continue; 862 863 q = &qdma->q_tx[qid]; 864 if (!q->ndesc) 865 continue; 866 867 index = FIELD_GET(IRQ_DESC_IDX_MASK, val); 868 if (index >= q->ndesc) 869 continue; 870 871 spin_lock_bh(&q->lock); 872 873 if (!q->queued) 874 goto unlock; 875 876 desc = &q->desc[index]; 877 desc_ctrl = le32_to_cpu(desc->ctrl); 878 879 if (!(desc_ctrl & QDMA_DESC_DONE_MASK) && 880 !(desc_ctrl & QDMA_DESC_DROP_MASK)) 881 goto unlock; 882 883 e = &q->entry[index]; 884 skb = e->skb; 885 886 dma_unmap_single(eth->dev, e->dma_addr, e->dma_len, 887 DMA_TO_DEVICE); 888 memset(e, 0, sizeof(*e)); 889 WRITE_ONCE(desc->msg0, 0); 890 WRITE_ONCE(desc->msg1, 0); 891 q->queued--; 892 893 /* completion ring can report out-of-order indexes if hw QoS 894 * is enabled and packets with different priority are queued 895 * to same DMA ring. Take into account possible out-of-order 896 * reports incrementing DMA ring tail pointer 897 */ 898 while (q->tail != q->head && !q->entry[q->tail].dma_addr) 899 q->tail = (q->tail + 1) % q->ndesc; 900 901 if (skb) { 902 u16 queue = skb_get_queue_mapping(skb); 903 struct netdev_queue *txq; 904 905 txq = netdev_get_tx_queue(skb->dev, queue); 906 netdev_tx_completed_queue(txq, 1, skb->len); 907 if (netif_tx_queue_stopped(txq) && 908 q->ndesc - q->queued >= q->free_thr) 909 netif_tx_wake_queue(txq); 910 911 dev_kfree_skb_any(skb); 912 } 913 unlock: 914 spin_unlock_bh(&q->lock); 915 } 916 917 if (done) { 918 int i, len = done >> 7; 919 920 for (i = 0; i < len; i++) 921 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id), 922 IRQ_CLEAR_LEN_MASK, 0x80); 923 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id), 924 IRQ_CLEAR_LEN_MASK, (done & 0x7f)); 925 } 926 927 if (done < budget && napi_complete(napi)) 928 airoha_qdma_irq_enable(qdma, QDMA_INT_REG_IDX0, 929 TX_DONE_INT_MASK(id)); 930 931 return done; 932 } 933 934 static int airoha_qdma_init_tx_queue(struct airoha_queue *q, 935 struct airoha_qdma *qdma, int size) 936 { 937 struct airoha_eth *eth = qdma->eth; 938 int i, qid = q - &qdma->q_tx[0]; 939 dma_addr_t dma_addr; 940 941 spin_lock_init(&q->lock); 942 q->ndesc = size; 943 q->qdma = qdma; 944 q->free_thr = 1 + MAX_SKB_FRAGS; 945 946 q->entry = devm_kzalloc(eth->dev, q->ndesc * sizeof(*q->entry), 947 GFP_KERNEL); 948 if (!q->entry) 949 return -ENOMEM; 950 951 q->desc = dmam_alloc_coherent(eth->dev, q->ndesc * sizeof(*q->desc), 952 &dma_addr, GFP_KERNEL); 953 if (!q->desc) 954 return -ENOMEM; 955 956 for (i = 0; i < q->ndesc; i++) { 957 u32 val; 958 959 val = FIELD_PREP(QDMA_DESC_DONE_MASK, 1); 960 WRITE_ONCE(q->desc[i].ctrl, cpu_to_le32(val)); 961 } 962 963 /* xmit ring drop default setting */ 964 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(qid), 965 TX_RING_IRQ_BLOCKING_TX_DROP_EN_MASK); 966 967 airoha_qdma_wr(qdma, REG_TX_RING_BASE(qid), dma_addr); 968 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK, 969 FIELD_PREP(TX_RING_CPU_IDX_MASK, q->head)); 970 airoha_qdma_rmw(qdma, REG_TX_DMA_IDX(qid), TX_RING_DMA_IDX_MASK, 971 FIELD_PREP(TX_RING_DMA_IDX_MASK, q->head)); 972 973 return 0; 974 } 975 976 static int airoha_qdma_tx_irq_init(struct airoha_tx_irq_queue *irq_q, 977 struct airoha_qdma *qdma, int size) 978 { 979 int id = irq_q - &qdma->q_tx_irq[0]; 980 struct airoha_eth *eth = qdma->eth; 981 dma_addr_t dma_addr; 982 983 netif_napi_add_tx(eth->napi_dev, &irq_q->napi, 984 airoha_qdma_tx_napi_poll); 985 irq_q->q = dmam_alloc_coherent(eth->dev, size * sizeof(u32), 986 &dma_addr, GFP_KERNEL); 987 if (!irq_q->q) 988 return -ENOMEM; 989 990 memset(irq_q->q, 0xff, size * sizeof(u32)); 991 irq_q->size = size; 992 irq_q->qdma = qdma; 993 994 airoha_qdma_wr(qdma, REG_TX_IRQ_BASE(id), dma_addr); 995 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_DEPTH_MASK, 996 FIELD_PREP(TX_IRQ_DEPTH_MASK, size)); 997 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_THR_MASK, 998 FIELD_PREP(TX_IRQ_THR_MASK, 1)); 999 1000 return 0; 1001 } 1002 1003 static int airoha_qdma_init_tx(struct airoha_qdma *qdma) 1004 { 1005 int i, err; 1006 1007 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) { 1008 err = airoha_qdma_tx_irq_init(&qdma->q_tx_irq[i], qdma, 1009 IRQ_QUEUE_LEN(i)); 1010 if (err) 1011 return err; 1012 } 1013 1014 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1015 err = airoha_qdma_init_tx_queue(&qdma->q_tx[i], qdma, 1016 TX_DSCP_NUM); 1017 if (err) 1018 return err; 1019 } 1020 1021 return 0; 1022 } 1023 1024 static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q) 1025 { 1026 struct airoha_eth *eth = q->qdma->eth; 1027 1028 spin_lock_bh(&q->lock); 1029 while (q->queued) { 1030 struct airoha_queue_entry *e = &q->entry[q->tail]; 1031 1032 dma_unmap_single(eth->dev, e->dma_addr, e->dma_len, 1033 DMA_TO_DEVICE); 1034 dev_kfree_skb_any(e->skb); 1035 e->skb = NULL; 1036 1037 q->tail = (q->tail + 1) % q->ndesc; 1038 q->queued--; 1039 } 1040 spin_unlock_bh(&q->lock); 1041 } 1042 1043 static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma) 1044 { 1045 struct airoha_eth *eth = qdma->eth; 1046 dma_addr_t dma_addr; 1047 u32 status; 1048 int size; 1049 1050 size = HW_DSCP_NUM * sizeof(struct airoha_qdma_fwd_desc); 1051 qdma->hfwd.desc = dmam_alloc_coherent(eth->dev, size, &dma_addr, 1052 GFP_KERNEL); 1053 if (!qdma->hfwd.desc) 1054 return -ENOMEM; 1055 1056 airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr); 1057 1058 size = AIROHA_MAX_PACKET_SIZE * HW_DSCP_NUM; 1059 qdma->hfwd.q = dmam_alloc_coherent(eth->dev, size, &dma_addr, 1060 GFP_KERNEL); 1061 if (!qdma->hfwd.q) 1062 return -ENOMEM; 1063 1064 airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr); 1065 1066 airoha_qdma_rmw(qdma, REG_HW_FWD_DSCP_CFG, 1067 HW_FWD_DSCP_PAYLOAD_SIZE_MASK, 1068 FIELD_PREP(HW_FWD_DSCP_PAYLOAD_SIZE_MASK, 0)); 1069 airoha_qdma_rmw(qdma, REG_FWD_DSCP_LOW_THR, FWD_DSCP_LOW_THR_MASK, 1070 FIELD_PREP(FWD_DSCP_LOW_THR_MASK, 128)); 1071 airoha_qdma_rmw(qdma, REG_LMGR_INIT_CFG, 1072 LMGR_INIT_START | LMGR_SRAM_MODE_MASK | 1073 HW_FWD_DESC_NUM_MASK, 1074 FIELD_PREP(HW_FWD_DESC_NUM_MASK, HW_DSCP_NUM) | 1075 LMGR_INIT_START); 1076 1077 return read_poll_timeout(airoha_qdma_rr, status, 1078 !(status & LMGR_INIT_START), USEC_PER_MSEC, 1079 30 * USEC_PER_MSEC, true, qdma, 1080 REG_LMGR_INIT_CFG); 1081 } 1082 1083 static void airoha_qdma_init_qos(struct airoha_qdma *qdma) 1084 { 1085 airoha_qdma_clear(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_SCALE_MASK); 1086 airoha_qdma_set(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_BASE_MASK); 1087 1088 airoha_qdma_clear(qdma, REG_PSE_BUF_USAGE_CFG, 1089 PSE_BUF_ESTIMATE_EN_MASK); 1090 1091 airoha_qdma_set(qdma, REG_EGRESS_RATE_METER_CFG, 1092 EGRESS_RATE_METER_EN_MASK | 1093 EGRESS_RATE_METER_EQ_RATE_EN_MASK); 1094 /* 2047us x 31 = 63.457ms */ 1095 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG, 1096 EGRESS_RATE_METER_WINDOW_SZ_MASK, 1097 FIELD_PREP(EGRESS_RATE_METER_WINDOW_SZ_MASK, 0x1f)); 1098 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG, 1099 EGRESS_RATE_METER_TIMESLICE_MASK, 1100 FIELD_PREP(EGRESS_RATE_METER_TIMESLICE_MASK, 0x7ff)); 1101 1102 /* ratelimit init */ 1103 airoha_qdma_set(qdma, REG_GLB_TRTCM_CFG, GLB_TRTCM_EN_MASK); 1104 /* fast-tick 25us */ 1105 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_FAST_TICK_MASK, 1106 FIELD_PREP(GLB_FAST_TICK_MASK, 25)); 1107 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_SLOW_TICK_RATIO_MASK, 1108 FIELD_PREP(GLB_SLOW_TICK_RATIO_MASK, 40)); 1109 1110 airoha_qdma_set(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_TRTCM_EN_MASK); 1111 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_FAST_TICK_MASK, 1112 FIELD_PREP(EGRESS_FAST_TICK_MASK, 25)); 1113 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG, 1114 EGRESS_SLOW_TICK_RATIO_MASK, 1115 FIELD_PREP(EGRESS_SLOW_TICK_RATIO_MASK, 40)); 1116 1117 airoha_qdma_set(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_TRTCM_EN_MASK); 1118 airoha_qdma_clear(qdma, REG_INGRESS_TRTCM_CFG, 1119 INGRESS_TRTCM_MODE_MASK); 1120 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_FAST_TICK_MASK, 1121 FIELD_PREP(INGRESS_FAST_TICK_MASK, 125)); 1122 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG, 1123 INGRESS_SLOW_TICK_RATIO_MASK, 1124 FIELD_PREP(INGRESS_SLOW_TICK_RATIO_MASK, 8)); 1125 1126 airoha_qdma_set(qdma, REG_SLA_TRTCM_CFG, SLA_TRTCM_EN_MASK); 1127 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_FAST_TICK_MASK, 1128 FIELD_PREP(SLA_FAST_TICK_MASK, 25)); 1129 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_SLOW_TICK_RATIO_MASK, 1130 FIELD_PREP(SLA_SLOW_TICK_RATIO_MASK, 40)); 1131 } 1132 1133 static void airoha_qdma_init_qos_stats(struct airoha_qdma *qdma) 1134 { 1135 int i; 1136 1137 for (i = 0; i < AIROHA_NUM_QOS_CHANNELS; i++) { 1138 /* Tx-cpu transferred count */ 1139 airoha_qdma_wr(qdma, REG_CNTR_VAL(i << 1), 0); 1140 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1), 1141 CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK | 1142 CNTR_ALL_DSCP_RING_EN_MASK | 1143 FIELD_PREP(CNTR_CHAN_MASK, i)); 1144 /* Tx-fwd transferred count */ 1145 airoha_qdma_wr(qdma, REG_CNTR_VAL((i << 1) + 1), 0); 1146 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1), 1147 CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK | 1148 CNTR_ALL_DSCP_RING_EN_MASK | 1149 FIELD_PREP(CNTR_SRC_MASK, 1) | 1150 FIELD_PREP(CNTR_CHAN_MASK, i)); 1151 } 1152 } 1153 1154 static int airoha_qdma_hw_init(struct airoha_qdma *qdma) 1155 { 1156 int i; 1157 1158 /* clear pending irqs */ 1159 for (i = 0; i < ARRAY_SIZE(qdma->irqmask); i++) 1160 airoha_qdma_wr(qdma, REG_INT_STATUS(i), 0xffffffff); 1161 1162 /* setup irqs */ 1163 airoha_qdma_irq_enable(qdma, QDMA_INT_REG_IDX0, INT_IDX0_MASK); 1164 airoha_qdma_irq_enable(qdma, QDMA_INT_REG_IDX1, INT_IDX1_MASK); 1165 airoha_qdma_irq_enable(qdma, QDMA_INT_REG_IDX4, INT_IDX4_MASK); 1166 1167 /* setup irq binding */ 1168 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1169 if (!qdma->q_tx[i].ndesc) 1170 continue; 1171 1172 if (TX_RING_IRQ_BLOCKING_MAP_MASK & BIT(i)) 1173 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(i), 1174 TX_RING_IRQ_BLOCKING_CFG_MASK); 1175 else 1176 airoha_qdma_clear(qdma, REG_TX_RING_BLOCKING(i), 1177 TX_RING_IRQ_BLOCKING_CFG_MASK); 1178 } 1179 1180 airoha_qdma_wr(qdma, REG_QDMA_GLOBAL_CFG, 1181 FIELD_PREP(GLOBAL_CFG_DMA_PREFERENCE_MASK, 3) | 1182 GLOBAL_CFG_CPU_TXR_RR_MASK | 1183 GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK | 1184 GLOBAL_CFG_MULTICAST_MODIFY_FP_MASK | 1185 GLOBAL_CFG_MULTICAST_EN_MASK | 1186 GLOBAL_CFG_IRQ0_EN_MASK | GLOBAL_CFG_IRQ1_EN_MASK | 1187 GLOBAL_CFG_TX_WB_DONE_MASK | 1188 FIELD_PREP(GLOBAL_CFG_MAX_ISSUE_NUM_MASK, 2)); 1189 1190 airoha_qdma_init_qos(qdma); 1191 1192 /* disable qdma rx delay interrupt */ 1193 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1194 if (!qdma->q_rx[i].ndesc) 1195 continue; 1196 1197 airoha_qdma_clear(qdma, REG_RX_DELAY_INT_IDX(i), 1198 RX_DELAY_INT_MASK); 1199 } 1200 1201 airoha_qdma_set(qdma, REG_TXQ_CNGST_CFG, 1202 TXQ_CNGST_DROP_EN | TXQ_CNGST_DEI_DROP_EN); 1203 airoha_qdma_init_qos_stats(qdma); 1204 1205 return 0; 1206 } 1207 1208 static irqreturn_t airoha_irq_handler(int irq, void *dev_instance) 1209 { 1210 struct airoha_qdma *qdma = dev_instance; 1211 u32 intr[ARRAY_SIZE(qdma->irqmask)]; 1212 int i; 1213 1214 for (i = 0; i < ARRAY_SIZE(qdma->irqmask); i++) { 1215 intr[i] = airoha_qdma_rr(qdma, REG_INT_STATUS(i)); 1216 intr[i] &= qdma->irqmask[i]; 1217 airoha_qdma_wr(qdma, REG_INT_STATUS(i), intr[i]); 1218 } 1219 1220 if (!test_bit(DEV_STATE_INITIALIZED, &qdma->eth->state)) 1221 return IRQ_NONE; 1222 1223 if (intr[1] & RX_DONE_INT_MASK) { 1224 airoha_qdma_irq_disable(qdma, QDMA_INT_REG_IDX1, 1225 RX_DONE_INT_MASK); 1226 1227 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1228 if (!qdma->q_rx[i].ndesc) 1229 continue; 1230 1231 if (intr[1] & BIT(i)) 1232 napi_schedule(&qdma->q_rx[i].napi); 1233 } 1234 } 1235 1236 if (intr[0] & INT_TX_MASK) { 1237 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) { 1238 if (!(intr[0] & TX_DONE_INT_MASK(i))) 1239 continue; 1240 1241 airoha_qdma_irq_disable(qdma, QDMA_INT_REG_IDX0, 1242 TX_DONE_INT_MASK(i)); 1243 napi_schedule(&qdma->q_tx_irq[i].napi); 1244 } 1245 } 1246 1247 return IRQ_HANDLED; 1248 } 1249 1250 static int airoha_qdma_init(struct platform_device *pdev, 1251 struct airoha_eth *eth, 1252 struct airoha_qdma *qdma) 1253 { 1254 int err, id = qdma - ð->qdma[0]; 1255 const char *res; 1256 1257 spin_lock_init(&qdma->irq_lock); 1258 qdma->eth = eth; 1259 1260 res = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d", id); 1261 if (!res) 1262 return -ENOMEM; 1263 1264 qdma->regs = devm_platform_ioremap_resource_byname(pdev, res); 1265 if (IS_ERR(qdma->regs)) 1266 return dev_err_probe(eth->dev, PTR_ERR(qdma->regs), 1267 "failed to iomap qdma%d regs\n", id); 1268 1269 qdma->irq = platform_get_irq(pdev, 4 * id); 1270 if (qdma->irq < 0) 1271 return qdma->irq; 1272 1273 err = devm_request_irq(eth->dev, qdma->irq, airoha_irq_handler, 1274 IRQF_SHARED, KBUILD_MODNAME, qdma); 1275 if (err) 1276 return err; 1277 1278 err = airoha_qdma_init_rx(qdma); 1279 if (err) 1280 return err; 1281 1282 err = airoha_qdma_init_tx(qdma); 1283 if (err) 1284 return err; 1285 1286 err = airoha_qdma_init_hfwd_queues(qdma); 1287 if (err) 1288 return err; 1289 1290 return airoha_qdma_hw_init(qdma); 1291 } 1292 1293 static int airoha_hw_init(struct platform_device *pdev, 1294 struct airoha_eth *eth) 1295 { 1296 int err, i; 1297 1298 /* disable xsi */ 1299 err = reset_control_bulk_assert(ARRAY_SIZE(eth->xsi_rsts), 1300 eth->xsi_rsts); 1301 if (err) 1302 return err; 1303 1304 err = reset_control_bulk_assert(ARRAY_SIZE(eth->rsts), eth->rsts); 1305 if (err) 1306 return err; 1307 1308 msleep(20); 1309 err = reset_control_bulk_deassert(ARRAY_SIZE(eth->rsts), eth->rsts); 1310 if (err) 1311 return err; 1312 1313 msleep(20); 1314 err = airoha_fe_init(eth); 1315 if (err) 1316 return err; 1317 1318 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) { 1319 err = airoha_qdma_init(pdev, eth, ð->qdma[i]); 1320 if (err) 1321 return err; 1322 } 1323 1324 err = airoha_ppe_init(eth); 1325 if (err) 1326 return err; 1327 1328 set_bit(DEV_STATE_INITIALIZED, ð->state); 1329 1330 return 0; 1331 } 1332 1333 static void airoha_hw_cleanup(struct airoha_qdma *qdma) 1334 { 1335 int i; 1336 1337 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1338 if (!qdma->q_rx[i].ndesc) 1339 continue; 1340 1341 netif_napi_del(&qdma->q_rx[i].napi); 1342 airoha_qdma_cleanup_rx_queue(&qdma->q_rx[i]); 1343 if (qdma->q_rx[i].page_pool) 1344 page_pool_destroy(qdma->q_rx[i].page_pool); 1345 } 1346 1347 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1348 netif_napi_del(&qdma->q_tx_irq[i].napi); 1349 1350 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1351 if (!qdma->q_tx[i].ndesc) 1352 continue; 1353 1354 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]); 1355 } 1356 } 1357 1358 static void airoha_qdma_start_napi(struct airoha_qdma *qdma) 1359 { 1360 int i; 1361 1362 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1363 napi_enable(&qdma->q_tx_irq[i].napi); 1364 1365 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1366 if (!qdma->q_rx[i].ndesc) 1367 continue; 1368 1369 napi_enable(&qdma->q_rx[i].napi); 1370 } 1371 } 1372 1373 static void airoha_qdma_stop_napi(struct airoha_qdma *qdma) 1374 { 1375 int i; 1376 1377 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1378 napi_disable(&qdma->q_tx_irq[i].napi); 1379 1380 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1381 if (!qdma->q_rx[i].ndesc) 1382 continue; 1383 1384 napi_disable(&qdma->q_rx[i].napi); 1385 } 1386 } 1387 1388 static void airoha_update_hw_stats(struct airoha_gdm_port *port) 1389 { 1390 struct airoha_eth *eth = port->qdma->eth; 1391 u32 val, i = 0; 1392 1393 spin_lock(&port->stats.lock); 1394 u64_stats_update_begin(&port->stats.syncp); 1395 1396 /* TX */ 1397 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_H(port->id)); 1398 port->stats.tx_ok_pkts += ((u64)val << 32); 1399 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_L(port->id)); 1400 port->stats.tx_ok_pkts += val; 1401 1402 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_H(port->id)); 1403 port->stats.tx_ok_bytes += ((u64)val << 32); 1404 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_L(port->id)); 1405 port->stats.tx_ok_bytes += val; 1406 1407 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_DROP_CNT(port->id)); 1408 port->stats.tx_drops += val; 1409 1410 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_BC_CNT(port->id)); 1411 port->stats.tx_broadcast += val; 1412 1413 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_MC_CNT(port->id)); 1414 port->stats.tx_multicast += val; 1415 1416 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_RUNT_CNT(port->id)); 1417 port->stats.tx_len[i] += val; 1418 1419 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_H(port->id)); 1420 port->stats.tx_len[i] += ((u64)val << 32); 1421 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_L(port->id)); 1422 port->stats.tx_len[i++] += val; 1423 1424 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_H(port->id)); 1425 port->stats.tx_len[i] += ((u64)val << 32); 1426 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_L(port->id)); 1427 port->stats.tx_len[i++] += val; 1428 1429 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_H(port->id)); 1430 port->stats.tx_len[i] += ((u64)val << 32); 1431 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_L(port->id)); 1432 port->stats.tx_len[i++] += val; 1433 1434 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_H(port->id)); 1435 port->stats.tx_len[i] += ((u64)val << 32); 1436 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_L(port->id)); 1437 port->stats.tx_len[i++] += val; 1438 1439 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_H(port->id)); 1440 port->stats.tx_len[i] += ((u64)val << 32); 1441 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_L(port->id)); 1442 port->stats.tx_len[i++] += val; 1443 1444 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_H(port->id)); 1445 port->stats.tx_len[i] += ((u64)val << 32); 1446 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_L(port->id)); 1447 port->stats.tx_len[i++] += val; 1448 1449 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_LONG_CNT(port->id)); 1450 port->stats.tx_len[i++] += val; 1451 1452 /* RX */ 1453 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_H(port->id)); 1454 port->stats.rx_ok_pkts += ((u64)val << 32); 1455 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_L(port->id)); 1456 port->stats.rx_ok_pkts += val; 1457 1458 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_H(port->id)); 1459 port->stats.rx_ok_bytes += ((u64)val << 32); 1460 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_L(port->id)); 1461 port->stats.rx_ok_bytes += val; 1462 1463 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_DROP_CNT(port->id)); 1464 port->stats.rx_drops += val; 1465 1466 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_BC_CNT(port->id)); 1467 port->stats.rx_broadcast += val; 1468 1469 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_MC_CNT(port->id)); 1470 port->stats.rx_multicast += val; 1471 1472 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ERROR_DROP_CNT(port->id)); 1473 port->stats.rx_errors += val; 1474 1475 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_CRC_ERR_CNT(port->id)); 1476 port->stats.rx_crc_error += val; 1477 1478 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OVERFLOW_DROP_CNT(port->id)); 1479 port->stats.rx_over_errors += val; 1480 1481 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_FRAG_CNT(port->id)); 1482 port->stats.rx_fragment += val; 1483 1484 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_JABBER_CNT(port->id)); 1485 port->stats.rx_jabber += val; 1486 1487 i = 0; 1488 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_RUNT_CNT(port->id)); 1489 port->stats.rx_len[i] += val; 1490 1491 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_H(port->id)); 1492 port->stats.rx_len[i] += ((u64)val << 32); 1493 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_L(port->id)); 1494 port->stats.rx_len[i++] += val; 1495 1496 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_H(port->id)); 1497 port->stats.rx_len[i] += ((u64)val << 32); 1498 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_L(port->id)); 1499 port->stats.rx_len[i++] += val; 1500 1501 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_H(port->id)); 1502 port->stats.rx_len[i] += ((u64)val << 32); 1503 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_L(port->id)); 1504 port->stats.rx_len[i++] += val; 1505 1506 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_H(port->id)); 1507 port->stats.rx_len[i] += ((u64)val << 32); 1508 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_L(port->id)); 1509 port->stats.rx_len[i++] += val; 1510 1511 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_H(port->id)); 1512 port->stats.rx_len[i] += ((u64)val << 32); 1513 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_L(port->id)); 1514 port->stats.rx_len[i++] += val; 1515 1516 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_H(port->id)); 1517 port->stats.rx_len[i] += ((u64)val << 32); 1518 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_L(port->id)); 1519 port->stats.rx_len[i++] += val; 1520 1521 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_LONG_CNT(port->id)); 1522 port->stats.rx_len[i++] += val; 1523 1524 /* reset mib counters */ 1525 airoha_fe_set(eth, REG_FE_GDM_MIB_CLEAR(port->id), 1526 FE_GDM_MIB_RX_CLEAR_MASK | FE_GDM_MIB_TX_CLEAR_MASK); 1527 1528 u64_stats_update_end(&port->stats.syncp); 1529 spin_unlock(&port->stats.lock); 1530 } 1531 1532 static int airoha_dev_open(struct net_device *dev) 1533 { 1534 int err, len = ETH_HLEN + dev->mtu + ETH_FCS_LEN; 1535 struct airoha_gdm_port *port = netdev_priv(dev); 1536 struct airoha_qdma *qdma = port->qdma; 1537 1538 netif_tx_start_all_queues(dev); 1539 err = airoha_set_vip_for_gdm_port(port, true); 1540 if (err) 1541 return err; 1542 1543 if (netdev_uses_dsa(dev)) 1544 airoha_fe_set(qdma->eth, REG_GDM_INGRESS_CFG(port->id), 1545 GDM_STAG_EN_MASK); 1546 else 1547 airoha_fe_clear(qdma->eth, REG_GDM_INGRESS_CFG(port->id), 1548 GDM_STAG_EN_MASK); 1549 1550 airoha_fe_rmw(qdma->eth, REG_GDM_LEN_CFG(port->id), 1551 GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK, 1552 FIELD_PREP(GDM_SHORT_LEN_MASK, 60) | 1553 FIELD_PREP(GDM_LONG_LEN_MASK, len)); 1554 1555 airoha_qdma_set(qdma, REG_QDMA_GLOBAL_CFG, 1556 GLOBAL_CFG_TX_DMA_EN_MASK | 1557 GLOBAL_CFG_RX_DMA_EN_MASK); 1558 atomic_inc(&qdma->users); 1559 1560 return 0; 1561 } 1562 1563 static int airoha_dev_stop(struct net_device *dev) 1564 { 1565 struct airoha_gdm_port *port = netdev_priv(dev); 1566 struct airoha_qdma *qdma = port->qdma; 1567 int i, err; 1568 1569 netif_tx_disable(dev); 1570 err = airoha_set_vip_for_gdm_port(port, false); 1571 if (err) 1572 return err; 1573 1574 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) 1575 netdev_tx_reset_subqueue(dev, i); 1576 1577 if (atomic_dec_and_test(&qdma->users)) { 1578 airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG, 1579 GLOBAL_CFG_TX_DMA_EN_MASK | 1580 GLOBAL_CFG_RX_DMA_EN_MASK); 1581 1582 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1583 if (!qdma->q_tx[i].ndesc) 1584 continue; 1585 1586 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]); 1587 } 1588 } 1589 1590 return 0; 1591 } 1592 1593 static int airoha_dev_set_macaddr(struct net_device *dev, void *p) 1594 { 1595 struct airoha_gdm_port *port = netdev_priv(dev); 1596 int err; 1597 1598 err = eth_mac_addr(dev, p); 1599 if (err) 1600 return err; 1601 1602 airoha_set_macaddr(port, dev->dev_addr); 1603 1604 return 0; 1605 } 1606 1607 static void airhoha_set_gdm2_loopback(struct airoha_gdm_port *port) 1608 { 1609 u32 pse_port = port->id == 3 ? FE_PSE_PORT_GDM3 : FE_PSE_PORT_GDM4; 1610 struct airoha_eth *eth = port->qdma->eth; 1611 u32 chan = port->id == 3 ? 4 : 0; 1612 1613 /* Forward the traffic to the proper GDM port */ 1614 airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(2), pse_port); 1615 airoha_fe_clear(eth, REG_GDM_FWD_CFG(2), GDM_STRIP_CRC); 1616 1617 /* Enable GDM2 loopback */ 1618 airoha_fe_wr(eth, REG_GDM_TXCHN_EN(2), 0xffffffff); 1619 airoha_fe_wr(eth, REG_GDM_RXCHN_EN(2), 0xffff); 1620 airoha_fe_rmw(eth, REG_GDM_LPBK_CFG(2), 1621 LPBK_CHAN_MASK | LPBK_MODE_MASK | LPBK_EN_MASK, 1622 FIELD_PREP(LPBK_CHAN_MASK, chan) | LPBK_EN_MASK); 1623 airoha_fe_rmw(eth, REG_GDM_LEN_CFG(2), 1624 GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK, 1625 FIELD_PREP(GDM_SHORT_LEN_MASK, 60) | 1626 FIELD_PREP(GDM_LONG_LEN_MASK, AIROHA_MAX_MTU)); 1627 1628 /* Disable VIP and IFC for GDM2 */ 1629 airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, BIT(2)); 1630 airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, BIT(2)); 1631 1632 if (port->id == 3) { 1633 /* FIXME: handle XSI_PCE1_PORT */ 1634 airoha_fe_wr(eth, REG_PPE_DFT_CPORT0(0), 0x5500); 1635 airoha_fe_rmw(eth, REG_FE_WAN_PORT, 1636 WAN1_EN_MASK | WAN1_MASK | WAN0_MASK, 1637 FIELD_PREP(WAN0_MASK, HSGMII_LAN_PCIE0_SRCPORT)); 1638 airoha_fe_rmw(eth, 1639 REG_SP_DFT_CPORT(HSGMII_LAN_PCIE0_SRCPORT >> 3), 1640 SP_CPORT_PCIE0_MASK, 1641 FIELD_PREP(SP_CPORT_PCIE0_MASK, 1642 FE_PSE_PORT_CDM2)); 1643 } else { 1644 /* FIXME: handle XSI_USB_PORT */ 1645 airoha_fe_rmw(eth, REG_SRC_PORT_FC_MAP6, 1646 FC_ID_OF_SRC_PORT24_MASK, 1647 FIELD_PREP(FC_ID_OF_SRC_PORT24_MASK, 2)); 1648 airoha_fe_rmw(eth, REG_FE_WAN_PORT, 1649 WAN1_EN_MASK | WAN1_MASK | WAN0_MASK, 1650 FIELD_PREP(WAN0_MASK, HSGMII_LAN_ETH_SRCPORT)); 1651 airoha_fe_rmw(eth, 1652 REG_SP_DFT_CPORT(HSGMII_LAN_ETH_SRCPORT >> 3), 1653 SP_CPORT_ETH_MASK, 1654 FIELD_PREP(SP_CPORT_ETH_MASK, FE_PSE_PORT_CDM2)); 1655 } 1656 } 1657 1658 static int airoha_dev_init(struct net_device *dev) 1659 { 1660 struct airoha_gdm_port *port = netdev_priv(dev); 1661 struct airoha_eth *eth = port->qdma->eth; 1662 u32 pse_port; 1663 1664 airoha_set_macaddr(port, dev->dev_addr); 1665 1666 switch (port->id) { 1667 case 3: 1668 case 4: 1669 /* If GDM2 is active we can't enable loopback */ 1670 if (!eth->ports[1]) 1671 airhoha_set_gdm2_loopback(port); 1672 fallthrough; 1673 case 2: 1674 pse_port = FE_PSE_PORT_PPE2; 1675 break; 1676 default: 1677 pse_port = FE_PSE_PORT_PPE1; 1678 break; 1679 } 1680 1681 airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(port->id), pse_port); 1682 1683 return 0; 1684 } 1685 1686 static void airoha_dev_get_stats64(struct net_device *dev, 1687 struct rtnl_link_stats64 *storage) 1688 { 1689 struct airoha_gdm_port *port = netdev_priv(dev); 1690 unsigned int start; 1691 1692 airoha_update_hw_stats(port); 1693 do { 1694 start = u64_stats_fetch_begin(&port->stats.syncp); 1695 storage->rx_packets = port->stats.rx_ok_pkts; 1696 storage->tx_packets = port->stats.tx_ok_pkts; 1697 storage->rx_bytes = port->stats.rx_ok_bytes; 1698 storage->tx_bytes = port->stats.tx_ok_bytes; 1699 storage->multicast = port->stats.rx_multicast; 1700 storage->rx_errors = port->stats.rx_errors; 1701 storage->rx_dropped = port->stats.rx_drops; 1702 storage->tx_dropped = port->stats.tx_drops; 1703 storage->rx_crc_errors = port->stats.rx_crc_error; 1704 storage->rx_over_errors = port->stats.rx_over_errors; 1705 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 1706 } 1707 1708 static int airoha_dev_change_mtu(struct net_device *dev, int mtu) 1709 { 1710 struct airoha_gdm_port *port = netdev_priv(dev); 1711 struct airoha_eth *eth = port->qdma->eth; 1712 u32 len = ETH_HLEN + mtu + ETH_FCS_LEN; 1713 1714 airoha_fe_rmw(eth, REG_GDM_LEN_CFG(port->id), 1715 GDM_LONG_LEN_MASK, 1716 FIELD_PREP(GDM_LONG_LEN_MASK, len)); 1717 WRITE_ONCE(dev->mtu, mtu); 1718 1719 return 0; 1720 } 1721 1722 static u16 airoha_dev_select_queue(struct net_device *dev, struct sk_buff *skb, 1723 struct net_device *sb_dev) 1724 { 1725 struct airoha_gdm_port *port = netdev_priv(dev); 1726 int queue, channel; 1727 1728 /* For dsa device select QoS channel according to the dsa user port 1729 * index, rely on port id otherwise. Select QoS queue based on the 1730 * skb priority. 1731 */ 1732 channel = netdev_uses_dsa(dev) ? skb_get_queue_mapping(skb) : port->id; 1733 channel = channel % AIROHA_NUM_QOS_CHANNELS; 1734 queue = (skb->priority - 1) % AIROHA_NUM_QOS_QUEUES; /* QoS queue */ 1735 queue = channel * AIROHA_NUM_QOS_QUEUES + queue; 1736 1737 return queue < dev->num_tx_queues ? queue : 0; 1738 } 1739 1740 static u32 airoha_get_dsa_tag(struct sk_buff *skb, struct net_device *dev) 1741 { 1742 #if IS_ENABLED(CONFIG_NET_DSA) 1743 struct ethhdr *ehdr; 1744 u8 xmit_tpid; 1745 u16 tag; 1746 1747 if (!netdev_uses_dsa(dev)) 1748 return 0; 1749 1750 if (dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK) 1751 return 0; 1752 1753 if (skb_cow_head(skb, 0)) 1754 return 0; 1755 1756 ehdr = (struct ethhdr *)skb->data; 1757 tag = be16_to_cpu(ehdr->h_proto); 1758 xmit_tpid = tag >> 8; 1759 1760 switch (xmit_tpid) { 1761 case MTK_HDR_XMIT_TAGGED_TPID_8100: 1762 ehdr->h_proto = cpu_to_be16(ETH_P_8021Q); 1763 tag &= ~(MTK_HDR_XMIT_TAGGED_TPID_8100 << 8); 1764 break; 1765 case MTK_HDR_XMIT_TAGGED_TPID_88A8: 1766 ehdr->h_proto = cpu_to_be16(ETH_P_8021AD); 1767 tag &= ~(MTK_HDR_XMIT_TAGGED_TPID_88A8 << 8); 1768 break; 1769 default: 1770 /* PPE module requires untagged DSA packets to work properly, 1771 * so move DSA tag to DMA descriptor. 1772 */ 1773 memmove(skb->data + MTK_HDR_LEN, skb->data, 2 * ETH_ALEN); 1774 __skb_pull(skb, MTK_HDR_LEN); 1775 break; 1776 } 1777 1778 return tag; 1779 #else 1780 return 0; 1781 #endif 1782 } 1783 1784 static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb, 1785 struct net_device *dev) 1786 { 1787 struct airoha_gdm_port *port = netdev_priv(dev); 1788 struct airoha_qdma *qdma = port->qdma; 1789 u32 nr_frags, tag, msg0, msg1, len; 1790 struct netdev_queue *txq; 1791 struct airoha_queue *q; 1792 void *data; 1793 int i, qid; 1794 u16 index; 1795 u8 fport; 1796 1797 qid = skb_get_queue_mapping(skb) % ARRAY_SIZE(qdma->q_tx); 1798 tag = airoha_get_dsa_tag(skb, dev); 1799 1800 msg0 = FIELD_PREP(QDMA_ETH_TXMSG_CHAN_MASK, 1801 qid / AIROHA_NUM_QOS_QUEUES) | 1802 FIELD_PREP(QDMA_ETH_TXMSG_QUEUE_MASK, 1803 qid % AIROHA_NUM_QOS_QUEUES) | 1804 FIELD_PREP(QDMA_ETH_TXMSG_SP_TAG_MASK, tag); 1805 if (skb->ip_summed == CHECKSUM_PARTIAL) 1806 msg0 |= FIELD_PREP(QDMA_ETH_TXMSG_TCO_MASK, 1) | 1807 FIELD_PREP(QDMA_ETH_TXMSG_UCO_MASK, 1) | 1808 FIELD_PREP(QDMA_ETH_TXMSG_ICO_MASK, 1); 1809 1810 /* TSO: fill MSS info in tcp checksum field */ 1811 if (skb_is_gso(skb)) { 1812 if (skb_cow_head(skb, 0)) 1813 goto error; 1814 1815 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | 1816 SKB_GSO_TCPV6)) { 1817 __be16 csum = cpu_to_be16(skb_shinfo(skb)->gso_size); 1818 1819 tcp_hdr(skb)->check = (__force __sum16)csum; 1820 msg0 |= FIELD_PREP(QDMA_ETH_TXMSG_TSO_MASK, 1); 1821 } 1822 } 1823 1824 fport = port->id == 4 ? FE_PSE_PORT_GDM4 : port->id; 1825 msg1 = FIELD_PREP(QDMA_ETH_TXMSG_FPORT_MASK, fport) | 1826 FIELD_PREP(QDMA_ETH_TXMSG_METER_MASK, 0x7f); 1827 1828 q = &qdma->q_tx[qid]; 1829 if (WARN_ON_ONCE(!q->ndesc)) 1830 goto error; 1831 1832 spin_lock_bh(&q->lock); 1833 1834 txq = netdev_get_tx_queue(dev, qid); 1835 nr_frags = 1 + skb_shinfo(skb)->nr_frags; 1836 1837 if (q->queued + nr_frags > q->ndesc) { 1838 /* not enough space in the queue */ 1839 netif_tx_stop_queue(txq); 1840 spin_unlock_bh(&q->lock); 1841 return NETDEV_TX_BUSY; 1842 } 1843 1844 len = skb_headlen(skb); 1845 data = skb->data; 1846 index = q->head; 1847 1848 for (i = 0; i < nr_frags; i++) { 1849 struct airoha_qdma_desc *desc = &q->desc[index]; 1850 struct airoha_queue_entry *e = &q->entry[index]; 1851 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1852 dma_addr_t addr; 1853 u32 val; 1854 1855 addr = dma_map_single(dev->dev.parent, data, len, 1856 DMA_TO_DEVICE); 1857 if (unlikely(dma_mapping_error(dev->dev.parent, addr))) 1858 goto error_unmap; 1859 1860 index = (index + 1) % q->ndesc; 1861 1862 val = FIELD_PREP(QDMA_DESC_LEN_MASK, len); 1863 if (i < nr_frags - 1) 1864 val |= FIELD_PREP(QDMA_DESC_MORE_MASK, 1); 1865 WRITE_ONCE(desc->ctrl, cpu_to_le32(val)); 1866 WRITE_ONCE(desc->addr, cpu_to_le32(addr)); 1867 val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, index); 1868 WRITE_ONCE(desc->data, cpu_to_le32(val)); 1869 WRITE_ONCE(desc->msg0, cpu_to_le32(msg0)); 1870 WRITE_ONCE(desc->msg1, cpu_to_le32(msg1)); 1871 WRITE_ONCE(desc->msg2, cpu_to_le32(0xffff)); 1872 1873 e->skb = i ? NULL : skb; 1874 e->dma_addr = addr; 1875 e->dma_len = len; 1876 1877 data = skb_frag_address(frag); 1878 len = skb_frag_size(frag); 1879 } 1880 1881 q->head = index; 1882 q->queued += i; 1883 1884 skb_tx_timestamp(skb); 1885 netdev_tx_sent_queue(txq, skb->len); 1886 1887 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) 1888 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), 1889 TX_RING_CPU_IDX_MASK, 1890 FIELD_PREP(TX_RING_CPU_IDX_MASK, q->head)); 1891 1892 if (q->ndesc - q->queued < q->free_thr) 1893 netif_tx_stop_queue(txq); 1894 1895 spin_unlock_bh(&q->lock); 1896 1897 return NETDEV_TX_OK; 1898 1899 error_unmap: 1900 for (i--; i >= 0; i--) { 1901 index = (q->head + i) % q->ndesc; 1902 dma_unmap_single(dev->dev.parent, q->entry[index].dma_addr, 1903 q->entry[index].dma_len, DMA_TO_DEVICE); 1904 } 1905 1906 spin_unlock_bh(&q->lock); 1907 error: 1908 dev_kfree_skb_any(skb); 1909 dev->stats.tx_dropped++; 1910 1911 return NETDEV_TX_OK; 1912 } 1913 1914 static void airoha_ethtool_get_drvinfo(struct net_device *dev, 1915 struct ethtool_drvinfo *info) 1916 { 1917 struct airoha_gdm_port *port = netdev_priv(dev); 1918 struct airoha_eth *eth = port->qdma->eth; 1919 1920 strscpy(info->driver, eth->dev->driver->name, sizeof(info->driver)); 1921 strscpy(info->bus_info, dev_name(eth->dev), sizeof(info->bus_info)); 1922 } 1923 1924 static void airoha_ethtool_get_mac_stats(struct net_device *dev, 1925 struct ethtool_eth_mac_stats *stats) 1926 { 1927 struct airoha_gdm_port *port = netdev_priv(dev); 1928 unsigned int start; 1929 1930 airoha_update_hw_stats(port); 1931 do { 1932 start = u64_stats_fetch_begin(&port->stats.syncp); 1933 stats->MulticastFramesXmittedOK = port->stats.tx_multicast; 1934 stats->BroadcastFramesXmittedOK = port->stats.tx_broadcast; 1935 stats->BroadcastFramesReceivedOK = port->stats.rx_broadcast; 1936 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 1937 } 1938 1939 static const struct ethtool_rmon_hist_range airoha_ethtool_rmon_ranges[] = { 1940 { 0, 64 }, 1941 { 65, 127 }, 1942 { 128, 255 }, 1943 { 256, 511 }, 1944 { 512, 1023 }, 1945 { 1024, 1518 }, 1946 { 1519, 10239 }, 1947 {}, 1948 }; 1949 1950 static void 1951 airoha_ethtool_get_rmon_stats(struct net_device *dev, 1952 struct ethtool_rmon_stats *stats, 1953 const struct ethtool_rmon_hist_range **ranges) 1954 { 1955 struct airoha_gdm_port *port = netdev_priv(dev); 1956 struct airoha_hw_stats *hw_stats = &port->stats; 1957 unsigned int start; 1958 1959 BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) != 1960 ARRAY_SIZE(hw_stats->tx_len) + 1); 1961 BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) != 1962 ARRAY_SIZE(hw_stats->rx_len) + 1); 1963 1964 *ranges = airoha_ethtool_rmon_ranges; 1965 airoha_update_hw_stats(port); 1966 do { 1967 int i; 1968 1969 start = u64_stats_fetch_begin(&port->stats.syncp); 1970 stats->fragments = hw_stats->rx_fragment; 1971 stats->jabbers = hw_stats->rx_jabber; 1972 for (i = 0; i < ARRAY_SIZE(airoha_ethtool_rmon_ranges) - 1; 1973 i++) { 1974 stats->hist[i] = hw_stats->rx_len[i]; 1975 stats->hist_tx[i] = hw_stats->tx_len[i]; 1976 } 1977 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 1978 } 1979 1980 static int airoha_qdma_set_chan_tx_sched(struct airoha_gdm_port *port, 1981 int channel, enum tx_sched_mode mode, 1982 const u16 *weights, u8 n_weights) 1983 { 1984 int i; 1985 1986 for (i = 0; i < AIROHA_NUM_TX_RING; i++) 1987 airoha_qdma_clear(port->qdma, REG_QUEUE_CLOSE_CFG(channel), 1988 TXQ_DISABLE_CHAN_QUEUE_MASK(channel, i)); 1989 1990 for (i = 0; i < n_weights; i++) { 1991 u32 status; 1992 int err; 1993 1994 airoha_qdma_wr(port->qdma, REG_TXWRR_WEIGHT_CFG, 1995 TWRR_RW_CMD_MASK | 1996 FIELD_PREP(TWRR_CHAN_IDX_MASK, channel) | 1997 FIELD_PREP(TWRR_QUEUE_IDX_MASK, i) | 1998 FIELD_PREP(TWRR_VALUE_MASK, weights[i])); 1999 err = read_poll_timeout(airoha_qdma_rr, status, 2000 status & TWRR_RW_CMD_DONE, 2001 USEC_PER_MSEC, 10 * USEC_PER_MSEC, 2002 true, port->qdma, 2003 REG_TXWRR_WEIGHT_CFG); 2004 if (err) 2005 return err; 2006 } 2007 2008 airoha_qdma_rmw(port->qdma, REG_CHAN_QOS_MODE(channel >> 3), 2009 CHAN_QOS_MODE_MASK(channel), 2010 mode << __ffs(CHAN_QOS_MODE_MASK(channel))); 2011 2012 return 0; 2013 } 2014 2015 static int airoha_qdma_set_tx_prio_sched(struct airoha_gdm_port *port, 2016 int channel) 2017 { 2018 static const u16 w[AIROHA_NUM_QOS_QUEUES] = {}; 2019 2020 return airoha_qdma_set_chan_tx_sched(port, channel, TC_SCH_SP, w, 2021 ARRAY_SIZE(w)); 2022 } 2023 2024 static int airoha_qdma_set_tx_ets_sched(struct airoha_gdm_port *port, 2025 int channel, 2026 struct tc_ets_qopt_offload *opt) 2027 { 2028 struct tc_ets_qopt_offload_replace_params *p = &opt->replace_params; 2029 enum tx_sched_mode mode = TC_SCH_SP; 2030 u16 w[AIROHA_NUM_QOS_QUEUES] = {}; 2031 int i, nstrict = 0, nwrr, qidx; 2032 2033 if (p->bands > AIROHA_NUM_QOS_QUEUES) 2034 return -EINVAL; 2035 2036 for (i = 0; i < p->bands; i++) { 2037 if (!p->quanta[i]) 2038 nstrict++; 2039 } 2040 2041 /* this configuration is not supported by the hw */ 2042 if (nstrict == AIROHA_NUM_QOS_QUEUES - 1) 2043 return -EINVAL; 2044 2045 /* EN7581 SoC supports fixed QoS band priority where WRR queues have 2046 * lowest priorities with respect to SP ones. 2047 * e.g: WRR0, WRR1, .., WRRm, SP0, SP1, .., SPn 2048 */ 2049 nwrr = p->bands - nstrict; 2050 qidx = nstrict && nwrr ? nstrict : 0; 2051 for (i = 1; i <= p->bands; i++) { 2052 if (p->priomap[i % AIROHA_NUM_QOS_QUEUES] != qidx) 2053 return -EINVAL; 2054 2055 qidx = i == nwrr ? 0 : qidx + 1; 2056 } 2057 2058 for (i = 0; i < nwrr; i++) 2059 w[i] = p->weights[nstrict + i]; 2060 2061 if (!nstrict) 2062 mode = TC_SCH_WRR8; 2063 else if (nstrict < AIROHA_NUM_QOS_QUEUES - 1) 2064 mode = nstrict + 1; 2065 2066 return airoha_qdma_set_chan_tx_sched(port, channel, mode, w, 2067 ARRAY_SIZE(w)); 2068 } 2069 2070 static int airoha_qdma_get_tx_ets_stats(struct airoha_gdm_port *port, 2071 int channel, 2072 struct tc_ets_qopt_offload *opt) 2073 { 2074 u64 cpu_tx_packets = airoha_qdma_rr(port->qdma, 2075 REG_CNTR_VAL(channel << 1)); 2076 u64 fwd_tx_packets = airoha_qdma_rr(port->qdma, 2077 REG_CNTR_VAL((channel << 1) + 1)); 2078 u64 tx_packets = (cpu_tx_packets - port->cpu_tx_packets) + 2079 (fwd_tx_packets - port->fwd_tx_packets); 2080 _bstats_update(opt->stats.bstats, 0, tx_packets); 2081 2082 port->cpu_tx_packets = cpu_tx_packets; 2083 port->fwd_tx_packets = fwd_tx_packets; 2084 2085 return 0; 2086 } 2087 2088 static int airoha_tc_setup_qdisc_ets(struct airoha_gdm_port *port, 2089 struct tc_ets_qopt_offload *opt) 2090 { 2091 int channel; 2092 2093 if (opt->parent == TC_H_ROOT) 2094 return -EINVAL; 2095 2096 channel = TC_H_MAJ(opt->handle) >> 16; 2097 channel = channel % AIROHA_NUM_QOS_CHANNELS; 2098 2099 switch (opt->command) { 2100 case TC_ETS_REPLACE: 2101 return airoha_qdma_set_tx_ets_sched(port, channel, opt); 2102 case TC_ETS_DESTROY: 2103 /* PRIO is default qdisc scheduler */ 2104 return airoha_qdma_set_tx_prio_sched(port, channel); 2105 case TC_ETS_STATS: 2106 return airoha_qdma_get_tx_ets_stats(port, channel, opt); 2107 default: 2108 return -EOPNOTSUPP; 2109 } 2110 } 2111 2112 static int airoha_qdma_get_trtcm_param(struct airoha_qdma *qdma, int channel, 2113 u32 addr, enum trtcm_param_type param, 2114 enum trtcm_mode_type mode, 2115 u32 *val_low, u32 *val_high) 2116 { 2117 u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel); 2118 u32 val, config = FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) | 2119 FIELD_PREP(TRTCM_METER_GROUP_MASK, group) | 2120 FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) | 2121 FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode); 2122 2123 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2124 if (read_poll_timeout(airoha_qdma_rr, val, 2125 val & TRTCM_PARAM_RW_DONE_MASK, 2126 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2127 qdma, REG_TRTCM_CFG_PARAM(addr))) 2128 return -ETIMEDOUT; 2129 2130 *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr)); 2131 if (val_high) 2132 *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr)); 2133 2134 return 0; 2135 } 2136 2137 static int airoha_qdma_set_trtcm_param(struct airoha_qdma *qdma, int channel, 2138 u32 addr, enum trtcm_param_type param, 2139 enum trtcm_mode_type mode, u32 val) 2140 { 2141 u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel); 2142 u32 config = TRTCM_PARAM_RW_MASK | 2143 FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) | 2144 FIELD_PREP(TRTCM_METER_GROUP_MASK, group) | 2145 FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) | 2146 FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode); 2147 2148 airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val); 2149 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2150 2151 return read_poll_timeout(airoha_qdma_rr, val, 2152 val & TRTCM_PARAM_RW_DONE_MASK, 2153 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2154 qdma, REG_TRTCM_CFG_PARAM(addr)); 2155 } 2156 2157 static int airoha_qdma_set_trtcm_config(struct airoha_qdma *qdma, int channel, 2158 u32 addr, enum trtcm_mode_type mode, 2159 bool enable, u32 enable_mask) 2160 { 2161 u32 val; 2162 2163 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2164 mode, &val, NULL)) 2165 return -EINVAL; 2166 2167 val = enable ? val | enable_mask : val & ~enable_mask; 2168 2169 return airoha_qdma_set_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2170 mode, val); 2171 } 2172 2173 static int airoha_qdma_set_trtcm_token_bucket(struct airoha_qdma *qdma, 2174 int channel, u32 addr, 2175 enum trtcm_mode_type mode, 2176 u32 rate_val, u32 bucket_size) 2177 { 2178 u32 val, config, tick, unit, rate, rate_frac; 2179 int err; 2180 2181 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2182 mode, &config, NULL)) 2183 return -EINVAL; 2184 2185 val = airoha_qdma_rr(qdma, addr); 2186 tick = FIELD_GET(INGRESS_FAST_TICK_MASK, val); 2187 if (config & TRTCM_TICK_SEL) 2188 tick *= FIELD_GET(INGRESS_SLOW_TICK_RATIO_MASK, val); 2189 if (!tick) 2190 return -EINVAL; 2191 2192 unit = (config & TRTCM_PKT_MODE) ? 1000000 / tick : 8000 / tick; 2193 if (!unit) 2194 return -EINVAL; 2195 2196 rate = rate_val / unit; 2197 rate_frac = rate_val % unit; 2198 rate_frac = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate_frac) / unit; 2199 rate = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate) | 2200 FIELD_PREP(TRTCM_TOKEN_RATE_FRACTION_MASK, rate_frac); 2201 2202 err = airoha_qdma_set_trtcm_param(qdma, channel, addr, 2203 TRTCM_TOKEN_RATE_MODE, mode, rate); 2204 if (err) 2205 return err; 2206 2207 val = max_t(u32, bucket_size, MIN_TOKEN_SIZE); 2208 val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET); 2209 2210 return airoha_qdma_set_trtcm_param(qdma, channel, addr, 2211 TRTCM_BUCKETSIZE_SHIFT_MODE, 2212 mode, val); 2213 } 2214 2215 static int airoha_qdma_set_tx_rate_limit(struct airoha_gdm_port *port, 2216 int channel, u32 rate, 2217 u32 bucket_size) 2218 { 2219 int i, err; 2220 2221 for (i = 0; i <= TRTCM_PEAK_MODE; i++) { 2222 err = airoha_qdma_set_trtcm_config(port->qdma, channel, 2223 REG_EGRESS_TRTCM_CFG, i, 2224 !!rate, TRTCM_METER_MODE); 2225 if (err) 2226 return err; 2227 2228 err = airoha_qdma_set_trtcm_token_bucket(port->qdma, channel, 2229 REG_EGRESS_TRTCM_CFG, 2230 i, rate, bucket_size); 2231 if (err) 2232 return err; 2233 } 2234 2235 return 0; 2236 } 2237 2238 static int airoha_tc_htb_alloc_leaf_queue(struct airoha_gdm_port *port, 2239 struct tc_htb_qopt_offload *opt) 2240 { 2241 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2242 u32 rate = div_u64(opt->rate, 1000) << 3; /* kbps */ 2243 struct net_device *dev = port->dev; 2244 int num_tx_queues = dev->real_num_tx_queues; 2245 int err; 2246 2247 if (opt->parent_classid != TC_HTB_CLASSID_ROOT) { 2248 NL_SET_ERR_MSG_MOD(opt->extack, "invalid parent classid"); 2249 return -EINVAL; 2250 } 2251 2252 err = airoha_qdma_set_tx_rate_limit(port, channel, rate, opt->quantum); 2253 if (err) { 2254 NL_SET_ERR_MSG_MOD(opt->extack, 2255 "failed configuring htb offload"); 2256 return err; 2257 } 2258 2259 if (opt->command == TC_HTB_NODE_MODIFY) 2260 return 0; 2261 2262 err = netif_set_real_num_tx_queues(dev, num_tx_queues + 1); 2263 if (err) { 2264 airoha_qdma_set_tx_rate_limit(port, channel, 0, opt->quantum); 2265 NL_SET_ERR_MSG_MOD(opt->extack, 2266 "failed setting real_num_tx_queues"); 2267 return err; 2268 } 2269 2270 set_bit(channel, port->qos_sq_bmap); 2271 opt->qid = AIROHA_NUM_TX_RING + channel; 2272 2273 return 0; 2274 } 2275 2276 static int airoha_dev_setup_tc_block(struct airoha_gdm_port *port, 2277 struct flow_block_offload *f) 2278 { 2279 flow_setup_cb_t *cb = airoha_ppe_setup_tc_block_cb; 2280 static LIST_HEAD(block_cb_list); 2281 struct flow_block_cb *block_cb; 2282 2283 if (f->binder_type != FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 2284 return -EOPNOTSUPP; 2285 2286 f->driver_block_list = &block_cb_list; 2287 switch (f->command) { 2288 case FLOW_BLOCK_BIND: 2289 block_cb = flow_block_cb_lookup(f->block, cb, port->dev); 2290 if (block_cb) { 2291 flow_block_cb_incref(block_cb); 2292 return 0; 2293 } 2294 block_cb = flow_block_cb_alloc(cb, port->dev, port->dev, NULL); 2295 if (IS_ERR(block_cb)) 2296 return PTR_ERR(block_cb); 2297 2298 flow_block_cb_incref(block_cb); 2299 flow_block_cb_add(block_cb, f); 2300 list_add_tail(&block_cb->driver_list, &block_cb_list); 2301 return 0; 2302 case FLOW_BLOCK_UNBIND: 2303 block_cb = flow_block_cb_lookup(f->block, cb, port->dev); 2304 if (!block_cb) 2305 return -ENOENT; 2306 2307 if (!flow_block_cb_decref(block_cb)) { 2308 flow_block_cb_remove(block_cb, f); 2309 list_del(&block_cb->driver_list); 2310 } 2311 return 0; 2312 default: 2313 return -EOPNOTSUPP; 2314 } 2315 } 2316 2317 static void airoha_tc_remove_htb_queue(struct airoha_gdm_port *port, int queue) 2318 { 2319 struct net_device *dev = port->dev; 2320 2321 netif_set_real_num_tx_queues(dev, dev->real_num_tx_queues - 1); 2322 airoha_qdma_set_tx_rate_limit(port, queue + 1, 0, 0); 2323 clear_bit(queue, port->qos_sq_bmap); 2324 } 2325 2326 static int airoha_tc_htb_delete_leaf_queue(struct airoha_gdm_port *port, 2327 struct tc_htb_qopt_offload *opt) 2328 { 2329 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2330 2331 if (!test_bit(channel, port->qos_sq_bmap)) { 2332 NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id"); 2333 return -EINVAL; 2334 } 2335 2336 airoha_tc_remove_htb_queue(port, channel); 2337 2338 return 0; 2339 } 2340 2341 static int airoha_tc_htb_destroy(struct airoha_gdm_port *port) 2342 { 2343 int q; 2344 2345 for_each_set_bit(q, port->qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS) 2346 airoha_tc_remove_htb_queue(port, q); 2347 2348 return 0; 2349 } 2350 2351 static int airoha_tc_get_htb_get_leaf_queue(struct airoha_gdm_port *port, 2352 struct tc_htb_qopt_offload *opt) 2353 { 2354 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2355 2356 if (!test_bit(channel, port->qos_sq_bmap)) { 2357 NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id"); 2358 return -EINVAL; 2359 } 2360 2361 opt->qid = channel; 2362 2363 return 0; 2364 } 2365 2366 static int airoha_tc_setup_qdisc_htb(struct airoha_gdm_port *port, 2367 struct tc_htb_qopt_offload *opt) 2368 { 2369 switch (opt->command) { 2370 case TC_HTB_CREATE: 2371 break; 2372 case TC_HTB_DESTROY: 2373 return airoha_tc_htb_destroy(port); 2374 case TC_HTB_NODE_MODIFY: 2375 case TC_HTB_LEAF_ALLOC_QUEUE: 2376 return airoha_tc_htb_alloc_leaf_queue(port, opt); 2377 case TC_HTB_LEAF_DEL: 2378 case TC_HTB_LEAF_DEL_LAST: 2379 case TC_HTB_LEAF_DEL_LAST_FORCE: 2380 return airoha_tc_htb_delete_leaf_queue(port, opt); 2381 case TC_HTB_LEAF_QUERY_QUEUE: 2382 return airoha_tc_get_htb_get_leaf_queue(port, opt); 2383 default: 2384 return -EOPNOTSUPP; 2385 } 2386 2387 return 0; 2388 } 2389 2390 static int airoha_dev_tc_setup(struct net_device *dev, enum tc_setup_type type, 2391 void *type_data) 2392 { 2393 struct airoha_gdm_port *port = netdev_priv(dev); 2394 2395 switch (type) { 2396 case TC_SETUP_QDISC_ETS: 2397 return airoha_tc_setup_qdisc_ets(port, type_data); 2398 case TC_SETUP_QDISC_HTB: 2399 return airoha_tc_setup_qdisc_htb(port, type_data); 2400 case TC_SETUP_BLOCK: 2401 case TC_SETUP_FT: 2402 return airoha_dev_setup_tc_block(port, type_data); 2403 default: 2404 return -EOPNOTSUPP; 2405 } 2406 } 2407 2408 static const struct net_device_ops airoha_netdev_ops = { 2409 .ndo_init = airoha_dev_init, 2410 .ndo_open = airoha_dev_open, 2411 .ndo_stop = airoha_dev_stop, 2412 .ndo_change_mtu = airoha_dev_change_mtu, 2413 .ndo_select_queue = airoha_dev_select_queue, 2414 .ndo_start_xmit = airoha_dev_xmit, 2415 .ndo_get_stats64 = airoha_dev_get_stats64, 2416 .ndo_set_mac_address = airoha_dev_set_macaddr, 2417 .ndo_setup_tc = airoha_dev_tc_setup, 2418 }; 2419 2420 static const struct ethtool_ops airoha_ethtool_ops = { 2421 .get_drvinfo = airoha_ethtool_get_drvinfo, 2422 .get_eth_mac_stats = airoha_ethtool_get_mac_stats, 2423 .get_rmon_stats = airoha_ethtool_get_rmon_stats, 2424 }; 2425 2426 static int airoha_metadata_dst_alloc(struct airoha_gdm_port *port) 2427 { 2428 int i; 2429 2430 for (i = 0; i < ARRAY_SIZE(port->dsa_meta); i++) { 2431 struct metadata_dst *md_dst; 2432 2433 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, 2434 GFP_KERNEL); 2435 if (!md_dst) 2436 return -ENOMEM; 2437 2438 md_dst->u.port_info.port_id = i; 2439 port->dsa_meta[i] = md_dst; 2440 } 2441 2442 return 0; 2443 } 2444 2445 static void airoha_metadata_dst_free(struct airoha_gdm_port *port) 2446 { 2447 int i; 2448 2449 for (i = 0; i < ARRAY_SIZE(port->dsa_meta); i++) { 2450 if (!port->dsa_meta[i]) 2451 continue; 2452 2453 metadata_dst_free(port->dsa_meta[i]); 2454 } 2455 } 2456 2457 static int airoha_alloc_gdm_port(struct airoha_eth *eth, 2458 struct device_node *np, int index) 2459 { 2460 const __be32 *id_ptr = of_get_property(np, "reg", NULL); 2461 struct airoha_gdm_port *port; 2462 struct airoha_qdma *qdma; 2463 struct net_device *dev; 2464 int err, p; 2465 u32 id; 2466 2467 if (!id_ptr) { 2468 dev_err(eth->dev, "missing gdm port id\n"); 2469 return -EINVAL; 2470 } 2471 2472 id = be32_to_cpup(id_ptr); 2473 p = id - 1; 2474 2475 if (!id || id > ARRAY_SIZE(eth->ports)) { 2476 dev_err(eth->dev, "invalid gdm port id: %d\n", id); 2477 return -EINVAL; 2478 } 2479 2480 if (eth->ports[p]) { 2481 dev_err(eth->dev, "duplicate gdm port id: %d\n", id); 2482 return -EINVAL; 2483 } 2484 2485 dev = devm_alloc_etherdev_mqs(eth->dev, sizeof(*port), 2486 AIROHA_NUM_NETDEV_TX_RINGS, 2487 AIROHA_NUM_RX_RING); 2488 if (!dev) { 2489 dev_err(eth->dev, "alloc_etherdev failed\n"); 2490 return -ENOMEM; 2491 } 2492 2493 qdma = ð->qdma[index % AIROHA_MAX_NUM_QDMA]; 2494 dev->netdev_ops = &airoha_netdev_ops; 2495 dev->ethtool_ops = &airoha_ethtool_ops; 2496 dev->max_mtu = AIROHA_MAX_MTU; 2497 dev->watchdog_timeo = 5 * HZ; 2498 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 2499 NETIF_F_TSO6 | NETIF_F_IPV6_CSUM | 2500 NETIF_F_SG | NETIF_F_TSO | 2501 NETIF_F_HW_TC; 2502 dev->features |= dev->hw_features; 2503 dev->vlan_features = dev->hw_features; 2504 dev->dev.of_node = np; 2505 dev->irq = qdma->irq; 2506 SET_NETDEV_DEV(dev, eth->dev); 2507 2508 /* reserve hw queues for HTB offloading */ 2509 err = netif_set_real_num_tx_queues(dev, AIROHA_NUM_TX_RING); 2510 if (err) 2511 return err; 2512 2513 err = of_get_ethdev_address(np, dev); 2514 if (err) { 2515 if (err == -EPROBE_DEFER) 2516 return err; 2517 2518 eth_hw_addr_random(dev); 2519 dev_info(eth->dev, "generated random MAC address %pM\n", 2520 dev->dev_addr); 2521 } 2522 2523 port = netdev_priv(dev); 2524 u64_stats_init(&port->stats.syncp); 2525 spin_lock_init(&port->stats.lock); 2526 port->qdma = qdma; 2527 port->dev = dev; 2528 port->id = id; 2529 eth->ports[p] = port; 2530 2531 err = airoha_metadata_dst_alloc(port); 2532 if (err) 2533 return err; 2534 2535 return register_netdev(dev); 2536 } 2537 2538 static int airoha_probe(struct platform_device *pdev) 2539 { 2540 struct device_node *np; 2541 struct airoha_eth *eth; 2542 int i, err; 2543 2544 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 2545 if (!eth) 2546 return -ENOMEM; 2547 2548 eth->dev = &pdev->dev; 2549 2550 err = dma_set_mask_and_coherent(eth->dev, DMA_BIT_MASK(32)); 2551 if (err) { 2552 dev_err(eth->dev, "failed configuring DMA mask\n"); 2553 return err; 2554 } 2555 2556 eth->fe_regs = devm_platform_ioremap_resource_byname(pdev, "fe"); 2557 if (IS_ERR(eth->fe_regs)) 2558 return dev_err_probe(eth->dev, PTR_ERR(eth->fe_regs), 2559 "failed to iomap fe regs\n"); 2560 2561 eth->rsts[0].id = "fe"; 2562 eth->rsts[1].id = "pdma"; 2563 eth->rsts[2].id = "qdma"; 2564 err = devm_reset_control_bulk_get_exclusive(eth->dev, 2565 ARRAY_SIZE(eth->rsts), 2566 eth->rsts); 2567 if (err) { 2568 dev_err(eth->dev, "failed to get bulk reset lines\n"); 2569 return err; 2570 } 2571 2572 eth->xsi_rsts[0].id = "xsi-mac"; 2573 eth->xsi_rsts[1].id = "hsi0-mac"; 2574 eth->xsi_rsts[2].id = "hsi1-mac"; 2575 eth->xsi_rsts[3].id = "hsi-mac"; 2576 eth->xsi_rsts[4].id = "xfp-mac"; 2577 err = devm_reset_control_bulk_get_exclusive(eth->dev, 2578 ARRAY_SIZE(eth->xsi_rsts), 2579 eth->xsi_rsts); 2580 if (err) { 2581 dev_err(eth->dev, "failed to get bulk xsi reset lines\n"); 2582 return err; 2583 } 2584 2585 eth->napi_dev = alloc_netdev_dummy(0); 2586 if (!eth->napi_dev) 2587 return -ENOMEM; 2588 2589 /* Enable threaded NAPI by default */ 2590 eth->napi_dev->threaded = true; 2591 strscpy(eth->napi_dev->name, "qdma_eth", sizeof(eth->napi_dev->name)); 2592 platform_set_drvdata(pdev, eth); 2593 2594 err = airoha_hw_init(pdev, eth); 2595 if (err) 2596 goto error_hw_cleanup; 2597 2598 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 2599 airoha_qdma_start_napi(ð->qdma[i]); 2600 2601 i = 0; 2602 for_each_child_of_node(pdev->dev.of_node, np) { 2603 if (!of_device_is_compatible(np, "airoha,eth-mac")) 2604 continue; 2605 2606 if (!of_device_is_available(np)) 2607 continue; 2608 2609 err = airoha_alloc_gdm_port(eth, np, i++); 2610 if (err) { 2611 of_node_put(np); 2612 goto error_napi_stop; 2613 } 2614 } 2615 2616 return 0; 2617 2618 error_napi_stop: 2619 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 2620 airoha_qdma_stop_napi(ð->qdma[i]); 2621 error_hw_cleanup: 2622 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 2623 airoha_hw_cleanup(ð->qdma[i]); 2624 2625 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 2626 struct airoha_gdm_port *port = eth->ports[i]; 2627 2628 if (port && port->dev->reg_state == NETREG_REGISTERED) { 2629 unregister_netdev(port->dev); 2630 airoha_metadata_dst_free(port); 2631 } 2632 } 2633 free_netdev(eth->napi_dev); 2634 platform_set_drvdata(pdev, NULL); 2635 2636 return err; 2637 } 2638 2639 static void airoha_remove(struct platform_device *pdev) 2640 { 2641 struct airoha_eth *eth = platform_get_drvdata(pdev); 2642 int i; 2643 2644 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) { 2645 airoha_qdma_stop_napi(ð->qdma[i]); 2646 airoha_hw_cleanup(ð->qdma[i]); 2647 } 2648 2649 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 2650 struct airoha_gdm_port *port = eth->ports[i]; 2651 2652 if (!port) 2653 continue; 2654 2655 airoha_dev_stop(port->dev); 2656 unregister_netdev(port->dev); 2657 airoha_metadata_dst_free(port); 2658 } 2659 free_netdev(eth->napi_dev); 2660 2661 airoha_ppe_deinit(eth); 2662 platform_set_drvdata(pdev, NULL); 2663 } 2664 2665 static const struct of_device_id of_airoha_match[] = { 2666 { .compatible = "airoha,en7581-eth" }, 2667 { /* sentinel */ } 2668 }; 2669 MODULE_DEVICE_TABLE(of, of_airoha_match); 2670 2671 static struct platform_driver airoha_driver = { 2672 .probe = airoha_probe, 2673 .remove = airoha_remove, 2674 .driver = { 2675 .name = KBUILD_MODNAME, 2676 .of_match_table = of_airoha_match, 2677 }, 2678 }; 2679 module_platform_driver(airoha_driver); 2680 2681 MODULE_LICENSE("GPL"); 2682 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 2683 MODULE_DESCRIPTION("Ethernet driver for Airoha SoC"); 2684