1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024 AIROHA Inc 4 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 5 */ 6 #include <linux/of.h> 7 #include <linux/of_net.h> 8 #include <linux/of_reserved_mem.h> 9 #include <linux/platform_device.h> 10 #include <linux/tcp.h> 11 #include <linux/u64_stats_sync.h> 12 #include <net/dst_metadata.h> 13 #include <net/page_pool/helpers.h> 14 #include <net/pkt_cls.h> 15 #include <uapi/linux/ppp_defs.h> 16 17 #include "airoha_regs.h" 18 #include "airoha_eth.h" 19 20 u32 airoha_rr(void __iomem *base, u32 offset) 21 { 22 return readl(base + offset); 23 } 24 25 void airoha_wr(void __iomem *base, u32 offset, u32 val) 26 { 27 writel(val, base + offset); 28 } 29 30 u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val) 31 { 32 val |= (airoha_rr(base, offset) & ~mask); 33 airoha_wr(base, offset, val); 34 35 return val; 36 } 37 38 static void airoha_qdma_set_irqmask(struct airoha_irq_bank *irq_bank, 39 int index, u32 clear, u32 set) 40 { 41 struct airoha_qdma *qdma = irq_bank->qdma; 42 int bank = irq_bank - &qdma->irq_banks[0]; 43 unsigned long flags; 44 45 if (WARN_ON_ONCE(index >= ARRAY_SIZE(irq_bank->irqmask))) 46 return; 47 48 spin_lock_irqsave(&irq_bank->irq_lock, flags); 49 50 irq_bank->irqmask[index] &= ~clear; 51 irq_bank->irqmask[index] |= set; 52 airoha_qdma_wr(qdma, REG_INT_ENABLE(bank, index), 53 irq_bank->irqmask[index]); 54 /* Read irq_enable register in order to guarantee the update above 55 * completes in the spinlock critical section. 56 */ 57 airoha_qdma_rr(qdma, REG_INT_ENABLE(bank, index)); 58 59 spin_unlock_irqrestore(&irq_bank->irq_lock, flags); 60 } 61 62 static void airoha_qdma_irq_enable(struct airoha_irq_bank *irq_bank, 63 int index, u32 mask) 64 { 65 airoha_qdma_set_irqmask(irq_bank, index, 0, mask); 66 } 67 68 static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank, 69 int index, u32 mask) 70 { 71 airoha_qdma_set_irqmask(irq_bank, index, mask, 0); 72 } 73 74 static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr) 75 { 76 struct airoha_eth *eth = port->qdma->eth; 77 u32 val, reg; 78 79 reg = airhoa_is_lan_gdm_port(port) ? REG_FE_LAN_MAC_H 80 : REG_FE_WAN_MAC_H; 81 val = (addr[0] << 16) | (addr[1] << 8) | addr[2]; 82 airoha_fe_wr(eth, reg, val); 83 84 val = (addr[3] << 16) | (addr[4] << 8) | addr[5]; 85 airoha_fe_wr(eth, REG_FE_MAC_LMIN(reg), val); 86 airoha_fe_wr(eth, REG_FE_MAC_LMAX(reg), val); 87 88 airoha_ppe_init_upd_mem(port); 89 } 90 91 static void airoha_set_gdm_port_fwd_cfg(struct airoha_eth *eth, u32 addr, 92 u32 val) 93 { 94 airoha_fe_rmw(eth, addr, GDM_OCFQ_MASK, 95 FIELD_PREP(GDM_OCFQ_MASK, val)); 96 airoha_fe_rmw(eth, addr, GDM_MCFQ_MASK, 97 FIELD_PREP(GDM_MCFQ_MASK, val)); 98 airoha_fe_rmw(eth, addr, GDM_BCFQ_MASK, 99 FIELD_PREP(GDM_BCFQ_MASK, val)); 100 airoha_fe_rmw(eth, addr, GDM_UCFQ_MASK, 101 FIELD_PREP(GDM_UCFQ_MASK, val)); 102 } 103 104 static int airoha_set_vip_for_gdm_port(struct airoha_gdm_port *port, 105 bool enable) 106 { 107 struct airoha_eth *eth = port->qdma->eth; 108 u32 vip_port; 109 110 switch (port->id) { 111 case 3: 112 /* FIXME: handle XSI_PCIE1_PORT */ 113 vip_port = XSI_PCIE0_VIP_PORT_MASK; 114 break; 115 case 4: 116 /* FIXME: handle XSI_USB_PORT */ 117 vip_port = XSI_ETH_VIP_PORT_MASK; 118 break; 119 default: 120 return 0; 121 } 122 123 if (enable) { 124 airoha_fe_set(eth, REG_FE_VIP_PORT_EN, vip_port); 125 airoha_fe_set(eth, REG_FE_IFC_PORT_EN, vip_port); 126 } else { 127 airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, vip_port); 128 airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, vip_port); 129 } 130 131 return 0; 132 } 133 134 static void airoha_fe_maccr_init(struct airoha_eth *eth) 135 { 136 int p; 137 138 for (p = 1; p <= ARRAY_SIZE(eth->ports); p++) 139 airoha_fe_set(eth, REG_GDM_FWD_CFG(p), 140 GDM_TCP_CKSUM | GDM_UDP_CKSUM | GDM_IP4_CKSUM | 141 GDM_DROP_CRC_ERR); 142 143 airoha_fe_rmw(eth, REG_CDM1_VLAN_CTRL, CDM1_VLAN_MASK, 144 FIELD_PREP(CDM1_VLAN_MASK, 0x8100)); 145 146 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PAD); 147 } 148 149 static void airoha_fe_vip_setup(struct airoha_eth *eth) 150 { 151 airoha_fe_wr(eth, REG_FE_VIP_PATN(3), ETH_P_PPP_DISC); 152 airoha_fe_wr(eth, REG_FE_VIP_EN(3), PATN_FCPU_EN_MASK | PATN_EN_MASK); 153 154 airoha_fe_wr(eth, REG_FE_VIP_PATN(4), PPP_LCP); 155 airoha_fe_wr(eth, REG_FE_VIP_EN(4), 156 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 157 PATN_EN_MASK); 158 159 airoha_fe_wr(eth, REG_FE_VIP_PATN(6), PPP_IPCP); 160 airoha_fe_wr(eth, REG_FE_VIP_EN(6), 161 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 162 PATN_EN_MASK); 163 164 airoha_fe_wr(eth, REG_FE_VIP_PATN(7), PPP_CHAP); 165 airoha_fe_wr(eth, REG_FE_VIP_EN(7), 166 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 167 PATN_EN_MASK); 168 169 /* BOOTP (0x43) */ 170 airoha_fe_wr(eth, REG_FE_VIP_PATN(8), 0x43); 171 airoha_fe_wr(eth, REG_FE_VIP_EN(8), 172 PATN_FCPU_EN_MASK | PATN_SP_EN_MASK | 173 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 174 175 /* BOOTP (0x44) */ 176 airoha_fe_wr(eth, REG_FE_VIP_PATN(9), 0x44); 177 airoha_fe_wr(eth, REG_FE_VIP_EN(9), 178 PATN_FCPU_EN_MASK | PATN_SP_EN_MASK | 179 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 180 181 /* ISAKMP */ 182 airoha_fe_wr(eth, REG_FE_VIP_PATN(10), 0x1f401f4); 183 airoha_fe_wr(eth, REG_FE_VIP_EN(10), 184 PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK | 185 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 186 187 airoha_fe_wr(eth, REG_FE_VIP_PATN(11), PPP_IPV6CP); 188 airoha_fe_wr(eth, REG_FE_VIP_EN(11), 189 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 190 PATN_EN_MASK); 191 192 /* DHCPv6 */ 193 airoha_fe_wr(eth, REG_FE_VIP_PATN(12), 0x2220223); 194 airoha_fe_wr(eth, REG_FE_VIP_EN(12), 195 PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK | 196 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 197 198 airoha_fe_wr(eth, REG_FE_VIP_PATN(19), PPP_PAP); 199 airoha_fe_wr(eth, REG_FE_VIP_EN(19), 200 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 201 PATN_EN_MASK); 202 203 /* ETH->ETH_P_1905 (0x893a) */ 204 airoha_fe_wr(eth, REG_FE_VIP_PATN(20), 0x893a); 205 airoha_fe_wr(eth, REG_FE_VIP_EN(20), 206 PATN_FCPU_EN_MASK | PATN_EN_MASK); 207 208 airoha_fe_wr(eth, REG_FE_VIP_PATN(21), ETH_P_LLDP); 209 airoha_fe_wr(eth, REG_FE_VIP_EN(21), 210 PATN_FCPU_EN_MASK | PATN_EN_MASK); 211 } 212 213 static u32 airoha_fe_get_pse_queue_rsv_pages(struct airoha_eth *eth, 214 u32 port, u32 queue) 215 { 216 u32 val; 217 218 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR, 219 PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK, 220 FIELD_PREP(PSE_CFG_PORT_ID_MASK, port) | 221 FIELD_PREP(PSE_CFG_QUEUE_ID_MASK, queue)); 222 val = airoha_fe_rr(eth, REG_FE_PSE_QUEUE_CFG_VAL); 223 224 return FIELD_GET(PSE_CFG_OQ_RSV_MASK, val); 225 } 226 227 static void airoha_fe_set_pse_queue_rsv_pages(struct airoha_eth *eth, 228 u32 port, u32 queue, u32 val) 229 { 230 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_VAL, PSE_CFG_OQ_RSV_MASK, 231 FIELD_PREP(PSE_CFG_OQ_RSV_MASK, val)); 232 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR, 233 PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK | 234 PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK, 235 FIELD_PREP(PSE_CFG_PORT_ID_MASK, port) | 236 FIELD_PREP(PSE_CFG_QUEUE_ID_MASK, queue) | 237 PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK); 238 } 239 240 static u32 airoha_fe_get_pse_all_rsv(struct airoha_eth *eth) 241 { 242 u32 val = airoha_fe_rr(eth, REG_FE_PSE_BUF_SET); 243 244 return FIELD_GET(PSE_ALLRSV_MASK, val); 245 } 246 247 static int airoha_fe_set_pse_oq_rsv(struct airoha_eth *eth, 248 u32 port, u32 queue, u32 val) 249 { 250 u32 orig_val = airoha_fe_get_pse_queue_rsv_pages(eth, port, queue); 251 u32 tmp, all_rsv, fq_limit; 252 253 airoha_fe_set_pse_queue_rsv_pages(eth, port, queue, val); 254 255 /* modify all rsv */ 256 all_rsv = airoha_fe_get_pse_all_rsv(eth); 257 all_rsv += (val - orig_val); 258 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK, 259 FIELD_PREP(PSE_ALLRSV_MASK, all_rsv)); 260 261 /* modify hthd */ 262 tmp = airoha_fe_rr(eth, PSE_FQ_CFG); 263 fq_limit = FIELD_GET(PSE_FQ_LIMIT_MASK, tmp); 264 tmp = fq_limit - all_rsv - 0x20; 265 airoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD, 266 PSE_SHARE_USED_HTHD_MASK, 267 FIELD_PREP(PSE_SHARE_USED_HTHD_MASK, tmp)); 268 269 tmp = fq_limit - all_rsv - 0x100; 270 airoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD, 271 PSE_SHARE_USED_MTHD_MASK, 272 FIELD_PREP(PSE_SHARE_USED_MTHD_MASK, tmp)); 273 tmp = (3 * tmp) >> 2; 274 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, 275 PSE_SHARE_USED_LTHD_MASK, 276 FIELD_PREP(PSE_SHARE_USED_LTHD_MASK, tmp)); 277 278 return 0; 279 } 280 281 static void airoha_fe_pse_ports_init(struct airoha_eth *eth) 282 { 283 const u32 pse_port_num_queues[] = { 284 [FE_PSE_PORT_CDM1] = 6, 285 [FE_PSE_PORT_GDM1] = 6, 286 [FE_PSE_PORT_GDM2] = 32, 287 [FE_PSE_PORT_GDM3] = 6, 288 [FE_PSE_PORT_PPE1] = 4, 289 [FE_PSE_PORT_CDM2] = 6, 290 [FE_PSE_PORT_CDM3] = 8, 291 [FE_PSE_PORT_CDM4] = 10, 292 [FE_PSE_PORT_PPE2] = 4, 293 [FE_PSE_PORT_GDM4] = 2, 294 [FE_PSE_PORT_CDM5] = 2, 295 }; 296 u32 all_rsv; 297 int q; 298 299 all_rsv = airoha_fe_get_pse_all_rsv(eth); 300 /* hw misses PPE2 oq rsv */ 301 all_rsv += PSE_RSV_PAGES * pse_port_num_queues[FE_PSE_PORT_PPE2]; 302 airoha_fe_set(eth, REG_FE_PSE_BUF_SET, all_rsv); 303 304 /* CMD1 */ 305 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM1]; q++) 306 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM1, q, 307 PSE_QUEUE_RSV_PAGES); 308 /* GMD1 */ 309 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM1]; q++) 310 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM1, q, 311 PSE_QUEUE_RSV_PAGES); 312 /* GMD2 */ 313 for (q = 6; q < pse_port_num_queues[FE_PSE_PORT_GDM2]; q++) 314 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM2, q, 0); 315 /* GMD3 */ 316 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM3]; q++) 317 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM3, q, 318 PSE_QUEUE_RSV_PAGES); 319 /* PPE1 */ 320 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE1]; q++) { 321 if (q < pse_port_num_queues[FE_PSE_PORT_PPE1]) 322 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 323 PSE_QUEUE_RSV_PAGES); 324 else 325 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 0); 326 } 327 /* CDM2 */ 328 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM2]; q++) 329 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM2, q, 330 PSE_QUEUE_RSV_PAGES); 331 /* CDM3 */ 332 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM3] - 1; q++) 333 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM3, q, 0); 334 /* CDM4 */ 335 for (q = 4; q < pse_port_num_queues[FE_PSE_PORT_CDM4]; q++) 336 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM4, q, 337 PSE_QUEUE_RSV_PAGES); 338 /* PPE2 */ 339 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE2]; q++) { 340 if (q < pse_port_num_queues[FE_PSE_PORT_PPE2] / 2) 341 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, q, 342 PSE_QUEUE_RSV_PAGES); 343 else 344 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, q, 0); 345 } 346 /* GMD4 */ 347 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM4]; q++) 348 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM4, q, 349 PSE_QUEUE_RSV_PAGES); 350 /* CDM5 */ 351 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM5]; q++) 352 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM5, q, 353 PSE_QUEUE_RSV_PAGES); 354 } 355 356 static int airoha_fe_mc_vlan_clear(struct airoha_eth *eth) 357 { 358 int i; 359 360 for (i = 0; i < AIROHA_FE_MC_MAX_VLAN_TABLE; i++) { 361 int err, j; 362 u32 val; 363 364 airoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0); 365 366 val = FIELD_PREP(MC_VLAN_CFG_TABLE_ID_MASK, i) | 367 MC_VLAN_CFG_TABLE_SEL_MASK | MC_VLAN_CFG_RW_MASK; 368 airoha_fe_wr(eth, REG_MC_VLAN_CFG, val); 369 err = read_poll_timeout(airoha_fe_rr, val, 370 val & MC_VLAN_CFG_CMD_DONE_MASK, 371 USEC_PER_MSEC, 5 * USEC_PER_MSEC, 372 false, eth, REG_MC_VLAN_CFG); 373 if (err) 374 return err; 375 376 for (j = 0; j < AIROHA_FE_MC_MAX_VLAN_PORT; j++) { 377 airoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0); 378 379 val = FIELD_PREP(MC_VLAN_CFG_TABLE_ID_MASK, i) | 380 FIELD_PREP(MC_VLAN_CFG_PORT_ID_MASK, j) | 381 MC_VLAN_CFG_RW_MASK; 382 airoha_fe_wr(eth, REG_MC_VLAN_CFG, val); 383 err = read_poll_timeout(airoha_fe_rr, val, 384 val & MC_VLAN_CFG_CMD_DONE_MASK, 385 USEC_PER_MSEC, 386 5 * USEC_PER_MSEC, false, eth, 387 REG_MC_VLAN_CFG); 388 if (err) 389 return err; 390 } 391 } 392 393 return 0; 394 } 395 396 static void airoha_fe_crsn_qsel_init(struct airoha_eth *eth) 397 { 398 /* CDM1_CRSN_QSEL */ 399 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_22 >> 2), 400 CDM1_CRSN_QSEL_REASON_MASK(CRSN_22), 401 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_22), 402 CDM_CRSN_QSEL_Q1)); 403 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_08 >> 2), 404 CDM1_CRSN_QSEL_REASON_MASK(CRSN_08), 405 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_08), 406 CDM_CRSN_QSEL_Q1)); 407 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_21 >> 2), 408 CDM1_CRSN_QSEL_REASON_MASK(CRSN_21), 409 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_21), 410 CDM_CRSN_QSEL_Q1)); 411 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_24 >> 2), 412 CDM1_CRSN_QSEL_REASON_MASK(CRSN_24), 413 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_24), 414 CDM_CRSN_QSEL_Q6)); 415 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_25 >> 2), 416 CDM1_CRSN_QSEL_REASON_MASK(CRSN_25), 417 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_25), 418 CDM_CRSN_QSEL_Q1)); 419 /* CDM2_CRSN_QSEL */ 420 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_08 >> 2), 421 CDM2_CRSN_QSEL_REASON_MASK(CRSN_08), 422 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_08), 423 CDM_CRSN_QSEL_Q1)); 424 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_21 >> 2), 425 CDM2_CRSN_QSEL_REASON_MASK(CRSN_21), 426 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_21), 427 CDM_CRSN_QSEL_Q1)); 428 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_22 >> 2), 429 CDM2_CRSN_QSEL_REASON_MASK(CRSN_22), 430 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_22), 431 CDM_CRSN_QSEL_Q1)); 432 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_24 >> 2), 433 CDM2_CRSN_QSEL_REASON_MASK(CRSN_24), 434 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_24), 435 CDM_CRSN_QSEL_Q6)); 436 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_25 >> 2), 437 CDM2_CRSN_QSEL_REASON_MASK(CRSN_25), 438 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_25), 439 CDM_CRSN_QSEL_Q1)); 440 } 441 442 static int airoha_fe_init(struct airoha_eth *eth) 443 { 444 airoha_fe_maccr_init(eth); 445 446 /* PSE IQ reserve */ 447 airoha_fe_rmw(eth, REG_PSE_IQ_REV1, PSE_IQ_RES1_P2_MASK, 448 FIELD_PREP(PSE_IQ_RES1_P2_MASK, 0x10)); 449 airoha_fe_rmw(eth, REG_PSE_IQ_REV2, 450 PSE_IQ_RES2_P5_MASK | PSE_IQ_RES2_P4_MASK, 451 FIELD_PREP(PSE_IQ_RES2_P5_MASK, 0x40) | 452 FIELD_PREP(PSE_IQ_RES2_P4_MASK, 0x34)); 453 454 /* enable FE copy engine for MC/KA/DPI */ 455 airoha_fe_wr(eth, REG_FE_PCE_CFG, 456 PCE_DPI_EN_MASK | PCE_KA_EN_MASK | PCE_MC_EN_MASK); 457 /* set vip queue selection to ring 1 */ 458 airoha_fe_rmw(eth, REG_CDM1_FWD_CFG, CDM1_VIP_QSEL_MASK, 459 FIELD_PREP(CDM1_VIP_QSEL_MASK, 0x4)); 460 airoha_fe_rmw(eth, REG_CDM2_FWD_CFG, CDM2_VIP_QSEL_MASK, 461 FIELD_PREP(CDM2_VIP_QSEL_MASK, 0x4)); 462 /* set GDM4 source interface offset to 8 */ 463 airoha_fe_rmw(eth, REG_GDM4_SRC_PORT_SET, 464 GDM4_SPORT_OFF2_MASK | 465 GDM4_SPORT_OFF1_MASK | 466 GDM4_SPORT_OFF0_MASK, 467 FIELD_PREP(GDM4_SPORT_OFF2_MASK, 8) | 468 FIELD_PREP(GDM4_SPORT_OFF1_MASK, 8) | 469 FIELD_PREP(GDM4_SPORT_OFF0_MASK, 8)); 470 471 /* set PSE Page as 128B */ 472 airoha_fe_rmw(eth, REG_FE_DMA_GLO_CFG, 473 FE_DMA_GLO_L2_SPACE_MASK | FE_DMA_GLO_PG_SZ_MASK, 474 FIELD_PREP(FE_DMA_GLO_L2_SPACE_MASK, 2) | 475 FE_DMA_GLO_PG_SZ_MASK); 476 airoha_fe_wr(eth, REG_FE_RST_GLO_CFG, 477 FE_RST_CORE_MASK | FE_RST_GDM3_MBI_ARB_MASK | 478 FE_RST_GDM4_MBI_ARB_MASK); 479 usleep_range(1000, 2000); 480 481 /* connect RxRing1 and RxRing15 to PSE Port0 OQ-1 482 * connect other rings to PSE Port0 OQ-0 483 */ 484 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP0, BIT(4)); 485 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP1, BIT(28)); 486 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP2, BIT(4)); 487 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP3, BIT(28)); 488 489 airoha_fe_vip_setup(eth); 490 airoha_fe_pse_ports_init(eth); 491 492 airoha_fe_set(eth, REG_GDM_MISC_CFG, 493 GDM2_RDM_ACK_WAIT_PREF_MASK | 494 GDM2_CHN_VLD_MODE_MASK); 495 airoha_fe_rmw(eth, REG_CDM2_FWD_CFG, CDM2_OAM_QSEL_MASK, 496 FIELD_PREP(CDM2_OAM_QSEL_MASK, 15)); 497 498 /* init fragment and assemble Force Port */ 499 /* NPU Core-3, NPU Bridge Channel-3 */ 500 airoha_fe_rmw(eth, REG_IP_FRAG_FP, 501 IP_FRAGMENT_PORT_MASK | IP_FRAGMENT_NBQ_MASK, 502 FIELD_PREP(IP_FRAGMENT_PORT_MASK, 6) | 503 FIELD_PREP(IP_FRAGMENT_NBQ_MASK, 3)); 504 /* QDMA LAN, RX Ring-22 */ 505 airoha_fe_rmw(eth, REG_IP_FRAG_FP, 506 IP_ASSEMBLE_PORT_MASK | IP_ASSEMBLE_NBQ_MASK, 507 FIELD_PREP(IP_ASSEMBLE_PORT_MASK, 0) | 508 FIELD_PREP(IP_ASSEMBLE_NBQ_MASK, 22)); 509 510 airoha_fe_set(eth, REG_GDM3_FWD_CFG, GDM3_PAD_EN_MASK); 511 airoha_fe_set(eth, REG_GDM4_FWD_CFG, GDM4_PAD_EN_MASK); 512 513 airoha_fe_crsn_qsel_init(eth); 514 515 airoha_fe_clear(eth, REG_FE_CPORT_CFG, FE_CPORT_QUEUE_XFC_MASK); 516 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PORT_XFC_MASK); 517 518 /* default aging mode for mbi unlock issue */ 519 airoha_fe_rmw(eth, REG_GDM2_CHN_RLS, 520 MBI_RX_AGE_SEL_MASK | MBI_TX_AGE_SEL_MASK, 521 FIELD_PREP(MBI_RX_AGE_SEL_MASK, 3) | 522 FIELD_PREP(MBI_TX_AGE_SEL_MASK, 3)); 523 524 /* disable IFC by default */ 525 airoha_fe_clear(eth, REG_FE_CSR_IFC_CFG, FE_IFC_EN_MASK); 526 527 airoha_fe_wr(eth, REG_PPE_DFT_CPORT0(0), 528 FIELD_PREP(DFT_CPORT_MASK(7), FE_PSE_PORT_CDM1) | 529 FIELD_PREP(DFT_CPORT_MASK(6), FE_PSE_PORT_CDM1) | 530 FIELD_PREP(DFT_CPORT_MASK(5), FE_PSE_PORT_CDM1) | 531 FIELD_PREP(DFT_CPORT_MASK(4), FE_PSE_PORT_CDM1) | 532 FIELD_PREP(DFT_CPORT_MASK(3), FE_PSE_PORT_CDM1) | 533 FIELD_PREP(DFT_CPORT_MASK(2), FE_PSE_PORT_CDM1) | 534 FIELD_PREP(DFT_CPORT_MASK(1), FE_PSE_PORT_CDM1) | 535 FIELD_PREP(DFT_CPORT_MASK(0), FE_PSE_PORT_CDM1)); 536 airoha_fe_wr(eth, REG_PPE_DFT_CPORT0(1), 537 FIELD_PREP(DFT_CPORT_MASK(7), FE_PSE_PORT_CDM2) | 538 FIELD_PREP(DFT_CPORT_MASK(6), FE_PSE_PORT_CDM2) | 539 FIELD_PREP(DFT_CPORT_MASK(5), FE_PSE_PORT_CDM2) | 540 FIELD_PREP(DFT_CPORT_MASK(4), FE_PSE_PORT_CDM2) | 541 FIELD_PREP(DFT_CPORT_MASK(3), FE_PSE_PORT_CDM2) | 542 FIELD_PREP(DFT_CPORT_MASK(2), FE_PSE_PORT_CDM2) | 543 FIELD_PREP(DFT_CPORT_MASK(1), FE_PSE_PORT_CDM2) | 544 FIELD_PREP(DFT_CPORT_MASK(0), FE_PSE_PORT_CDM2)); 545 546 /* enable 1:N vlan action, init vlan table */ 547 airoha_fe_set(eth, REG_MC_VLAN_EN, MC_VLAN_EN_MASK); 548 549 return airoha_fe_mc_vlan_clear(eth); 550 } 551 552 static int airoha_qdma_fill_rx_queue(struct airoha_queue *q) 553 { 554 enum dma_data_direction dir = page_pool_get_dma_dir(q->page_pool); 555 struct airoha_qdma *qdma = q->qdma; 556 struct airoha_eth *eth = qdma->eth; 557 int qid = q - &qdma->q_rx[0]; 558 int nframes = 0; 559 560 while (q->queued < q->ndesc - 1) { 561 struct airoha_queue_entry *e = &q->entry[q->head]; 562 struct airoha_qdma_desc *desc = &q->desc[q->head]; 563 struct page *page; 564 int offset; 565 u32 val; 566 567 page = page_pool_dev_alloc_frag(q->page_pool, &offset, 568 q->buf_size); 569 if (!page) 570 break; 571 572 q->head = (q->head + 1) % q->ndesc; 573 q->queued++; 574 nframes++; 575 576 e->buf = page_address(page) + offset; 577 e->dma_addr = page_pool_get_dma_addr(page) + offset; 578 e->dma_len = SKB_WITH_OVERHEAD(q->buf_size); 579 580 dma_sync_single_for_device(eth->dev, e->dma_addr, e->dma_len, 581 dir); 582 583 val = FIELD_PREP(QDMA_DESC_LEN_MASK, e->dma_len); 584 WRITE_ONCE(desc->ctrl, cpu_to_le32(val)); 585 WRITE_ONCE(desc->addr, cpu_to_le32(e->dma_addr)); 586 val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, q->head); 587 WRITE_ONCE(desc->data, cpu_to_le32(val)); 588 WRITE_ONCE(desc->msg0, 0); 589 WRITE_ONCE(desc->msg1, 0); 590 WRITE_ONCE(desc->msg2, 0); 591 WRITE_ONCE(desc->msg3, 0); 592 593 airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), 594 RX_RING_CPU_IDX_MASK, 595 FIELD_PREP(RX_RING_CPU_IDX_MASK, q->head)); 596 } 597 598 return nframes; 599 } 600 601 static int airoha_qdma_get_gdm_port(struct airoha_eth *eth, 602 struct airoha_qdma_desc *desc) 603 { 604 u32 port, sport, msg1 = le32_to_cpu(desc->msg1); 605 606 sport = FIELD_GET(QDMA_ETH_RXMSG_SPORT_MASK, msg1); 607 switch (sport) { 608 case 0x10 ... 0x14: 609 port = 0; 610 break; 611 case 0x2 ... 0x4: 612 port = sport - 1; 613 break; 614 default: 615 return -EINVAL; 616 } 617 618 return port >= ARRAY_SIZE(eth->ports) ? -EINVAL : port; 619 } 620 621 static int airoha_qdma_rx_process(struct airoha_queue *q, int budget) 622 { 623 enum dma_data_direction dir = page_pool_get_dma_dir(q->page_pool); 624 struct airoha_qdma *qdma = q->qdma; 625 struct airoha_eth *eth = qdma->eth; 626 int qid = q - &qdma->q_rx[0]; 627 int done = 0; 628 629 while (done < budget) { 630 struct airoha_queue_entry *e = &q->entry[q->tail]; 631 struct airoha_qdma_desc *desc = &q->desc[q->tail]; 632 u32 hash, reason, msg1 = le32_to_cpu(desc->msg1); 633 struct page *page = virt_to_head_page(e->buf); 634 u32 desc_ctrl = le32_to_cpu(desc->ctrl); 635 struct airoha_gdm_port *port; 636 int data_len, len, p; 637 638 if (!(desc_ctrl & QDMA_DESC_DONE_MASK)) 639 break; 640 641 q->tail = (q->tail + 1) % q->ndesc; 642 q->queued--; 643 644 dma_sync_single_for_cpu(eth->dev, e->dma_addr, 645 SKB_WITH_OVERHEAD(q->buf_size), dir); 646 647 len = FIELD_GET(QDMA_DESC_LEN_MASK, desc_ctrl); 648 data_len = q->skb ? q->buf_size 649 : SKB_WITH_OVERHEAD(q->buf_size); 650 if (!len || data_len < len) 651 goto free_frag; 652 653 p = airoha_qdma_get_gdm_port(eth, desc); 654 if (p < 0 || !eth->ports[p]) 655 goto free_frag; 656 657 port = eth->ports[p]; 658 if (!q->skb) { /* first buffer */ 659 q->skb = napi_build_skb(e->buf, q->buf_size); 660 if (!q->skb) 661 goto free_frag; 662 663 __skb_put(q->skb, len); 664 skb_mark_for_recycle(q->skb); 665 q->skb->dev = port->dev; 666 q->skb->protocol = eth_type_trans(q->skb, port->dev); 667 q->skb->ip_summed = CHECKSUM_UNNECESSARY; 668 skb_record_rx_queue(q->skb, qid); 669 } else { /* scattered frame */ 670 struct skb_shared_info *shinfo = skb_shinfo(q->skb); 671 int nr_frags = shinfo->nr_frags; 672 673 if (nr_frags >= ARRAY_SIZE(shinfo->frags)) 674 goto free_frag; 675 676 skb_add_rx_frag(q->skb, nr_frags, page, 677 e->buf - page_address(page), len, 678 q->buf_size); 679 } 680 681 if (FIELD_GET(QDMA_DESC_MORE_MASK, desc_ctrl)) 682 continue; 683 684 if (netdev_uses_dsa(port->dev)) { 685 /* PPE module requires untagged packets to work 686 * properly and it provides DSA port index via the 687 * DMA descriptor. Report DSA tag to the DSA stack 688 * via skb dst info. 689 */ 690 u32 sptag = FIELD_GET(QDMA_ETH_RXMSG_SPTAG, 691 le32_to_cpu(desc->msg0)); 692 693 if (sptag < ARRAY_SIZE(port->dsa_meta) && 694 port->dsa_meta[sptag]) 695 skb_dst_set_noref(q->skb, 696 &port->dsa_meta[sptag]->dst); 697 } 698 699 hash = FIELD_GET(AIROHA_RXD4_FOE_ENTRY, msg1); 700 if (hash != AIROHA_RXD4_FOE_ENTRY) 701 skb_set_hash(q->skb, jhash_1word(hash, 0), 702 PKT_HASH_TYPE_L4); 703 704 reason = FIELD_GET(AIROHA_RXD4_PPE_CPU_REASON, msg1); 705 if (reason == PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 706 airoha_ppe_check_skb(eth->ppe, q->skb, hash); 707 708 done++; 709 napi_gro_receive(&q->napi, q->skb); 710 q->skb = NULL; 711 continue; 712 free_frag: 713 if (q->skb) { 714 dev_kfree_skb(q->skb); 715 q->skb = NULL; 716 } else { 717 page_pool_put_full_page(q->page_pool, page, true); 718 } 719 } 720 airoha_qdma_fill_rx_queue(q); 721 722 return done; 723 } 724 725 static int airoha_qdma_rx_napi_poll(struct napi_struct *napi, int budget) 726 { 727 struct airoha_queue *q = container_of(napi, struct airoha_queue, napi); 728 int cur, done = 0; 729 730 do { 731 cur = airoha_qdma_rx_process(q, budget - done); 732 done += cur; 733 } while (cur && done < budget); 734 735 if (done < budget && napi_complete(napi)) { 736 struct airoha_qdma *qdma = q->qdma; 737 int i, qid = q - &qdma->q_rx[0]; 738 int intr_reg = qid < RX_DONE_HIGH_OFFSET ? QDMA_INT_REG_IDX1 739 : QDMA_INT_REG_IDX2; 740 741 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 742 if (!(BIT(qid) & RX_IRQ_BANK_PIN_MASK(i))) 743 continue; 744 745 airoha_qdma_irq_enable(&qdma->irq_banks[i], intr_reg, 746 BIT(qid % RX_DONE_HIGH_OFFSET)); 747 } 748 } 749 750 return done; 751 } 752 753 static int airoha_qdma_init_rx_queue(struct airoha_queue *q, 754 struct airoha_qdma *qdma, int ndesc) 755 { 756 const struct page_pool_params pp_params = { 757 .order = 0, 758 .pool_size = 256, 759 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 760 .dma_dir = DMA_FROM_DEVICE, 761 .max_len = PAGE_SIZE, 762 .nid = NUMA_NO_NODE, 763 .dev = qdma->eth->dev, 764 .napi = &q->napi, 765 }; 766 struct airoha_eth *eth = qdma->eth; 767 int qid = q - &qdma->q_rx[0], thr; 768 dma_addr_t dma_addr; 769 770 q->buf_size = PAGE_SIZE / 2; 771 q->ndesc = ndesc; 772 q->qdma = qdma; 773 774 q->entry = devm_kzalloc(eth->dev, q->ndesc * sizeof(*q->entry), 775 GFP_KERNEL); 776 if (!q->entry) 777 return -ENOMEM; 778 779 q->page_pool = page_pool_create(&pp_params); 780 if (IS_ERR(q->page_pool)) { 781 int err = PTR_ERR(q->page_pool); 782 783 q->page_pool = NULL; 784 return err; 785 } 786 787 q->desc = dmam_alloc_coherent(eth->dev, q->ndesc * sizeof(*q->desc), 788 &dma_addr, GFP_KERNEL); 789 if (!q->desc) 790 return -ENOMEM; 791 792 netif_napi_add(eth->napi_dev, &q->napi, airoha_qdma_rx_napi_poll); 793 794 airoha_qdma_wr(qdma, REG_RX_RING_BASE(qid), dma_addr); 795 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), 796 RX_RING_SIZE_MASK, 797 FIELD_PREP(RX_RING_SIZE_MASK, ndesc)); 798 799 thr = clamp(ndesc >> 3, 1, 32); 800 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), RX_RING_THR_MASK, 801 FIELD_PREP(RX_RING_THR_MASK, thr)); 802 airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK, 803 FIELD_PREP(RX_RING_DMA_IDX_MASK, q->head)); 804 airoha_qdma_set(qdma, REG_RX_SCATTER_CFG(qid), RX_RING_SG_EN_MASK); 805 806 airoha_qdma_fill_rx_queue(q); 807 808 return 0; 809 } 810 811 static void airoha_qdma_cleanup_rx_queue(struct airoha_queue *q) 812 { 813 struct airoha_eth *eth = q->qdma->eth; 814 815 while (q->queued) { 816 struct airoha_queue_entry *e = &q->entry[q->tail]; 817 struct page *page = virt_to_head_page(e->buf); 818 819 dma_sync_single_for_cpu(eth->dev, e->dma_addr, e->dma_len, 820 page_pool_get_dma_dir(q->page_pool)); 821 page_pool_put_full_page(q->page_pool, page, false); 822 q->tail = (q->tail + 1) % q->ndesc; 823 q->queued--; 824 } 825 } 826 827 static int airoha_qdma_init_rx(struct airoha_qdma *qdma) 828 { 829 int i; 830 831 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 832 int err; 833 834 if (!(RX_DONE_INT_MASK & BIT(i))) { 835 /* rx-queue not binded to irq */ 836 continue; 837 } 838 839 err = airoha_qdma_init_rx_queue(&qdma->q_rx[i], qdma, 840 RX_DSCP_NUM(i)); 841 if (err) 842 return err; 843 } 844 845 return 0; 846 } 847 848 static int airoha_qdma_tx_napi_poll(struct napi_struct *napi, int budget) 849 { 850 struct airoha_tx_irq_queue *irq_q; 851 int id, done = 0, irq_queued; 852 struct airoha_qdma *qdma; 853 struct airoha_eth *eth; 854 u32 status, head; 855 856 irq_q = container_of(napi, struct airoha_tx_irq_queue, napi); 857 qdma = irq_q->qdma; 858 id = irq_q - &qdma->q_tx_irq[0]; 859 eth = qdma->eth; 860 861 status = airoha_qdma_rr(qdma, REG_IRQ_STATUS(id)); 862 head = FIELD_GET(IRQ_HEAD_IDX_MASK, status); 863 head = head % irq_q->size; 864 irq_queued = FIELD_GET(IRQ_ENTRY_LEN_MASK, status); 865 866 while (irq_queued > 0 && done < budget) { 867 u32 qid, val = irq_q->q[head]; 868 struct airoha_qdma_desc *desc; 869 struct airoha_queue_entry *e; 870 struct airoha_queue *q; 871 u32 index, desc_ctrl; 872 struct sk_buff *skb; 873 874 if (val == 0xff) 875 break; 876 877 irq_q->q[head] = 0xff; /* mark as done */ 878 head = (head + 1) % irq_q->size; 879 irq_queued--; 880 done++; 881 882 qid = FIELD_GET(IRQ_RING_IDX_MASK, val); 883 if (qid >= ARRAY_SIZE(qdma->q_tx)) 884 continue; 885 886 q = &qdma->q_tx[qid]; 887 if (!q->ndesc) 888 continue; 889 890 index = FIELD_GET(IRQ_DESC_IDX_MASK, val); 891 if (index >= q->ndesc) 892 continue; 893 894 spin_lock_bh(&q->lock); 895 896 if (!q->queued) 897 goto unlock; 898 899 desc = &q->desc[index]; 900 desc_ctrl = le32_to_cpu(desc->ctrl); 901 902 if (!(desc_ctrl & QDMA_DESC_DONE_MASK) && 903 !(desc_ctrl & QDMA_DESC_DROP_MASK)) 904 goto unlock; 905 906 e = &q->entry[index]; 907 skb = e->skb; 908 909 dma_unmap_single(eth->dev, e->dma_addr, e->dma_len, 910 DMA_TO_DEVICE); 911 memset(e, 0, sizeof(*e)); 912 WRITE_ONCE(desc->msg0, 0); 913 WRITE_ONCE(desc->msg1, 0); 914 q->queued--; 915 916 /* completion ring can report out-of-order indexes if hw QoS 917 * is enabled and packets with different priority are queued 918 * to same DMA ring. Take into account possible out-of-order 919 * reports incrementing DMA ring tail pointer 920 */ 921 while (q->tail != q->head && !q->entry[q->tail].dma_addr) 922 q->tail = (q->tail + 1) % q->ndesc; 923 924 if (skb) { 925 u16 queue = skb_get_queue_mapping(skb); 926 struct netdev_queue *txq; 927 928 txq = netdev_get_tx_queue(skb->dev, queue); 929 netdev_tx_completed_queue(txq, 1, skb->len); 930 if (netif_tx_queue_stopped(txq) && 931 q->ndesc - q->queued >= q->free_thr) 932 netif_tx_wake_queue(txq); 933 934 dev_kfree_skb_any(skb); 935 } 936 unlock: 937 spin_unlock_bh(&q->lock); 938 } 939 940 if (done) { 941 int i, len = done >> 7; 942 943 for (i = 0; i < len; i++) 944 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id), 945 IRQ_CLEAR_LEN_MASK, 0x80); 946 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id), 947 IRQ_CLEAR_LEN_MASK, (done & 0x7f)); 948 } 949 950 if (done < budget && napi_complete(napi)) 951 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0, 952 TX_DONE_INT_MASK(id)); 953 954 return done; 955 } 956 957 static int airoha_qdma_init_tx_queue(struct airoha_queue *q, 958 struct airoha_qdma *qdma, int size) 959 { 960 struct airoha_eth *eth = qdma->eth; 961 int i, qid = q - &qdma->q_tx[0]; 962 dma_addr_t dma_addr; 963 964 spin_lock_init(&q->lock); 965 q->ndesc = size; 966 q->qdma = qdma; 967 q->free_thr = 1 + MAX_SKB_FRAGS; 968 969 q->entry = devm_kzalloc(eth->dev, q->ndesc * sizeof(*q->entry), 970 GFP_KERNEL); 971 if (!q->entry) 972 return -ENOMEM; 973 974 q->desc = dmam_alloc_coherent(eth->dev, q->ndesc * sizeof(*q->desc), 975 &dma_addr, GFP_KERNEL); 976 if (!q->desc) 977 return -ENOMEM; 978 979 for (i = 0; i < q->ndesc; i++) { 980 u32 val; 981 982 val = FIELD_PREP(QDMA_DESC_DONE_MASK, 1); 983 WRITE_ONCE(q->desc[i].ctrl, cpu_to_le32(val)); 984 } 985 986 /* xmit ring drop default setting */ 987 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(qid), 988 TX_RING_IRQ_BLOCKING_TX_DROP_EN_MASK); 989 990 airoha_qdma_wr(qdma, REG_TX_RING_BASE(qid), dma_addr); 991 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK, 992 FIELD_PREP(TX_RING_CPU_IDX_MASK, q->head)); 993 airoha_qdma_rmw(qdma, REG_TX_DMA_IDX(qid), TX_RING_DMA_IDX_MASK, 994 FIELD_PREP(TX_RING_DMA_IDX_MASK, q->head)); 995 996 return 0; 997 } 998 999 static int airoha_qdma_tx_irq_init(struct airoha_tx_irq_queue *irq_q, 1000 struct airoha_qdma *qdma, int size) 1001 { 1002 int id = irq_q - &qdma->q_tx_irq[0]; 1003 struct airoha_eth *eth = qdma->eth; 1004 dma_addr_t dma_addr; 1005 1006 netif_napi_add_tx(eth->napi_dev, &irq_q->napi, 1007 airoha_qdma_tx_napi_poll); 1008 irq_q->q = dmam_alloc_coherent(eth->dev, size * sizeof(u32), 1009 &dma_addr, GFP_KERNEL); 1010 if (!irq_q->q) 1011 return -ENOMEM; 1012 1013 memset(irq_q->q, 0xff, size * sizeof(u32)); 1014 irq_q->size = size; 1015 irq_q->qdma = qdma; 1016 1017 airoha_qdma_wr(qdma, REG_TX_IRQ_BASE(id), dma_addr); 1018 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_DEPTH_MASK, 1019 FIELD_PREP(TX_IRQ_DEPTH_MASK, size)); 1020 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_THR_MASK, 1021 FIELD_PREP(TX_IRQ_THR_MASK, 1)); 1022 1023 return 0; 1024 } 1025 1026 static int airoha_qdma_init_tx(struct airoha_qdma *qdma) 1027 { 1028 int i, err; 1029 1030 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) { 1031 err = airoha_qdma_tx_irq_init(&qdma->q_tx_irq[i], qdma, 1032 IRQ_QUEUE_LEN(i)); 1033 if (err) 1034 return err; 1035 } 1036 1037 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1038 err = airoha_qdma_init_tx_queue(&qdma->q_tx[i], qdma, 1039 TX_DSCP_NUM); 1040 if (err) 1041 return err; 1042 } 1043 1044 return 0; 1045 } 1046 1047 static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q) 1048 { 1049 struct airoha_eth *eth = q->qdma->eth; 1050 1051 spin_lock_bh(&q->lock); 1052 while (q->queued) { 1053 struct airoha_queue_entry *e = &q->entry[q->tail]; 1054 1055 dma_unmap_single(eth->dev, e->dma_addr, e->dma_len, 1056 DMA_TO_DEVICE); 1057 dev_kfree_skb_any(e->skb); 1058 e->skb = NULL; 1059 1060 q->tail = (q->tail + 1) % q->ndesc; 1061 q->queued--; 1062 } 1063 spin_unlock_bh(&q->lock); 1064 } 1065 1066 static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma) 1067 { 1068 int size, index, num_desc = HW_DSCP_NUM; 1069 struct airoha_eth *eth = qdma->eth; 1070 int id = qdma - ð->qdma[0]; 1071 u32 status, buf_size; 1072 dma_addr_t dma_addr; 1073 const char *name; 1074 1075 name = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d-buf", id); 1076 if (!name) 1077 return -ENOMEM; 1078 1079 buf_size = id ? AIROHA_MAX_PACKET_SIZE / 2 : AIROHA_MAX_PACKET_SIZE; 1080 index = of_property_match_string(eth->dev->of_node, 1081 "memory-region-names", name); 1082 if (index >= 0) { 1083 struct reserved_mem *rmem; 1084 struct device_node *np; 1085 1086 /* Consume reserved memory for hw forwarding buffers queue if 1087 * available in the DTS 1088 */ 1089 np = of_parse_phandle(eth->dev->of_node, "memory-region", 1090 index); 1091 if (!np) 1092 return -ENODEV; 1093 1094 rmem = of_reserved_mem_lookup(np); 1095 of_node_put(np); 1096 dma_addr = rmem->base; 1097 /* Compute the number of hw descriptors according to the 1098 * reserved memory size and the payload buffer size 1099 */ 1100 num_desc = div_u64(rmem->size, buf_size); 1101 } else { 1102 size = buf_size * num_desc; 1103 if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, 1104 GFP_KERNEL)) 1105 return -ENOMEM; 1106 } 1107 1108 airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr); 1109 1110 size = num_desc * sizeof(struct airoha_qdma_fwd_desc); 1111 if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, GFP_KERNEL)) 1112 return -ENOMEM; 1113 1114 airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr); 1115 /* QDMA0: 2KB. QDMA1: 1KB */ 1116 airoha_qdma_rmw(qdma, REG_HW_FWD_DSCP_CFG, 1117 HW_FWD_DSCP_PAYLOAD_SIZE_MASK, 1118 FIELD_PREP(HW_FWD_DSCP_PAYLOAD_SIZE_MASK, !!id)); 1119 airoha_qdma_rmw(qdma, REG_FWD_DSCP_LOW_THR, FWD_DSCP_LOW_THR_MASK, 1120 FIELD_PREP(FWD_DSCP_LOW_THR_MASK, 128)); 1121 airoha_qdma_rmw(qdma, REG_LMGR_INIT_CFG, 1122 LMGR_INIT_START | LMGR_SRAM_MODE_MASK | 1123 HW_FWD_DESC_NUM_MASK, 1124 FIELD_PREP(HW_FWD_DESC_NUM_MASK, num_desc) | 1125 LMGR_INIT_START | LMGR_SRAM_MODE_MASK); 1126 1127 return read_poll_timeout(airoha_qdma_rr, status, 1128 !(status & LMGR_INIT_START), USEC_PER_MSEC, 1129 30 * USEC_PER_MSEC, true, qdma, 1130 REG_LMGR_INIT_CFG); 1131 } 1132 1133 static void airoha_qdma_init_qos(struct airoha_qdma *qdma) 1134 { 1135 airoha_qdma_clear(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_SCALE_MASK); 1136 airoha_qdma_set(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_BASE_MASK); 1137 1138 airoha_qdma_clear(qdma, REG_PSE_BUF_USAGE_CFG, 1139 PSE_BUF_ESTIMATE_EN_MASK); 1140 1141 airoha_qdma_set(qdma, REG_EGRESS_RATE_METER_CFG, 1142 EGRESS_RATE_METER_EN_MASK | 1143 EGRESS_RATE_METER_EQ_RATE_EN_MASK); 1144 /* 2047us x 31 = 63.457ms */ 1145 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG, 1146 EGRESS_RATE_METER_WINDOW_SZ_MASK, 1147 FIELD_PREP(EGRESS_RATE_METER_WINDOW_SZ_MASK, 0x1f)); 1148 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG, 1149 EGRESS_RATE_METER_TIMESLICE_MASK, 1150 FIELD_PREP(EGRESS_RATE_METER_TIMESLICE_MASK, 0x7ff)); 1151 1152 /* ratelimit init */ 1153 airoha_qdma_set(qdma, REG_GLB_TRTCM_CFG, GLB_TRTCM_EN_MASK); 1154 /* fast-tick 25us */ 1155 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_FAST_TICK_MASK, 1156 FIELD_PREP(GLB_FAST_TICK_MASK, 25)); 1157 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_SLOW_TICK_RATIO_MASK, 1158 FIELD_PREP(GLB_SLOW_TICK_RATIO_MASK, 40)); 1159 1160 airoha_qdma_set(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_TRTCM_EN_MASK); 1161 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_FAST_TICK_MASK, 1162 FIELD_PREP(EGRESS_FAST_TICK_MASK, 25)); 1163 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG, 1164 EGRESS_SLOW_TICK_RATIO_MASK, 1165 FIELD_PREP(EGRESS_SLOW_TICK_RATIO_MASK, 40)); 1166 1167 airoha_qdma_set(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_TRTCM_EN_MASK); 1168 airoha_qdma_clear(qdma, REG_INGRESS_TRTCM_CFG, 1169 INGRESS_TRTCM_MODE_MASK); 1170 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_FAST_TICK_MASK, 1171 FIELD_PREP(INGRESS_FAST_TICK_MASK, 125)); 1172 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG, 1173 INGRESS_SLOW_TICK_RATIO_MASK, 1174 FIELD_PREP(INGRESS_SLOW_TICK_RATIO_MASK, 8)); 1175 1176 airoha_qdma_set(qdma, REG_SLA_TRTCM_CFG, SLA_TRTCM_EN_MASK); 1177 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_FAST_TICK_MASK, 1178 FIELD_PREP(SLA_FAST_TICK_MASK, 25)); 1179 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_SLOW_TICK_RATIO_MASK, 1180 FIELD_PREP(SLA_SLOW_TICK_RATIO_MASK, 40)); 1181 } 1182 1183 static void airoha_qdma_init_qos_stats(struct airoha_qdma *qdma) 1184 { 1185 int i; 1186 1187 for (i = 0; i < AIROHA_NUM_QOS_CHANNELS; i++) { 1188 /* Tx-cpu transferred count */ 1189 airoha_qdma_wr(qdma, REG_CNTR_VAL(i << 1), 0); 1190 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1), 1191 CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK | 1192 CNTR_ALL_DSCP_RING_EN_MASK | 1193 FIELD_PREP(CNTR_CHAN_MASK, i)); 1194 /* Tx-fwd transferred count */ 1195 airoha_qdma_wr(qdma, REG_CNTR_VAL((i << 1) + 1), 0); 1196 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1), 1197 CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK | 1198 CNTR_ALL_DSCP_RING_EN_MASK | 1199 FIELD_PREP(CNTR_SRC_MASK, 1) | 1200 FIELD_PREP(CNTR_CHAN_MASK, i)); 1201 } 1202 } 1203 1204 static int airoha_qdma_hw_init(struct airoha_qdma *qdma) 1205 { 1206 int i; 1207 1208 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 1209 /* clear pending irqs */ 1210 airoha_qdma_wr(qdma, REG_INT_STATUS(i), 0xffffffff); 1211 /* setup rx irqs */ 1212 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX0, 1213 INT_RX0_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1214 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX1, 1215 INT_RX1_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1216 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX2, 1217 INT_RX2_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1218 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX3, 1219 INT_RX3_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1220 } 1221 /* setup tx irqs */ 1222 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0, 1223 TX_COHERENT_LOW_INT_MASK | INT_TX_MASK); 1224 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX4, 1225 TX_COHERENT_HIGH_INT_MASK); 1226 1227 /* setup irq binding */ 1228 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1229 if (!qdma->q_tx[i].ndesc) 1230 continue; 1231 1232 if (TX_RING_IRQ_BLOCKING_MAP_MASK & BIT(i)) 1233 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(i), 1234 TX_RING_IRQ_BLOCKING_CFG_MASK); 1235 else 1236 airoha_qdma_clear(qdma, REG_TX_RING_BLOCKING(i), 1237 TX_RING_IRQ_BLOCKING_CFG_MASK); 1238 } 1239 1240 airoha_qdma_wr(qdma, REG_QDMA_GLOBAL_CFG, 1241 FIELD_PREP(GLOBAL_CFG_DMA_PREFERENCE_MASK, 3) | 1242 GLOBAL_CFG_CPU_TXR_RR_MASK | 1243 GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK | 1244 GLOBAL_CFG_MULTICAST_MODIFY_FP_MASK | 1245 GLOBAL_CFG_MULTICAST_EN_MASK | 1246 GLOBAL_CFG_IRQ0_EN_MASK | GLOBAL_CFG_IRQ1_EN_MASK | 1247 GLOBAL_CFG_TX_WB_DONE_MASK | 1248 FIELD_PREP(GLOBAL_CFG_MAX_ISSUE_NUM_MASK, 2)); 1249 1250 airoha_qdma_init_qos(qdma); 1251 1252 /* disable qdma rx delay interrupt */ 1253 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1254 if (!qdma->q_rx[i].ndesc) 1255 continue; 1256 1257 airoha_qdma_clear(qdma, REG_RX_DELAY_INT_IDX(i), 1258 RX_DELAY_INT_MASK); 1259 } 1260 1261 airoha_qdma_set(qdma, REG_TXQ_CNGST_CFG, 1262 TXQ_CNGST_DROP_EN | TXQ_CNGST_DEI_DROP_EN); 1263 airoha_qdma_init_qos_stats(qdma); 1264 1265 return 0; 1266 } 1267 1268 static irqreturn_t airoha_irq_handler(int irq, void *dev_instance) 1269 { 1270 struct airoha_irq_bank *irq_bank = dev_instance; 1271 struct airoha_qdma *qdma = irq_bank->qdma; 1272 u32 rx_intr_mask = 0, rx_intr1, rx_intr2; 1273 u32 intr[ARRAY_SIZE(irq_bank->irqmask)]; 1274 int i; 1275 1276 for (i = 0; i < ARRAY_SIZE(intr); i++) { 1277 intr[i] = airoha_qdma_rr(qdma, REG_INT_STATUS(i)); 1278 intr[i] &= irq_bank->irqmask[i]; 1279 airoha_qdma_wr(qdma, REG_INT_STATUS(i), intr[i]); 1280 } 1281 1282 if (!test_bit(DEV_STATE_INITIALIZED, &qdma->eth->state)) 1283 return IRQ_NONE; 1284 1285 rx_intr1 = intr[1] & RX_DONE_LOW_INT_MASK; 1286 if (rx_intr1) { 1287 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX1, rx_intr1); 1288 rx_intr_mask |= rx_intr1; 1289 } 1290 1291 rx_intr2 = intr[2] & RX_DONE_HIGH_INT_MASK; 1292 if (rx_intr2) { 1293 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX2, rx_intr2); 1294 rx_intr_mask |= (rx_intr2 << 16); 1295 } 1296 1297 for (i = 0; rx_intr_mask && i < ARRAY_SIZE(qdma->q_rx); i++) { 1298 if (!qdma->q_rx[i].ndesc) 1299 continue; 1300 1301 if (rx_intr_mask & BIT(i)) 1302 napi_schedule(&qdma->q_rx[i].napi); 1303 } 1304 1305 if (intr[0] & INT_TX_MASK) { 1306 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) { 1307 if (!(intr[0] & TX_DONE_INT_MASK(i))) 1308 continue; 1309 1310 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX0, 1311 TX_DONE_INT_MASK(i)); 1312 napi_schedule(&qdma->q_tx_irq[i].napi); 1313 } 1314 } 1315 1316 return IRQ_HANDLED; 1317 } 1318 1319 static int airoha_qdma_init_irq_banks(struct platform_device *pdev, 1320 struct airoha_qdma *qdma) 1321 { 1322 struct airoha_eth *eth = qdma->eth; 1323 int i, id = qdma - ð->qdma[0]; 1324 1325 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 1326 struct airoha_irq_bank *irq_bank = &qdma->irq_banks[i]; 1327 int err, irq_index = 4 * id + i; 1328 const char *name; 1329 1330 spin_lock_init(&irq_bank->irq_lock); 1331 irq_bank->qdma = qdma; 1332 1333 irq_bank->irq = platform_get_irq(pdev, irq_index); 1334 if (irq_bank->irq < 0) 1335 return irq_bank->irq; 1336 1337 name = devm_kasprintf(eth->dev, GFP_KERNEL, 1338 KBUILD_MODNAME ".%d", irq_index); 1339 if (!name) 1340 return -ENOMEM; 1341 1342 err = devm_request_irq(eth->dev, irq_bank->irq, 1343 airoha_irq_handler, IRQF_SHARED, name, 1344 irq_bank); 1345 if (err) 1346 return err; 1347 } 1348 1349 return 0; 1350 } 1351 1352 static int airoha_qdma_init(struct platform_device *pdev, 1353 struct airoha_eth *eth, 1354 struct airoha_qdma *qdma) 1355 { 1356 int err, id = qdma - ð->qdma[0]; 1357 const char *res; 1358 1359 qdma->eth = eth; 1360 res = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d", id); 1361 if (!res) 1362 return -ENOMEM; 1363 1364 qdma->regs = devm_platform_ioremap_resource_byname(pdev, res); 1365 if (IS_ERR(qdma->regs)) 1366 return dev_err_probe(eth->dev, PTR_ERR(qdma->regs), 1367 "failed to iomap qdma%d regs\n", id); 1368 1369 err = airoha_qdma_init_irq_banks(pdev, qdma); 1370 if (err) 1371 return err; 1372 1373 err = airoha_qdma_init_rx(qdma); 1374 if (err) 1375 return err; 1376 1377 err = airoha_qdma_init_tx(qdma); 1378 if (err) 1379 return err; 1380 1381 err = airoha_qdma_init_hfwd_queues(qdma); 1382 if (err) 1383 return err; 1384 1385 return airoha_qdma_hw_init(qdma); 1386 } 1387 1388 static int airoha_hw_init(struct platform_device *pdev, 1389 struct airoha_eth *eth) 1390 { 1391 int err, i; 1392 1393 /* disable xsi */ 1394 err = reset_control_bulk_assert(ARRAY_SIZE(eth->xsi_rsts), 1395 eth->xsi_rsts); 1396 if (err) 1397 return err; 1398 1399 err = reset_control_bulk_assert(ARRAY_SIZE(eth->rsts), eth->rsts); 1400 if (err) 1401 return err; 1402 1403 msleep(20); 1404 err = reset_control_bulk_deassert(ARRAY_SIZE(eth->rsts), eth->rsts); 1405 if (err) 1406 return err; 1407 1408 msleep(20); 1409 err = airoha_fe_init(eth); 1410 if (err) 1411 return err; 1412 1413 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) { 1414 err = airoha_qdma_init(pdev, eth, ð->qdma[i]); 1415 if (err) 1416 return err; 1417 } 1418 1419 err = airoha_ppe_init(eth); 1420 if (err) 1421 return err; 1422 1423 set_bit(DEV_STATE_INITIALIZED, ð->state); 1424 1425 return 0; 1426 } 1427 1428 static void airoha_hw_cleanup(struct airoha_qdma *qdma) 1429 { 1430 int i; 1431 1432 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1433 if (!qdma->q_rx[i].ndesc) 1434 continue; 1435 1436 netif_napi_del(&qdma->q_rx[i].napi); 1437 airoha_qdma_cleanup_rx_queue(&qdma->q_rx[i]); 1438 if (qdma->q_rx[i].page_pool) 1439 page_pool_destroy(qdma->q_rx[i].page_pool); 1440 } 1441 1442 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1443 netif_napi_del(&qdma->q_tx_irq[i].napi); 1444 1445 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1446 if (!qdma->q_tx[i].ndesc) 1447 continue; 1448 1449 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]); 1450 } 1451 } 1452 1453 static void airoha_qdma_start_napi(struct airoha_qdma *qdma) 1454 { 1455 int i; 1456 1457 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1458 napi_enable(&qdma->q_tx_irq[i].napi); 1459 1460 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1461 if (!qdma->q_rx[i].ndesc) 1462 continue; 1463 1464 napi_enable(&qdma->q_rx[i].napi); 1465 } 1466 } 1467 1468 static void airoha_qdma_stop_napi(struct airoha_qdma *qdma) 1469 { 1470 int i; 1471 1472 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1473 napi_disable(&qdma->q_tx_irq[i].napi); 1474 1475 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1476 if (!qdma->q_rx[i].ndesc) 1477 continue; 1478 1479 napi_disable(&qdma->q_rx[i].napi); 1480 } 1481 } 1482 1483 static void airoha_update_hw_stats(struct airoha_gdm_port *port) 1484 { 1485 struct airoha_eth *eth = port->qdma->eth; 1486 u32 val, i = 0; 1487 1488 spin_lock(&port->stats.lock); 1489 u64_stats_update_begin(&port->stats.syncp); 1490 1491 /* TX */ 1492 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_H(port->id)); 1493 port->stats.tx_ok_pkts += ((u64)val << 32); 1494 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_L(port->id)); 1495 port->stats.tx_ok_pkts += val; 1496 1497 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_H(port->id)); 1498 port->stats.tx_ok_bytes += ((u64)val << 32); 1499 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_L(port->id)); 1500 port->stats.tx_ok_bytes += val; 1501 1502 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_DROP_CNT(port->id)); 1503 port->stats.tx_drops += val; 1504 1505 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_BC_CNT(port->id)); 1506 port->stats.tx_broadcast += val; 1507 1508 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_MC_CNT(port->id)); 1509 port->stats.tx_multicast += val; 1510 1511 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_RUNT_CNT(port->id)); 1512 port->stats.tx_len[i] += val; 1513 1514 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_H(port->id)); 1515 port->stats.tx_len[i] += ((u64)val << 32); 1516 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_L(port->id)); 1517 port->stats.tx_len[i++] += val; 1518 1519 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_H(port->id)); 1520 port->stats.tx_len[i] += ((u64)val << 32); 1521 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_L(port->id)); 1522 port->stats.tx_len[i++] += val; 1523 1524 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_H(port->id)); 1525 port->stats.tx_len[i] += ((u64)val << 32); 1526 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_L(port->id)); 1527 port->stats.tx_len[i++] += val; 1528 1529 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_H(port->id)); 1530 port->stats.tx_len[i] += ((u64)val << 32); 1531 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_L(port->id)); 1532 port->stats.tx_len[i++] += val; 1533 1534 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_H(port->id)); 1535 port->stats.tx_len[i] += ((u64)val << 32); 1536 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_L(port->id)); 1537 port->stats.tx_len[i++] += val; 1538 1539 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_H(port->id)); 1540 port->stats.tx_len[i] += ((u64)val << 32); 1541 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_L(port->id)); 1542 port->stats.tx_len[i++] += val; 1543 1544 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_LONG_CNT(port->id)); 1545 port->stats.tx_len[i++] += val; 1546 1547 /* RX */ 1548 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_H(port->id)); 1549 port->stats.rx_ok_pkts += ((u64)val << 32); 1550 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_L(port->id)); 1551 port->stats.rx_ok_pkts += val; 1552 1553 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_H(port->id)); 1554 port->stats.rx_ok_bytes += ((u64)val << 32); 1555 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_L(port->id)); 1556 port->stats.rx_ok_bytes += val; 1557 1558 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_DROP_CNT(port->id)); 1559 port->stats.rx_drops += val; 1560 1561 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_BC_CNT(port->id)); 1562 port->stats.rx_broadcast += val; 1563 1564 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_MC_CNT(port->id)); 1565 port->stats.rx_multicast += val; 1566 1567 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ERROR_DROP_CNT(port->id)); 1568 port->stats.rx_errors += val; 1569 1570 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_CRC_ERR_CNT(port->id)); 1571 port->stats.rx_crc_error += val; 1572 1573 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OVERFLOW_DROP_CNT(port->id)); 1574 port->stats.rx_over_errors += val; 1575 1576 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_FRAG_CNT(port->id)); 1577 port->stats.rx_fragment += val; 1578 1579 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_JABBER_CNT(port->id)); 1580 port->stats.rx_jabber += val; 1581 1582 i = 0; 1583 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_RUNT_CNT(port->id)); 1584 port->stats.rx_len[i] += val; 1585 1586 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_H(port->id)); 1587 port->stats.rx_len[i] += ((u64)val << 32); 1588 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_L(port->id)); 1589 port->stats.rx_len[i++] += val; 1590 1591 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_H(port->id)); 1592 port->stats.rx_len[i] += ((u64)val << 32); 1593 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_L(port->id)); 1594 port->stats.rx_len[i++] += val; 1595 1596 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_H(port->id)); 1597 port->stats.rx_len[i] += ((u64)val << 32); 1598 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_L(port->id)); 1599 port->stats.rx_len[i++] += val; 1600 1601 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_H(port->id)); 1602 port->stats.rx_len[i] += ((u64)val << 32); 1603 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_L(port->id)); 1604 port->stats.rx_len[i++] += val; 1605 1606 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_H(port->id)); 1607 port->stats.rx_len[i] += ((u64)val << 32); 1608 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_L(port->id)); 1609 port->stats.rx_len[i++] += val; 1610 1611 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_H(port->id)); 1612 port->stats.rx_len[i] += ((u64)val << 32); 1613 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_L(port->id)); 1614 port->stats.rx_len[i++] += val; 1615 1616 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_LONG_CNT(port->id)); 1617 port->stats.rx_len[i++] += val; 1618 1619 /* reset mib counters */ 1620 airoha_fe_set(eth, REG_FE_GDM_MIB_CLEAR(port->id), 1621 FE_GDM_MIB_RX_CLEAR_MASK | FE_GDM_MIB_TX_CLEAR_MASK); 1622 1623 u64_stats_update_end(&port->stats.syncp); 1624 spin_unlock(&port->stats.lock); 1625 } 1626 1627 static int airoha_dev_open(struct net_device *dev) 1628 { 1629 int err, len = ETH_HLEN + dev->mtu + ETH_FCS_LEN; 1630 struct airoha_gdm_port *port = netdev_priv(dev); 1631 struct airoha_qdma *qdma = port->qdma; 1632 1633 netif_tx_start_all_queues(dev); 1634 err = airoha_set_vip_for_gdm_port(port, true); 1635 if (err) 1636 return err; 1637 1638 if (netdev_uses_dsa(dev)) 1639 airoha_fe_set(qdma->eth, REG_GDM_INGRESS_CFG(port->id), 1640 GDM_STAG_EN_MASK); 1641 else 1642 airoha_fe_clear(qdma->eth, REG_GDM_INGRESS_CFG(port->id), 1643 GDM_STAG_EN_MASK); 1644 1645 airoha_fe_rmw(qdma->eth, REG_GDM_LEN_CFG(port->id), 1646 GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK, 1647 FIELD_PREP(GDM_SHORT_LEN_MASK, 60) | 1648 FIELD_PREP(GDM_LONG_LEN_MASK, len)); 1649 1650 airoha_qdma_set(qdma, REG_QDMA_GLOBAL_CFG, 1651 GLOBAL_CFG_TX_DMA_EN_MASK | 1652 GLOBAL_CFG_RX_DMA_EN_MASK); 1653 atomic_inc(&qdma->users); 1654 1655 return 0; 1656 } 1657 1658 static int airoha_dev_stop(struct net_device *dev) 1659 { 1660 struct airoha_gdm_port *port = netdev_priv(dev); 1661 struct airoha_qdma *qdma = port->qdma; 1662 int i, err; 1663 1664 netif_tx_disable(dev); 1665 err = airoha_set_vip_for_gdm_port(port, false); 1666 if (err) 1667 return err; 1668 1669 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) 1670 netdev_tx_reset_subqueue(dev, i); 1671 1672 if (atomic_dec_and_test(&qdma->users)) { 1673 airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG, 1674 GLOBAL_CFG_TX_DMA_EN_MASK | 1675 GLOBAL_CFG_RX_DMA_EN_MASK); 1676 1677 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1678 if (!qdma->q_tx[i].ndesc) 1679 continue; 1680 1681 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]); 1682 } 1683 } 1684 1685 return 0; 1686 } 1687 1688 static int airoha_dev_set_macaddr(struct net_device *dev, void *p) 1689 { 1690 struct airoha_gdm_port *port = netdev_priv(dev); 1691 int err; 1692 1693 err = eth_mac_addr(dev, p); 1694 if (err) 1695 return err; 1696 1697 airoha_set_macaddr(port, dev->dev_addr); 1698 1699 return 0; 1700 } 1701 1702 static void airhoha_set_gdm2_loopback(struct airoha_gdm_port *port) 1703 { 1704 u32 pse_port = port->id == 3 ? FE_PSE_PORT_GDM3 : FE_PSE_PORT_GDM4; 1705 struct airoha_eth *eth = port->qdma->eth; 1706 u32 chan = port->id == 3 ? 4 : 0; 1707 1708 /* Forward the traffic to the proper GDM port */ 1709 airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(2), pse_port); 1710 airoha_fe_clear(eth, REG_GDM_FWD_CFG(2), GDM_STRIP_CRC); 1711 1712 /* Enable GDM2 loopback */ 1713 airoha_fe_wr(eth, REG_GDM_TXCHN_EN(2), 0xffffffff); 1714 airoha_fe_wr(eth, REG_GDM_RXCHN_EN(2), 0xffff); 1715 airoha_fe_rmw(eth, REG_GDM_LPBK_CFG(2), 1716 LPBK_CHAN_MASK | LPBK_MODE_MASK | LPBK_EN_MASK, 1717 FIELD_PREP(LPBK_CHAN_MASK, chan) | LPBK_EN_MASK); 1718 airoha_fe_rmw(eth, REG_GDM_LEN_CFG(2), 1719 GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK, 1720 FIELD_PREP(GDM_SHORT_LEN_MASK, 60) | 1721 FIELD_PREP(GDM_LONG_LEN_MASK, AIROHA_MAX_MTU)); 1722 1723 /* Disable VIP and IFC for GDM2 */ 1724 airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, BIT(2)); 1725 airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, BIT(2)); 1726 1727 if (port->id == 3) { 1728 /* FIXME: handle XSI_PCE1_PORT */ 1729 airoha_fe_rmw(eth, REG_FE_WAN_PORT, 1730 WAN1_EN_MASK | WAN1_MASK | WAN0_MASK, 1731 FIELD_PREP(WAN0_MASK, HSGMII_LAN_PCIE0_SRCPORT)); 1732 airoha_fe_rmw(eth, 1733 REG_SP_DFT_CPORT(HSGMII_LAN_PCIE0_SRCPORT >> 3), 1734 SP_CPORT_PCIE0_MASK, 1735 FIELD_PREP(SP_CPORT_PCIE0_MASK, 1736 FE_PSE_PORT_CDM2)); 1737 } else { 1738 /* FIXME: handle XSI_USB_PORT */ 1739 airoha_fe_rmw(eth, REG_SRC_PORT_FC_MAP6, 1740 FC_ID_OF_SRC_PORT24_MASK, 1741 FIELD_PREP(FC_ID_OF_SRC_PORT24_MASK, 2)); 1742 airoha_fe_rmw(eth, REG_FE_WAN_PORT, 1743 WAN1_EN_MASK | WAN1_MASK | WAN0_MASK, 1744 FIELD_PREP(WAN0_MASK, HSGMII_LAN_ETH_SRCPORT)); 1745 airoha_fe_rmw(eth, 1746 REG_SP_DFT_CPORT(HSGMII_LAN_ETH_SRCPORT >> 3), 1747 SP_CPORT_ETH_MASK, 1748 FIELD_PREP(SP_CPORT_ETH_MASK, FE_PSE_PORT_CDM2)); 1749 } 1750 } 1751 1752 static int airoha_dev_init(struct net_device *dev) 1753 { 1754 struct airoha_gdm_port *port = netdev_priv(dev); 1755 struct airoha_eth *eth = port->qdma->eth; 1756 u32 pse_port; 1757 1758 airoha_set_macaddr(port, dev->dev_addr); 1759 1760 switch (port->id) { 1761 case 3: 1762 case 4: 1763 /* If GDM2 is active we can't enable loopback */ 1764 if (!eth->ports[1]) 1765 airhoha_set_gdm2_loopback(port); 1766 fallthrough; 1767 case 2: 1768 pse_port = FE_PSE_PORT_PPE2; 1769 break; 1770 default: 1771 pse_port = FE_PSE_PORT_PPE1; 1772 break; 1773 } 1774 1775 airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(port->id), pse_port); 1776 1777 return 0; 1778 } 1779 1780 static void airoha_dev_get_stats64(struct net_device *dev, 1781 struct rtnl_link_stats64 *storage) 1782 { 1783 struct airoha_gdm_port *port = netdev_priv(dev); 1784 unsigned int start; 1785 1786 airoha_update_hw_stats(port); 1787 do { 1788 start = u64_stats_fetch_begin(&port->stats.syncp); 1789 storage->rx_packets = port->stats.rx_ok_pkts; 1790 storage->tx_packets = port->stats.tx_ok_pkts; 1791 storage->rx_bytes = port->stats.rx_ok_bytes; 1792 storage->tx_bytes = port->stats.tx_ok_bytes; 1793 storage->multicast = port->stats.rx_multicast; 1794 storage->rx_errors = port->stats.rx_errors; 1795 storage->rx_dropped = port->stats.rx_drops; 1796 storage->tx_dropped = port->stats.tx_drops; 1797 storage->rx_crc_errors = port->stats.rx_crc_error; 1798 storage->rx_over_errors = port->stats.rx_over_errors; 1799 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 1800 } 1801 1802 static int airoha_dev_change_mtu(struct net_device *dev, int mtu) 1803 { 1804 struct airoha_gdm_port *port = netdev_priv(dev); 1805 struct airoha_eth *eth = port->qdma->eth; 1806 u32 len = ETH_HLEN + mtu + ETH_FCS_LEN; 1807 1808 airoha_fe_rmw(eth, REG_GDM_LEN_CFG(port->id), 1809 GDM_LONG_LEN_MASK, 1810 FIELD_PREP(GDM_LONG_LEN_MASK, len)); 1811 WRITE_ONCE(dev->mtu, mtu); 1812 1813 return 0; 1814 } 1815 1816 static u16 airoha_dev_select_queue(struct net_device *dev, struct sk_buff *skb, 1817 struct net_device *sb_dev) 1818 { 1819 struct airoha_gdm_port *port = netdev_priv(dev); 1820 int queue, channel; 1821 1822 /* For dsa device select QoS channel according to the dsa user port 1823 * index, rely on port id otherwise. Select QoS queue based on the 1824 * skb priority. 1825 */ 1826 channel = netdev_uses_dsa(dev) ? skb_get_queue_mapping(skb) : port->id; 1827 channel = channel % AIROHA_NUM_QOS_CHANNELS; 1828 queue = (skb->priority - 1) % AIROHA_NUM_QOS_QUEUES; /* QoS queue */ 1829 queue = channel * AIROHA_NUM_QOS_QUEUES + queue; 1830 1831 return queue < dev->num_tx_queues ? queue : 0; 1832 } 1833 1834 static u32 airoha_get_dsa_tag(struct sk_buff *skb, struct net_device *dev) 1835 { 1836 #if IS_ENABLED(CONFIG_NET_DSA) 1837 struct ethhdr *ehdr; 1838 u8 xmit_tpid; 1839 u16 tag; 1840 1841 if (!netdev_uses_dsa(dev)) 1842 return 0; 1843 1844 if (dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK) 1845 return 0; 1846 1847 if (skb_cow_head(skb, 0)) 1848 return 0; 1849 1850 ehdr = (struct ethhdr *)skb->data; 1851 tag = be16_to_cpu(ehdr->h_proto); 1852 xmit_tpid = tag >> 8; 1853 1854 switch (xmit_tpid) { 1855 case MTK_HDR_XMIT_TAGGED_TPID_8100: 1856 ehdr->h_proto = cpu_to_be16(ETH_P_8021Q); 1857 tag &= ~(MTK_HDR_XMIT_TAGGED_TPID_8100 << 8); 1858 break; 1859 case MTK_HDR_XMIT_TAGGED_TPID_88A8: 1860 ehdr->h_proto = cpu_to_be16(ETH_P_8021AD); 1861 tag &= ~(MTK_HDR_XMIT_TAGGED_TPID_88A8 << 8); 1862 break; 1863 default: 1864 /* PPE module requires untagged DSA packets to work properly, 1865 * so move DSA tag to DMA descriptor. 1866 */ 1867 memmove(skb->data + MTK_HDR_LEN, skb->data, 2 * ETH_ALEN); 1868 __skb_pull(skb, MTK_HDR_LEN); 1869 break; 1870 } 1871 1872 return tag; 1873 #else 1874 return 0; 1875 #endif 1876 } 1877 1878 static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb, 1879 struct net_device *dev) 1880 { 1881 struct airoha_gdm_port *port = netdev_priv(dev); 1882 struct airoha_qdma *qdma = port->qdma; 1883 u32 nr_frags, tag, msg0, msg1, len; 1884 struct netdev_queue *txq; 1885 struct airoha_queue *q; 1886 void *data; 1887 int i, qid; 1888 u16 index; 1889 u8 fport; 1890 1891 qid = skb_get_queue_mapping(skb) % ARRAY_SIZE(qdma->q_tx); 1892 tag = airoha_get_dsa_tag(skb, dev); 1893 1894 msg0 = FIELD_PREP(QDMA_ETH_TXMSG_CHAN_MASK, 1895 qid / AIROHA_NUM_QOS_QUEUES) | 1896 FIELD_PREP(QDMA_ETH_TXMSG_QUEUE_MASK, 1897 qid % AIROHA_NUM_QOS_QUEUES) | 1898 FIELD_PREP(QDMA_ETH_TXMSG_SP_TAG_MASK, tag); 1899 if (skb->ip_summed == CHECKSUM_PARTIAL) 1900 msg0 |= FIELD_PREP(QDMA_ETH_TXMSG_TCO_MASK, 1) | 1901 FIELD_PREP(QDMA_ETH_TXMSG_UCO_MASK, 1) | 1902 FIELD_PREP(QDMA_ETH_TXMSG_ICO_MASK, 1); 1903 1904 /* TSO: fill MSS info in tcp checksum field */ 1905 if (skb_is_gso(skb)) { 1906 if (skb_cow_head(skb, 0)) 1907 goto error; 1908 1909 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | 1910 SKB_GSO_TCPV6)) { 1911 __be16 csum = cpu_to_be16(skb_shinfo(skb)->gso_size); 1912 1913 tcp_hdr(skb)->check = (__force __sum16)csum; 1914 msg0 |= FIELD_PREP(QDMA_ETH_TXMSG_TSO_MASK, 1); 1915 } 1916 } 1917 1918 fport = port->id == 4 ? FE_PSE_PORT_GDM4 : port->id; 1919 msg1 = FIELD_PREP(QDMA_ETH_TXMSG_FPORT_MASK, fport) | 1920 FIELD_PREP(QDMA_ETH_TXMSG_METER_MASK, 0x7f); 1921 1922 q = &qdma->q_tx[qid]; 1923 if (WARN_ON_ONCE(!q->ndesc)) 1924 goto error; 1925 1926 spin_lock_bh(&q->lock); 1927 1928 txq = netdev_get_tx_queue(dev, qid); 1929 nr_frags = 1 + skb_shinfo(skb)->nr_frags; 1930 1931 if (q->queued + nr_frags > q->ndesc) { 1932 /* not enough space in the queue */ 1933 netif_tx_stop_queue(txq); 1934 spin_unlock_bh(&q->lock); 1935 return NETDEV_TX_BUSY; 1936 } 1937 1938 len = skb_headlen(skb); 1939 data = skb->data; 1940 index = q->head; 1941 1942 for (i = 0; i < nr_frags; i++) { 1943 struct airoha_qdma_desc *desc = &q->desc[index]; 1944 struct airoha_queue_entry *e = &q->entry[index]; 1945 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1946 dma_addr_t addr; 1947 u32 val; 1948 1949 addr = dma_map_single(dev->dev.parent, data, len, 1950 DMA_TO_DEVICE); 1951 if (unlikely(dma_mapping_error(dev->dev.parent, addr))) 1952 goto error_unmap; 1953 1954 index = (index + 1) % q->ndesc; 1955 1956 val = FIELD_PREP(QDMA_DESC_LEN_MASK, len); 1957 if (i < nr_frags - 1) 1958 val |= FIELD_PREP(QDMA_DESC_MORE_MASK, 1); 1959 WRITE_ONCE(desc->ctrl, cpu_to_le32(val)); 1960 WRITE_ONCE(desc->addr, cpu_to_le32(addr)); 1961 val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, index); 1962 WRITE_ONCE(desc->data, cpu_to_le32(val)); 1963 WRITE_ONCE(desc->msg0, cpu_to_le32(msg0)); 1964 WRITE_ONCE(desc->msg1, cpu_to_le32(msg1)); 1965 WRITE_ONCE(desc->msg2, cpu_to_le32(0xffff)); 1966 1967 e->skb = i ? NULL : skb; 1968 e->dma_addr = addr; 1969 e->dma_len = len; 1970 1971 data = skb_frag_address(frag); 1972 len = skb_frag_size(frag); 1973 } 1974 1975 q->head = index; 1976 q->queued += i; 1977 1978 skb_tx_timestamp(skb); 1979 netdev_tx_sent_queue(txq, skb->len); 1980 1981 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) 1982 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), 1983 TX_RING_CPU_IDX_MASK, 1984 FIELD_PREP(TX_RING_CPU_IDX_MASK, q->head)); 1985 1986 if (q->ndesc - q->queued < q->free_thr) 1987 netif_tx_stop_queue(txq); 1988 1989 spin_unlock_bh(&q->lock); 1990 1991 return NETDEV_TX_OK; 1992 1993 error_unmap: 1994 for (i--; i >= 0; i--) { 1995 index = (q->head + i) % q->ndesc; 1996 dma_unmap_single(dev->dev.parent, q->entry[index].dma_addr, 1997 q->entry[index].dma_len, DMA_TO_DEVICE); 1998 } 1999 2000 spin_unlock_bh(&q->lock); 2001 error: 2002 dev_kfree_skb_any(skb); 2003 dev->stats.tx_dropped++; 2004 2005 return NETDEV_TX_OK; 2006 } 2007 2008 static void airoha_ethtool_get_drvinfo(struct net_device *dev, 2009 struct ethtool_drvinfo *info) 2010 { 2011 struct airoha_gdm_port *port = netdev_priv(dev); 2012 struct airoha_eth *eth = port->qdma->eth; 2013 2014 strscpy(info->driver, eth->dev->driver->name, sizeof(info->driver)); 2015 strscpy(info->bus_info, dev_name(eth->dev), sizeof(info->bus_info)); 2016 } 2017 2018 static void airoha_ethtool_get_mac_stats(struct net_device *dev, 2019 struct ethtool_eth_mac_stats *stats) 2020 { 2021 struct airoha_gdm_port *port = netdev_priv(dev); 2022 unsigned int start; 2023 2024 airoha_update_hw_stats(port); 2025 do { 2026 start = u64_stats_fetch_begin(&port->stats.syncp); 2027 stats->MulticastFramesXmittedOK = port->stats.tx_multicast; 2028 stats->BroadcastFramesXmittedOK = port->stats.tx_broadcast; 2029 stats->BroadcastFramesReceivedOK = port->stats.rx_broadcast; 2030 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 2031 } 2032 2033 static const struct ethtool_rmon_hist_range airoha_ethtool_rmon_ranges[] = { 2034 { 0, 64 }, 2035 { 65, 127 }, 2036 { 128, 255 }, 2037 { 256, 511 }, 2038 { 512, 1023 }, 2039 { 1024, 1518 }, 2040 { 1519, 10239 }, 2041 {}, 2042 }; 2043 2044 static void 2045 airoha_ethtool_get_rmon_stats(struct net_device *dev, 2046 struct ethtool_rmon_stats *stats, 2047 const struct ethtool_rmon_hist_range **ranges) 2048 { 2049 struct airoha_gdm_port *port = netdev_priv(dev); 2050 struct airoha_hw_stats *hw_stats = &port->stats; 2051 unsigned int start; 2052 2053 BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) != 2054 ARRAY_SIZE(hw_stats->tx_len) + 1); 2055 BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) != 2056 ARRAY_SIZE(hw_stats->rx_len) + 1); 2057 2058 *ranges = airoha_ethtool_rmon_ranges; 2059 airoha_update_hw_stats(port); 2060 do { 2061 int i; 2062 2063 start = u64_stats_fetch_begin(&port->stats.syncp); 2064 stats->fragments = hw_stats->rx_fragment; 2065 stats->jabbers = hw_stats->rx_jabber; 2066 for (i = 0; i < ARRAY_SIZE(airoha_ethtool_rmon_ranges) - 1; 2067 i++) { 2068 stats->hist[i] = hw_stats->rx_len[i]; 2069 stats->hist_tx[i] = hw_stats->tx_len[i]; 2070 } 2071 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 2072 } 2073 2074 static int airoha_qdma_set_chan_tx_sched(struct airoha_gdm_port *port, 2075 int channel, enum tx_sched_mode mode, 2076 const u16 *weights, u8 n_weights) 2077 { 2078 int i; 2079 2080 for (i = 0; i < AIROHA_NUM_TX_RING; i++) 2081 airoha_qdma_clear(port->qdma, REG_QUEUE_CLOSE_CFG(channel), 2082 TXQ_DISABLE_CHAN_QUEUE_MASK(channel, i)); 2083 2084 for (i = 0; i < n_weights; i++) { 2085 u32 status; 2086 int err; 2087 2088 airoha_qdma_wr(port->qdma, REG_TXWRR_WEIGHT_CFG, 2089 TWRR_RW_CMD_MASK | 2090 FIELD_PREP(TWRR_CHAN_IDX_MASK, channel) | 2091 FIELD_PREP(TWRR_QUEUE_IDX_MASK, i) | 2092 FIELD_PREP(TWRR_VALUE_MASK, weights[i])); 2093 err = read_poll_timeout(airoha_qdma_rr, status, 2094 status & TWRR_RW_CMD_DONE, 2095 USEC_PER_MSEC, 10 * USEC_PER_MSEC, 2096 true, port->qdma, 2097 REG_TXWRR_WEIGHT_CFG); 2098 if (err) 2099 return err; 2100 } 2101 2102 airoha_qdma_rmw(port->qdma, REG_CHAN_QOS_MODE(channel >> 3), 2103 CHAN_QOS_MODE_MASK(channel), 2104 mode << __ffs(CHAN_QOS_MODE_MASK(channel))); 2105 2106 return 0; 2107 } 2108 2109 static int airoha_qdma_set_tx_prio_sched(struct airoha_gdm_port *port, 2110 int channel) 2111 { 2112 static const u16 w[AIROHA_NUM_QOS_QUEUES] = {}; 2113 2114 return airoha_qdma_set_chan_tx_sched(port, channel, TC_SCH_SP, w, 2115 ARRAY_SIZE(w)); 2116 } 2117 2118 static int airoha_qdma_set_tx_ets_sched(struct airoha_gdm_port *port, 2119 int channel, 2120 struct tc_ets_qopt_offload *opt) 2121 { 2122 struct tc_ets_qopt_offload_replace_params *p = &opt->replace_params; 2123 enum tx_sched_mode mode = TC_SCH_SP; 2124 u16 w[AIROHA_NUM_QOS_QUEUES] = {}; 2125 int i, nstrict = 0; 2126 2127 if (p->bands > AIROHA_NUM_QOS_QUEUES) 2128 return -EINVAL; 2129 2130 for (i = 0; i < p->bands; i++) { 2131 if (!p->quanta[i]) 2132 nstrict++; 2133 } 2134 2135 /* this configuration is not supported by the hw */ 2136 if (nstrict == AIROHA_NUM_QOS_QUEUES - 1) 2137 return -EINVAL; 2138 2139 /* EN7581 SoC supports fixed QoS band priority where WRR queues have 2140 * lowest priorities with respect to SP ones. 2141 * e.g: WRR0, WRR1, .., WRRm, SP0, SP1, .., SPn 2142 */ 2143 for (i = 0; i < nstrict; i++) { 2144 if (p->priomap[p->bands - i - 1] != i) 2145 return -EINVAL; 2146 } 2147 2148 for (i = 0; i < p->bands - nstrict; i++) { 2149 if (p->priomap[i] != nstrict + i) 2150 return -EINVAL; 2151 2152 w[i] = p->weights[nstrict + i]; 2153 } 2154 2155 if (!nstrict) 2156 mode = TC_SCH_WRR8; 2157 else if (nstrict < AIROHA_NUM_QOS_QUEUES - 1) 2158 mode = nstrict + 1; 2159 2160 return airoha_qdma_set_chan_tx_sched(port, channel, mode, w, 2161 ARRAY_SIZE(w)); 2162 } 2163 2164 static int airoha_qdma_get_tx_ets_stats(struct airoha_gdm_port *port, 2165 int channel, 2166 struct tc_ets_qopt_offload *opt) 2167 { 2168 u64 cpu_tx_packets = airoha_qdma_rr(port->qdma, 2169 REG_CNTR_VAL(channel << 1)); 2170 u64 fwd_tx_packets = airoha_qdma_rr(port->qdma, 2171 REG_CNTR_VAL((channel << 1) + 1)); 2172 u64 tx_packets = (cpu_tx_packets - port->cpu_tx_packets) + 2173 (fwd_tx_packets - port->fwd_tx_packets); 2174 _bstats_update(opt->stats.bstats, 0, tx_packets); 2175 2176 port->cpu_tx_packets = cpu_tx_packets; 2177 port->fwd_tx_packets = fwd_tx_packets; 2178 2179 return 0; 2180 } 2181 2182 static int airoha_tc_setup_qdisc_ets(struct airoha_gdm_port *port, 2183 struct tc_ets_qopt_offload *opt) 2184 { 2185 int channel; 2186 2187 if (opt->parent == TC_H_ROOT) 2188 return -EINVAL; 2189 2190 channel = TC_H_MAJ(opt->handle) >> 16; 2191 channel = channel % AIROHA_NUM_QOS_CHANNELS; 2192 2193 switch (opt->command) { 2194 case TC_ETS_REPLACE: 2195 return airoha_qdma_set_tx_ets_sched(port, channel, opt); 2196 case TC_ETS_DESTROY: 2197 /* PRIO is default qdisc scheduler */ 2198 return airoha_qdma_set_tx_prio_sched(port, channel); 2199 case TC_ETS_STATS: 2200 return airoha_qdma_get_tx_ets_stats(port, channel, opt); 2201 default: 2202 return -EOPNOTSUPP; 2203 } 2204 } 2205 2206 static int airoha_qdma_get_rl_param(struct airoha_qdma *qdma, int queue_id, 2207 u32 addr, enum trtcm_param_type param, 2208 u32 *val_low, u32 *val_high) 2209 { 2210 u32 idx = QDMA_METER_IDX(queue_id), group = QDMA_METER_GROUP(queue_id); 2211 u32 val, config = FIELD_PREP(RATE_LIMIT_PARAM_TYPE_MASK, param) | 2212 FIELD_PREP(RATE_LIMIT_METER_GROUP_MASK, group) | 2213 FIELD_PREP(RATE_LIMIT_PARAM_INDEX_MASK, idx); 2214 2215 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2216 if (read_poll_timeout(airoha_qdma_rr, val, 2217 val & RATE_LIMIT_PARAM_RW_DONE_MASK, 2218 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, qdma, 2219 REG_TRTCM_CFG_PARAM(addr))) 2220 return -ETIMEDOUT; 2221 2222 *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr)); 2223 if (val_high) 2224 *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr)); 2225 2226 return 0; 2227 } 2228 2229 static int airoha_qdma_set_rl_param(struct airoha_qdma *qdma, int queue_id, 2230 u32 addr, enum trtcm_param_type param, 2231 u32 val) 2232 { 2233 u32 idx = QDMA_METER_IDX(queue_id), group = QDMA_METER_GROUP(queue_id); 2234 u32 config = RATE_LIMIT_PARAM_RW_MASK | 2235 FIELD_PREP(RATE_LIMIT_PARAM_TYPE_MASK, param) | 2236 FIELD_PREP(RATE_LIMIT_METER_GROUP_MASK, group) | 2237 FIELD_PREP(RATE_LIMIT_PARAM_INDEX_MASK, idx); 2238 2239 airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val); 2240 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2241 2242 return read_poll_timeout(airoha_qdma_rr, val, 2243 val & RATE_LIMIT_PARAM_RW_DONE_MASK, 2244 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2245 qdma, REG_TRTCM_CFG_PARAM(addr)); 2246 } 2247 2248 static int airoha_qdma_set_rl_config(struct airoha_qdma *qdma, int queue_id, 2249 u32 addr, bool enable, u32 enable_mask) 2250 { 2251 u32 val; 2252 int err; 2253 2254 err = airoha_qdma_get_rl_param(qdma, queue_id, addr, TRTCM_MISC_MODE, 2255 &val, NULL); 2256 if (err) 2257 return err; 2258 2259 val = enable ? val | enable_mask : val & ~enable_mask; 2260 2261 return airoha_qdma_set_rl_param(qdma, queue_id, addr, TRTCM_MISC_MODE, 2262 val); 2263 } 2264 2265 static int airoha_qdma_set_rl_token_bucket(struct airoha_qdma *qdma, 2266 int queue_id, u32 rate_val, 2267 u32 bucket_size) 2268 { 2269 u32 val, config, tick, unit, rate, rate_frac; 2270 int err; 2271 2272 err = airoha_qdma_get_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2273 TRTCM_MISC_MODE, &config, NULL); 2274 if (err) 2275 return err; 2276 2277 val = airoha_qdma_rr(qdma, REG_INGRESS_TRTCM_CFG); 2278 tick = FIELD_GET(INGRESS_FAST_TICK_MASK, val); 2279 if (config & TRTCM_TICK_SEL) 2280 tick *= FIELD_GET(INGRESS_SLOW_TICK_RATIO_MASK, val); 2281 if (!tick) 2282 return -EINVAL; 2283 2284 unit = (config & TRTCM_PKT_MODE) ? 1000000 / tick : 8000 / tick; 2285 if (!unit) 2286 return -EINVAL; 2287 2288 rate = rate_val / unit; 2289 rate_frac = rate_val % unit; 2290 rate_frac = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate_frac) / unit; 2291 rate = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate) | 2292 FIELD_PREP(TRTCM_TOKEN_RATE_FRACTION_MASK, rate_frac); 2293 2294 err = airoha_qdma_set_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2295 TRTCM_TOKEN_RATE_MODE, rate); 2296 if (err) 2297 return err; 2298 2299 val = bucket_size; 2300 if (!(config & TRTCM_PKT_MODE)) 2301 val = max_t(u32, val, MIN_TOKEN_SIZE); 2302 val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET); 2303 2304 return airoha_qdma_set_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2305 TRTCM_BUCKETSIZE_SHIFT_MODE, val); 2306 } 2307 2308 static int airoha_qdma_init_rl_config(struct airoha_qdma *qdma, int queue_id, 2309 bool enable, enum trtcm_unit_type unit) 2310 { 2311 bool tick_sel = queue_id == 0 || queue_id == 2 || queue_id == 8; 2312 enum trtcm_param mode = TRTCM_METER_MODE; 2313 int err; 2314 2315 mode |= unit == TRTCM_PACKET_UNIT ? TRTCM_PKT_MODE : 0; 2316 err = airoha_qdma_set_rl_config(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2317 enable, mode); 2318 if (err) 2319 return err; 2320 2321 return airoha_qdma_set_rl_config(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2322 tick_sel, TRTCM_TICK_SEL); 2323 } 2324 2325 static int airoha_qdma_get_trtcm_param(struct airoha_qdma *qdma, int channel, 2326 u32 addr, enum trtcm_param_type param, 2327 enum trtcm_mode_type mode, 2328 u32 *val_low, u32 *val_high) 2329 { 2330 u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel); 2331 u32 val, config = FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) | 2332 FIELD_PREP(TRTCM_METER_GROUP_MASK, group) | 2333 FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) | 2334 FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode); 2335 2336 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2337 if (read_poll_timeout(airoha_qdma_rr, val, 2338 val & TRTCM_PARAM_RW_DONE_MASK, 2339 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2340 qdma, REG_TRTCM_CFG_PARAM(addr))) 2341 return -ETIMEDOUT; 2342 2343 *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr)); 2344 if (val_high) 2345 *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr)); 2346 2347 return 0; 2348 } 2349 2350 static int airoha_qdma_set_trtcm_param(struct airoha_qdma *qdma, int channel, 2351 u32 addr, enum trtcm_param_type param, 2352 enum trtcm_mode_type mode, u32 val) 2353 { 2354 u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel); 2355 u32 config = TRTCM_PARAM_RW_MASK | 2356 FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) | 2357 FIELD_PREP(TRTCM_METER_GROUP_MASK, group) | 2358 FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) | 2359 FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode); 2360 2361 airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val); 2362 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2363 2364 return read_poll_timeout(airoha_qdma_rr, val, 2365 val & TRTCM_PARAM_RW_DONE_MASK, 2366 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2367 qdma, REG_TRTCM_CFG_PARAM(addr)); 2368 } 2369 2370 static int airoha_qdma_set_trtcm_config(struct airoha_qdma *qdma, int channel, 2371 u32 addr, enum trtcm_mode_type mode, 2372 bool enable, u32 enable_mask) 2373 { 2374 u32 val; 2375 2376 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2377 mode, &val, NULL)) 2378 return -EINVAL; 2379 2380 val = enable ? val | enable_mask : val & ~enable_mask; 2381 2382 return airoha_qdma_set_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2383 mode, val); 2384 } 2385 2386 static int airoha_qdma_set_trtcm_token_bucket(struct airoha_qdma *qdma, 2387 int channel, u32 addr, 2388 enum trtcm_mode_type mode, 2389 u32 rate_val, u32 bucket_size) 2390 { 2391 u32 val, config, tick, unit, rate, rate_frac; 2392 int err; 2393 2394 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2395 mode, &config, NULL)) 2396 return -EINVAL; 2397 2398 val = airoha_qdma_rr(qdma, addr); 2399 tick = FIELD_GET(INGRESS_FAST_TICK_MASK, val); 2400 if (config & TRTCM_TICK_SEL) 2401 tick *= FIELD_GET(INGRESS_SLOW_TICK_RATIO_MASK, val); 2402 if (!tick) 2403 return -EINVAL; 2404 2405 unit = (config & TRTCM_PKT_MODE) ? 1000000 / tick : 8000 / tick; 2406 if (!unit) 2407 return -EINVAL; 2408 2409 rate = rate_val / unit; 2410 rate_frac = rate_val % unit; 2411 rate_frac = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate_frac) / unit; 2412 rate = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate) | 2413 FIELD_PREP(TRTCM_TOKEN_RATE_FRACTION_MASK, rate_frac); 2414 2415 err = airoha_qdma_set_trtcm_param(qdma, channel, addr, 2416 TRTCM_TOKEN_RATE_MODE, mode, rate); 2417 if (err) 2418 return err; 2419 2420 val = max_t(u32, bucket_size, MIN_TOKEN_SIZE); 2421 val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET); 2422 2423 return airoha_qdma_set_trtcm_param(qdma, channel, addr, 2424 TRTCM_BUCKETSIZE_SHIFT_MODE, 2425 mode, val); 2426 } 2427 2428 static int airoha_qdma_set_tx_rate_limit(struct airoha_gdm_port *port, 2429 int channel, u32 rate, 2430 u32 bucket_size) 2431 { 2432 int i, err; 2433 2434 for (i = 0; i <= TRTCM_PEAK_MODE; i++) { 2435 err = airoha_qdma_set_trtcm_config(port->qdma, channel, 2436 REG_EGRESS_TRTCM_CFG, i, 2437 !!rate, TRTCM_METER_MODE); 2438 if (err) 2439 return err; 2440 2441 err = airoha_qdma_set_trtcm_token_bucket(port->qdma, channel, 2442 REG_EGRESS_TRTCM_CFG, 2443 i, rate, bucket_size); 2444 if (err) 2445 return err; 2446 } 2447 2448 return 0; 2449 } 2450 2451 static int airoha_tc_htb_alloc_leaf_queue(struct airoha_gdm_port *port, 2452 struct tc_htb_qopt_offload *opt) 2453 { 2454 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2455 u32 rate = div_u64(opt->rate, 1000) << 3; /* kbps */ 2456 struct net_device *dev = port->dev; 2457 int num_tx_queues = dev->real_num_tx_queues; 2458 int err; 2459 2460 if (opt->parent_classid != TC_HTB_CLASSID_ROOT) { 2461 NL_SET_ERR_MSG_MOD(opt->extack, "invalid parent classid"); 2462 return -EINVAL; 2463 } 2464 2465 err = airoha_qdma_set_tx_rate_limit(port, channel, rate, opt->quantum); 2466 if (err) { 2467 NL_SET_ERR_MSG_MOD(opt->extack, 2468 "failed configuring htb offload"); 2469 return err; 2470 } 2471 2472 if (opt->command == TC_HTB_NODE_MODIFY) 2473 return 0; 2474 2475 err = netif_set_real_num_tx_queues(dev, num_tx_queues + 1); 2476 if (err) { 2477 airoha_qdma_set_tx_rate_limit(port, channel, 0, opt->quantum); 2478 NL_SET_ERR_MSG_MOD(opt->extack, 2479 "failed setting real_num_tx_queues"); 2480 return err; 2481 } 2482 2483 set_bit(channel, port->qos_sq_bmap); 2484 opt->qid = AIROHA_NUM_TX_RING + channel; 2485 2486 return 0; 2487 } 2488 2489 static int airoha_qdma_set_rx_meter(struct airoha_gdm_port *port, 2490 u32 rate, u32 bucket_size, 2491 enum trtcm_unit_type unit_type) 2492 { 2493 struct airoha_qdma *qdma = port->qdma; 2494 int i; 2495 2496 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 2497 int err; 2498 2499 if (!qdma->q_rx[i].ndesc) 2500 continue; 2501 2502 err = airoha_qdma_init_rl_config(qdma, i, !!rate, unit_type); 2503 if (err) 2504 return err; 2505 2506 err = airoha_qdma_set_rl_token_bucket(qdma, i, rate, 2507 bucket_size); 2508 if (err) 2509 return err; 2510 } 2511 2512 return 0; 2513 } 2514 2515 static int airoha_tc_matchall_act_validate(struct tc_cls_matchall_offload *f) 2516 { 2517 const struct flow_action *actions = &f->rule->action; 2518 const struct flow_action_entry *act; 2519 2520 if (!flow_action_has_entries(actions)) { 2521 NL_SET_ERR_MSG_MOD(f->common.extack, 2522 "filter run with no actions"); 2523 return -EINVAL; 2524 } 2525 2526 if (!flow_offload_has_one_action(actions)) { 2527 NL_SET_ERR_MSG_MOD(f->common.extack, 2528 "only once action per filter is supported"); 2529 return -EOPNOTSUPP; 2530 } 2531 2532 act = &actions->entries[0]; 2533 if (act->id != FLOW_ACTION_POLICE) { 2534 NL_SET_ERR_MSG_MOD(f->common.extack, "unsupported action"); 2535 return -EOPNOTSUPP; 2536 } 2537 2538 if (act->police.exceed.act_id != FLOW_ACTION_DROP) { 2539 NL_SET_ERR_MSG_MOD(f->common.extack, 2540 "invalid exceed action id"); 2541 return -EOPNOTSUPP; 2542 } 2543 2544 if (act->police.notexceed.act_id != FLOW_ACTION_ACCEPT) { 2545 NL_SET_ERR_MSG_MOD(f->common.extack, 2546 "invalid notexceed action id"); 2547 return -EOPNOTSUPP; 2548 } 2549 2550 if (act->police.notexceed.act_id == FLOW_ACTION_ACCEPT && 2551 !flow_action_is_last_entry(actions, act)) { 2552 NL_SET_ERR_MSG_MOD(f->common.extack, 2553 "action accept must be last"); 2554 return -EOPNOTSUPP; 2555 } 2556 2557 if (act->police.peakrate_bytes_ps || act->police.avrate || 2558 act->police.overhead || act->police.mtu) { 2559 NL_SET_ERR_MSG_MOD(f->common.extack, 2560 "peakrate/avrate/overhead/mtu unsupported"); 2561 return -EOPNOTSUPP; 2562 } 2563 2564 return 0; 2565 } 2566 2567 static int airoha_dev_tc_matchall(struct net_device *dev, 2568 struct tc_cls_matchall_offload *f) 2569 { 2570 enum trtcm_unit_type unit_type = TRTCM_BYTE_UNIT; 2571 struct airoha_gdm_port *port = netdev_priv(dev); 2572 u32 rate = 0, bucket_size = 0; 2573 2574 switch (f->command) { 2575 case TC_CLSMATCHALL_REPLACE: { 2576 const struct flow_action_entry *act; 2577 int err; 2578 2579 err = airoha_tc_matchall_act_validate(f); 2580 if (err) 2581 return err; 2582 2583 act = &f->rule->action.entries[0]; 2584 if (act->police.rate_pkt_ps) { 2585 rate = act->police.rate_pkt_ps; 2586 bucket_size = act->police.burst_pkt; 2587 unit_type = TRTCM_PACKET_UNIT; 2588 } else { 2589 rate = div_u64(act->police.rate_bytes_ps, 1000); 2590 rate = rate << 3; /* Kbps */ 2591 bucket_size = act->police.burst; 2592 } 2593 fallthrough; 2594 } 2595 case TC_CLSMATCHALL_DESTROY: 2596 return airoha_qdma_set_rx_meter(port, rate, bucket_size, 2597 unit_type); 2598 default: 2599 return -EOPNOTSUPP; 2600 } 2601 } 2602 2603 static int airoha_dev_setup_tc_block_cb(enum tc_setup_type type, 2604 void *type_data, void *cb_priv) 2605 { 2606 struct net_device *dev = cb_priv; 2607 2608 if (!tc_can_offload(dev)) 2609 return -EOPNOTSUPP; 2610 2611 switch (type) { 2612 case TC_SETUP_CLSFLOWER: 2613 return airoha_ppe_setup_tc_block_cb(dev, type_data); 2614 case TC_SETUP_CLSMATCHALL: 2615 return airoha_dev_tc_matchall(dev, type_data); 2616 default: 2617 return -EOPNOTSUPP; 2618 } 2619 } 2620 2621 static int airoha_dev_setup_tc_block(struct airoha_gdm_port *port, 2622 struct flow_block_offload *f) 2623 { 2624 flow_setup_cb_t *cb = airoha_dev_setup_tc_block_cb; 2625 static LIST_HEAD(block_cb_list); 2626 struct flow_block_cb *block_cb; 2627 2628 if (f->binder_type != FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 2629 return -EOPNOTSUPP; 2630 2631 f->driver_block_list = &block_cb_list; 2632 switch (f->command) { 2633 case FLOW_BLOCK_BIND: 2634 block_cb = flow_block_cb_lookup(f->block, cb, port->dev); 2635 if (block_cb) { 2636 flow_block_cb_incref(block_cb); 2637 return 0; 2638 } 2639 block_cb = flow_block_cb_alloc(cb, port->dev, port->dev, NULL); 2640 if (IS_ERR(block_cb)) 2641 return PTR_ERR(block_cb); 2642 2643 flow_block_cb_incref(block_cb); 2644 flow_block_cb_add(block_cb, f); 2645 list_add_tail(&block_cb->driver_list, &block_cb_list); 2646 return 0; 2647 case FLOW_BLOCK_UNBIND: 2648 block_cb = flow_block_cb_lookup(f->block, cb, port->dev); 2649 if (!block_cb) 2650 return -ENOENT; 2651 2652 if (!flow_block_cb_decref(block_cb)) { 2653 flow_block_cb_remove(block_cb, f); 2654 list_del(&block_cb->driver_list); 2655 } 2656 return 0; 2657 default: 2658 return -EOPNOTSUPP; 2659 } 2660 } 2661 2662 static void airoha_tc_remove_htb_queue(struct airoha_gdm_port *port, int queue) 2663 { 2664 struct net_device *dev = port->dev; 2665 2666 netif_set_real_num_tx_queues(dev, dev->real_num_tx_queues - 1); 2667 airoha_qdma_set_tx_rate_limit(port, queue + 1, 0, 0); 2668 clear_bit(queue, port->qos_sq_bmap); 2669 } 2670 2671 static int airoha_tc_htb_delete_leaf_queue(struct airoha_gdm_port *port, 2672 struct tc_htb_qopt_offload *opt) 2673 { 2674 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2675 2676 if (!test_bit(channel, port->qos_sq_bmap)) { 2677 NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id"); 2678 return -EINVAL; 2679 } 2680 2681 airoha_tc_remove_htb_queue(port, channel); 2682 2683 return 0; 2684 } 2685 2686 static int airoha_tc_htb_destroy(struct airoha_gdm_port *port) 2687 { 2688 int q; 2689 2690 for_each_set_bit(q, port->qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS) 2691 airoha_tc_remove_htb_queue(port, q); 2692 2693 return 0; 2694 } 2695 2696 static int airoha_tc_get_htb_get_leaf_queue(struct airoha_gdm_port *port, 2697 struct tc_htb_qopt_offload *opt) 2698 { 2699 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2700 2701 if (!test_bit(channel, port->qos_sq_bmap)) { 2702 NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id"); 2703 return -EINVAL; 2704 } 2705 2706 opt->qid = AIROHA_NUM_TX_RING + channel; 2707 2708 return 0; 2709 } 2710 2711 static int airoha_tc_setup_qdisc_htb(struct airoha_gdm_port *port, 2712 struct tc_htb_qopt_offload *opt) 2713 { 2714 switch (opt->command) { 2715 case TC_HTB_CREATE: 2716 break; 2717 case TC_HTB_DESTROY: 2718 return airoha_tc_htb_destroy(port); 2719 case TC_HTB_NODE_MODIFY: 2720 case TC_HTB_LEAF_ALLOC_QUEUE: 2721 return airoha_tc_htb_alloc_leaf_queue(port, opt); 2722 case TC_HTB_LEAF_DEL: 2723 case TC_HTB_LEAF_DEL_LAST: 2724 case TC_HTB_LEAF_DEL_LAST_FORCE: 2725 return airoha_tc_htb_delete_leaf_queue(port, opt); 2726 case TC_HTB_LEAF_QUERY_QUEUE: 2727 return airoha_tc_get_htb_get_leaf_queue(port, opt); 2728 default: 2729 return -EOPNOTSUPP; 2730 } 2731 2732 return 0; 2733 } 2734 2735 static int airoha_dev_tc_setup(struct net_device *dev, enum tc_setup_type type, 2736 void *type_data) 2737 { 2738 struct airoha_gdm_port *port = netdev_priv(dev); 2739 2740 switch (type) { 2741 case TC_SETUP_QDISC_ETS: 2742 return airoha_tc_setup_qdisc_ets(port, type_data); 2743 case TC_SETUP_QDISC_HTB: 2744 return airoha_tc_setup_qdisc_htb(port, type_data); 2745 case TC_SETUP_BLOCK: 2746 case TC_SETUP_FT: 2747 return airoha_dev_setup_tc_block(port, type_data); 2748 default: 2749 return -EOPNOTSUPP; 2750 } 2751 } 2752 2753 static const struct net_device_ops airoha_netdev_ops = { 2754 .ndo_init = airoha_dev_init, 2755 .ndo_open = airoha_dev_open, 2756 .ndo_stop = airoha_dev_stop, 2757 .ndo_change_mtu = airoha_dev_change_mtu, 2758 .ndo_select_queue = airoha_dev_select_queue, 2759 .ndo_start_xmit = airoha_dev_xmit, 2760 .ndo_get_stats64 = airoha_dev_get_stats64, 2761 .ndo_set_mac_address = airoha_dev_set_macaddr, 2762 .ndo_setup_tc = airoha_dev_tc_setup, 2763 }; 2764 2765 static const struct ethtool_ops airoha_ethtool_ops = { 2766 .get_drvinfo = airoha_ethtool_get_drvinfo, 2767 .get_eth_mac_stats = airoha_ethtool_get_mac_stats, 2768 .get_rmon_stats = airoha_ethtool_get_rmon_stats, 2769 }; 2770 2771 static int airoha_metadata_dst_alloc(struct airoha_gdm_port *port) 2772 { 2773 int i; 2774 2775 for (i = 0; i < ARRAY_SIZE(port->dsa_meta); i++) { 2776 struct metadata_dst *md_dst; 2777 2778 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, 2779 GFP_KERNEL); 2780 if (!md_dst) 2781 return -ENOMEM; 2782 2783 md_dst->u.port_info.port_id = i; 2784 port->dsa_meta[i] = md_dst; 2785 } 2786 2787 return 0; 2788 } 2789 2790 static void airoha_metadata_dst_free(struct airoha_gdm_port *port) 2791 { 2792 int i; 2793 2794 for (i = 0; i < ARRAY_SIZE(port->dsa_meta); i++) { 2795 if (!port->dsa_meta[i]) 2796 continue; 2797 2798 metadata_dst_free(port->dsa_meta[i]); 2799 } 2800 } 2801 2802 bool airoha_is_valid_gdm_port(struct airoha_eth *eth, 2803 struct airoha_gdm_port *port) 2804 { 2805 int i; 2806 2807 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 2808 if (eth->ports[i] == port) 2809 return true; 2810 } 2811 2812 return false; 2813 } 2814 2815 static int airoha_alloc_gdm_port(struct airoha_eth *eth, 2816 struct device_node *np, int index) 2817 { 2818 const __be32 *id_ptr = of_get_property(np, "reg", NULL); 2819 struct airoha_gdm_port *port; 2820 struct airoha_qdma *qdma; 2821 struct net_device *dev; 2822 int err, p; 2823 u32 id; 2824 2825 if (!id_ptr) { 2826 dev_err(eth->dev, "missing gdm port id\n"); 2827 return -EINVAL; 2828 } 2829 2830 id = be32_to_cpup(id_ptr); 2831 p = id - 1; 2832 2833 if (!id || id > ARRAY_SIZE(eth->ports)) { 2834 dev_err(eth->dev, "invalid gdm port id: %d\n", id); 2835 return -EINVAL; 2836 } 2837 2838 if (eth->ports[p]) { 2839 dev_err(eth->dev, "duplicate gdm port id: %d\n", id); 2840 return -EINVAL; 2841 } 2842 2843 dev = devm_alloc_etherdev_mqs(eth->dev, sizeof(*port), 2844 AIROHA_NUM_NETDEV_TX_RINGS, 2845 AIROHA_NUM_RX_RING); 2846 if (!dev) { 2847 dev_err(eth->dev, "alloc_etherdev failed\n"); 2848 return -ENOMEM; 2849 } 2850 2851 qdma = ð->qdma[index % AIROHA_MAX_NUM_QDMA]; 2852 dev->netdev_ops = &airoha_netdev_ops; 2853 dev->ethtool_ops = &airoha_ethtool_ops; 2854 dev->max_mtu = AIROHA_MAX_MTU; 2855 dev->watchdog_timeo = 5 * HZ; 2856 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 2857 NETIF_F_TSO6 | NETIF_F_IPV6_CSUM | 2858 NETIF_F_SG | NETIF_F_TSO | 2859 NETIF_F_HW_TC; 2860 dev->features |= dev->hw_features; 2861 dev->vlan_features = dev->hw_features; 2862 dev->dev.of_node = np; 2863 dev->irq = qdma->irq_banks[0].irq; 2864 SET_NETDEV_DEV(dev, eth->dev); 2865 2866 /* reserve hw queues for HTB offloading */ 2867 err = netif_set_real_num_tx_queues(dev, AIROHA_NUM_TX_RING); 2868 if (err) 2869 return err; 2870 2871 err = of_get_ethdev_address(np, dev); 2872 if (err) { 2873 if (err == -EPROBE_DEFER) 2874 return err; 2875 2876 eth_hw_addr_random(dev); 2877 dev_info(eth->dev, "generated random MAC address %pM\n", 2878 dev->dev_addr); 2879 } 2880 2881 port = netdev_priv(dev); 2882 u64_stats_init(&port->stats.syncp); 2883 spin_lock_init(&port->stats.lock); 2884 port->qdma = qdma; 2885 port->dev = dev; 2886 port->id = id; 2887 eth->ports[p] = port; 2888 2889 err = airoha_metadata_dst_alloc(port); 2890 if (err) 2891 return err; 2892 2893 err = register_netdev(dev); 2894 if (err) 2895 goto free_metadata_dst; 2896 2897 return 0; 2898 2899 free_metadata_dst: 2900 airoha_metadata_dst_free(port); 2901 return err; 2902 } 2903 2904 static int airoha_probe(struct platform_device *pdev) 2905 { 2906 struct device_node *np; 2907 struct airoha_eth *eth; 2908 int i, err; 2909 2910 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 2911 if (!eth) 2912 return -ENOMEM; 2913 2914 eth->dev = &pdev->dev; 2915 2916 err = dma_set_mask_and_coherent(eth->dev, DMA_BIT_MASK(32)); 2917 if (err) { 2918 dev_err(eth->dev, "failed configuring DMA mask\n"); 2919 return err; 2920 } 2921 2922 eth->fe_regs = devm_platform_ioremap_resource_byname(pdev, "fe"); 2923 if (IS_ERR(eth->fe_regs)) 2924 return dev_err_probe(eth->dev, PTR_ERR(eth->fe_regs), 2925 "failed to iomap fe regs\n"); 2926 2927 eth->rsts[0].id = "fe"; 2928 eth->rsts[1].id = "pdma"; 2929 eth->rsts[2].id = "qdma"; 2930 err = devm_reset_control_bulk_get_exclusive(eth->dev, 2931 ARRAY_SIZE(eth->rsts), 2932 eth->rsts); 2933 if (err) { 2934 dev_err(eth->dev, "failed to get bulk reset lines\n"); 2935 return err; 2936 } 2937 2938 eth->xsi_rsts[0].id = "xsi-mac"; 2939 eth->xsi_rsts[1].id = "hsi0-mac"; 2940 eth->xsi_rsts[2].id = "hsi1-mac"; 2941 eth->xsi_rsts[3].id = "hsi-mac"; 2942 eth->xsi_rsts[4].id = "xfp-mac"; 2943 err = devm_reset_control_bulk_get_exclusive(eth->dev, 2944 ARRAY_SIZE(eth->xsi_rsts), 2945 eth->xsi_rsts); 2946 if (err) { 2947 dev_err(eth->dev, "failed to get bulk xsi reset lines\n"); 2948 return err; 2949 } 2950 2951 eth->napi_dev = alloc_netdev_dummy(0); 2952 if (!eth->napi_dev) 2953 return -ENOMEM; 2954 2955 /* Enable threaded NAPI by default */ 2956 eth->napi_dev->threaded = true; 2957 strscpy(eth->napi_dev->name, "qdma_eth", sizeof(eth->napi_dev->name)); 2958 platform_set_drvdata(pdev, eth); 2959 2960 err = airoha_hw_init(pdev, eth); 2961 if (err) 2962 goto error_hw_cleanup; 2963 2964 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 2965 airoha_qdma_start_napi(ð->qdma[i]); 2966 2967 i = 0; 2968 for_each_child_of_node(pdev->dev.of_node, np) { 2969 if (!of_device_is_compatible(np, "airoha,eth-mac")) 2970 continue; 2971 2972 if (!of_device_is_available(np)) 2973 continue; 2974 2975 err = airoha_alloc_gdm_port(eth, np, i++); 2976 if (err) { 2977 of_node_put(np); 2978 goto error_napi_stop; 2979 } 2980 } 2981 2982 return 0; 2983 2984 error_napi_stop: 2985 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 2986 airoha_qdma_stop_napi(ð->qdma[i]); 2987 error_hw_cleanup: 2988 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 2989 airoha_hw_cleanup(ð->qdma[i]); 2990 2991 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 2992 struct airoha_gdm_port *port = eth->ports[i]; 2993 2994 if (port && port->dev->reg_state == NETREG_REGISTERED) { 2995 unregister_netdev(port->dev); 2996 airoha_metadata_dst_free(port); 2997 } 2998 } 2999 free_netdev(eth->napi_dev); 3000 platform_set_drvdata(pdev, NULL); 3001 3002 return err; 3003 } 3004 3005 static void airoha_remove(struct platform_device *pdev) 3006 { 3007 struct airoha_eth *eth = platform_get_drvdata(pdev); 3008 int i; 3009 3010 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) { 3011 airoha_qdma_stop_napi(ð->qdma[i]); 3012 airoha_hw_cleanup(ð->qdma[i]); 3013 } 3014 3015 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 3016 struct airoha_gdm_port *port = eth->ports[i]; 3017 3018 if (!port) 3019 continue; 3020 3021 airoha_dev_stop(port->dev); 3022 unregister_netdev(port->dev); 3023 airoha_metadata_dst_free(port); 3024 } 3025 free_netdev(eth->napi_dev); 3026 3027 airoha_ppe_deinit(eth); 3028 platform_set_drvdata(pdev, NULL); 3029 } 3030 3031 static const struct of_device_id of_airoha_match[] = { 3032 { .compatible = "airoha,en7581-eth" }, 3033 { /* sentinel */ } 3034 }; 3035 MODULE_DEVICE_TABLE(of, of_airoha_match); 3036 3037 static struct platform_driver airoha_driver = { 3038 .probe = airoha_probe, 3039 .remove = airoha_remove, 3040 .driver = { 3041 .name = KBUILD_MODNAME, 3042 .of_match_table = of_airoha_match, 3043 }, 3044 }; 3045 module_platform_driver(airoha_driver); 3046 3047 MODULE_LICENSE("GPL"); 3048 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 3049 MODULE_DESCRIPTION("Ethernet driver for Airoha SoC"); 3050