1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024 AIROHA Inc 4 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 5 */ 6 #include <linux/of.h> 7 #include <linux/of_net.h> 8 #include <linux/of_reserved_mem.h> 9 #include <linux/platform_device.h> 10 #include <linux/tcp.h> 11 #include <linux/u64_stats_sync.h> 12 #include <net/dst_metadata.h> 13 #include <net/page_pool/helpers.h> 14 #include <net/pkt_cls.h> 15 #include <uapi/linux/ppp_defs.h> 16 17 #include "airoha_regs.h" 18 #include "airoha_eth.h" 19 20 u32 airoha_rr(void __iomem *base, u32 offset) 21 { 22 return readl(base + offset); 23 } 24 25 void airoha_wr(void __iomem *base, u32 offset, u32 val) 26 { 27 writel(val, base + offset); 28 } 29 30 u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val) 31 { 32 val |= (airoha_rr(base, offset) & ~mask); 33 airoha_wr(base, offset, val); 34 35 return val; 36 } 37 38 static void airoha_qdma_set_irqmask(struct airoha_irq_bank *irq_bank, 39 int index, u32 clear, u32 set) 40 { 41 struct airoha_qdma *qdma = irq_bank->qdma; 42 int bank = irq_bank - &qdma->irq_banks[0]; 43 unsigned long flags; 44 45 if (WARN_ON_ONCE(index >= ARRAY_SIZE(irq_bank->irqmask))) 46 return; 47 48 spin_lock_irqsave(&irq_bank->irq_lock, flags); 49 50 irq_bank->irqmask[index] &= ~clear; 51 irq_bank->irqmask[index] |= set; 52 airoha_qdma_wr(qdma, REG_INT_ENABLE(bank, index), 53 irq_bank->irqmask[index]); 54 /* Read irq_enable register in order to guarantee the update above 55 * completes in the spinlock critical section. 56 */ 57 airoha_qdma_rr(qdma, REG_INT_ENABLE(bank, index)); 58 59 spin_unlock_irqrestore(&irq_bank->irq_lock, flags); 60 } 61 62 static void airoha_qdma_irq_enable(struct airoha_irq_bank *irq_bank, 63 int index, u32 mask) 64 { 65 airoha_qdma_set_irqmask(irq_bank, index, 0, mask); 66 } 67 68 static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank, 69 int index, u32 mask) 70 { 71 airoha_qdma_set_irqmask(irq_bank, index, mask, 0); 72 } 73 74 static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr) 75 { 76 struct airoha_eth *eth = port->qdma->eth; 77 u32 val, reg; 78 79 reg = airhoa_is_lan_gdm_port(port) ? REG_FE_LAN_MAC_H 80 : REG_FE_WAN_MAC_H; 81 val = (addr[0] << 16) | (addr[1] << 8) | addr[2]; 82 airoha_fe_wr(eth, reg, val); 83 84 val = (addr[3] << 16) | (addr[4] << 8) | addr[5]; 85 airoha_fe_wr(eth, REG_FE_MAC_LMIN(reg), val); 86 airoha_fe_wr(eth, REG_FE_MAC_LMAX(reg), val); 87 } 88 89 static void airoha_set_gdm_port_fwd_cfg(struct airoha_eth *eth, u32 addr, 90 u32 val) 91 { 92 airoha_fe_rmw(eth, addr, GDM_OCFQ_MASK, 93 FIELD_PREP(GDM_OCFQ_MASK, val)); 94 airoha_fe_rmw(eth, addr, GDM_MCFQ_MASK, 95 FIELD_PREP(GDM_MCFQ_MASK, val)); 96 airoha_fe_rmw(eth, addr, GDM_BCFQ_MASK, 97 FIELD_PREP(GDM_BCFQ_MASK, val)); 98 airoha_fe_rmw(eth, addr, GDM_UCFQ_MASK, 99 FIELD_PREP(GDM_UCFQ_MASK, val)); 100 } 101 102 static int airoha_set_vip_for_gdm_port(struct airoha_gdm_port *port, 103 bool enable) 104 { 105 struct airoha_eth *eth = port->qdma->eth; 106 u32 vip_port; 107 108 switch (port->id) { 109 case 3: 110 /* FIXME: handle XSI_PCIE1_PORT */ 111 vip_port = XSI_PCIE0_VIP_PORT_MASK; 112 break; 113 case 4: 114 /* FIXME: handle XSI_USB_PORT */ 115 vip_port = XSI_ETH_VIP_PORT_MASK; 116 break; 117 default: 118 return 0; 119 } 120 121 if (enable) { 122 airoha_fe_set(eth, REG_FE_VIP_PORT_EN, vip_port); 123 airoha_fe_set(eth, REG_FE_IFC_PORT_EN, vip_port); 124 } else { 125 airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, vip_port); 126 airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, vip_port); 127 } 128 129 return 0; 130 } 131 132 static void airoha_fe_maccr_init(struct airoha_eth *eth) 133 { 134 int p; 135 136 for (p = 1; p <= ARRAY_SIZE(eth->ports); p++) 137 airoha_fe_set(eth, REG_GDM_FWD_CFG(p), 138 GDM_TCP_CKSUM | GDM_UDP_CKSUM | GDM_IP4_CKSUM | 139 GDM_DROP_CRC_ERR); 140 141 airoha_fe_rmw(eth, REG_CDM1_VLAN_CTRL, CDM1_VLAN_MASK, 142 FIELD_PREP(CDM1_VLAN_MASK, 0x8100)); 143 144 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PAD); 145 } 146 147 static void airoha_fe_vip_setup(struct airoha_eth *eth) 148 { 149 airoha_fe_wr(eth, REG_FE_VIP_PATN(3), ETH_P_PPP_DISC); 150 airoha_fe_wr(eth, REG_FE_VIP_EN(3), PATN_FCPU_EN_MASK | PATN_EN_MASK); 151 152 airoha_fe_wr(eth, REG_FE_VIP_PATN(4), PPP_LCP); 153 airoha_fe_wr(eth, REG_FE_VIP_EN(4), 154 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 155 PATN_EN_MASK); 156 157 airoha_fe_wr(eth, REG_FE_VIP_PATN(6), PPP_IPCP); 158 airoha_fe_wr(eth, REG_FE_VIP_EN(6), 159 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 160 PATN_EN_MASK); 161 162 airoha_fe_wr(eth, REG_FE_VIP_PATN(7), PPP_CHAP); 163 airoha_fe_wr(eth, REG_FE_VIP_EN(7), 164 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 165 PATN_EN_MASK); 166 167 /* BOOTP (0x43) */ 168 airoha_fe_wr(eth, REG_FE_VIP_PATN(8), 0x43); 169 airoha_fe_wr(eth, REG_FE_VIP_EN(8), 170 PATN_FCPU_EN_MASK | PATN_SP_EN_MASK | 171 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 172 173 /* BOOTP (0x44) */ 174 airoha_fe_wr(eth, REG_FE_VIP_PATN(9), 0x44); 175 airoha_fe_wr(eth, REG_FE_VIP_EN(9), 176 PATN_FCPU_EN_MASK | PATN_SP_EN_MASK | 177 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 178 179 /* ISAKMP */ 180 airoha_fe_wr(eth, REG_FE_VIP_PATN(10), 0x1f401f4); 181 airoha_fe_wr(eth, REG_FE_VIP_EN(10), 182 PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK | 183 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 184 185 airoha_fe_wr(eth, REG_FE_VIP_PATN(11), PPP_IPV6CP); 186 airoha_fe_wr(eth, REG_FE_VIP_EN(11), 187 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 188 PATN_EN_MASK); 189 190 /* DHCPv6 */ 191 airoha_fe_wr(eth, REG_FE_VIP_PATN(12), 0x2220223); 192 airoha_fe_wr(eth, REG_FE_VIP_EN(12), 193 PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK | 194 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 195 196 airoha_fe_wr(eth, REG_FE_VIP_PATN(19), PPP_PAP); 197 airoha_fe_wr(eth, REG_FE_VIP_EN(19), 198 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 199 PATN_EN_MASK); 200 201 /* ETH->ETH_P_1905 (0x893a) */ 202 airoha_fe_wr(eth, REG_FE_VIP_PATN(20), 0x893a); 203 airoha_fe_wr(eth, REG_FE_VIP_EN(20), 204 PATN_FCPU_EN_MASK | PATN_EN_MASK); 205 206 airoha_fe_wr(eth, REG_FE_VIP_PATN(21), ETH_P_LLDP); 207 airoha_fe_wr(eth, REG_FE_VIP_EN(21), 208 PATN_FCPU_EN_MASK | PATN_EN_MASK); 209 } 210 211 static u32 airoha_fe_get_pse_queue_rsv_pages(struct airoha_eth *eth, 212 u32 port, u32 queue) 213 { 214 u32 val; 215 216 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR, 217 PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK, 218 FIELD_PREP(PSE_CFG_PORT_ID_MASK, port) | 219 FIELD_PREP(PSE_CFG_QUEUE_ID_MASK, queue)); 220 val = airoha_fe_rr(eth, REG_FE_PSE_QUEUE_CFG_VAL); 221 222 return FIELD_GET(PSE_CFG_OQ_RSV_MASK, val); 223 } 224 225 static void airoha_fe_set_pse_queue_rsv_pages(struct airoha_eth *eth, 226 u32 port, u32 queue, u32 val) 227 { 228 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_VAL, PSE_CFG_OQ_RSV_MASK, 229 FIELD_PREP(PSE_CFG_OQ_RSV_MASK, val)); 230 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR, 231 PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK | 232 PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK, 233 FIELD_PREP(PSE_CFG_PORT_ID_MASK, port) | 234 FIELD_PREP(PSE_CFG_QUEUE_ID_MASK, queue) | 235 PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK); 236 } 237 238 static u32 airoha_fe_get_pse_all_rsv(struct airoha_eth *eth) 239 { 240 u32 val = airoha_fe_rr(eth, REG_FE_PSE_BUF_SET); 241 242 return FIELD_GET(PSE_ALLRSV_MASK, val); 243 } 244 245 static int airoha_fe_set_pse_oq_rsv(struct airoha_eth *eth, 246 u32 port, u32 queue, u32 val) 247 { 248 u32 orig_val = airoha_fe_get_pse_queue_rsv_pages(eth, port, queue); 249 u32 tmp, all_rsv, fq_limit; 250 251 airoha_fe_set_pse_queue_rsv_pages(eth, port, queue, val); 252 253 /* modify all rsv */ 254 all_rsv = airoha_fe_get_pse_all_rsv(eth); 255 all_rsv += (val - orig_val); 256 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK, 257 FIELD_PREP(PSE_ALLRSV_MASK, all_rsv)); 258 259 /* modify hthd */ 260 tmp = airoha_fe_rr(eth, PSE_FQ_CFG); 261 fq_limit = FIELD_GET(PSE_FQ_LIMIT_MASK, tmp); 262 tmp = fq_limit - all_rsv - 0x20; 263 airoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD, 264 PSE_SHARE_USED_HTHD_MASK, 265 FIELD_PREP(PSE_SHARE_USED_HTHD_MASK, tmp)); 266 267 tmp = fq_limit - all_rsv - 0x100; 268 airoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD, 269 PSE_SHARE_USED_MTHD_MASK, 270 FIELD_PREP(PSE_SHARE_USED_MTHD_MASK, tmp)); 271 tmp = (3 * tmp) >> 2; 272 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, 273 PSE_SHARE_USED_LTHD_MASK, 274 FIELD_PREP(PSE_SHARE_USED_LTHD_MASK, tmp)); 275 276 return 0; 277 } 278 279 static void airoha_fe_pse_ports_init(struct airoha_eth *eth) 280 { 281 const u32 pse_port_num_queues[] = { 282 [FE_PSE_PORT_CDM1] = 6, 283 [FE_PSE_PORT_GDM1] = 6, 284 [FE_PSE_PORT_GDM2] = 32, 285 [FE_PSE_PORT_GDM3] = 6, 286 [FE_PSE_PORT_PPE1] = 4, 287 [FE_PSE_PORT_CDM2] = 6, 288 [FE_PSE_PORT_CDM3] = 8, 289 [FE_PSE_PORT_CDM4] = 10, 290 [FE_PSE_PORT_PPE2] = 4, 291 [FE_PSE_PORT_GDM4] = 2, 292 [FE_PSE_PORT_CDM5] = 2, 293 }; 294 u32 all_rsv; 295 int q; 296 297 all_rsv = airoha_fe_get_pse_all_rsv(eth); 298 /* hw misses PPE2 oq rsv */ 299 all_rsv += PSE_RSV_PAGES * pse_port_num_queues[FE_PSE_PORT_PPE2]; 300 airoha_fe_set(eth, REG_FE_PSE_BUF_SET, all_rsv); 301 302 /* CMD1 */ 303 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM1]; q++) 304 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM1, q, 305 PSE_QUEUE_RSV_PAGES); 306 /* GMD1 */ 307 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM1]; q++) 308 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM1, q, 309 PSE_QUEUE_RSV_PAGES); 310 /* GMD2 */ 311 for (q = 6; q < pse_port_num_queues[FE_PSE_PORT_GDM2]; q++) 312 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM2, q, 0); 313 /* GMD3 */ 314 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM3]; q++) 315 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM3, q, 316 PSE_QUEUE_RSV_PAGES); 317 /* PPE1 */ 318 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE1]; q++) { 319 if (q < pse_port_num_queues[FE_PSE_PORT_PPE1]) 320 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 321 PSE_QUEUE_RSV_PAGES); 322 else 323 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 0); 324 } 325 /* CDM2 */ 326 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM2]; q++) 327 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM2, q, 328 PSE_QUEUE_RSV_PAGES); 329 /* CDM3 */ 330 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM3] - 1; q++) 331 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM3, q, 0); 332 /* CDM4 */ 333 for (q = 4; q < pse_port_num_queues[FE_PSE_PORT_CDM4]; q++) 334 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM4, q, 335 PSE_QUEUE_RSV_PAGES); 336 /* PPE2 */ 337 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE2]; q++) { 338 if (q < pse_port_num_queues[FE_PSE_PORT_PPE2] / 2) 339 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, q, 340 PSE_QUEUE_RSV_PAGES); 341 else 342 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, q, 0); 343 } 344 /* GMD4 */ 345 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM4]; q++) 346 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM4, q, 347 PSE_QUEUE_RSV_PAGES); 348 /* CDM5 */ 349 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM5]; q++) 350 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM5, q, 351 PSE_QUEUE_RSV_PAGES); 352 } 353 354 static int airoha_fe_mc_vlan_clear(struct airoha_eth *eth) 355 { 356 int i; 357 358 for (i = 0; i < AIROHA_FE_MC_MAX_VLAN_TABLE; i++) { 359 int err, j; 360 u32 val; 361 362 airoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0); 363 364 val = FIELD_PREP(MC_VLAN_CFG_TABLE_ID_MASK, i) | 365 MC_VLAN_CFG_TABLE_SEL_MASK | MC_VLAN_CFG_RW_MASK; 366 airoha_fe_wr(eth, REG_MC_VLAN_CFG, val); 367 err = read_poll_timeout(airoha_fe_rr, val, 368 val & MC_VLAN_CFG_CMD_DONE_MASK, 369 USEC_PER_MSEC, 5 * USEC_PER_MSEC, 370 false, eth, REG_MC_VLAN_CFG); 371 if (err) 372 return err; 373 374 for (j = 0; j < AIROHA_FE_MC_MAX_VLAN_PORT; j++) { 375 airoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0); 376 377 val = FIELD_PREP(MC_VLAN_CFG_TABLE_ID_MASK, i) | 378 FIELD_PREP(MC_VLAN_CFG_PORT_ID_MASK, j) | 379 MC_VLAN_CFG_RW_MASK; 380 airoha_fe_wr(eth, REG_MC_VLAN_CFG, val); 381 err = read_poll_timeout(airoha_fe_rr, val, 382 val & MC_VLAN_CFG_CMD_DONE_MASK, 383 USEC_PER_MSEC, 384 5 * USEC_PER_MSEC, false, eth, 385 REG_MC_VLAN_CFG); 386 if (err) 387 return err; 388 } 389 } 390 391 return 0; 392 } 393 394 static void airoha_fe_crsn_qsel_init(struct airoha_eth *eth) 395 { 396 /* CDM1_CRSN_QSEL */ 397 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_22 >> 2), 398 CDM1_CRSN_QSEL_REASON_MASK(CRSN_22), 399 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_22), 400 CDM_CRSN_QSEL_Q1)); 401 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_08 >> 2), 402 CDM1_CRSN_QSEL_REASON_MASK(CRSN_08), 403 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_08), 404 CDM_CRSN_QSEL_Q1)); 405 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_21 >> 2), 406 CDM1_CRSN_QSEL_REASON_MASK(CRSN_21), 407 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_21), 408 CDM_CRSN_QSEL_Q1)); 409 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_24 >> 2), 410 CDM1_CRSN_QSEL_REASON_MASK(CRSN_24), 411 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_24), 412 CDM_CRSN_QSEL_Q6)); 413 airoha_fe_rmw(eth, REG_CDM1_CRSN_QSEL(CRSN_25 >> 2), 414 CDM1_CRSN_QSEL_REASON_MASK(CRSN_25), 415 FIELD_PREP(CDM1_CRSN_QSEL_REASON_MASK(CRSN_25), 416 CDM_CRSN_QSEL_Q1)); 417 /* CDM2_CRSN_QSEL */ 418 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_08 >> 2), 419 CDM2_CRSN_QSEL_REASON_MASK(CRSN_08), 420 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_08), 421 CDM_CRSN_QSEL_Q1)); 422 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_21 >> 2), 423 CDM2_CRSN_QSEL_REASON_MASK(CRSN_21), 424 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_21), 425 CDM_CRSN_QSEL_Q1)); 426 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_22 >> 2), 427 CDM2_CRSN_QSEL_REASON_MASK(CRSN_22), 428 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_22), 429 CDM_CRSN_QSEL_Q1)); 430 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_24 >> 2), 431 CDM2_CRSN_QSEL_REASON_MASK(CRSN_24), 432 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_24), 433 CDM_CRSN_QSEL_Q6)); 434 airoha_fe_rmw(eth, REG_CDM2_CRSN_QSEL(CRSN_25 >> 2), 435 CDM2_CRSN_QSEL_REASON_MASK(CRSN_25), 436 FIELD_PREP(CDM2_CRSN_QSEL_REASON_MASK(CRSN_25), 437 CDM_CRSN_QSEL_Q1)); 438 } 439 440 static int airoha_fe_init(struct airoha_eth *eth) 441 { 442 airoha_fe_maccr_init(eth); 443 444 /* PSE IQ reserve */ 445 airoha_fe_rmw(eth, REG_PSE_IQ_REV1, PSE_IQ_RES1_P2_MASK, 446 FIELD_PREP(PSE_IQ_RES1_P2_MASK, 0x10)); 447 airoha_fe_rmw(eth, REG_PSE_IQ_REV2, 448 PSE_IQ_RES2_P5_MASK | PSE_IQ_RES2_P4_MASK, 449 FIELD_PREP(PSE_IQ_RES2_P5_MASK, 0x40) | 450 FIELD_PREP(PSE_IQ_RES2_P4_MASK, 0x34)); 451 452 /* enable FE copy engine for MC/KA/DPI */ 453 airoha_fe_wr(eth, REG_FE_PCE_CFG, 454 PCE_DPI_EN_MASK | PCE_KA_EN_MASK | PCE_MC_EN_MASK); 455 /* set vip queue selection to ring 1 */ 456 airoha_fe_rmw(eth, REG_CDM1_FWD_CFG, CDM1_VIP_QSEL_MASK, 457 FIELD_PREP(CDM1_VIP_QSEL_MASK, 0x4)); 458 airoha_fe_rmw(eth, REG_CDM2_FWD_CFG, CDM2_VIP_QSEL_MASK, 459 FIELD_PREP(CDM2_VIP_QSEL_MASK, 0x4)); 460 /* set GDM4 source interface offset to 8 */ 461 airoha_fe_rmw(eth, REG_GDM4_SRC_PORT_SET, 462 GDM4_SPORT_OFF2_MASK | 463 GDM4_SPORT_OFF1_MASK | 464 GDM4_SPORT_OFF0_MASK, 465 FIELD_PREP(GDM4_SPORT_OFF2_MASK, 8) | 466 FIELD_PREP(GDM4_SPORT_OFF1_MASK, 8) | 467 FIELD_PREP(GDM4_SPORT_OFF0_MASK, 8)); 468 469 /* set PSE Page as 128B */ 470 airoha_fe_rmw(eth, REG_FE_DMA_GLO_CFG, 471 FE_DMA_GLO_L2_SPACE_MASK | FE_DMA_GLO_PG_SZ_MASK, 472 FIELD_PREP(FE_DMA_GLO_L2_SPACE_MASK, 2) | 473 FE_DMA_GLO_PG_SZ_MASK); 474 airoha_fe_wr(eth, REG_FE_RST_GLO_CFG, 475 FE_RST_CORE_MASK | FE_RST_GDM3_MBI_ARB_MASK | 476 FE_RST_GDM4_MBI_ARB_MASK); 477 usleep_range(1000, 2000); 478 479 /* connect RxRing1 and RxRing15 to PSE Port0 OQ-1 480 * connect other rings to PSE Port0 OQ-0 481 */ 482 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP0, BIT(4)); 483 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP1, BIT(28)); 484 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP2, BIT(4)); 485 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP3, BIT(28)); 486 487 airoha_fe_vip_setup(eth); 488 airoha_fe_pse_ports_init(eth); 489 490 airoha_fe_set(eth, REG_GDM_MISC_CFG, 491 GDM2_RDM_ACK_WAIT_PREF_MASK | 492 GDM2_CHN_VLD_MODE_MASK); 493 airoha_fe_rmw(eth, REG_CDM2_FWD_CFG, CDM2_OAM_QSEL_MASK, 494 FIELD_PREP(CDM2_OAM_QSEL_MASK, 15)); 495 496 /* init fragment and assemble Force Port */ 497 /* NPU Core-3, NPU Bridge Channel-3 */ 498 airoha_fe_rmw(eth, REG_IP_FRAG_FP, 499 IP_FRAGMENT_PORT_MASK | IP_FRAGMENT_NBQ_MASK, 500 FIELD_PREP(IP_FRAGMENT_PORT_MASK, 6) | 501 FIELD_PREP(IP_FRAGMENT_NBQ_MASK, 3)); 502 /* QDMA LAN, RX Ring-22 */ 503 airoha_fe_rmw(eth, REG_IP_FRAG_FP, 504 IP_ASSEMBLE_PORT_MASK | IP_ASSEMBLE_NBQ_MASK, 505 FIELD_PREP(IP_ASSEMBLE_PORT_MASK, 0) | 506 FIELD_PREP(IP_ASSEMBLE_NBQ_MASK, 22)); 507 508 airoha_fe_set(eth, REG_GDM3_FWD_CFG, GDM3_PAD_EN_MASK); 509 airoha_fe_set(eth, REG_GDM4_FWD_CFG, GDM4_PAD_EN_MASK); 510 511 airoha_fe_crsn_qsel_init(eth); 512 513 airoha_fe_clear(eth, REG_FE_CPORT_CFG, FE_CPORT_QUEUE_XFC_MASK); 514 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PORT_XFC_MASK); 515 516 /* default aging mode for mbi unlock issue */ 517 airoha_fe_rmw(eth, REG_GDM2_CHN_RLS, 518 MBI_RX_AGE_SEL_MASK | MBI_TX_AGE_SEL_MASK, 519 FIELD_PREP(MBI_RX_AGE_SEL_MASK, 3) | 520 FIELD_PREP(MBI_TX_AGE_SEL_MASK, 3)); 521 522 /* disable IFC by default */ 523 airoha_fe_clear(eth, REG_FE_CSR_IFC_CFG, FE_IFC_EN_MASK); 524 525 airoha_fe_wr(eth, REG_PPE_DFT_CPORT0(0), 526 FIELD_PREP(DFT_CPORT_MASK(7), FE_PSE_PORT_CDM1) | 527 FIELD_PREP(DFT_CPORT_MASK(6), FE_PSE_PORT_CDM1) | 528 FIELD_PREP(DFT_CPORT_MASK(5), FE_PSE_PORT_CDM1) | 529 FIELD_PREP(DFT_CPORT_MASK(4), FE_PSE_PORT_CDM1) | 530 FIELD_PREP(DFT_CPORT_MASK(3), FE_PSE_PORT_CDM1) | 531 FIELD_PREP(DFT_CPORT_MASK(2), FE_PSE_PORT_CDM1) | 532 FIELD_PREP(DFT_CPORT_MASK(1), FE_PSE_PORT_CDM1) | 533 FIELD_PREP(DFT_CPORT_MASK(0), FE_PSE_PORT_CDM1)); 534 airoha_fe_wr(eth, REG_PPE_DFT_CPORT0(1), 535 FIELD_PREP(DFT_CPORT_MASK(7), FE_PSE_PORT_CDM2) | 536 FIELD_PREP(DFT_CPORT_MASK(6), FE_PSE_PORT_CDM2) | 537 FIELD_PREP(DFT_CPORT_MASK(5), FE_PSE_PORT_CDM2) | 538 FIELD_PREP(DFT_CPORT_MASK(4), FE_PSE_PORT_CDM2) | 539 FIELD_PREP(DFT_CPORT_MASK(3), FE_PSE_PORT_CDM2) | 540 FIELD_PREP(DFT_CPORT_MASK(2), FE_PSE_PORT_CDM2) | 541 FIELD_PREP(DFT_CPORT_MASK(1), FE_PSE_PORT_CDM2) | 542 FIELD_PREP(DFT_CPORT_MASK(0), FE_PSE_PORT_CDM2)); 543 544 /* enable 1:N vlan action, init vlan table */ 545 airoha_fe_set(eth, REG_MC_VLAN_EN, MC_VLAN_EN_MASK); 546 547 return airoha_fe_mc_vlan_clear(eth); 548 } 549 550 static int airoha_qdma_fill_rx_queue(struct airoha_queue *q) 551 { 552 enum dma_data_direction dir = page_pool_get_dma_dir(q->page_pool); 553 struct airoha_qdma *qdma = q->qdma; 554 struct airoha_eth *eth = qdma->eth; 555 int qid = q - &qdma->q_rx[0]; 556 int nframes = 0; 557 558 while (q->queued < q->ndesc - 1) { 559 struct airoha_queue_entry *e = &q->entry[q->head]; 560 struct airoha_qdma_desc *desc = &q->desc[q->head]; 561 struct page *page; 562 int offset; 563 u32 val; 564 565 page = page_pool_dev_alloc_frag(q->page_pool, &offset, 566 q->buf_size); 567 if (!page) 568 break; 569 570 q->head = (q->head + 1) % q->ndesc; 571 q->queued++; 572 nframes++; 573 574 e->buf = page_address(page) + offset; 575 e->dma_addr = page_pool_get_dma_addr(page) + offset; 576 e->dma_len = SKB_WITH_OVERHEAD(q->buf_size); 577 578 dma_sync_single_for_device(eth->dev, e->dma_addr, e->dma_len, 579 dir); 580 581 val = FIELD_PREP(QDMA_DESC_LEN_MASK, e->dma_len); 582 WRITE_ONCE(desc->ctrl, cpu_to_le32(val)); 583 WRITE_ONCE(desc->addr, cpu_to_le32(e->dma_addr)); 584 val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, q->head); 585 WRITE_ONCE(desc->data, cpu_to_le32(val)); 586 WRITE_ONCE(desc->msg0, 0); 587 WRITE_ONCE(desc->msg1, 0); 588 WRITE_ONCE(desc->msg2, 0); 589 WRITE_ONCE(desc->msg3, 0); 590 591 airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), 592 RX_RING_CPU_IDX_MASK, 593 FIELD_PREP(RX_RING_CPU_IDX_MASK, q->head)); 594 } 595 596 return nframes; 597 } 598 599 static int airoha_qdma_get_gdm_port(struct airoha_eth *eth, 600 struct airoha_qdma_desc *desc) 601 { 602 u32 port, sport, msg1 = le32_to_cpu(desc->msg1); 603 604 sport = FIELD_GET(QDMA_ETH_RXMSG_SPORT_MASK, msg1); 605 switch (sport) { 606 case 0x10 ... 0x14: 607 port = 0; 608 break; 609 case 0x2 ... 0x4: 610 port = sport - 1; 611 break; 612 default: 613 return -EINVAL; 614 } 615 616 return port >= ARRAY_SIZE(eth->ports) ? -EINVAL : port; 617 } 618 619 static int airoha_qdma_rx_process(struct airoha_queue *q, int budget) 620 { 621 enum dma_data_direction dir = page_pool_get_dma_dir(q->page_pool); 622 struct airoha_qdma *qdma = q->qdma; 623 struct airoha_eth *eth = qdma->eth; 624 int qid = q - &qdma->q_rx[0]; 625 int done = 0; 626 627 while (done < budget) { 628 struct airoha_queue_entry *e = &q->entry[q->tail]; 629 struct airoha_qdma_desc *desc = &q->desc[q->tail]; 630 u32 hash, reason, msg1 = le32_to_cpu(desc->msg1); 631 struct page *page = virt_to_head_page(e->buf); 632 u32 desc_ctrl = le32_to_cpu(desc->ctrl); 633 struct airoha_gdm_port *port; 634 int data_len, len, p; 635 636 if (!(desc_ctrl & QDMA_DESC_DONE_MASK)) 637 break; 638 639 q->tail = (q->tail + 1) % q->ndesc; 640 q->queued--; 641 642 dma_sync_single_for_cpu(eth->dev, e->dma_addr, 643 SKB_WITH_OVERHEAD(q->buf_size), dir); 644 645 len = FIELD_GET(QDMA_DESC_LEN_MASK, desc_ctrl); 646 data_len = q->skb ? q->buf_size 647 : SKB_WITH_OVERHEAD(q->buf_size); 648 if (!len || data_len < len) 649 goto free_frag; 650 651 p = airoha_qdma_get_gdm_port(eth, desc); 652 if (p < 0 || !eth->ports[p]) 653 goto free_frag; 654 655 port = eth->ports[p]; 656 if (!q->skb) { /* first buffer */ 657 q->skb = napi_build_skb(e->buf, q->buf_size); 658 if (!q->skb) 659 goto free_frag; 660 661 __skb_put(q->skb, len); 662 skb_mark_for_recycle(q->skb); 663 q->skb->dev = port->dev; 664 q->skb->protocol = eth_type_trans(q->skb, port->dev); 665 q->skb->ip_summed = CHECKSUM_UNNECESSARY; 666 skb_record_rx_queue(q->skb, qid); 667 } else { /* scattered frame */ 668 struct skb_shared_info *shinfo = skb_shinfo(q->skb); 669 int nr_frags = shinfo->nr_frags; 670 671 if (nr_frags >= ARRAY_SIZE(shinfo->frags)) 672 goto free_frag; 673 674 skb_add_rx_frag(q->skb, nr_frags, page, 675 e->buf - page_address(page), len, 676 q->buf_size); 677 } 678 679 if (FIELD_GET(QDMA_DESC_MORE_MASK, desc_ctrl)) 680 continue; 681 682 if (netdev_uses_dsa(port->dev)) { 683 /* PPE module requires untagged packets to work 684 * properly and it provides DSA port index via the 685 * DMA descriptor. Report DSA tag to the DSA stack 686 * via skb dst info. 687 */ 688 u32 sptag = FIELD_GET(QDMA_ETH_RXMSG_SPTAG, 689 le32_to_cpu(desc->msg0)); 690 691 if (sptag < ARRAY_SIZE(port->dsa_meta) && 692 port->dsa_meta[sptag]) 693 skb_dst_set_noref(q->skb, 694 &port->dsa_meta[sptag]->dst); 695 } 696 697 hash = FIELD_GET(AIROHA_RXD4_FOE_ENTRY, msg1); 698 if (hash != AIROHA_RXD4_FOE_ENTRY) 699 skb_set_hash(q->skb, jhash_1word(hash, 0), 700 PKT_HASH_TYPE_L4); 701 702 reason = FIELD_GET(AIROHA_RXD4_PPE_CPU_REASON, msg1); 703 if (reason == PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 704 airoha_ppe_check_skb(eth->ppe, q->skb, hash); 705 706 done++; 707 napi_gro_receive(&q->napi, q->skb); 708 q->skb = NULL; 709 continue; 710 free_frag: 711 if (q->skb) { 712 dev_kfree_skb(q->skb); 713 q->skb = NULL; 714 } else { 715 page_pool_put_full_page(q->page_pool, page, true); 716 } 717 } 718 airoha_qdma_fill_rx_queue(q); 719 720 return done; 721 } 722 723 static int airoha_qdma_rx_napi_poll(struct napi_struct *napi, int budget) 724 { 725 struct airoha_queue *q = container_of(napi, struct airoha_queue, napi); 726 int cur, done = 0; 727 728 do { 729 cur = airoha_qdma_rx_process(q, budget - done); 730 done += cur; 731 } while (cur && done < budget); 732 733 if (done < budget && napi_complete(napi)) { 734 struct airoha_qdma *qdma = q->qdma; 735 int i, qid = q - &qdma->q_rx[0]; 736 int intr_reg = qid < RX_DONE_HIGH_OFFSET ? QDMA_INT_REG_IDX1 737 : QDMA_INT_REG_IDX2; 738 739 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 740 if (!(BIT(qid) & RX_IRQ_BANK_PIN_MASK(i))) 741 continue; 742 743 airoha_qdma_irq_enable(&qdma->irq_banks[i], intr_reg, 744 BIT(qid % RX_DONE_HIGH_OFFSET)); 745 } 746 } 747 748 return done; 749 } 750 751 static int airoha_qdma_init_rx_queue(struct airoha_queue *q, 752 struct airoha_qdma *qdma, int ndesc) 753 { 754 const struct page_pool_params pp_params = { 755 .order = 0, 756 .pool_size = 256, 757 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 758 .dma_dir = DMA_FROM_DEVICE, 759 .max_len = PAGE_SIZE, 760 .nid = NUMA_NO_NODE, 761 .dev = qdma->eth->dev, 762 .napi = &q->napi, 763 }; 764 struct airoha_eth *eth = qdma->eth; 765 int qid = q - &qdma->q_rx[0], thr; 766 dma_addr_t dma_addr; 767 768 q->buf_size = PAGE_SIZE / 2; 769 q->ndesc = ndesc; 770 q->qdma = qdma; 771 772 q->entry = devm_kzalloc(eth->dev, q->ndesc * sizeof(*q->entry), 773 GFP_KERNEL); 774 if (!q->entry) 775 return -ENOMEM; 776 777 q->page_pool = page_pool_create(&pp_params); 778 if (IS_ERR(q->page_pool)) { 779 int err = PTR_ERR(q->page_pool); 780 781 q->page_pool = NULL; 782 return err; 783 } 784 785 q->desc = dmam_alloc_coherent(eth->dev, q->ndesc * sizeof(*q->desc), 786 &dma_addr, GFP_KERNEL); 787 if (!q->desc) 788 return -ENOMEM; 789 790 netif_napi_add(eth->napi_dev, &q->napi, airoha_qdma_rx_napi_poll); 791 792 airoha_qdma_wr(qdma, REG_RX_RING_BASE(qid), dma_addr); 793 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), 794 RX_RING_SIZE_MASK, 795 FIELD_PREP(RX_RING_SIZE_MASK, ndesc)); 796 797 thr = clamp(ndesc >> 3, 1, 32); 798 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), RX_RING_THR_MASK, 799 FIELD_PREP(RX_RING_THR_MASK, thr)); 800 airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK, 801 FIELD_PREP(RX_RING_DMA_IDX_MASK, q->head)); 802 airoha_qdma_set(qdma, REG_RX_SCATTER_CFG(qid), RX_RING_SG_EN_MASK); 803 804 airoha_qdma_fill_rx_queue(q); 805 806 return 0; 807 } 808 809 static void airoha_qdma_cleanup_rx_queue(struct airoha_queue *q) 810 { 811 struct airoha_eth *eth = q->qdma->eth; 812 813 while (q->queued) { 814 struct airoha_queue_entry *e = &q->entry[q->tail]; 815 struct page *page = virt_to_head_page(e->buf); 816 817 dma_sync_single_for_cpu(eth->dev, e->dma_addr, e->dma_len, 818 page_pool_get_dma_dir(q->page_pool)); 819 page_pool_put_full_page(q->page_pool, page, false); 820 q->tail = (q->tail + 1) % q->ndesc; 821 q->queued--; 822 } 823 } 824 825 static int airoha_qdma_init_rx(struct airoha_qdma *qdma) 826 { 827 int i; 828 829 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 830 int err; 831 832 if (!(RX_DONE_INT_MASK & BIT(i))) { 833 /* rx-queue not binded to irq */ 834 continue; 835 } 836 837 err = airoha_qdma_init_rx_queue(&qdma->q_rx[i], qdma, 838 RX_DSCP_NUM(i)); 839 if (err) 840 return err; 841 } 842 843 return 0; 844 } 845 846 static int airoha_qdma_tx_napi_poll(struct napi_struct *napi, int budget) 847 { 848 struct airoha_tx_irq_queue *irq_q; 849 int id, done = 0, irq_queued; 850 struct airoha_qdma *qdma; 851 struct airoha_eth *eth; 852 u32 status, head; 853 854 irq_q = container_of(napi, struct airoha_tx_irq_queue, napi); 855 qdma = irq_q->qdma; 856 id = irq_q - &qdma->q_tx_irq[0]; 857 eth = qdma->eth; 858 859 status = airoha_qdma_rr(qdma, REG_IRQ_STATUS(id)); 860 head = FIELD_GET(IRQ_HEAD_IDX_MASK, status); 861 head = head % irq_q->size; 862 irq_queued = FIELD_GET(IRQ_ENTRY_LEN_MASK, status); 863 864 while (irq_queued > 0 && done < budget) { 865 u32 qid, val = irq_q->q[head]; 866 struct airoha_qdma_desc *desc; 867 struct airoha_queue_entry *e; 868 struct airoha_queue *q; 869 u32 index, desc_ctrl; 870 struct sk_buff *skb; 871 872 if (val == 0xff) 873 break; 874 875 irq_q->q[head] = 0xff; /* mark as done */ 876 head = (head + 1) % irq_q->size; 877 irq_queued--; 878 done++; 879 880 qid = FIELD_GET(IRQ_RING_IDX_MASK, val); 881 if (qid >= ARRAY_SIZE(qdma->q_tx)) 882 continue; 883 884 q = &qdma->q_tx[qid]; 885 if (!q->ndesc) 886 continue; 887 888 index = FIELD_GET(IRQ_DESC_IDX_MASK, val); 889 if (index >= q->ndesc) 890 continue; 891 892 spin_lock_bh(&q->lock); 893 894 if (!q->queued) 895 goto unlock; 896 897 desc = &q->desc[index]; 898 desc_ctrl = le32_to_cpu(desc->ctrl); 899 900 if (!(desc_ctrl & QDMA_DESC_DONE_MASK) && 901 !(desc_ctrl & QDMA_DESC_DROP_MASK)) 902 goto unlock; 903 904 e = &q->entry[index]; 905 skb = e->skb; 906 907 dma_unmap_single(eth->dev, e->dma_addr, e->dma_len, 908 DMA_TO_DEVICE); 909 memset(e, 0, sizeof(*e)); 910 WRITE_ONCE(desc->msg0, 0); 911 WRITE_ONCE(desc->msg1, 0); 912 q->queued--; 913 914 /* completion ring can report out-of-order indexes if hw QoS 915 * is enabled and packets with different priority are queued 916 * to same DMA ring. Take into account possible out-of-order 917 * reports incrementing DMA ring tail pointer 918 */ 919 while (q->tail != q->head && !q->entry[q->tail].dma_addr) 920 q->tail = (q->tail + 1) % q->ndesc; 921 922 if (skb) { 923 u16 queue = skb_get_queue_mapping(skb); 924 struct netdev_queue *txq; 925 926 txq = netdev_get_tx_queue(skb->dev, queue); 927 netdev_tx_completed_queue(txq, 1, skb->len); 928 if (netif_tx_queue_stopped(txq) && 929 q->ndesc - q->queued >= q->free_thr) 930 netif_tx_wake_queue(txq); 931 932 dev_kfree_skb_any(skb); 933 } 934 unlock: 935 spin_unlock_bh(&q->lock); 936 } 937 938 if (done) { 939 int i, len = done >> 7; 940 941 for (i = 0; i < len; i++) 942 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id), 943 IRQ_CLEAR_LEN_MASK, 0x80); 944 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id), 945 IRQ_CLEAR_LEN_MASK, (done & 0x7f)); 946 } 947 948 if (done < budget && napi_complete(napi)) 949 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0, 950 TX_DONE_INT_MASK(id)); 951 952 return done; 953 } 954 955 static int airoha_qdma_init_tx_queue(struct airoha_queue *q, 956 struct airoha_qdma *qdma, int size) 957 { 958 struct airoha_eth *eth = qdma->eth; 959 int i, qid = q - &qdma->q_tx[0]; 960 dma_addr_t dma_addr; 961 962 spin_lock_init(&q->lock); 963 q->ndesc = size; 964 q->qdma = qdma; 965 q->free_thr = 1 + MAX_SKB_FRAGS; 966 967 q->entry = devm_kzalloc(eth->dev, q->ndesc * sizeof(*q->entry), 968 GFP_KERNEL); 969 if (!q->entry) 970 return -ENOMEM; 971 972 q->desc = dmam_alloc_coherent(eth->dev, q->ndesc * sizeof(*q->desc), 973 &dma_addr, GFP_KERNEL); 974 if (!q->desc) 975 return -ENOMEM; 976 977 for (i = 0; i < q->ndesc; i++) { 978 u32 val; 979 980 val = FIELD_PREP(QDMA_DESC_DONE_MASK, 1); 981 WRITE_ONCE(q->desc[i].ctrl, cpu_to_le32(val)); 982 } 983 984 /* xmit ring drop default setting */ 985 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(qid), 986 TX_RING_IRQ_BLOCKING_TX_DROP_EN_MASK); 987 988 airoha_qdma_wr(qdma, REG_TX_RING_BASE(qid), dma_addr); 989 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK, 990 FIELD_PREP(TX_RING_CPU_IDX_MASK, q->head)); 991 airoha_qdma_rmw(qdma, REG_TX_DMA_IDX(qid), TX_RING_DMA_IDX_MASK, 992 FIELD_PREP(TX_RING_DMA_IDX_MASK, q->head)); 993 994 return 0; 995 } 996 997 static int airoha_qdma_tx_irq_init(struct airoha_tx_irq_queue *irq_q, 998 struct airoha_qdma *qdma, int size) 999 { 1000 int id = irq_q - &qdma->q_tx_irq[0]; 1001 struct airoha_eth *eth = qdma->eth; 1002 dma_addr_t dma_addr; 1003 1004 netif_napi_add_tx(eth->napi_dev, &irq_q->napi, 1005 airoha_qdma_tx_napi_poll); 1006 irq_q->q = dmam_alloc_coherent(eth->dev, size * sizeof(u32), 1007 &dma_addr, GFP_KERNEL); 1008 if (!irq_q->q) 1009 return -ENOMEM; 1010 1011 memset(irq_q->q, 0xff, size * sizeof(u32)); 1012 irq_q->size = size; 1013 irq_q->qdma = qdma; 1014 1015 airoha_qdma_wr(qdma, REG_TX_IRQ_BASE(id), dma_addr); 1016 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_DEPTH_MASK, 1017 FIELD_PREP(TX_IRQ_DEPTH_MASK, size)); 1018 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_THR_MASK, 1019 FIELD_PREP(TX_IRQ_THR_MASK, 1)); 1020 1021 return 0; 1022 } 1023 1024 static int airoha_qdma_init_tx(struct airoha_qdma *qdma) 1025 { 1026 int i, err; 1027 1028 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) { 1029 err = airoha_qdma_tx_irq_init(&qdma->q_tx_irq[i], qdma, 1030 IRQ_QUEUE_LEN(i)); 1031 if (err) 1032 return err; 1033 } 1034 1035 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1036 err = airoha_qdma_init_tx_queue(&qdma->q_tx[i], qdma, 1037 TX_DSCP_NUM); 1038 if (err) 1039 return err; 1040 } 1041 1042 return 0; 1043 } 1044 1045 static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q) 1046 { 1047 struct airoha_eth *eth = q->qdma->eth; 1048 1049 spin_lock_bh(&q->lock); 1050 while (q->queued) { 1051 struct airoha_queue_entry *e = &q->entry[q->tail]; 1052 1053 dma_unmap_single(eth->dev, e->dma_addr, e->dma_len, 1054 DMA_TO_DEVICE); 1055 dev_kfree_skb_any(e->skb); 1056 e->skb = NULL; 1057 1058 q->tail = (q->tail + 1) % q->ndesc; 1059 q->queued--; 1060 } 1061 spin_unlock_bh(&q->lock); 1062 } 1063 1064 static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma) 1065 { 1066 struct airoha_eth *eth = qdma->eth; 1067 int id = qdma - ð->qdma[0]; 1068 dma_addr_t dma_addr; 1069 const char *name; 1070 int size, index; 1071 u32 status; 1072 1073 size = HW_DSCP_NUM * sizeof(struct airoha_qdma_fwd_desc); 1074 if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, GFP_KERNEL)) 1075 return -ENOMEM; 1076 1077 airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr); 1078 1079 name = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d-buf", id); 1080 if (!name) 1081 return -ENOMEM; 1082 1083 index = of_property_match_string(eth->dev->of_node, 1084 "memory-region-names", name); 1085 if (index >= 0) { 1086 struct reserved_mem *rmem; 1087 struct device_node *np; 1088 1089 /* Consume reserved memory for hw forwarding buffers queue if 1090 * available in the DTS 1091 */ 1092 np = of_parse_phandle(eth->dev->of_node, "memory-region", 1093 index); 1094 if (!np) 1095 return -ENODEV; 1096 1097 rmem = of_reserved_mem_lookup(np); 1098 of_node_put(np); 1099 dma_addr = rmem->base; 1100 } else { 1101 size = AIROHA_MAX_PACKET_SIZE * HW_DSCP_NUM; 1102 if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, 1103 GFP_KERNEL)) 1104 return -ENOMEM; 1105 } 1106 1107 airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr); 1108 1109 airoha_qdma_rmw(qdma, REG_HW_FWD_DSCP_CFG, 1110 HW_FWD_DSCP_PAYLOAD_SIZE_MASK, 1111 FIELD_PREP(HW_FWD_DSCP_PAYLOAD_SIZE_MASK, 0)); 1112 airoha_qdma_rmw(qdma, REG_FWD_DSCP_LOW_THR, FWD_DSCP_LOW_THR_MASK, 1113 FIELD_PREP(FWD_DSCP_LOW_THR_MASK, 128)); 1114 airoha_qdma_rmw(qdma, REG_LMGR_INIT_CFG, 1115 LMGR_INIT_START | LMGR_SRAM_MODE_MASK | 1116 HW_FWD_DESC_NUM_MASK, 1117 FIELD_PREP(HW_FWD_DESC_NUM_MASK, HW_DSCP_NUM) | 1118 LMGR_INIT_START | LMGR_SRAM_MODE_MASK); 1119 1120 return read_poll_timeout(airoha_qdma_rr, status, 1121 !(status & LMGR_INIT_START), USEC_PER_MSEC, 1122 30 * USEC_PER_MSEC, true, qdma, 1123 REG_LMGR_INIT_CFG); 1124 } 1125 1126 static void airoha_qdma_init_qos(struct airoha_qdma *qdma) 1127 { 1128 airoha_qdma_clear(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_SCALE_MASK); 1129 airoha_qdma_set(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_BASE_MASK); 1130 1131 airoha_qdma_clear(qdma, REG_PSE_BUF_USAGE_CFG, 1132 PSE_BUF_ESTIMATE_EN_MASK); 1133 1134 airoha_qdma_set(qdma, REG_EGRESS_RATE_METER_CFG, 1135 EGRESS_RATE_METER_EN_MASK | 1136 EGRESS_RATE_METER_EQ_RATE_EN_MASK); 1137 /* 2047us x 31 = 63.457ms */ 1138 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG, 1139 EGRESS_RATE_METER_WINDOW_SZ_MASK, 1140 FIELD_PREP(EGRESS_RATE_METER_WINDOW_SZ_MASK, 0x1f)); 1141 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG, 1142 EGRESS_RATE_METER_TIMESLICE_MASK, 1143 FIELD_PREP(EGRESS_RATE_METER_TIMESLICE_MASK, 0x7ff)); 1144 1145 /* ratelimit init */ 1146 airoha_qdma_set(qdma, REG_GLB_TRTCM_CFG, GLB_TRTCM_EN_MASK); 1147 /* fast-tick 25us */ 1148 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_FAST_TICK_MASK, 1149 FIELD_PREP(GLB_FAST_TICK_MASK, 25)); 1150 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_SLOW_TICK_RATIO_MASK, 1151 FIELD_PREP(GLB_SLOW_TICK_RATIO_MASK, 40)); 1152 1153 airoha_qdma_set(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_TRTCM_EN_MASK); 1154 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_FAST_TICK_MASK, 1155 FIELD_PREP(EGRESS_FAST_TICK_MASK, 25)); 1156 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG, 1157 EGRESS_SLOW_TICK_RATIO_MASK, 1158 FIELD_PREP(EGRESS_SLOW_TICK_RATIO_MASK, 40)); 1159 1160 airoha_qdma_set(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_TRTCM_EN_MASK); 1161 airoha_qdma_clear(qdma, REG_INGRESS_TRTCM_CFG, 1162 INGRESS_TRTCM_MODE_MASK); 1163 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_FAST_TICK_MASK, 1164 FIELD_PREP(INGRESS_FAST_TICK_MASK, 125)); 1165 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG, 1166 INGRESS_SLOW_TICK_RATIO_MASK, 1167 FIELD_PREP(INGRESS_SLOW_TICK_RATIO_MASK, 8)); 1168 1169 airoha_qdma_set(qdma, REG_SLA_TRTCM_CFG, SLA_TRTCM_EN_MASK); 1170 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_FAST_TICK_MASK, 1171 FIELD_PREP(SLA_FAST_TICK_MASK, 25)); 1172 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_SLOW_TICK_RATIO_MASK, 1173 FIELD_PREP(SLA_SLOW_TICK_RATIO_MASK, 40)); 1174 } 1175 1176 static void airoha_qdma_init_qos_stats(struct airoha_qdma *qdma) 1177 { 1178 int i; 1179 1180 for (i = 0; i < AIROHA_NUM_QOS_CHANNELS; i++) { 1181 /* Tx-cpu transferred count */ 1182 airoha_qdma_wr(qdma, REG_CNTR_VAL(i << 1), 0); 1183 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1), 1184 CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK | 1185 CNTR_ALL_DSCP_RING_EN_MASK | 1186 FIELD_PREP(CNTR_CHAN_MASK, i)); 1187 /* Tx-fwd transferred count */ 1188 airoha_qdma_wr(qdma, REG_CNTR_VAL((i << 1) + 1), 0); 1189 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1), 1190 CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK | 1191 CNTR_ALL_DSCP_RING_EN_MASK | 1192 FIELD_PREP(CNTR_SRC_MASK, 1) | 1193 FIELD_PREP(CNTR_CHAN_MASK, i)); 1194 } 1195 } 1196 1197 static int airoha_qdma_hw_init(struct airoha_qdma *qdma) 1198 { 1199 int i; 1200 1201 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 1202 /* clear pending irqs */ 1203 airoha_qdma_wr(qdma, REG_INT_STATUS(i), 0xffffffff); 1204 /* setup rx irqs */ 1205 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX0, 1206 INT_RX0_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1207 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX1, 1208 INT_RX1_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1209 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX2, 1210 INT_RX2_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1211 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX3, 1212 INT_RX3_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1213 } 1214 /* setup tx irqs */ 1215 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0, 1216 TX_COHERENT_LOW_INT_MASK | INT_TX_MASK); 1217 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX4, 1218 TX_COHERENT_HIGH_INT_MASK); 1219 1220 /* setup irq binding */ 1221 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1222 if (!qdma->q_tx[i].ndesc) 1223 continue; 1224 1225 if (TX_RING_IRQ_BLOCKING_MAP_MASK & BIT(i)) 1226 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(i), 1227 TX_RING_IRQ_BLOCKING_CFG_MASK); 1228 else 1229 airoha_qdma_clear(qdma, REG_TX_RING_BLOCKING(i), 1230 TX_RING_IRQ_BLOCKING_CFG_MASK); 1231 } 1232 1233 airoha_qdma_wr(qdma, REG_QDMA_GLOBAL_CFG, 1234 FIELD_PREP(GLOBAL_CFG_DMA_PREFERENCE_MASK, 3) | 1235 GLOBAL_CFG_CPU_TXR_RR_MASK | 1236 GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK | 1237 GLOBAL_CFG_MULTICAST_MODIFY_FP_MASK | 1238 GLOBAL_CFG_MULTICAST_EN_MASK | 1239 GLOBAL_CFG_IRQ0_EN_MASK | GLOBAL_CFG_IRQ1_EN_MASK | 1240 GLOBAL_CFG_TX_WB_DONE_MASK | 1241 FIELD_PREP(GLOBAL_CFG_MAX_ISSUE_NUM_MASK, 2)); 1242 1243 airoha_qdma_init_qos(qdma); 1244 1245 /* disable qdma rx delay interrupt */ 1246 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1247 if (!qdma->q_rx[i].ndesc) 1248 continue; 1249 1250 airoha_qdma_clear(qdma, REG_RX_DELAY_INT_IDX(i), 1251 RX_DELAY_INT_MASK); 1252 } 1253 1254 airoha_qdma_set(qdma, REG_TXQ_CNGST_CFG, 1255 TXQ_CNGST_DROP_EN | TXQ_CNGST_DEI_DROP_EN); 1256 airoha_qdma_init_qos_stats(qdma); 1257 1258 return 0; 1259 } 1260 1261 static irqreturn_t airoha_irq_handler(int irq, void *dev_instance) 1262 { 1263 struct airoha_irq_bank *irq_bank = dev_instance; 1264 struct airoha_qdma *qdma = irq_bank->qdma; 1265 u32 rx_intr_mask = 0, rx_intr1, rx_intr2; 1266 u32 intr[ARRAY_SIZE(irq_bank->irqmask)]; 1267 int i; 1268 1269 for (i = 0; i < ARRAY_SIZE(intr); i++) { 1270 intr[i] = airoha_qdma_rr(qdma, REG_INT_STATUS(i)); 1271 intr[i] &= irq_bank->irqmask[i]; 1272 airoha_qdma_wr(qdma, REG_INT_STATUS(i), intr[i]); 1273 } 1274 1275 if (!test_bit(DEV_STATE_INITIALIZED, &qdma->eth->state)) 1276 return IRQ_NONE; 1277 1278 rx_intr1 = intr[1] & RX_DONE_LOW_INT_MASK; 1279 if (rx_intr1) { 1280 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX1, rx_intr1); 1281 rx_intr_mask |= rx_intr1; 1282 } 1283 1284 rx_intr2 = intr[2] & RX_DONE_HIGH_INT_MASK; 1285 if (rx_intr2) { 1286 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX2, rx_intr2); 1287 rx_intr_mask |= (rx_intr2 << 16); 1288 } 1289 1290 for (i = 0; rx_intr_mask && i < ARRAY_SIZE(qdma->q_rx); i++) { 1291 if (!qdma->q_rx[i].ndesc) 1292 continue; 1293 1294 if (rx_intr_mask & BIT(i)) 1295 napi_schedule(&qdma->q_rx[i].napi); 1296 } 1297 1298 if (intr[0] & INT_TX_MASK) { 1299 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) { 1300 if (!(intr[0] & TX_DONE_INT_MASK(i))) 1301 continue; 1302 1303 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX0, 1304 TX_DONE_INT_MASK(i)); 1305 napi_schedule(&qdma->q_tx_irq[i].napi); 1306 } 1307 } 1308 1309 return IRQ_HANDLED; 1310 } 1311 1312 static int airoha_qdma_init_irq_banks(struct platform_device *pdev, 1313 struct airoha_qdma *qdma) 1314 { 1315 struct airoha_eth *eth = qdma->eth; 1316 int i, id = qdma - ð->qdma[0]; 1317 1318 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 1319 struct airoha_irq_bank *irq_bank = &qdma->irq_banks[i]; 1320 int err, irq_index = 4 * id + i; 1321 const char *name; 1322 1323 spin_lock_init(&irq_bank->irq_lock); 1324 irq_bank->qdma = qdma; 1325 1326 irq_bank->irq = platform_get_irq(pdev, irq_index); 1327 if (irq_bank->irq < 0) 1328 return irq_bank->irq; 1329 1330 name = devm_kasprintf(eth->dev, GFP_KERNEL, 1331 KBUILD_MODNAME ".%d", irq_index); 1332 if (!name) 1333 return -ENOMEM; 1334 1335 err = devm_request_irq(eth->dev, irq_bank->irq, 1336 airoha_irq_handler, IRQF_SHARED, name, 1337 irq_bank); 1338 if (err) 1339 return err; 1340 } 1341 1342 return 0; 1343 } 1344 1345 static int airoha_qdma_init(struct platform_device *pdev, 1346 struct airoha_eth *eth, 1347 struct airoha_qdma *qdma) 1348 { 1349 int err, id = qdma - ð->qdma[0]; 1350 const char *res; 1351 1352 qdma->eth = eth; 1353 res = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d", id); 1354 if (!res) 1355 return -ENOMEM; 1356 1357 qdma->regs = devm_platform_ioremap_resource_byname(pdev, res); 1358 if (IS_ERR(qdma->regs)) 1359 return dev_err_probe(eth->dev, PTR_ERR(qdma->regs), 1360 "failed to iomap qdma%d regs\n", id); 1361 1362 err = airoha_qdma_init_irq_banks(pdev, qdma); 1363 if (err) 1364 return err; 1365 1366 err = airoha_qdma_init_rx(qdma); 1367 if (err) 1368 return err; 1369 1370 err = airoha_qdma_init_tx(qdma); 1371 if (err) 1372 return err; 1373 1374 err = airoha_qdma_init_hfwd_queues(qdma); 1375 if (err) 1376 return err; 1377 1378 return airoha_qdma_hw_init(qdma); 1379 } 1380 1381 static int airoha_hw_init(struct platform_device *pdev, 1382 struct airoha_eth *eth) 1383 { 1384 int err, i; 1385 1386 /* disable xsi */ 1387 err = reset_control_bulk_assert(ARRAY_SIZE(eth->xsi_rsts), 1388 eth->xsi_rsts); 1389 if (err) 1390 return err; 1391 1392 err = reset_control_bulk_assert(ARRAY_SIZE(eth->rsts), eth->rsts); 1393 if (err) 1394 return err; 1395 1396 msleep(20); 1397 err = reset_control_bulk_deassert(ARRAY_SIZE(eth->rsts), eth->rsts); 1398 if (err) 1399 return err; 1400 1401 msleep(20); 1402 err = airoha_fe_init(eth); 1403 if (err) 1404 return err; 1405 1406 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) { 1407 err = airoha_qdma_init(pdev, eth, ð->qdma[i]); 1408 if (err) 1409 return err; 1410 } 1411 1412 err = airoha_ppe_init(eth); 1413 if (err) 1414 return err; 1415 1416 set_bit(DEV_STATE_INITIALIZED, ð->state); 1417 1418 return 0; 1419 } 1420 1421 static void airoha_hw_cleanup(struct airoha_qdma *qdma) 1422 { 1423 int i; 1424 1425 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1426 if (!qdma->q_rx[i].ndesc) 1427 continue; 1428 1429 netif_napi_del(&qdma->q_rx[i].napi); 1430 airoha_qdma_cleanup_rx_queue(&qdma->q_rx[i]); 1431 if (qdma->q_rx[i].page_pool) 1432 page_pool_destroy(qdma->q_rx[i].page_pool); 1433 } 1434 1435 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1436 netif_napi_del(&qdma->q_tx_irq[i].napi); 1437 1438 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1439 if (!qdma->q_tx[i].ndesc) 1440 continue; 1441 1442 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]); 1443 } 1444 } 1445 1446 static void airoha_qdma_start_napi(struct airoha_qdma *qdma) 1447 { 1448 int i; 1449 1450 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1451 napi_enable(&qdma->q_tx_irq[i].napi); 1452 1453 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1454 if (!qdma->q_rx[i].ndesc) 1455 continue; 1456 1457 napi_enable(&qdma->q_rx[i].napi); 1458 } 1459 } 1460 1461 static void airoha_qdma_stop_napi(struct airoha_qdma *qdma) 1462 { 1463 int i; 1464 1465 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1466 napi_disable(&qdma->q_tx_irq[i].napi); 1467 1468 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1469 if (!qdma->q_rx[i].ndesc) 1470 continue; 1471 1472 napi_disable(&qdma->q_rx[i].napi); 1473 } 1474 } 1475 1476 static void airoha_update_hw_stats(struct airoha_gdm_port *port) 1477 { 1478 struct airoha_eth *eth = port->qdma->eth; 1479 u32 val, i = 0; 1480 1481 spin_lock(&port->stats.lock); 1482 u64_stats_update_begin(&port->stats.syncp); 1483 1484 /* TX */ 1485 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_H(port->id)); 1486 port->stats.tx_ok_pkts += ((u64)val << 32); 1487 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_L(port->id)); 1488 port->stats.tx_ok_pkts += val; 1489 1490 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_H(port->id)); 1491 port->stats.tx_ok_bytes += ((u64)val << 32); 1492 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_L(port->id)); 1493 port->stats.tx_ok_bytes += val; 1494 1495 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_DROP_CNT(port->id)); 1496 port->stats.tx_drops += val; 1497 1498 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_BC_CNT(port->id)); 1499 port->stats.tx_broadcast += val; 1500 1501 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_MC_CNT(port->id)); 1502 port->stats.tx_multicast += val; 1503 1504 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_RUNT_CNT(port->id)); 1505 port->stats.tx_len[i] += val; 1506 1507 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_H(port->id)); 1508 port->stats.tx_len[i] += ((u64)val << 32); 1509 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_L(port->id)); 1510 port->stats.tx_len[i++] += val; 1511 1512 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_H(port->id)); 1513 port->stats.tx_len[i] += ((u64)val << 32); 1514 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_L(port->id)); 1515 port->stats.tx_len[i++] += val; 1516 1517 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_H(port->id)); 1518 port->stats.tx_len[i] += ((u64)val << 32); 1519 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_L(port->id)); 1520 port->stats.tx_len[i++] += val; 1521 1522 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_H(port->id)); 1523 port->stats.tx_len[i] += ((u64)val << 32); 1524 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_L(port->id)); 1525 port->stats.tx_len[i++] += val; 1526 1527 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_H(port->id)); 1528 port->stats.tx_len[i] += ((u64)val << 32); 1529 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_L(port->id)); 1530 port->stats.tx_len[i++] += val; 1531 1532 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_H(port->id)); 1533 port->stats.tx_len[i] += ((u64)val << 32); 1534 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_L(port->id)); 1535 port->stats.tx_len[i++] += val; 1536 1537 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_LONG_CNT(port->id)); 1538 port->stats.tx_len[i++] += val; 1539 1540 /* RX */ 1541 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_H(port->id)); 1542 port->stats.rx_ok_pkts += ((u64)val << 32); 1543 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_L(port->id)); 1544 port->stats.rx_ok_pkts += val; 1545 1546 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_H(port->id)); 1547 port->stats.rx_ok_bytes += ((u64)val << 32); 1548 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_L(port->id)); 1549 port->stats.rx_ok_bytes += val; 1550 1551 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_DROP_CNT(port->id)); 1552 port->stats.rx_drops += val; 1553 1554 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_BC_CNT(port->id)); 1555 port->stats.rx_broadcast += val; 1556 1557 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_MC_CNT(port->id)); 1558 port->stats.rx_multicast += val; 1559 1560 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ERROR_DROP_CNT(port->id)); 1561 port->stats.rx_errors += val; 1562 1563 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_CRC_ERR_CNT(port->id)); 1564 port->stats.rx_crc_error += val; 1565 1566 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OVERFLOW_DROP_CNT(port->id)); 1567 port->stats.rx_over_errors += val; 1568 1569 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_FRAG_CNT(port->id)); 1570 port->stats.rx_fragment += val; 1571 1572 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_JABBER_CNT(port->id)); 1573 port->stats.rx_jabber += val; 1574 1575 i = 0; 1576 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_RUNT_CNT(port->id)); 1577 port->stats.rx_len[i] += val; 1578 1579 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_H(port->id)); 1580 port->stats.rx_len[i] += ((u64)val << 32); 1581 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_L(port->id)); 1582 port->stats.rx_len[i++] += val; 1583 1584 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_H(port->id)); 1585 port->stats.rx_len[i] += ((u64)val << 32); 1586 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_L(port->id)); 1587 port->stats.rx_len[i++] += val; 1588 1589 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_H(port->id)); 1590 port->stats.rx_len[i] += ((u64)val << 32); 1591 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_L(port->id)); 1592 port->stats.rx_len[i++] += val; 1593 1594 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_H(port->id)); 1595 port->stats.rx_len[i] += ((u64)val << 32); 1596 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_L(port->id)); 1597 port->stats.rx_len[i++] += val; 1598 1599 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_H(port->id)); 1600 port->stats.rx_len[i] += ((u64)val << 32); 1601 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_L(port->id)); 1602 port->stats.rx_len[i++] += val; 1603 1604 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_H(port->id)); 1605 port->stats.rx_len[i] += ((u64)val << 32); 1606 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_L(port->id)); 1607 port->stats.rx_len[i++] += val; 1608 1609 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_LONG_CNT(port->id)); 1610 port->stats.rx_len[i++] += val; 1611 1612 /* reset mib counters */ 1613 airoha_fe_set(eth, REG_FE_GDM_MIB_CLEAR(port->id), 1614 FE_GDM_MIB_RX_CLEAR_MASK | FE_GDM_MIB_TX_CLEAR_MASK); 1615 1616 u64_stats_update_end(&port->stats.syncp); 1617 spin_unlock(&port->stats.lock); 1618 } 1619 1620 static int airoha_dev_open(struct net_device *dev) 1621 { 1622 int err, len = ETH_HLEN + dev->mtu + ETH_FCS_LEN; 1623 struct airoha_gdm_port *port = netdev_priv(dev); 1624 struct airoha_qdma *qdma = port->qdma; 1625 1626 netif_tx_start_all_queues(dev); 1627 err = airoha_set_vip_for_gdm_port(port, true); 1628 if (err) 1629 return err; 1630 1631 if (netdev_uses_dsa(dev)) 1632 airoha_fe_set(qdma->eth, REG_GDM_INGRESS_CFG(port->id), 1633 GDM_STAG_EN_MASK); 1634 else 1635 airoha_fe_clear(qdma->eth, REG_GDM_INGRESS_CFG(port->id), 1636 GDM_STAG_EN_MASK); 1637 1638 airoha_fe_rmw(qdma->eth, REG_GDM_LEN_CFG(port->id), 1639 GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK, 1640 FIELD_PREP(GDM_SHORT_LEN_MASK, 60) | 1641 FIELD_PREP(GDM_LONG_LEN_MASK, len)); 1642 1643 airoha_qdma_set(qdma, REG_QDMA_GLOBAL_CFG, 1644 GLOBAL_CFG_TX_DMA_EN_MASK | 1645 GLOBAL_CFG_RX_DMA_EN_MASK); 1646 atomic_inc(&qdma->users); 1647 1648 return 0; 1649 } 1650 1651 static int airoha_dev_stop(struct net_device *dev) 1652 { 1653 struct airoha_gdm_port *port = netdev_priv(dev); 1654 struct airoha_qdma *qdma = port->qdma; 1655 int i, err; 1656 1657 netif_tx_disable(dev); 1658 err = airoha_set_vip_for_gdm_port(port, false); 1659 if (err) 1660 return err; 1661 1662 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) 1663 netdev_tx_reset_subqueue(dev, i); 1664 1665 if (atomic_dec_and_test(&qdma->users)) { 1666 airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG, 1667 GLOBAL_CFG_TX_DMA_EN_MASK | 1668 GLOBAL_CFG_RX_DMA_EN_MASK); 1669 1670 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1671 if (!qdma->q_tx[i].ndesc) 1672 continue; 1673 1674 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]); 1675 } 1676 } 1677 1678 return 0; 1679 } 1680 1681 static int airoha_dev_set_macaddr(struct net_device *dev, void *p) 1682 { 1683 struct airoha_gdm_port *port = netdev_priv(dev); 1684 int err; 1685 1686 err = eth_mac_addr(dev, p); 1687 if (err) 1688 return err; 1689 1690 airoha_set_macaddr(port, dev->dev_addr); 1691 1692 return 0; 1693 } 1694 1695 static void airhoha_set_gdm2_loopback(struct airoha_gdm_port *port) 1696 { 1697 u32 pse_port = port->id == 3 ? FE_PSE_PORT_GDM3 : FE_PSE_PORT_GDM4; 1698 struct airoha_eth *eth = port->qdma->eth; 1699 u32 chan = port->id == 3 ? 4 : 0; 1700 1701 /* Forward the traffic to the proper GDM port */ 1702 airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(2), pse_port); 1703 airoha_fe_clear(eth, REG_GDM_FWD_CFG(2), GDM_STRIP_CRC); 1704 1705 /* Enable GDM2 loopback */ 1706 airoha_fe_wr(eth, REG_GDM_TXCHN_EN(2), 0xffffffff); 1707 airoha_fe_wr(eth, REG_GDM_RXCHN_EN(2), 0xffff); 1708 airoha_fe_rmw(eth, REG_GDM_LPBK_CFG(2), 1709 LPBK_CHAN_MASK | LPBK_MODE_MASK | LPBK_EN_MASK, 1710 FIELD_PREP(LPBK_CHAN_MASK, chan) | LPBK_EN_MASK); 1711 airoha_fe_rmw(eth, REG_GDM_LEN_CFG(2), 1712 GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK, 1713 FIELD_PREP(GDM_SHORT_LEN_MASK, 60) | 1714 FIELD_PREP(GDM_LONG_LEN_MASK, AIROHA_MAX_MTU)); 1715 1716 /* Disable VIP and IFC for GDM2 */ 1717 airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, BIT(2)); 1718 airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, BIT(2)); 1719 1720 if (port->id == 3) { 1721 /* FIXME: handle XSI_PCE1_PORT */ 1722 airoha_fe_rmw(eth, REG_FE_WAN_PORT, 1723 WAN1_EN_MASK | WAN1_MASK | WAN0_MASK, 1724 FIELD_PREP(WAN0_MASK, HSGMII_LAN_PCIE0_SRCPORT)); 1725 airoha_fe_rmw(eth, 1726 REG_SP_DFT_CPORT(HSGMII_LAN_PCIE0_SRCPORT >> 3), 1727 SP_CPORT_PCIE0_MASK, 1728 FIELD_PREP(SP_CPORT_PCIE0_MASK, 1729 FE_PSE_PORT_CDM2)); 1730 } else { 1731 /* FIXME: handle XSI_USB_PORT */ 1732 airoha_fe_rmw(eth, REG_SRC_PORT_FC_MAP6, 1733 FC_ID_OF_SRC_PORT24_MASK, 1734 FIELD_PREP(FC_ID_OF_SRC_PORT24_MASK, 2)); 1735 airoha_fe_rmw(eth, REG_FE_WAN_PORT, 1736 WAN1_EN_MASK | WAN1_MASK | WAN0_MASK, 1737 FIELD_PREP(WAN0_MASK, HSGMII_LAN_ETH_SRCPORT)); 1738 airoha_fe_rmw(eth, 1739 REG_SP_DFT_CPORT(HSGMII_LAN_ETH_SRCPORT >> 3), 1740 SP_CPORT_ETH_MASK, 1741 FIELD_PREP(SP_CPORT_ETH_MASK, FE_PSE_PORT_CDM2)); 1742 } 1743 } 1744 1745 static int airoha_dev_init(struct net_device *dev) 1746 { 1747 struct airoha_gdm_port *port = netdev_priv(dev); 1748 struct airoha_eth *eth = port->qdma->eth; 1749 u32 pse_port; 1750 1751 airoha_set_macaddr(port, dev->dev_addr); 1752 1753 switch (port->id) { 1754 case 3: 1755 case 4: 1756 /* If GDM2 is active we can't enable loopback */ 1757 if (!eth->ports[1]) 1758 airhoha_set_gdm2_loopback(port); 1759 fallthrough; 1760 case 2: 1761 pse_port = FE_PSE_PORT_PPE2; 1762 break; 1763 default: 1764 pse_port = FE_PSE_PORT_PPE1; 1765 break; 1766 } 1767 1768 airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(port->id), pse_port); 1769 1770 return 0; 1771 } 1772 1773 static void airoha_dev_get_stats64(struct net_device *dev, 1774 struct rtnl_link_stats64 *storage) 1775 { 1776 struct airoha_gdm_port *port = netdev_priv(dev); 1777 unsigned int start; 1778 1779 airoha_update_hw_stats(port); 1780 do { 1781 start = u64_stats_fetch_begin(&port->stats.syncp); 1782 storage->rx_packets = port->stats.rx_ok_pkts; 1783 storage->tx_packets = port->stats.tx_ok_pkts; 1784 storage->rx_bytes = port->stats.rx_ok_bytes; 1785 storage->tx_bytes = port->stats.tx_ok_bytes; 1786 storage->multicast = port->stats.rx_multicast; 1787 storage->rx_errors = port->stats.rx_errors; 1788 storage->rx_dropped = port->stats.rx_drops; 1789 storage->tx_dropped = port->stats.tx_drops; 1790 storage->rx_crc_errors = port->stats.rx_crc_error; 1791 storage->rx_over_errors = port->stats.rx_over_errors; 1792 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 1793 } 1794 1795 static int airoha_dev_change_mtu(struct net_device *dev, int mtu) 1796 { 1797 struct airoha_gdm_port *port = netdev_priv(dev); 1798 struct airoha_eth *eth = port->qdma->eth; 1799 u32 len = ETH_HLEN + mtu + ETH_FCS_LEN; 1800 1801 airoha_fe_rmw(eth, REG_GDM_LEN_CFG(port->id), 1802 GDM_LONG_LEN_MASK, 1803 FIELD_PREP(GDM_LONG_LEN_MASK, len)); 1804 WRITE_ONCE(dev->mtu, mtu); 1805 1806 return 0; 1807 } 1808 1809 static u16 airoha_dev_select_queue(struct net_device *dev, struct sk_buff *skb, 1810 struct net_device *sb_dev) 1811 { 1812 struct airoha_gdm_port *port = netdev_priv(dev); 1813 int queue, channel; 1814 1815 /* For dsa device select QoS channel according to the dsa user port 1816 * index, rely on port id otherwise. Select QoS queue based on the 1817 * skb priority. 1818 */ 1819 channel = netdev_uses_dsa(dev) ? skb_get_queue_mapping(skb) : port->id; 1820 channel = channel % AIROHA_NUM_QOS_CHANNELS; 1821 queue = (skb->priority - 1) % AIROHA_NUM_QOS_QUEUES; /* QoS queue */ 1822 queue = channel * AIROHA_NUM_QOS_QUEUES + queue; 1823 1824 return queue < dev->num_tx_queues ? queue : 0; 1825 } 1826 1827 static u32 airoha_get_dsa_tag(struct sk_buff *skb, struct net_device *dev) 1828 { 1829 #if IS_ENABLED(CONFIG_NET_DSA) 1830 struct ethhdr *ehdr; 1831 u8 xmit_tpid; 1832 u16 tag; 1833 1834 if (!netdev_uses_dsa(dev)) 1835 return 0; 1836 1837 if (dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK) 1838 return 0; 1839 1840 if (skb_cow_head(skb, 0)) 1841 return 0; 1842 1843 ehdr = (struct ethhdr *)skb->data; 1844 tag = be16_to_cpu(ehdr->h_proto); 1845 xmit_tpid = tag >> 8; 1846 1847 switch (xmit_tpid) { 1848 case MTK_HDR_XMIT_TAGGED_TPID_8100: 1849 ehdr->h_proto = cpu_to_be16(ETH_P_8021Q); 1850 tag &= ~(MTK_HDR_XMIT_TAGGED_TPID_8100 << 8); 1851 break; 1852 case MTK_HDR_XMIT_TAGGED_TPID_88A8: 1853 ehdr->h_proto = cpu_to_be16(ETH_P_8021AD); 1854 tag &= ~(MTK_HDR_XMIT_TAGGED_TPID_88A8 << 8); 1855 break; 1856 default: 1857 /* PPE module requires untagged DSA packets to work properly, 1858 * so move DSA tag to DMA descriptor. 1859 */ 1860 memmove(skb->data + MTK_HDR_LEN, skb->data, 2 * ETH_ALEN); 1861 __skb_pull(skb, MTK_HDR_LEN); 1862 break; 1863 } 1864 1865 return tag; 1866 #else 1867 return 0; 1868 #endif 1869 } 1870 1871 static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb, 1872 struct net_device *dev) 1873 { 1874 struct airoha_gdm_port *port = netdev_priv(dev); 1875 struct airoha_qdma *qdma = port->qdma; 1876 u32 nr_frags, tag, msg0, msg1, len; 1877 struct netdev_queue *txq; 1878 struct airoha_queue *q; 1879 void *data; 1880 int i, qid; 1881 u16 index; 1882 u8 fport; 1883 1884 qid = skb_get_queue_mapping(skb) % ARRAY_SIZE(qdma->q_tx); 1885 tag = airoha_get_dsa_tag(skb, dev); 1886 1887 msg0 = FIELD_PREP(QDMA_ETH_TXMSG_CHAN_MASK, 1888 qid / AIROHA_NUM_QOS_QUEUES) | 1889 FIELD_PREP(QDMA_ETH_TXMSG_QUEUE_MASK, 1890 qid % AIROHA_NUM_QOS_QUEUES) | 1891 FIELD_PREP(QDMA_ETH_TXMSG_SP_TAG_MASK, tag); 1892 if (skb->ip_summed == CHECKSUM_PARTIAL) 1893 msg0 |= FIELD_PREP(QDMA_ETH_TXMSG_TCO_MASK, 1) | 1894 FIELD_PREP(QDMA_ETH_TXMSG_UCO_MASK, 1) | 1895 FIELD_PREP(QDMA_ETH_TXMSG_ICO_MASK, 1); 1896 1897 /* TSO: fill MSS info in tcp checksum field */ 1898 if (skb_is_gso(skb)) { 1899 if (skb_cow_head(skb, 0)) 1900 goto error; 1901 1902 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | 1903 SKB_GSO_TCPV6)) { 1904 __be16 csum = cpu_to_be16(skb_shinfo(skb)->gso_size); 1905 1906 tcp_hdr(skb)->check = (__force __sum16)csum; 1907 msg0 |= FIELD_PREP(QDMA_ETH_TXMSG_TSO_MASK, 1); 1908 } 1909 } 1910 1911 fport = port->id == 4 ? FE_PSE_PORT_GDM4 : port->id; 1912 msg1 = FIELD_PREP(QDMA_ETH_TXMSG_FPORT_MASK, fport) | 1913 FIELD_PREP(QDMA_ETH_TXMSG_METER_MASK, 0x7f); 1914 1915 q = &qdma->q_tx[qid]; 1916 if (WARN_ON_ONCE(!q->ndesc)) 1917 goto error; 1918 1919 spin_lock_bh(&q->lock); 1920 1921 txq = netdev_get_tx_queue(dev, qid); 1922 nr_frags = 1 + skb_shinfo(skb)->nr_frags; 1923 1924 if (q->queued + nr_frags > q->ndesc) { 1925 /* not enough space in the queue */ 1926 netif_tx_stop_queue(txq); 1927 spin_unlock_bh(&q->lock); 1928 return NETDEV_TX_BUSY; 1929 } 1930 1931 len = skb_headlen(skb); 1932 data = skb->data; 1933 index = q->head; 1934 1935 for (i = 0; i < nr_frags; i++) { 1936 struct airoha_qdma_desc *desc = &q->desc[index]; 1937 struct airoha_queue_entry *e = &q->entry[index]; 1938 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1939 dma_addr_t addr; 1940 u32 val; 1941 1942 addr = dma_map_single(dev->dev.parent, data, len, 1943 DMA_TO_DEVICE); 1944 if (unlikely(dma_mapping_error(dev->dev.parent, addr))) 1945 goto error_unmap; 1946 1947 index = (index + 1) % q->ndesc; 1948 1949 val = FIELD_PREP(QDMA_DESC_LEN_MASK, len); 1950 if (i < nr_frags - 1) 1951 val |= FIELD_PREP(QDMA_DESC_MORE_MASK, 1); 1952 WRITE_ONCE(desc->ctrl, cpu_to_le32(val)); 1953 WRITE_ONCE(desc->addr, cpu_to_le32(addr)); 1954 val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, index); 1955 WRITE_ONCE(desc->data, cpu_to_le32(val)); 1956 WRITE_ONCE(desc->msg0, cpu_to_le32(msg0)); 1957 WRITE_ONCE(desc->msg1, cpu_to_le32(msg1)); 1958 WRITE_ONCE(desc->msg2, cpu_to_le32(0xffff)); 1959 1960 e->skb = i ? NULL : skb; 1961 e->dma_addr = addr; 1962 e->dma_len = len; 1963 1964 data = skb_frag_address(frag); 1965 len = skb_frag_size(frag); 1966 } 1967 1968 q->head = index; 1969 q->queued += i; 1970 1971 skb_tx_timestamp(skb); 1972 netdev_tx_sent_queue(txq, skb->len); 1973 1974 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) 1975 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), 1976 TX_RING_CPU_IDX_MASK, 1977 FIELD_PREP(TX_RING_CPU_IDX_MASK, q->head)); 1978 1979 if (q->ndesc - q->queued < q->free_thr) 1980 netif_tx_stop_queue(txq); 1981 1982 spin_unlock_bh(&q->lock); 1983 1984 return NETDEV_TX_OK; 1985 1986 error_unmap: 1987 for (i--; i >= 0; i--) { 1988 index = (q->head + i) % q->ndesc; 1989 dma_unmap_single(dev->dev.parent, q->entry[index].dma_addr, 1990 q->entry[index].dma_len, DMA_TO_DEVICE); 1991 } 1992 1993 spin_unlock_bh(&q->lock); 1994 error: 1995 dev_kfree_skb_any(skb); 1996 dev->stats.tx_dropped++; 1997 1998 return NETDEV_TX_OK; 1999 } 2000 2001 static void airoha_ethtool_get_drvinfo(struct net_device *dev, 2002 struct ethtool_drvinfo *info) 2003 { 2004 struct airoha_gdm_port *port = netdev_priv(dev); 2005 struct airoha_eth *eth = port->qdma->eth; 2006 2007 strscpy(info->driver, eth->dev->driver->name, sizeof(info->driver)); 2008 strscpy(info->bus_info, dev_name(eth->dev), sizeof(info->bus_info)); 2009 } 2010 2011 static void airoha_ethtool_get_mac_stats(struct net_device *dev, 2012 struct ethtool_eth_mac_stats *stats) 2013 { 2014 struct airoha_gdm_port *port = netdev_priv(dev); 2015 unsigned int start; 2016 2017 airoha_update_hw_stats(port); 2018 do { 2019 start = u64_stats_fetch_begin(&port->stats.syncp); 2020 stats->MulticastFramesXmittedOK = port->stats.tx_multicast; 2021 stats->BroadcastFramesXmittedOK = port->stats.tx_broadcast; 2022 stats->BroadcastFramesReceivedOK = port->stats.rx_broadcast; 2023 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 2024 } 2025 2026 static const struct ethtool_rmon_hist_range airoha_ethtool_rmon_ranges[] = { 2027 { 0, 64 }, 2028 { 65, 127 }, 2029 { 128, 255 }, 2030 { 256, 511 }, 2031 { 512, 1023 }, 2032 { 1024, 1518 }, 2033 { 1519, 10239 }, 2034 {}, 2035 }; 2036 2037 static void 2038 airoha_ethtool_get_rmon_stats(struct net_device *dev, 2039 struct ethtool_rmon_stats *stats, 2040 const struct ethtool_rmon_hist_range **ranges) 2041 { 2042 struct airoha_gdm_port *port = netdev_priv(dev); 2043 struct airoha_hw_stats *hw_stats = &port->stats; 2044 unsigned int start; 2045 2046 BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) != 2047 ARRAY_SIZE(hw_stats->tx_len) + 1); 2048 BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) != 2049 ARRAY_SIZE(hw_stats->rx_len) + 1); 2050 2051 *ranges = airoha_ethtool_rmon_ranges; 2052 airoha_update_hw_stats(port); 2053 do { 2054 int i; 2055 2056 start = u64_stats_fetch_begin(&port->stats.syncp); 2057 stats->fragments = hw_stats->rx_fragment; 2058 stats->jabbers = hw_stats->rx_jabber; 2059 for (i = 0; i < ARRAY_SIZE(airoha_ethtool_rmon_ranges) - 1; 2060 i++) { 2061 stats->hist[i] = hw_stats->rx_len[i]; 2062 stats->hist_tx[i] = hw_stats->tx_len[i]; 2063 } 2064 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 2065 } 2066 2067 static int airoha_qdma_set_chan_tx_sched(struct airoha_gdm_port *port, 2068 int channel, enum tx_sched_mode mode, 2069 const u16 *weights, u8 n_weights) 2070 { 2071 int i; 2072 2073 for (i = 0; i < AIROHA_NUM_TX_RING; i++) 2074 airoha_qdma_clear(port->qdma, REG_QUEUE_CLOSE_CFG(channel), 2075 TXQ_DISABLE_CHAN_QUEUE_MASK(channel, i)); 2076 2077 for (i = 0; i < n_weights; i++) { 2078 u32 status; 2079 int err; 2080 2081 airoha_qdma_wr(port->qdma, REG_TXWRR_WEIGHT_CFG, 2082 TWRR_RW_CMD_MASK | 2083 FIELD_PREP(TWRR_CHAN_IDX_MASK, channel) | 2084 FIELD_PREP(TWRR_QUEUE_IDX_MASK, i) | 2085 FIELD_PREP(TWRR_VALUE_MASK, weights[i])); 2086 err = read_poll_timeout(airoha_qdma_rr, status, 2087 status & TWRR_RW_CMD_DONE, 2088 USEC_PER_MSEC, 10 * USEC_PER_MSEC, 2089 true, port->qdma, 2090 REG_TXWRR_WEIGHT_CFG); 2091 if (err) 2092 return err; 2093 } 2094 2095 airoha_qdma_rmw(port->qdma, REG_CHAN_QOS_MODE(channel >> 3), 2096 CHAN_QOS_MODE_MASK(channel), 2097 mode << __ffs(CHAN_QOS_MODE_MASK(channel))); 2098 2099 return 0; 2100 } 2101 2102 static int airoha_qdma_set_tx_prio_sched(struct airoha_gdm_port *port, 2103 int channel) 2104 { 2105 static const u16 w[AIROHA_NUM_QOS_QUEUES] = {}; 2106 2107 return airoha_qdma_set_chan_tx_sched(port, channel, TC_SCH_SP, w, 2108 ARRAY_SIZE(w)); 2109 } 2110 2111 static int airoha_qdma_set_tx_ets_sched(struct airoha_gdm_port *port, 2112 int channel, 2113 struct tc_ets_qopt_offload *opt) 2114 { 2115 struct tc_ets_qopt_offload_replace_params *p = &opt->replace_params; 2116 enum tx_sched_mode mode = TC_SCH_SP; 2117 u16 w[AIROHA_NUM_QOS_QUEUES] = {}; 2118 int i, nstrict = 0; 2119 2120 if (p->bands > AIROHA_NUM_QOS_QUEUES) 2121 return -EINVAL; 2122 2123 for (i = 0; i < p->bands; i++) { 2124 if (!p->quanta[i]) 2125 nstrict++; 2126 } 2127 2128 /* this configuration is not supported by the hw */ 2129 if (nstrict == AIROHA_NUM_QOS_QUEUES - 1) 2130 return -EINVAL; 2131 2132 /* EN7581 SoC supports fixed QoS band priority where WRR queues have 2133 * lowest priorities with respect to SP ones. 2134 * e.g: WRR0, WRR1, .., WRRm, SP0, SP1, .., SPn 2135 */ 2136 for (i = 0; i < nstrict; i++) { 2137 if (p->priomap[p->bands - i - 1] != i) 2138 return -EINVAL; 2139 } 2140 2141 for (i = 0; i < p->bands - nstrict; i++) { 2142 if (p->priomap[i] != nstrict + i) 2143 return -EINVAL; 2144 2145 w[i] = p->weights[nstrict + i]; 2146 } 2147 2148 if (!nstrict) 2149 mode = TC_SCH_WRR8; 2150 else if (nstrict < AIROHA_NUM_QOS_QUEUES - 1) 2151 mode = nstrict + 1; 2152 2153 return airoha_qdma_set_chan_tx_sched(port, channel, mode, w, 2154 ARRAY_SIZE(w)); 2155 } 2156 2157 static int airoha_qdma_get_tx_ets_stats(struct airoha_gdm_port *port, 2158 int channel, 2159 struct tc_ets_qopt_offload *opt) 2160 { 2161 u64 cpu_tx_packets = airoha_qdma_rr(port->qdma, 2162 REG_CNTR_VAL(channel << 1)); 2163 u64 fwd_tx_packets = airoha_qdma_rr(port->qdma, 2164 REG_CNTR_VAL((channel << 1) + 1)); 2165 u64 tx_packets = (cpu_tx_packets - port->cpu_tx_packets) + 2166 (fwd_tx_packets - port->fwd_tx_packets); 2167 _bstats_update(opt->stats.bstats, 0, tx_packets); 2168 2169 port->cpu_tx_packets = cpu_tx_packets; 2170 port->fwd_tx_packets = fwd_tx_packets; 2171 2172 return 0; 2173 } 2174 2175 static int airoha_tc_setup_qdisc_ets(struct airoha_gdm_port *port, 2176 struct tc_ets_qopt_offload *opt) 2177 { 2178 int channel; 2179 2180 if (opt->parent == TC_H_ROOT) 2181 return -EINVAL; 2182 2183 channel = TC_H_MAJ(opt->handle) >> 16; 2184 channel = channel % AIROHA_NUM_QOS_CHANNELS; 2185 2186 switch (opt->command) { 2187 case TC_ETS_REPLACE: 2188 return airoha_qdma_set_tx_ets_sched(port, channel, opt); 2189 case TC_ETS_DESTROY: 2190 /* PRIO is default qdisc scheduler */ 2191 return airoha_qdma_set_tx_prio_sched(port, channel); 2192 case TC_ETS_STATS: 2193 return airoha_qdma_get_tx_ets_stats(port, channel, opt); 2194 default: 2195 return -EOPNOTSUPP; 2196 } 2197 } 2198 2199 static int airoha_qdma_get_rl_param(struct airoha_qdma *qdma, int queue_id, 2200 u32 addr, enum trtcm_param_type param, 2201 u32 *val_low, u32 *val_high) 2202 { 2203 u32 idx = QDMA_METER_IDX(queue_id), group = QDMA_METER_GROUP(queue_id); 2204 u32 val, config = FIELD_PREP(RATE_LIMIT_PARAM_TYPE_MASK, param) | 2205 FIELD_PREP(RATE_LIMIT_METER_GROUP_MASK, group) | 2206 FIELD_PREP(RATE_LIMIT_PARAM_INDEX_MASK, idx); 2207 2208 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2209 if (read_poll_timeout(airoha_qdma_rr, val, 2210 val & RATE_LIMIT_PARAM_RW_DONE_MASK, 2211 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, qdma, 2212 REG_TRTCM_CFG_PARAM(addr))) 2213 return -ETIMEDOUT; 2214 2215 *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr)); 2216 if (val_high) 2217 *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr)); 2218 2219 return 0; 2220 } 2221 2222 static int airoha_qdma_set_rl_param(struct airoha_qdma *qdma, int queue_id, 2223 u32 addr, enum trtcm_param_type param, 2224 u32 val) 2225 { 2226 u32 idx = QDMA_METER_IDX(queue_id), group = QDMA_METER_GROUP(queue_id); 2227 u32 config = RATE_LIMIT_PARAM_RW_MASK | 2228 FIELD_PREP(RATE_LIMIT_PARAM_TYPE_MASK, param) | 2229 FIELD_PREP(RATE_LIMIT_METER_GROUP_MASK, group) | 2230 FIELD_PREP(RATE_LIMIT_PARAM_INDEX_MASK, idx); 2231 2232 airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val); 2233 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2234 2235 return read_poll_timeout(airoha_qdma_rr, val, 2236 val & RATE_LIMIT_PARAM_RW_DONE_MASK, 2237 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2238 qdma, REG_TRTCM_CFG_PARAM(addr)); 2239 } 2240 2241 static int airoha_qdma_set_rl_config(struct airoha_qdma *qdma, int queue_id, 2242 u32 addr, bool enable, u32 enable_mask) 2243 { 2244 u32 val; 2245 int err; 2246 2247 err = airoha_qdma_get_rl_param(qdma, queue_id, addr, TRTCM_MISC_MODE, 2248 &val, NULL); 2249 if (err) 2250 return err; 2251 2252 val = enable ? val | enable_mask : val & ~enable_mask; 2253 2254 return airoha_qdma_set_rl_param(qdma, queue_id, addr, TRTCM_MISC_MODE, 2255 val); 2256 } 2257 2258 static int airoha_qdma_set_rl_token_bucket(struct airoha_qdma *qdma, 2259 int queue_id, u32 rate_val, 2260 u32 bucket_size) 2261 { 2262 u32 val, config, tick, unit, rate, rate_frac; 2263 int err; 2264 2265 err = airoha_qdma_get_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2266 TRTCM_MISC_MODE, &config, NULL); 2267 if (err) 2268 return err; 2269 2270 val = airoha_qdma_rr(qdma, REG_INGRESS_TRTCM_CFG); 2271 tick = FIELD_GET(INGRESS_FAST_TICK_MASK, val); 2272 if (config & TRTCM_TICK_SEL) 2273 tick *= FIELD_GET(INGRESS_SLOW_TICK_RATIO_MASK, val); 2274 if (!tick) 2275 return -EINVAL; 2276 2277 unit = (config & TRTCM_PKT_MODE) ? 1000000 / tick : 8000 / tick; 2278 if (!unit) 2279 return -EINVAL; 2280 2281 rate = rate_val / unit; 2282 rate_frac = rate_val % unit; 2283 rate_frac = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate_frac) / unit; 2284 rate = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate) | 2285 FIELD_PREP(TRTCM_TOKEN_RATE_FRACTION_MASK, rate_frac); 2286 2287 err = airoha_qdma_set_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2288 TRTCM_TOKEN_RATE_MODE, rate); 2289 if (err) 2290 return err; 2291 2292 val = bucket_size; 2293 if (!(config & TRTCM_PKT_MODE)) 2294 val = max_t(u32, val, MIN_TOKEN_SIZE); 2295 val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET); 2296 2297 return airoha_qdma_set_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2298 TRTCM_BUCKETSIZE_SHIFT_MODE, val); 2299 } 2300 2301 static int airoha_qdma_init_rl_config(struct airoha_qdma *qdma, int queue_id, 2302 bool enable, enum trtcm_unit_type unit) 2303 { 2304 bool tick_sel = queue_id == 0 || queue_id == 2 || queue_id == 8; 2305 enum trtcm_param mode = TRTCM_METER_MODE; 2306 int err; 2307 2308 mode |= unit == TRTCM_PACKET_UNIT ? TRTCM_PKT_MODE : 0; 2309 err = airoha_qdma_set_rl_config(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2310 enable, mode); 2311 if (err) 2312 return err; 2313 2314 return airoha_qdma_set_rl_config(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2315 tick_sel, TRTCM_TICK_SEL); 2316 } 2317 2318 static int airoha_qdma_get_trtcm_param(struct airoha_qdma *qdma, int channel, 2319 u32 addr, enum trtcm_param_type param, 2320 enum trtcm_mode_type mode, 2321 u32 *val_low, u32 *val_high) 2322 { 2323 u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel); 2324 u32 val, config = FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) | 2325 FIELD_PREP(TRTCM_METER_GROUP_MASK, group) | 2326 FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) | 2327 FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode); 2328 2329 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2330 if (read_poll_timeout(airoha_qdma_rr, val, 2331 val & TRTCM_PARAM_RW_DONE_MASK, 2332 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2333 qdma, REG_TRTCM_CFG_PARAM(addr))) 2334 return -ETIMEDOUT; 2335 2336 *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr)); 2337 if (val_high) 2338 *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr)); 2339 2340 return 0; 2341 } 2342 2343 static int airoha_qdma_set_trtcm_param(struct airoha_qdma *qdma, int channel, 2344 u32 addr, enum trtcm_param_type param, 2345 enum trtcm_mode_type mode, u32 val) 2346 { 2347 u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel); 2348 u32 config = TRTCM_PARAM_RW_MASK | 2349 FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) | 2350 FIELD_PREP(TRTCM_METER_GROUP_MASK, group) | 2351 FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) | 2352 FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode); 2353 2354 airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val); 2355 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2356 2357 return read_poll_timeout(airoha_qdma_rr, val, 2358 val & TRTCM_PARAM_RW_DONE_MASK, 2359 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2360 qdma, REG_TRTCM_CFG_PARAM(addr)); 2361 } 2362 2363 static int airoha_qdma_set_trtcm_config(struct airoha_qdma *qdma, int channel, 2364 u32 addr, enum trtcm_mode_type mode, 2365 bool enable, u32 enable_mask) 2366 { 2367 u32 val; 2368 2369 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2370 mode, &val, NULL)) 2371 return -EINVAL; 2372 2373 val = enable ? val | enable_mask : val & ~enable_mask; 2374 2375 return airoha_qdma_set_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2376 mode, val); 2377 } 2378 2379 static int airoha_qdma_set_trtcm_token_bucket(struct airoha_qdma *qdma, 2380 int channel, u32 addr, 2381 enum trtcm_mode_type mode, 2382 u32 rate_val, u32 bucket_size) 2383 { 2384 u32 val, config, tick, unit, rate, rate_frac; 2385 int err; 2386 2387 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2388 mode, &config, NULL)) 2389 return -EINVAL; 2390 2391 val = airoha_qdma_rr(qdma, addr); 2392 tick = FIELD_GET(INGRESS_FAST_TICK_MASK, val); 2393 if (config & TRTCM_TICK_SEL) 2394 tick *= FIELD_GET(INGRESS_SLOW_TICK_RATIO_MASK, val); 2395 if (!tick) 2396 return -EINVAL; 2397 2398 unit = (config & TRTCM_PKT_MODE) ? 1000000 / tick : 8000 / tick; 2399 if (!unit) 2400 return -EINVAL; 2401 2402 rate = rate_val / unit; 2403 rate_frac = rate_val % unit; 2404 rate_frac = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate_frac) / unit; 2405 rate = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate) | 2406 FIELD_PREP(TRTCM_TOKEN_RATE_FRACTION_MASK, rate_frac); 2407 2408 err = airoha_qdma_set_trtcm_param(qdma, channel, addr, 2409 TRTCM_TOKEN_RATE_MODE, mode, rate); 2410 if (err) 2411 return err; 2412 2413 val = max_t(u32, bucket_size, MIN_TOKEN_SIZE); 2414 val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET); 2415 2416 return airoha_qdma_set_trtcm_param(qdma, channel, addr, 2417 TRTCM_BUCKETSIZE_SHIFT_MODE, 2418 mode, val); 2419 } 2420 2421 static int airoha_qdma_set_tx_rate_limit(struct airoha_gdm_port *port, 2422 int channel, u32 rate, 2423 u32 bucket_size) 2424 { 2425 int i, err; 2426 2427 for (i = 0; i <= TRTCM_PEAK_MODE; i++) { 2428 err = airoha_qdma_set_trtcm_config(port->qdma, channel, 2429 REG_EGRESS_TRTCM_CFG, i, 2430 !!rate, TRTCM_METER_MODE); 2431 if (err) 2432 return err; 2433 2434 err = airoha_qdma_set_trtcm_token_bucket(port->qdma, channel, 2435 REG_EGRESS_TRTCM_CFG, 2436 i, rate, bucket_size); 2437 if (err) 2438 return err; 2439 } 2440 2441 return 0; 2442 } 2443 2444 static int airoha_tc_htb_alloc_leaf_queue(struct airoha_gdm_port *port, 2445 struct tc_htb_qopt_offload *opt) 2446 { 2447 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2448 u32 rate = div_u64(opt->rate, 1000) << 3; /* kbps */ 2449 struct net_device *dev = port->dev; 2450 int num_tx_queues = dev->real_num_tx_queues; 2451 int err; 2452 2453 if (opt->parent_classid != TC_HTB_CLASSID_ROOT) { 2454 NL_SET_ERR_MSG_MOD(opt->extack, "invalid parent classid"); 2455 return -EINVAL; 2456 } 2457 2458 err = airoha_qdma_set_tx_rate_limit(port, channel, rate, opt->quantum); 2459 if (err) { 2460 NL_SET_ERR_MSG_MOD(opt->extack, 2461 "failed configuring htb offload"); 2462 return err; 2463 } 2464 2465 if (opt->command == TC_HTB_NODE_MODIFY) 2466 return 0; 2467 2468 err = netif_set_real_num_tx_queues(dev, num_tx_queues + 1); 2469 if (err) { 2470 airoha_qdma_set_tx_rate_limit(port, channel, 0, opt->quantum); 2471 NL_SET_ERR_MSG_MOD(opt->extack, 2472 "failed setting real_num_tx_queues"); 2473 return err; 2474 } 2475 2476 set_bit(channel, port->qos_sq_bmap); 2477 opt->qid = AIROHA_NUM_TX_RING + channel; 2478 2479 return 0; 2480 } 2481 2482 static int airoha_qdma_set_rx_meter(struct airoha_gdm_port *port, 2483 u32 rate, u32 bucket_size, 2484 enum trtcm_unit_type unit_type) 2485 { 2486 struct airoha_qdma *qdma = port->qdma; 2487 int i; 2488 2489 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 2490 int err; 2491 2492 if (!qdma->q_rx[i].ndesc) 2493 continue; 2494 2495 err = airoha_qdma_init_rl_config(qdma, i, !!rate, unit_type); 2496 if (err) 2497 return err; 2498 2499 err = airoha_qdma_set_rl_token_bucket(qdma, i, rate, 2500 bucket_size); 2501 if (err) 2502 return err; 2503 } 2504 2505 return 0; 2506 } 2507 2508 static int airoha_tc_matchall_act_validate(struct tc_cls_matchall_offload *f) 2509 { 2510 const struct flow_action *actions = &f->rule->action; 2511 const struct flow_action_entry *act; 2512 2513 if (!flow_action_has_entries(actions)) { 2514 NL_SET_ERR_MSG_MOD(f->common.extack, 2515 "filter run with no actions"); 2516 return -EINVAL; 2517 } 2518 2519 if (!flow_offload_has_one_action(actions)) { 2520 NL_SET_ERR_MSG_MOD(f->common.extack, 2521 "only once action per filter is supported"); 2522 return -EOPNOTSUPP; 2523 } 2524 2525 act = &actions->entries[0]; 2526 if (act->id != FLOW_ACTION_POLICE) { 2527 NL_SET_ERR_MSG_MOD(f->common.extack, "unsupported action"); 2528 return -EOPNOTSUPP; 2529 } 2530 2531 if (act->police.exceed.act_id != FLOW_ACTION_DROP) { 2532 NL_SET_ERR_MSG_MOD(f->common.extack, 2533 "invalid exceed action id"); 2534 return -EOPNOTSUPP; 2535 } 2536 2537 if (act->police.notexceed.act_id != FLOW_ACTION_ACCEPT) { 2538 NL_SET_ERR_MSG_MOD(f->common.extack, 2539 "invalid notexceed action id"); 2540 return -EOPNOTSUPP; 2541 } 2542 2543 if (act->police.notexceed.act_id == FLOW_ACTION_ACCEPT && 2544 !flow_action_is_last_entry(actions, act)) { 2545 NL_SET_ERR_MSG_MOD(f->common.extack, 2546 "action accept must be last"); 2547 return -EOPNOTSUPP; 2548 } 2549 2550 if (act->police.peakrate_bytes_ps || act->police.avrate || 2551 act->police.overhead || act->police.mtu) { 2552 NL_SET_ERR_MSG_MOD(f->common.extack, 2553 "peakrate/avrate/overhead/mtu unsupported"); 2554 return -EOPNOTSUPP; 2555 } 2556 2557 return 0; 2558 } 2559 2560 static int airoha_dev_tc_matchall(struct net_device *dev, 2561 struct tc_cls_matchall_offload *f) 2562 { 2563 enum trtcm_unit_type unit_type = TRTCM_BYTE_UNIT; 2564 struct airoha_gdm_port *port = netdev_priv(dev); 2565 u32 rate = 0, bucket_size = 0; 2566 2567 switch (f->command) { 2568 case TC_CLSMATCHALL_REPLACE: { 2569 const struct flow_action_entry *act; 2570 int err; 2571 2572 err = airoha_tc_matchall_act_validate(f); 2573 if (err) 2574 return err; 2575 2576 act = &f->rule->action.entries[0]; 2577 if (act->police.rate_pkt_ps) { 2578 rate = act->police.rate_pkt_ps; 2579 bucket_size = act->police.burst_pkt; 2580 unit_type = TRTCM_PACKET_UNIT; 2581 } else { 2582 rate = div_u64(act->police.rate_bytes_ps, 1000); 2583 rate = rate << 3; /* Kbps */ 2584 bucket_size = act->police.burst; 2585 } 2586 fallthrough; 2587 } 2588 case TC_CLSMATCHALL_DESTROY: 2589 return airoha_qdma_set_rx_meter(port, rate, bucket_size, 2590 unit_type); 2591 default: 2592 return -EOPNOTSUPP; 2593 } 2594 } 2595 2596 static int airoha_dev_setup_tc_block_cb(enum tc_setup_type type, 2597 void *type_data, void *cb_priv) 2598 { 2599 struct net_device *dev = cb_priv; 2600 2601 if (!tc_can_offload(dev)) 2602 return -EOPNOTSUPP; 2603 2604 switch (type) { 2605 case TC_SETUP_CLSFLOWER: 2606 return airoha_ppe_setup_tc_block_cb(dev, type_data); 2607 case TC_SETUP_CLSMATCHALL: 2608 return airoha_dev_tc_matchall(dev, type_data); 2609 default: 2610 return -EOPNOTSUPP; 2611 } 2612 } 2613 2614 static int airoha_dev_setup_tc_block(struct airoha_gdm_port *port, 2615 struct flow_block_offload *f) 2616 { 2617 flow_setup_cb_t *cb = airoha_dev_setup_tc_block_cb; 2618 static LIST_HEAD(block_cb_list); 2619 struct flow_block_cb *block_cb; 2620 2621 if (f->binder_type != FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 2622 return -EOPNOTSUPP; 2623 2624 f->driver_block_list = &block_cb_list; 2625 switch (f->command) { 2626 case FLOW_BLOCK_BIND: 2627 block_cb = flow_block_cb_lookup(f->block, cb, port->dev); 2628 if (block_cb) { 2629 flow_block_cb_incref(block_cb); 2630 return 0; 2631 } 2632 block_cb = flow_block_cb_alloc(cb, port->dev, port->dev, NULL); 2633 if (IS_ERR(block_cb)) 2634 return PTR_ERR(block_cb); 2635 2636 flow_block_cb_incref(block_cb); 2637 flow_block_cb_add(block_cb, f); 2638 list_add_tail(&block_cb->driver_list, &block_cb_list); 2639 return 0; 2640 case FLOW_BLOCK_UNBIND: 2641 block_cb = flow_block_cb_lookup(f->block, cb, port->dev); 2642 if (!block_cb) 2643 return -ENOENT; 2644 2645 if (!flow_block_cb_decref(block_cb)) { 2646 flow_block_cb_remove(block_cb, f); 2647 list_del(&block_cb->driver_list); 2648 } 2649 return 0; 2650 default: 2651 return -EOPNOTSUPP; 2652 } 2653 } 2654 2655 static void airoha_tc_remove_htb_queue(struct airoha_gdm_port *port, int queue) 2656 { 2657 struct net_device *dev = port->dev; 2658 2659 netif_set_real_num_tx_queues(dev, dev->real_num_tx_queues - 1); 2660 airoha_qdma_set_tx_rate_limit(port, queue + 1, 0, 0); 2661 clear_bit(queue, port->qos_sq_bmap); 2662 } 2663 2664 static int airoha_tc_htb_delete_leaf_queue(struct airoha_gdm_port *port, 2665 struct tc_htb_qopt_offload *opt) 2666 { 2667 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2668 2669 if (!test_bit(channel, port->qos_sq_bmap)) { 2670 NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id"); 2671 return -EINVAL; 2672 } 2673 2674 airoha_tc_remove_htb_queue(port, channel); 2675 2676 return 0; 2677 } 2678 2679 static int airoha_tc_htb_destroy(struct airoha_gdm_port *port) 2680 { 2681 int q; 2682 2683 for_each_set_bit(q, port->qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS) 2684 airoha_tc_remove_htb_queue(port, q); 2685 2686 return 0; 2687 } 2688 2689 static int airoha_tc_get_htb_get_leaf_queue(struct airoha_gdm_port *port, 2690 struct tc_htb_qopt_offload *opt) 2691 { 2692 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2693 2694 if (!test_bit(channel, port->qos_sq_bmap)) { 2695 NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id"); 2696 return -EINVAL; 2697 } 2698 2699 opt->qid = AIROHA_NUM_TX_RING + channel; 2700 2701 return 0; 2702 } 2703 2704 static int airoha_tc_setup_qdisc_htb(struct airoha_gdm_port *port, 2705 struct tc_htb_qopt_offload *opt) 2706 { 2707 switch (opt->command) { 2708 case TC_HTB_CREATE: 2709 break; 2710 case TC_HTB_DESTROY: 2711 return airoha_tc_htb_destroy(port); 2712 case TC_HTB_NODE_MODIFY: 2713 case TC_HTB_LEAF_ALLOC_QUEUE: 2714 return airoha_tc_htb_alloc_leaf_queue(port, opt); 2715 case TC_HTB_LEAF_DEL: 2716 case TC_HTB_LEAF_DEL_LAST: 2717 case TC_HTB_LEAF_DEL_LAST_FORCE: 2718 return airoha_tc_htb_delete_leaf_queue(port, opt); 2719 case TC_HTB_LEAF_QUERY_QUEUE: 2720 return airoha_tc_get_htb_get_leaf_queue(port, opt); 2721 default: 2722 return -EOPNOTSUPP; 2723 } 2724 2725 return 0; 2726 } 2727 2728 static int airoha_dev_tc_setup(struct net_device *dev, enum tc_setup_type type, 2729 void *type_data) 2730 { 2731 struct airoha_gdm_port *port = netdev_priv(dev); 2732 2733 switch (type) { 2734 case TC_SETUP_QDISC_ETS: 2735 return airoha_tc_setup_qdisc_ets(port, type_data); 2736 case TC_SETUP_QDISC_HTB: 2737 return airoha_tc_setup_qdisc_htb(port, type_data); 2738 case TC_SETUP_BLOCK: 2739 case TC_SETUP_FT: 2740 return airoha_dev_setup_tc_block(port, type_data); 2741 default: 2742 return -EOPNOTSUPP; 2743 } 2744 } 2745 2746 static const struct net_device_ops airoha_netdev_ops = { 2747 .ndo_init = airoha_dev_init, 2748 .ndo_open = airoha_dev_open, 2749 .ndo_stop = airoha_dev_stop, 2750 .ndo_change_mtu = airoha_dev_change_mtu, 2751 .ndo_select_queue = airoha_dev_select_queue, 2752 .ndo_start_xmit = airoha_dev_xmit, 2753 .ndo_get_stats64 = airoha_dev_get_stats64, 2754 .ndo_set_mac_address = airoha_dev_set_macaddr, 2755 .ndo_setup_tc = airoha_dev_tc_setup, 2756 }; 2757 2758 static const struct ethtool_ops airoha_ethtool_ops = { 2759 .get_drvinfo = airoha_ethtool_get_drvinfo, 2760 .get_eth_mac_stats = airoha_ethtool_get_mac_stats, 2761 .get_rmon_stats = airoha_ethtool_get_rmon_stats, 2762 }; 2763 2764 static int airoha_metadata_dst_alloc(struct airoha_gdm_port *port) 2765 { 2766 int i; 2767 2768 for (i = 0; i < ARRAY_SIZE(port->dsa_meta); i++) { 2769 struct metadata_dst *md_dst; 2770 2771 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, 2772 GFP_KERNEL); 2773 if (!md_dst) 2774 return -ENOMEM; 2775 2776 md_dst->u.port_info.port_id = i; 2777 port->dsa_meta[i] = md_dst; 2778 } 2779 2780 return 0; 2781 } 2782 2783 static void airoha_metadata_dst_free(struct airoha_gdm_port *port) 2784 { 2785 int i; 2786 2787 for (i = 0; i < ARRAY_SIZE(port->dsa_meta); i++) { 2788 if (!port->dsa_meta[i]) 2789 continue; 2790 2791 metadata_dst_free(port->dsa_meta[i]); 2792 } 2793 } 2794 2795 bool airoha_is_valid_gdm_port(struct airoha_eth *eth, 2796 struct airoha_gdm_port *port) 2797 { 2798 int i; 2799 2800 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 2801 if (eth->ports[i] == port) 2802 return true; 2803 } 2804 2805 return false; 2806 } 2807 2808 static int airoha_alloc_gdm_port(struct airoha_eth *eth, 2809 struct device_node *np, int index) 2810 { 2811 const __be32 *id_ptr = of_get_property(np, "reg", NULL); 2812 struct airoha_gdm_port *port; 2813 struct airoha_qdma *qdma; 2814 struct net_device *dev; 2815 int err, p; 2816 u32 id; 2817 2818 if (!id_ptr) { 2819 dev_err(eth->dev, "missing gdm port id\n"); 2820 return -EINVAL; 2821 } 2822 2823 id = be32_to_cpup(id_ptr); 2824 p = id - 1; 2825 2826 if (!id || id > ARRAY_SIZE(eth->ports)) { 2827 dev_err(eth->dev, "invalid gdm port id: %d\n", id); 2828 return -EINVAL; 2829 } 2830 2831 if (eth->ports[p]) { 2832 dev_err(eth->dev, "duplicate gdm port id: %d\n", id); 2833 return -EINVAL; 2834 } 2835 2836 dev = devm_alloc_etherdev_mqs(eth->dev, sizeof(*port), 2837 AIROHA_NUM_NETDEV_TX_RINGS, 2838 AIROHA_NUM_RX_RING); 2839 if (!dev) { 2840 dev_err(eth->dev, "alloc_etherdev failed\n"); 2841 return -ENOMEM; 2842 } 2843 2844 qdma = ð->qdma[index % AIROHA_MAX_NUM_QDMA]; 2845 dev->netdev_ops = &airoha_netdev_ops; 2846 dev->ethtool_ops = &airoha_ethtool_ops; 2847 dev->max_mtu = AIROHA_MAX_MTU; 2848 dev->watchdog_timeo = 5 * HZ; 2849 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 2850 NETIF_F_TSO6 | NETIF_F_IPV6_CSUM | 2851 NETIF_F_SG | NETIF_F_TSO | 2852 NETIF_F_HW_TC; 2853 dev->features |= dev->hw_features; 2854 dev->vlan_features = dev->hw_features; 2855 dev->dev.of_node = np; 2856 dev->irq = qdma->irq_banks[0].irq; 2857 SET_NETDEV_DEV(dev, eth->dev); 2858 2859 /* reserve hw queues for HTB offloading */ 2860 err = netif_set_real_num_tx_queues(dev, AIROHA_NUM_TX_RING); 2861 if (err) 2862 return err; 2863 2864 err = of_get_ethdev_address(np, dev); 2865 if (err) { 2866 if (err == -EPROBE_DEFER) 2867 return err; 2868 2869 eth_hw_addr_random(dev); 2870 dev_info(eth->dev, "generated random MAC address %pM\n", 2871 dev->dev_addr); 2872 } 2873 2874 port = netdev_priv(dev); 2875 u64_stats_init(&port->stats.syncp); 2876 spin_lock_init(&port->stats.lock); 2877 port->qdma = qdma; 2878 port->dev = dev; 2879 port->id = id; 2880 eth->ports[p] = port; 2881 2882 err = airoha_metadata_dst_alloc(port); 2883 if (err) 2884 return err; 2885 2886 err = register_netdev(dev); 2887 if (err) 2888 goto free_metadata_dst; 2889 2890 return 0; 2891 2892 free_metadata_dst: 2893 airoha_metadata_dst_free(port); 2894 return err; 2895 } 2896 2897 static int airoha_probe(struct platform_device *pdev) 2898 { 2899 struct device_node *np; 2900 struct airoha_eth *eth; 2901 int i, err; 2902 2903 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 2904 if (!eth) 2905 return -ENOMEM; 2906 2907 eth->dev = &pdev->dev; 2908 2909 err = dma_set_mask_and_coherent(eth->dev, DMA_BIT_MASK(32)); 2910 if (err) { 2911 dev_err(eth->dev, "failed configuring DMA mask\n"); 2912 return err; 2913 } 2914 2915 eth->fe_regs = devm_platform_ioremap_resource_byname(pdev, "fe"); 2916 if (IS_ERR(eth->fe_regs)) 2917 return dev_err_probe(eth->dev, PTR_ERR(eth->fe_regs), 2918 "failed to iomap fe regs\n"); 2919 2920 eth->rsts[0].id = "fe"; 2921 eth->rsts[1].id = "pdma"; 2922 eth->rsts[2].id = "qdma"; 2923 err = devm_reset_control_bulk_get_exclusive(eth->dev, 2924 ARRAY_SIZE(eth->rsts), 2925 eth->rsts); 2926 if (err) { 2927 dev_err(eth->dev, "failed to get bulk reset lines\n"); 2928 return err; 2929 } 2930 2931 eth->xsi_rsts[0].id = "xsi-mac"; 2932 eth->xsi_rsts[1].id = "hsi0-mac"; 2933 eth->xsi_rsts[2].id = "hsi1-mac"; 2934 eth->xsi_rsts[3].id = "hsi-mac"; 2935 eth->xsi_rsts[4].id = "xfp-mac"; 2936 err = devm_reset_control_bulk_get_exclusive(eth->dev, 2937 ARRAY_SIZE(eth->xsi_rsts), 2938 eth->xsi_rsts); 2939 if (err) { 2940 dev_err(eth->dev, "failed to get bulk xsi reset lines\n"); 2941 return err; 2942 } 2943 2944 eth->napi_dev = alloc_netdev_dummy(0); 2945 if (!eth->napi_dev) 2946 return -ENOMEM; 2947 2948 /* Enable threaded NAPI by default */ 2949 eth->napi_dev->threaded = true; 2950 strscpy(eth->napi_dev->name, "qdma_eth", sizeof(eth->napi_dev->name)); 2951 platform_set_drvdata(pdev, eth); 2952 2953 err = airoha_hw_init(pdev, eth); 2954 if (err) 2955 goto error_hw_cleanup; 2956 2957 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 2958 airoha_qdma_start_napi(ð->qdma[i]); 2959 2960 i = 0; 2961 for_each_child_of_node(pdev->dev.of_node, np) { 2962 if (!of_device_is_compatible(np, "airoha,eth-mac")) 2963 continue; 2964 2965 if (!of_device_is_available(np)) 2966 continue; 2967 2968 err = airoha_alloc_gdm_port(eth, np, i++); 2969 if (err) { 2970 of_node_put(np); 2971 goto error_napi_stop; 2972 } 2973 } 2974 2975 return 0; 2976 2977 error_napi_stop: 2978 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 2979 airoha_qdma_stop_napi(ð->qdma[i]); 2980 error_hw_cleanup: 2981 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 2982 airoha_hw_cleanup(ð->qdma[i]); 2983 2984 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 2985 struct airoha_gdm_port *port = eth->ports[i]; 2986 2987 if (port && port->dev->reg_state == NETREG_REGISTERED) { 2988 unregister_netdev(port->dev); 2989 airoha_metadata_dst_free(port); 2990 } 2991 } 2992 free_netdev(eth->napi_dev); 2993 platform_set_drvdata(pdev, NULL); 2994 2995 return err; 2996 } 2997 2998 static void airoha_remove(struct platform_device *pdev) 2999 { 3000 struct airoha_eth *eth = platform_get_drvdata(pdev); 3001 int i; 3002 3003 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) { 3004 airoha_qdma_stop_napi(ð->qdma[i]); 3005 airoha_hw_cleanup(ð->qdma[i]); 3006 } 3007 3008 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 3009 struct airoha_gdm_port *port = eth->ports[i]; 3010 3011 if (!port) 3012 continue; 3013 3014 airoha_dev_stop(port->dev); 3015 unregister_netdev(port->dev); 3016 airoha_metadata_dst_free(port); 3017 } 3018 free_netdev(eth->napi_dev); 3019 3020 airoha_ppe_deinit(eth); 3021 platform_set_drvdata(pdev, NULL); 3022 } 3023 3024 static const struct of_device_id of_airoha_match[] = { 3025 { .compatible = "airoha,en7581-eth" }, 3026 { /* sentinel */ } 3027 }; 3028 MODULE_DEVICE_TABLE(of, of_airoha_match); 3029 3030 static struct platform_driver airoha_driver = { 3031 .probe = airoha_probe, 3032 .remove = airoha_remove, 3033 .driver = { 3034 .name = KBUILD_MODNAME, 3035 .of_match_table = of_airoha_match, 3036 }, 3037 }; 3038 module_platform_driver(airoha_driver); 3039 3040 MODULE_LICENSE("GPL"); 3041 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 3042 MODULE_DESCRIPTION("Ethernet driver for Airoha SoC"); 3043