1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024 AIROHA Inc 4 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 5 */ 6 #include <linux/of.h> 7 #include <linux/of_net.h> 8 #include <linux/of_reserved_mem.h> 9 #include <linux/platform_device.h> 10 #include <linux/tcp.h> 11 #include <linux/u64_stats_sync.h> 12 #include <net/dst_metadata.h> 13 #include <net/page_pool/helpers.h> 14 #include <net/pkt_cls.h> 15 #include <uapi/linux/ppp_defs.h> 16 17 #include "airoha_regs.h" 18 #include "airoha_eth.h" 19 20 u32 airoha_rr(void __iomem *base, u32 offset) 21 { 22 return readl(base + offset); 23 } 24 25 void airoha_wr(void __iomem *base, u32 offset, u32 val) 26 { 27 writel(val, base + offset); 28 } 29 30 u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val) 31 { 32 val |= (airoha_rr(base, offset) & ~mask); 33 airoha_wr(base, offset, val); 34 35 return val; 36 } 37 38 static void airoha_qdma_set_irqmask(struct airoha_irq_bank *irq_bank, 39 int index, u32 clear, u32 set) 40 { 41 struct airoha_qdma *qdma = irq_bank->qdma; 42 int bank = irq_bank - &qdma->irq_banks[0]; 43 unsigned long flags; 44 45 if (WARN_ON_ONCE(index >= ARRAY_SIZE(irq_bank->irqmask))) 46 return; 47 48 spin_lock_irqsave(&irq_bank->irq_lock, flags); 49 50 irq_bank->irqmask[index] &= ~clear; 51 irq_bank->irqmask[index] |= set; 52 airoha_qdma_wr(qdma, REG_INT_ENABLE(bank, index), 53 irq_bank->irqmask[index]); 54 /* Read irq_enable register in order to guarantee the update above 55 * completes in the spinlock critical section. 56 */ 57 airoha_qdma_rr(qdma, REG_INT_ENABLE(bank, index)); 58 59 spin_unlock_irqrestore(&irq_bank->irq_lock, flags); 60 } 61 62 static void airoha_qdma_irq_enable(struct airoha_irq_bank *irq_bank, 63 int index, u32 mask) 64 { 65 airoha_qdma_set_irqmask(irq_bank, index, 0, mask); 66 } 67 68 static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank, 69 int index, u32 mask) 70 { 71 airoha_qdma_set_irqmask(irq_bank, index, mask, 0); 72 } 73 74 static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr) 75 { 76 struct airoha_eth *eth = port->qdma->eth; 77 u32 val, reg; 78 79 reg = airhoa_is_lan_gdm_port(port) ? REG_FE_LAN_MAC_H 80 : REG_FE_WAN_MAC_H; 81 val = (addr[0] << 16) | (addr[1] << 8) | addr[2]; 82 airoha_fe_wr(eth, reg, val); 83 84 val = (addr[3] << 16) | (addr[4] << 8) | addr[5]; 85 airoha_fe_wr(eth, REG_FE_MAC_LMIN(reg), val); 86 airoha_fe_wr(eth, REG_FE_MAC_LMAX(reg), val); 87 88 airoha_ppe_init_upd_mem(port); 89 } 90 91 static void airoha_set_gdm_port_fwd_cfg(struct airoha_eth *eth, u32 addr, 92 u32 val) 93 { 94 airoha_fe_rmw(eth, addr, GDM_OCFQ_MASK, 95 FIELD_PREP(GDM_OCFQ_MASK, val)); 96 airoha_fe_rmw(eth, addr, GDM_MCFQ_MASK, 97 FIELD_PREP(GDM_MCFQ_MASK, val)); 98 airoha_fe_rmw(eth, addr, GDM_BCFQ_MASK, 99 FIELD_PREP(GDM_BCFQ_MASK, val)); 100 airoha_fe_rmw(eth, addr, GDM_UCFQ_MASK, 101 FIELD_PREP(GDM_UCFQ_MASK, val)); 102 } 103 104 static int airoha_set_vip_for_gdm_port(struct airoha_gdm_port *port, 105 bool enable) 106 { 107 struct airoha_eth *eth = port->qdma->eth; 108 u32 vip_port; 109 110 switch (port->id) { 111 case AIROHA_GDM3_IDX: 112 /* FIXME: handle XSI_PCIE1_PORT */ 113 vip_port = XSI_PCIE0_VIP_PORT_MASK; 114 break; 115 case AIROHA_GDM4_IDX: 116 /* FIXME: handle XSI_USB_PORT */ 117 vip_port = XSI_ETH_VIP_PORT_MASK; 118 break; 119 default: 120 return 0; 121 } 122 123 if (enable) { 124 airoha_fe_set(eth, REG_FE_VIP_PORT_EN, vip_port); 125 airoha_fe_set(eth, REG_FE_IFC_PORT_EN, vip_port); 126 } else { 127 airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, vip_port); 128 airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, vip_port); 129 } 130 131 return 0; 132 } 133 134 static void airoha_fe_maccr_init(struct airoha_eth *eth) 135 { 136 int p; 137 138 for (p = 1; p <= ARRAY_SIZE(eth->ports); p++) 139 airoha_fe_set(eth, REG_GDM_FWD_CFG(p), 140 GDM_TCP_CKSUM_MASK | GDM_UDP_CKSUM_MASK | 141 GDM_IP4_CKSUM_MASK | GDM_DROP_CRC_ERR_MASK); 142 143 airoha_fe_rmw(eth, REG_CDM_VLAN_CTRL(1), CDM_VLAN_MASK, 144 FIELD_PREP(CDM_VLAN_MASK, 0x8100)); 145 146 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PAD); 147 } 148 149 static void airoha_fe_vip_setup(struct airoha_eth *eth) 150 { 151 airoha_fe_wr(eth, REG_FE_VIP_PATN(3), ETH_P_PPP_DISC); 152 airoha_fe_wr(eth, REG_FE_VIP_EN(3), PATN_FCPU_EN_MASK | PATN_EN_MASK); 153 154 airoha_fe_wr(eth, REG_FE_VIP_PATN(4), PPP_LCP); 155 airoha_fe_wr(eth, REG_FE_VIP_EN(4), 156 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 157 PATN_EN_MASK); 158 159 airoha_fe_wr(eth, REG_FE_VIP_PATN(6), PPP_IPCP); 160 airoha_fe_wr(eth, REG_FE_VIP_EN(6), 161 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 162 PATN_EN_MASK); 163 164 airoha_fe_wr(eth, REG_FE_VIP_PATN(7), PPP_CHAP); 165 airoha_fe_wr(eth, REG_FE_VIP_EN(7), 166 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 167 PATN_EN_MASK); 168 169 /* BOOTP (0x43) */ 170 airoha_fe_wr(eth, REG_FE_VIP_PATN(8), 0x43); 171 airoha_fe_wr(eth, REG_FE_VIP_EN(8), 172 PATN_FCPU_EN_MASK | PATN_SP_EN_MASK | 173 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 174 175 /* BOOTP (0x44) */ 176 airoha_fe_wr(eth, REG_FE_VIP_PATN(9), 0x44); 177 airoha_fe_wr(eth, REG_FE_VIP_EN(9), 178 PATN_FCPU_EN_MASK | PATN_SP_EN_MASK | 179 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 180 181 /* ISAKMP */ 182 airoha_fe_wr(eth, REG_FE_VIP_PATN(10), 0x1f401f4); 183 airoha_fe_wr(eth, REG_FE_VIP_EN(10), 184 PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK | 185 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 186 187 airoha_fe_wr(eth, REG_FE_VIP_PATN(11), PPP_IPV6CP); 188 airoha_fe_wr(eth, REG_FE_VIP_EN(11), 189 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 190 PATN_EN_MASK); 191 192 /* DHCPv6 */ 193 airoha_fe_wr(eth, REG_FE_VIP_PATN(12), 0x2220223); 194 airoha_fe_wr(eth, REG_FE_VIP_EN(12), 195 PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK | 196 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 197 198 airoha_fe_wr(eth, REG_FE_VIP_PATN(19), PPP_PAP); 199 airoha_fe_wr(eth, REG_FE_VIP_EN(19), 200 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 201 PATN_EN_MASK); 202 203 /* ETH->ETH_P_1905 (0x893a) */ 204 airoha_fe_wr(eth, REG_FE_VIP_PATN(20), 0x893a); 205 airoha_fe_wr(eth, REG_FE_VIP_EN(20), 206 PATN_FCPU_EN_MASK | PATN_EN_MASK); 207 208 airoha_fe_wr(eth, REG_FE_VIP_PATN(21), ETH_P_LLDP); 209 airoha_fe_wr(eth, REG_FE_VIP_EN(21), 210 PATN_FCPU_EN_MASK | PATN_EN_MASK); 211 } 212 213 static u32 airoha_fe_get_pse_queue_rsv_pages(struct airoha_eth *eth, 214 u32 port, u32 queue) 215 { 216 u32 val; 217 218 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR, 219 PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK, 220 FIELD_PREP(PSE_CFG_PORT_ID_MASK, port) | 221 FIELD_PREP(PSE_CFG_QUEUE_ID_MASK, queue)); 222 val = airoha_fe_rr(eth, REG_FE_PSE_QUEUE_CFG_VAL); 223 224 return FIELD_GET(PSE_CFG_OQ_RSV_MASK, val); 225 } 226 227 static void airoha_fe_set_pse_queue_rsv_pages(struct airoha_eth *eth, 228 u32 port, u32 queue, u32 val) 229 { 230 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_VAL, PSE_CFG_OQ_RSV_MASK, 231 FIELD_PREP(PSE_CFG_OQ_RSV_MASK, val)); 232 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR, 233 PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK | 234 PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK, 235 FIELD_PREP(PSE_CFG_PORT_ID_MASK, port) | 236 FIELD_PREP(PSE_CFG_QUEUE_ID_MASK, queue) | 237 PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK); 238 } 239 240 static u32 airoha_fe_get_pse_all_rsv(struct airoha_eth *eth) 241 { 242 u32 val = airoha_fe_rr(eth, REG_FE_PSE_BUF_SET); 243 244 return FIELD_GET(PSE_ALLRSV_MASK, val); 245 } 246 247 static int airoha_fe_set_pse_oq_rsv(struct airoha_eth *eth, 248 u32 port, u32 queue, u32 val) 249 { 250 u32 orig_val = airoha_fe_get_pse_queue_rsv_pages(eth, port, queue); 251 u32 tmp, all_rsv, fq_limit; 252 253 airoha_fe_set_pse_queue_rsv_pages(eth, port, queue, val); 254 255 /* modify all rsv */ 256 all_rsv = airoha_fe_get_pse_all_rsv(eth); 257 all_rsv += (val - orig_val); 258 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK, 259 FIELD_PREP(PSE_ALLRSV_MASK, all_rsv)); 260 261 /* modify hthd */ 262 tmp = airoha_fe_rr(eth, PSE_FQ_CFG); 263 fq_limit = FIELD_GET(PSE_FQ_LIMIT_MASK, tmp); 264 tmp = fq_limit - all_rsv - 0x20; 265 airoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD, 266 PSE_SHARE_USED_HTHD_MASK, 267 FIELD_PREP(PSE_SHARE_USED_HTHD_MASK, tmp)); 268 269 tmp = fq_limit - all_rsv - 0x100; 270 airoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD, 271 PSE_SHARE_USED_MTHD_MASK, 272 FIELD_PREP(PSE_SHARE_USED_MTHD_MASK, tmp)); 273 tmp = (3 * tmp) >> 2; 274 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, 275 PSE_SHARE_USED_LTHD_MASK, 276 FIELD_PREP(PSE_SHARE_USED_LTHD_MASK, tmp)); 277 278 return 0; 279 } 280 281 static void airoha_fe_pse_ports_init(struct airoha_eth *eth) 282 { 283 const u32 pse_port_num_queues[] = { 284 [FE_PSE_PORT_CDM1] = 6, 285 [FE_PSE_PORT_GDM1] = 6, 286 [FE_PSE_PORT_GDM2] = 32, 287 [FE_PSE_PORT_GDM3] = 6, 288 [FE_PSE_PORT_PPE1] = 4, 289 [FE_PSE_PORT_CDM2] = 6, 290 [FE_PSE_PORT_CDM3] = 8, 291 [FE_PSE_PORT_CDM4] = 10, 292 [FE_PSE_PORT_PPE2] = 4, 293 [FE_PSE_PORT_GDM4] = 2, 294 [FE_PSE_PORT_CDM5] = 2, 295 }; 296 u32 all_rsv; 297 int q; 298 299 all_rsv = airoha_fe_get_pse_all_rsv(eth); 300 if (airoha_ppe_is_enabled(eth, 1)) { 301 /* hw misses PPE2 oq rsv */ 302 all_rsv += PSE_RSV_PAGES * 303 pse_port_num_queues[FE_PSE_PORT_PPE2]; 304 } 305 airoha_fe_set(eth, REG_FE_PSE_BUF_SET, all_rsv); 306 307 /* CMD1 */ 308 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM1]; q++) 309 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM1, q, 310 PSE_QUEUE_RSV_PAGES); 311 /* GMD1 */ 312 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM1]; q++) 313 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM1, q, 314 PSE_QUEUE_RSV_PAGES); 315 /* GMD2 */ 316 for (q = 6; q < pse_port_num_queues[FE_PSE_PORT_GDM2]; q++) 317 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM2, q, 0); 318 /* GMD3 */ 319 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM3]; q++) 320 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM3, q, 321 PSE_QUEUE_RSV_PAGES); 322 /* PPE1 */ 323 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE1]; q++) { 324 if (q < pse_port_num_queues[FE_PSE_PORT_PPE1]) 325 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 326 PSE_QUEUE_RSV_PAGES); 327 else 328 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 0); 329 } 330 /* CDM2 */ 331 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM2]; q++) 332 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM2, q, 333 PSE_QUEUE_RSV_PAGES); 334 /* CDM3 */ 335 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM3] - 1; q++) 336 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM3, q, 0); 337 /* CDM4 */ 338 for (q = 4; q < pse_port_num_queues[FE_PSE_PORT_CDM4]; q++) 339 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM4, q, 340 PSE_QUEUE_RSV_PAGES); 341 if (airoha_ppe_is_enabled(eth, 1)) { 342 /* PPE2 */ 343 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE2]; q++) { 344 if (q < pse_port_num_queues[FE_PSE_PORT_PPE2] / 2) 345 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, 346 q, 347 PSE_QUEUE_RSV_PAGES); 348 else 349 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, 350 q, 0); 351 } 352 } 353 /* GMD4 */ 354 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM4]; q++) 355 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM4, q, 356 PSE_QUEUE_RSV_PAGES); 357 /* CDM5 */ 358 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM5]; q++) 359 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM5, q, 360 PSE_QUEUE_RSV_PAGES); 361 } 362 363 static int airoha_fe_mc_vlan_clear(struct airoha_eth *eth) 364 { 365 int i; 366 367 for (i = 0; i < AIROHA_FE_MC_MAX_VLAN_TABLE; i++) { 368 int err, j; 369 u32 val; 370 371 airoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0); 372 373 val = FIELD_PREP(MC_VLAN_CFG_TABLE_ID_MASK, i) | 374 MC_VLAN_CFG_TABLE_SEL_MASK | MC_VLAN_CFG_RW_MASK; 375 airoha_fe_wr(eth, REG_MC_VLAN_CFG, val); 376 err = read_poll_timeout(airoha_fe_rr, val, 377 val & MC_VLAN_CFG_CMD_DONE_MASK, 378 USEC_PER_MSEC, 5 * USEC_PER_MSEC, 379 false, eth, REG_MC_VLAN_CFG); 380 if (err) 381 return err; 382 383 for (j = 0; j < AIROHA_FE_MC_MAX_VLAN_PORT; j++) { 384 airoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0); 385 386 val = FIELD_PREP(MC_VLAN_CFG_TABLE_ID_MASK, i) | 387 FIELD_PREP(MC_VLAN_CFG_PORT_ID_MASK, j) | 388 MC_VLAN_CFG_RW_MASK; 389 airoha_fe_wr(eth, REG_MC_VLAN_CFG, val); 390 err = read_poll_timeout(airoha_fe_rr, val, 391 val & MC_VLAN_CFG_CMD_DONE_MASK, 392 USEC_PER_MSEC, 393 5 * USEC_PER_MSEC, false, eth, 394 REG_MC_VLAN_CFG); 395 if (err) 396 return err; 397 } 398 } 399 400 return 0; 401 } 402 403 static void airoha_fe_crsn_qsel_init(struct airoha_eth *eth) 404 { 405 /* CDM1_CRSN_QSEL */ 406 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_22 >> 2), 407 CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 408 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 409 CDM_CRSN_QSEL_Q1)); 410 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_08 >> 2), 411 CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 412 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 413 CDM_CRSN_QSEL_Q1)); 414 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_21 >> 2), 415 CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 416 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 417 CDM_CRSN_QSEL_Q1)); 418 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_24 >> 2), 419 CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 420 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 421 CDM_CRSN_QSEL_Q6)); 422 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_25 >> 2), 423 CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 424 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 425 CDM_CRSN_QSEL_Q1)); 426 /* CDM2_CRSN_QSEL */ 427 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_08 >> 2), 428 CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 429 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 430 CDM_CRSN_QSEL_Q1)); 431 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_21 >> 2), 432 CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 433 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 434 CDM_CRSN_QSEL_Q1)); 435 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_22 >> 2), 436 CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 437 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 438 CDM_CRSN_QSEL_Q1)); 439 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_24 >> 2), 440 CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 441 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 442 CDM_CRSN_QSEL_Q6)); 443 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_25 >> 2), 444 CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 445 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 446 CDM_CRSN_QSEL_Q1)); 447 } 448 449 static int airoha_fe_init(struct airoha_eth *eth) 450 { 451 airoha_fe_maccr_init(eth); 452 453 /* PSE IQ reserve */ 454 airoha_fe_rmw(eth, REG_PSE_IQ_REV1, PSE_IQ_RES1_P2_MASK, 455 FIELD_PREP(PSE_IQ_RES1_P2_MASK, 0x10)); 456 airoha_fe_rmw(eth, REG_PSE_IQ_REV2, 457 PSE_IQ_RES2_P5_MASK | PSE_IQ_RES2_P4_MASK, 458 FIELD_PREP(PSE_IQ_RES2_P5_MASK, 0x40) | 459 FIELD_PREP(PSE_IQ_RES2_P4_MASK, 0x34)); 460 461 /* enable FE copy engine for MC/KA/DPI */ 462 airoha_fe_wr(eth, REG_FE_PCE_CFG, 463 PCE_DPI_EN_MASK | PCE_KA_EN_MASK | PCE_MC_EN_MASK); 464 /* set vip queue selection to ring 1 */ 465 airoha_fe_rmw(eth, REG_CDM_FWD_CFG(1), CDM_VIP_QSEL_MASK, 466 FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4)); 467 airoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_VIP_QSEL_MASK, 468 FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4)); 469 /* set GDM4 source interface offset to 8 */ 470 airoha_fe_rmw(eth, REG_GDM_SRC_PORT_SET(4), 471 GDM_SPORT_OFF2_MASK | 472 GDM_SPORT_OFF1_MASK | 473 GDM_SPORT_OFF0_MASK, 474 FIELD_PREP(GDM_SPORT_OFF2_MASK, 8) | 475 FIELD_PREP(GDM_SPORT_OFF1_MASK, 8) | 476 FIELD_PREP(GDM_SPORT_OFF0_MASK, 8)); 477 478 /* set PSE Page as 128B */ 479 airoha_fe_rmw(eth, REG_FE_DMA_GLO_CFG, 480 FE_DMA_GLO_L2_SPACE_MASK | FE_DMA_GLO_PG_SZ_MASK, 481 FIELD_PREP(FE_DMA_GLO_L2_SPACE_MASK, 2) | 482 FE_DMA_GLO_PG_SZ_MASK); 483 airoha_fe_wr(eth, REG_FE_RST_GLO_CFG, 484 FE_RST_CORE_MASK | FE_RST_GDM3_MBI_ARB_MASK | 485 FE_RST_GDM4_MBI_ARB_MASK); 486 usleep_range(1000, 2000); 487 488 /* connect RxRing1 and RxRing15 to PSE Port0 OQ-1 489 * connect other rings to PSE Port0 OQ-0 490 */ 491 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP0, BIT(4)); 492 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP1, BIT(28)); 493 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP2, BIT(4)); 494 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP3, BIT(28)); 495 496 airoha_fe_vip_setup(eth); 497 airoha_fe_pse_ports_init(eth); 498 499 airoha_fe_set(eth, REG_GDM_MISC_CFG, 500 GDM2_RDM_ACK_WAIT_PREF_MASK | 501 GDM2_CHN_VLD_MODE_MASK); 502 airoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_OAM_QSEL_MASK, 503 FIELD_PREP(CDM_OAM_QSEL_MASK, 15)); 504 505 /* init fragment and assemble Force Port */ 506 /* NPU Core-3, NPU Bridge Channel-3 */ 507 airoha_fe_rmw(eth, REG_IP_FRAG_FP, 508 IP_FRAGMENT_PORT_MASK | IP_FRAGMENT_NBQ_MASK, 509 FIELD_PREP(IP_FRAGMENT_PORT_MASK, 6) | 510 FIELD_PREP(IP_FRAGMENT_NBQ_MASK, 3)); 511 /* QDMA LAN, RX Ring-22 */ 512 airoha_fe_rmw(eth, REG_IP_FRAG_FP, 513 IP_ASSEMBLE_PORT_MASK | IP_ASSEMBLE_NBQ_MASK, 514 FIELD_PREP(IP_ASSEMBLE_PORT_MASK, 0) | 515 FIELD_PREP(IP_ASSEMBLE_NBQ_MASK, 22)); 516 517 airoha_fe_set(eth, REG_GDM_FWD_CFG(AIROHA_GDM3_IDX), GDM_PAD_EN_MASK); 518 airoha_fe_set(eth, REG_GDM_FWD_CFG(AIROHA_GDM4_IDX), GDM_PAD_EN_MASK); 519 520 airoha_fe_crsn_qsel_init(eth); 521 522 airoha_fe_clear(eth, REG_FE_CPORT_CFG, FE_CPORT_QUEUE_XFC_MASK); 523 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PORT_XFC_MASK); 524 525 /* default aging mode for mbi unlock issue */ 526 airoha_fe_rmw(eth, REG_GDM_CHN_RLS(2), 527 MBI_RX_AGE_SEL_MASK | MBI_TX_AGE_SEL_MASK, 528 FIELD_PREP(MBI_RX_AGE_SEL_MASK, 3) | 529 FIELD_PREP(MBI_TX_AGE_SEL_MASK, 3)); 530 531 /* disable IFC by default */ 532 airoha_fe_clear(eth, REG_FE_CSR_IFC_CFG, FE_IFC_EN_MASK); 533 534 /* enable 1:N vlan action, init vlan table */ 535 airoha_fe_set(eth, REG_MC_VLAN_EN, MC_VLAN_EN_MASK); 536 537 return airoha_fe_mc_vlan_clear(eth); 538 } 539 540 static int airoha_qdma_fill_rx_queue(struct airoha_queue *q) 541 { 542 struct airoha_qdma *qdma = q->qdma; 543 int qid = q - &qdma->q_rx[0]; 544 int nframes = 0; 545 546 while (q->queued < q->ndesc - 1) { 547 struct airoha_queue_entry *e = &q->entry[q->head]; 548 struct airoha_qdma_desc *desc = &q->desc[q->head]; 549 struct page *page; 550 int offset; 551 u32 val; 552 553 page = page_pool_dev_alloc_frag(q->page_pool, &offset, 554 q->buf_size); 555 if (!page) 556 break; 557 558 q->head = (q->head + 1) % q->ndesc; 559 q->queued++; 560 nframes++; 561 562 e->buf = page_address(page) + offset; 563 e->dma_addr = page_pool_get_dma_addr(page) + offset; 564 e->dma_len = SKB_WITH_OVERHEAD(q->buf_size); 565 566 val = FIELD_PREP(QDMA_DESC_LEN_MASK, e->dma_len); 567 WRITE_ONCE(desc->ctrl, cpu_to_le32(val)); 568 WRITE_ONCE(desc->addr, cpu_to_le32(e->dma_addr)); 569 val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, q->head); 570 WRITE_ONCE(desc->data, cpu_to_le32(val)); 571 WRITE_ONCE(desc->msg0, 0); 572 WRITE_ONCE(desc->msg1, 0); 573 WRITE_ONCE(desc->msg2, 0); 574 WRITE_ONCE(desc->msg3, 0); 575 576 airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), 577 RX_RING_CPU_IDX_MASK, 578 FIELD_PREP(RX_RING_CPU_IDX_MASK, q->head)); 579 } 580 581 return nframes; 582 } 583 584 static int airoha_qdma_get_gdm_port(struct airoha_eth *eth, 585 struct airoha_qdma_desc *desc) 586 { 587 u32 port, sport, msg1 = le32_to_cpu(desc->msg1); 588 589 sport = FIELD_GET(QDMA_ETH_RXMSG_SPORT_MASK, msg1); 590 switch (sport) { 591 case 0x10 ... 0x14: 592 port = 0; 593 break; 594 case 0x2 ... 0x4: 595 port = sport - 1; 596 break; 597 default: 598 return -EINVAL; 599 } 600 601 return port >= ARRAY_SIZE(eth->ports) ? -EINVAL : port; 602 } 603 604 static int airoha_qdma_rx_process(struct airoha_queue *q, int budget) 605 { 606 enum dma_data_direction dir = page_pool_get_dma_dir(q->page_pool); 607 struct airoha_qdma *qdma = q->qdma; 608 struct airoha_eth *eth = qdma->eth; 609 int qid = q - &qdma->q_rx[0]; 610 int done = 0; 611 612 while (done < budget) { 613 struct airoha_queue_entry *e = &q->entry[q->tail]; 614 struct airoha_qdma_desc *desc = &q->desc[q->tail]; 615 u32 hash, reason, msg1 = le32_to_cpu(desc->msg1); 616 struct page *page = virt_to_head_page(e->buf); 617 u32 desc_ctrl = le32_to_cpu(desc->ctrl); 618 struct airoha_gdm_port *port; 619 int data_len, len, p; 620 621 if (!(desc_ctrl & QDMA_DESC_DONE_MASK)) 622 break; 623 624 q->tail = (q->tail + 1) % q->ndesc; 625 q->queued--; 626 627 dma_sync_single_for_cpu(eth->dev, e->dma_addr, 628 SKB_WITH_OVERHEAD(q->buf_size), dir); 629 630 len = FIELD_GET(QDMA_DESC_LEN_MASK, desc_ctrl); 631 data_len = q->skb ? q->buf_size 632 : SKB_WITH_OVERHEAD(q->buf_size); 633 if (!len || data_len < len) 634 goto free_frag; 635 636 p = airoha_qdma_get_gdm_port(eth, desc); 637 if (p < 0 || !eth->ports[p]) 638 goto free_frag; 639 640 port = eth->ports[p]; 641 if (!q->skb) { /* first buffer */ 642 q->skb = napi_build_skb(e->buf, q->buf_size); 643 if (!q->skb) 644 goto free_frag; 645 646 __skb_put(q->skb, len); 647 skb_mark_for_recycle(q->skb); 648 q->skb->dev = port->dev; 649 q->skb->protocol = eth_type_trans(q->skb, port->dev); 650 q->skb->ip_summed = CHECKSUM_UNNECESSARY; 651 skb_record_rx_queue(q->skb, qid); 652 } else { /* scattered frame */ 653 struct skb_shared_info *shinfo = skb_shinfo(q->skb); 654 int nr_frags = shinfo->nr_frags; 655 656 if (nr_frags >= ARRAY_SIZE(shinfo->frags)) 657 goto free_frag; 658 659 skb_add_rx_frag(q->skb, nr_frags, page, 660 e->buf - page_address(page), len, 661 q->buf_size); 662 } 663 664 if (FIELD_GET(QDMA_DESC_MORE_MASK, desc_ctrl)) 665 continue; 666 667 if (netdev_uses_dsa(port->dev)) { 668 /* PPE module requires untagged packets to work 669 * properly and it provides DSA port index via the 670 * DMA descriptor. Report DSA tag to the DSA stack 671 * via skb dst info. 672 */ 673 u32 sptag = FIELD_GET(QDMA_ETH_RXMSG_SPTAG, 674 le32_to_cpu(desc->msg0)); 675 676 if (sptag < ARRAY_SIZE(port->dsa_meta) && 677 port->dsa_meta[sptag]) 678 skb_dst_set_noref(q->skb, 679 &port->dsa_meta[sptag]->dst); 680 } 681 682 hash = FIELD_GET(AIROHA_RXD4_FOE_ENTRY, msg1); 683 if (hash != AIROHA_RXD4_FOE_ENTRY) 684 skb_set_hash(q->skb, jhash_1word(hash, 0), 685 PKT_HASH_TYPE_L4); 686 687 reason = FIELD_GET(AIROHA_RXD4_PPE_CPU_REASON, msg1); 688 if (reason == PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 689 airoha_ppe_check_skb(ð->ppe->dev, q->skb, hash, 690 false); 691 692 done++; 693 napi_gro_receive(&q->napi, q->skb); 694 q->skb = NULL; 695 continue; 696 free_frag: 697 if (q->skb) { 698 dev_kfree_skb(q->skb); 699 q->skb = NULL; 700 } else { 701 page_pool_put_full_page(q->page_pool, page, true); 702 } 703 } 704 airoha_qdma_fill_rx_queue(q); 705 706 return done; 707 } 708 709 static int airoha_qdma_rx_napi_poll(struct napi_struct *napi, int budget) 710 { 711 struct airoha_queue *q = container_of(napi, struct airoha_queue, napi); 712 int cur, done = 0; 713 714 do { 715 cur = airoha_qdma_rx_process(q, budget - done); 716 done += cur; 717 } while (cur && done < budget); 718 719 if (done < budget && napi_complete(napi)) { 720 struct airoha_qdma *qdma = q->qdma; 721 int i, qid = q - &qdma->q_rx[0]; 722 int intr_reg = qid < RX_DONE_HIGH_OFFSET ? QDMA_INT_REG_IDX1 723 : QDMA_INT_REG_IDX2; 724 725 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 726 if (!(BIT(qid) & RX_IRQ_BANK_PIN_MASK(i))) 727 continue; 728 729 airoha_qdma_irq_enable(&qdma->irq_banks[i], intr_reg, 730 BIT(qid % RX_DONE_HIGH_OFFSET)); 731 } 732 } 733 734 return done; 735 } 736 737 static int airoha_qdma_init_rx_queue(struct airoha_queue *q, 738 struct airoha_qdma *qdma, int ndesc) 739 { 740 const struct page_pool_params pp_params = { 741 .order = 0, 742 .pool_size = 256, 743 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 744 .dma_dir = DMA_FROM_DEVICE, 745 .max_len = PAGE_SIZE, 746 .nid = NUMA_NO_NODE, 747 .dev = qdma->eth->dev, 748 .napi = &q->napi, 749 }; 750 struct airoha_eth *eth = qdma->eth; 751 int qid = q - &qdma->q_rx[0], thr; 752 dma_addr_t dma_addr; 753 754 q->buf_size = PAGE_SIZE / 2; 755 q->ndesc = ndesc; 756 q->qdma = qdma; 757 758 q->entry = devm_kzalloc(eth->dev, q->ndesc * sizeof(*q->entry), 759 GFP_KERNEL); 760 if (!q->entry) 761 return -ENOMEM; 762 763 q->page_pool = page_pool_create(&pp_params); 764 if (IS_ERR(q->page_pool)) { 765 int err = PTR_ERR(q->page_pool); 766 767 q->page_pool = NULL; 768 return err; 769 } 770 771 q->desc = dmam_alloc_coherent(eth->dev, q->ndesc * sizeof(*q->desc), 772 &dma_addr, GFP_KERNEL); 773 if (!q->desc) 774 return -ENOMEM; 775 776 netif_napi_add(eth->napi_dev, &q->napi, airoha_qdma_rx_napi_poll); 777 778 airoha_qdma_wr(qdma, REG_RX_RING_BASE(qid), dma_addr); 779 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), 780 RX_RING_SIZE_MASK, 781 FIELD_PREP(RX_RING_SIZE_MASK, ndesc)); 782 783 thr = clamp(ndesc >> 3, 1, 32); 784 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), RX_RING_THR_MASK, 785 FIELD_PREP(RX_RING_THR_MASK, thr)); 786 airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK, 787 FIELD_PREP(RX_RING_DMA_IDX_MASK, q->head)); 788 airoha_qdma_set(qdma, REG_RX_SCATTER_CFG(qid), RX_RING_SG_EN_MASK); 789 790 airoha_qdma_fill_rx_queue(q); 791 792 return 0; 793 } 794 795 static void airoha_qdma_cleanup_rx_queue(struct airoha_queue *q) 796 { 797 struct airoha_eth *eth = q->qdma->eth; 798 799 while (q->queued) { 800 struct airoha_queue_entry *e = &q->entry[q->tail]; 801 struct page *page = virt_to_head_page(e->buf); 802 803 dma_sync_single_for_cpu(eth->dev, e->dma_addr, e->dma_len, 804 page_pool_get_dma_dir(q->page_pool)); 805 page_pool_put_full_page(q->page_pool, page, false); 806 q->tail = (q->tail + 1) % q->ndesc; 807 q->queued--; 808 } 809 } 810 811 static int airoha_qdma_init_rx(struct airoha_qdma *qdma) 812 { 813 int i; 814 815 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 816 int err; 817 818 if (!(RX_DONE_INT_MASK & BIT(i))) { 819 /* rx-queue not binded to irq */ 820 continue; 821 } 822 823 err = airoha_qdma_init_rx_queue(&qdma->q_rx[i], qdma, 824 RX_DSCP_NUM(i)); 825 if (err) 826 return err; 827 } 828 829 return 0; 830 } 831 832 static int airoha_qdma_tx_napi_poll(struct napi_struct *napi, int budget) 833 { 834 struct airoha_tx_irq_queue *irq_q; 835 int id, done = 0, irq_queued; 836 struct airoha_qdma *qdma; 837 struct airoha_eth *eth; 838 u32 status, head; 839 840 irq_q = container_of(napi, struct airoha_tx_irq_queue, napi); 841 qdma = irq_q->qdma; 842 id = irq_q - &qdma->q_tx_irq[0]; 843 eth = qdma->eth; 844 845 status = airoha_qdma_rr(qdma, REG_IRQ_STATUS(id)); 846 head = FIELD_GET(IRQ_HEAD_IDX_MASK, status); 847 head = head % irq_q->size; 848 irq_queued = FIELD_GET(IRQ_ENTRY_LEN_MASK, status); 849 850 while (irq_queued > 0 && done < budget) { 851 u32 qid, val = irq_q->q[head]; 852 struct airoha_qdma_desc *desc; 853 struct airoha_queue_entry *e; 854 struct airoha_queue *q; 855 u32 index, desc_ctrl; 856 struct sk_buff *skb; 857 858 if (val == 0xff) 859 break; 860 861 irq_q->q[head] = 0xff; /* mark as done */ 862 head = (head + 1) % irq_q->size; 863 irq_queued--; 864 done++; 865 866 qid = FIELD_GET(IRQ_RING_IDX_MASK, val); 867 if (qid >= ARRAY_SIZE(qdma->q_tx)) 868 continue; 869 870 q = &qdma->q_tx[qid]; 871 if (!q->ndesc) 872 continue; 873 874 index = FIELD_GET(IRQ_DESC_IDX_MASK, val); 875 if (index >= q->ndesc) 876 continue; 877 878 spin_lock_bh(&q->lock); 879 880 if (!q->queued) 881 goto unlock; 882 883 desc = &q->desc[index]; 884 desc_ctrl = le32_to_cpu(desc->ctrl); 885 886 if (!(desc_ctrl & QDMA_DESC_DONE_MASK) && 887 !(desc_ctrl & QDMA_DESC_DROP_MASK)) 888 goto unlock; 889 890 e = &q->entry[index]; 891 skb = e->skb; 892 893 dma_unmap_single(eth->dev, e->dma_addr, e->dma_len, 894 DMA_TO_DEVICE); 895 e->dma_addr = 0; 896 list_add_tail(&e->list, &q->tx_list); 897 898 WRITE_ONCE(desc->msg0, 0); 899 WRITE_ONCE(desc->msg1, 0); 900 q->queued--; 901 902 if (skb) { 903 u16 queue = skb_get_queue_mapping(skb); 904 struct netdev_queue *txq; 905 906 txq = netdev_get_tx_queue(skb->dev, queue); 907 netdev_tx_completed_queue(txq, 1, skb->len); 908 if (netif_tx_queue_stopped(txq) && 909 q->ndesc - q->queued >= q->free_thr) 910 netif_tx_wake_queue(txq); 911 912 dev_kfree_skb_any(skb); 913 } 914 unlock: 915 spin_unlock_bh(&q->lock); 916 } 917 918 if (done) { 919 int i, len = done >> 7; 920 921 for (i = 0; i < len; i++) 922 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id), 923 IRQ_CLEAR_LEN_MASK, 0x80); 924 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id), 925 IRQ_CLEAR_LEN_MASK, (done & 0x7f)); 926 } 927 928 if (done < budget && napi_complete(napi)) 929 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0, 930 TX_DONE_INT_MASK(id)); 931 932 return done; 933 } 934 935 static int airoha_qdma_init_tx_queue(struct airoha_queue *q, 936 struct airoha_qdma *qdma, int size) 937 { 938 struct airoha_eth *eth = qdma->eth; 939 int i, qid = q - &qdma->q_tx[0]; 940 dma_addr_t dma_addr; 941 942 spin_lock_init(&q->lock); 943 q->ndesc = size; 944 q->qdma = qdma; 945 q->free_thr = 1 + MAX_SKB_FRAGS; 946 INIT_LIST_HEAD(&q->tx_list); 947 948 q->entry = devm_kzalloc(eth->dev, q->ndesc * sizeof(*q->entry), 949 GFP_KERNEL); 950 if (!q->entry) 951 return -ENOMEM; 952 953 q->desc = dmam_alloc_coherent(eth->dev, q->ndesc * sizeof(*q->desc), 954 &dma_addr, GFP_KERNEL); 955 if (!q->desc) 956 return -ENOMEM; 957 958 for (i = 0; i < q->ndesc; i++) { 959 u32 val = FIELD_PREP(QDMA_DESC_DONE_MASK, 1); 960 961 list_add_tail(&q->entry[i].list, &q->tx_list); 962 WRITE_ONCE(q->desc[i].ctrl, cpu_to_le32(val)); 963 } 964 965 /* xmit ring drop default setting */ 966 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(qid), 967 TX_RING_IRQ_BLOCKING_TX_DROP_EN_MASK); 968 969 airoha_qdma_wr(qdma, REG_TX_RING_BASE(qid), dma_addr); 970 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK, 971 FIELD_PREP(TX_RING_CPU_IDX_MASK, 0)); 972 airoha_qdma_rmw(qdma, REG_TX_DMA_IDX(qid), TX_RING_DMA_IDX_MASK, 973 FIELD_PREP(TX_RING_DMA_IDX_MASK, 0)); 974 975 return 0; 976 } 977 978 static int airoha_qdma_tx_irq_init(struct airoha_tx_irq_queue *irq_q, 979 struct airoha_qdma *qdma, int size) 980 { 981 int id = irq_q - &qdma->q_tx_irq[0]; 982 struct airoha_eth *eth = qdma->eth; 983 dma_addr_t dma_addr; 984 985 netif_napi_add_tx(eth->napi_dev, &irq_q->napi, 986 airoha_qdma_tx_napi_poll); 987 irq_q->q = dmam_alloc_coherent(eth->dev, size * sizeof(u32), 988 &dma_addr, GFP_KERNEL); 989 if (!irq_q->q) 990 return -ENOMEM; 991 992 memset(irq_q->q, 0xff, size * sizeof(u32)); 993 irq_q->size = size; 994 irq_q->qdma = qdma; 995 996 airoha_qdma_wr(qdma, REG_TX_IRQ_BASE(id), dma_addr); 997 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_DEPTH_MASK, 998 FIELD_PREP(TX_IRQ_DEPTH_MASK, size)); 999 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_THR_MASK, 1000 FIELD_PREP(TX_IRQ_THR_MASK, 1)); 1001 1002 return 0; 1003 } 1004 1005 static int airoha_qdma_init_tx(struct airoha_qdma *qdma) 1006 { 1007 int i, err; 1008 1009 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) { 1010 err = airoha_qdma_tx_irq_init(&qdma->q_tx_irq[i], qdma, 1011 IRQ_QUEUE_LEN(i)); 1012 if (err) 1013 return err; 1014 } 1015 1016 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1017 err = airoha_qdma_init_tx_queue(&qdma->q_tx[i], qdma, 1018 TX_DSCP_NUM); 1019 if (err) 1020 return err; 1021 } 1022 1023 return 0; 1024 } 1025 1026 static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q) 1027 { 1028 struct airoha_eth *eth = q->qdma->eth; 1029 int i; 1030 1031 spin_lock_bh(&q->lock); 1032 for (i = 0; i < q->ndesc; i++) { 1033 struct airoha_queue_entry *e = &q->entry[i]; 1034 1035 if (!e->dma_addr) 1036 continue; 1037 1038 dma_unmap_single(eth->dev, e->dma_addr, e->dma_len, 1039 DMA_TO_DEVICE); 1040 dev_kfree_skb_any(e->skb); 1041 e->dma_addr = 0; 1042 e->skb = NULL; 1043 list_add_tail(&e->list, &q->tx_list); 1044 q->queued--; 1045 } 1046 spin_unlock_bh(&q->lock); 1047 } 1048 1049 static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma) 1050 { 1051 int size, index, num_desc = HW_DSCP_NUM; 1052 struct airoha_eth *eth = qdma->eth; 1053 int id = qdma - ð->qdma[0]; 1054 u32 status, buf_size; 1055 dma_addr_t dma_addr; 1056 const char *name; 1057 1058 name = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d-buf", id); 1059 if (!name) 1060 return -ENOMEM; 1061 1062 buf_size = id ? AIROHA_MAX_PACKET_SIZE / 2 : AIROHA_MAX_PACKET_SIZE; 1063 index = of_property_match_string(eth->dev->of_node, 1064 "memory-region-names", name); 1065 if (index >= 0) { 1066 struct reserved_mem *rmem; 1067 struct device_node *np; 1068 1069 /* Consume reserved memory for hw forwarding buffers queue if 1070 * available in the DTS 1071 */ 1072 np = of_parse_phandle(eth->dev->of_node, "memory-region", 1073 index); 1074 if (!np) 1075 return -ENODEV; 1076 1077 rmem = of_reserved_mem_lookup(np); 1078 of_node_put(np); 1079 dma_addr = rmem->base; 1080 /* Compute the number of hw descriptors according to the 1081 * reserved memory size and the payload buffer size 1082 */ 1083 num_desc = div_u64(rmem->size, buf_size); 1084 } else { 1085 size = buf_size * num_desc; 1086 if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, 1087 GFP_KERNEL)) 1088 return -ENOMEM; 1089 } 1090 1091 airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr); 1092 1093 size = num_desc * sizeof(struct airoha_qdma_fwd_desc); 1094 if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, GFP_KERNEL)) 1095 return -ENOMEM; 1096 1097 airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr); 1098 /* QDMA0: 2KB. QDMA1: 1KB */ 1099 airoha_qdma_rmw(qdma, REG_HW_FWD_DSCP_CFG, 1100 HW_FWD_DSCP_PAYLOAD_SIZE_MASK, 1101 FIELD_PREP(HW_FWD_DSCP_PAYLOAD_SIZE_MASK, !!id)); 1102 airoha_qdma_rmw(qdma, REG_FWD_DSCP_LOW_THR, FWD_DSCP_LOW_THR_MASK, 1103 FIELD_PREP(FWD_DSCP_LOW_THR_MASK, 128)); 1104 airoha_qdma_rmw(qdma, REG_LMGR_INIT_CFG, 1105 LMGR_INIT_START | LMGR_SRAM_MODE_MASK | 1106 HW_FWD_DESC_NUM_MASK, 1107 FIELD_PREP(HW_FWD_DESC_NUM_MASK, num_desc) | 1108 LMGR_INIT_START | LMGR_SRAM_MODE_MASK); 1109 1110 return read_poll_timeout(airoha_qdma_rr, status, 1111 !(status & LMGR_INIT_START), USEC_PER_MSEC, 1112 30 * USEC_PER_MSEC, true, qdma, 1113 REG_LMGR_INIT_CFG); 1114 } 1115 1116 static void airoha_qdma_init_qos(struct airoha_qdma *qdma) 1117 { 1118 airoha_qdma_clear(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_SCALE_MASK); 1119 airoha_qdma_set(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_BASE_MASK); 1120 1121 airoha_qdma_clear(qdma, REG_PSE_BUF_USAGE_CFG, 1122 PSE_BUF_ESTIMATE_EN_MASK); 1123 1124 airoha_qdma_set(qdma, REG_EGRESS_RATE_METER_CFG, 1125 EGRESS_RATE_METER_EN_MASK | 1126 EGRESS_RATE_METER_EQ_RATE_EN_MASK); 1127 /* 2047us x 31 = 63.457ms */ 1128 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG, 1129 EGRESS_RATE_METER_WINDOW_SZ_MASK, 1130 FIELD_PREP(EGRESS_RATE_METER_WINDOW_SZ_MASK, 0x1f)); 1131 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG, 1132 EGRESS_RATE_METER_TIMESLICE_MASK, 1133 FIELD_PREP(EGRESS_RATE_METER_TIMESLICE_MASK, 0x7ff)); 1134 1135 /* ratelimit init */ 1136 airoha_qdma_set(qdma, REG_GLB_TRTCM_CFG, GLB_TRTCM_EN_MASK); 1137 /* fast-tick 25us */ 1138 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_FAST_TICK_MASK, 1139 FIELD_PREP(GLB_FAST_TICK_MASK, 25)); 1140 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_SLOW_TICK_RATIO_MASK, 1141 FIELD_PREP(GLB_SLOW_TICK_RATIO_MASK, 40)); 1142 1143 airoha_qdma_set(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_TRTCM_EN_MASK); 1144 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_FAST_TICK_MASK, 1145 FIELD_PREP(EGRESS_FAST_TICK_MASK, 25)); 1146 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG, 1147 EGRESS_SLOW_TICK_RATIO_MASK, 1148 FIELD_PREP(EGRESS_SLOW_TICK_RATIO_MASK, 40)); 1149 1150 airoha_qdma_set(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_TRTCM_EN_MASK); 1151 airoha_qdma_clear(qdma, REG_INGRESS_TRTCM_CFG, 1152 INGRESS_TRTCM_MODE_MASK); 1153 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_FAST_TICK_MASK, 1154 FIELD_PREP(INGRESS_FAST_TICK_MASK, 125)); 1155 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG, 1156 INGRESS_SLOW_TICK_RATIO_MASK, 1157 FIELD_PREP(INGRESS_SLOW_TICK_RATIO_MASK, 8)); 1158 1159 airoha_qdma_set(qdma, REG_SLA_TRTCM_CFG, SLA_TRTCM_EN_MASK); 1160 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_FAST_TICK_MASK, 1161 FIELD_PREP(SLA_FAST_TICK_MASK, 25)); 1162 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_SLOW_TICK_RATIO_MASK, 1163 FIELD_PREP(SLA_SLOW_TICK_RATIO_MASK, 40)); 1164 } 1165 1166 static void airoha_qdma_init_qos_stats(struct airoha_qdma *qdma) 1167 { 1168 int i; 1169 1170 for (i = 0; i < AIROHA_NUM_QOS_CHANNELS; i++) { 1171 /* Tx-cpu transferred count */ 1172 airoha_qdma_wr(qdma, REG_CNTR_VAL(i << 1), 0); 1173 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1), 1174 CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK | 1175 CNTR_ALL_DSCP_RING_EN_MASK | 1176 FIELD_PREP(CNTR_CHAN_MASK, i)); 1177 /* Tx-fwd transferred count */ 1178 airoha_qdma_wr(qdma, REG_CNTR_VAL((i << 1) + 1), 0); 1179 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1), 1180 CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK | 1181 CNTR_ALL_DSCP_RING_EN_MASK | 1182 FIELD_PREP(CNTR_SRC_MASK, 1) | 1183 FIELD_PREP(CNTR_CHAN_MASK, i)); 1184 } 1185 } 1186 1187 static int airoha_qdma_hw_init(struct airoha_qdma *qdma) 1188 { 1189 int i; 1190 1191 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 1192 /* clear pending irqs */ 1193 airoha_qdma_wr(qdma, REG_INT_STATUS(i), 0xffffffff); 1194 /* setup rx irqs */ 1195 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX0, 1196 INT_RX0_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1197 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX1, 1198 INT_RX1_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1199 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX2, 1200 INT_RX2_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1201 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX3, 1202 INT_RX3_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1203 } 1204 /* setup tx irqs */ 1205 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0, 1206 TX_COHERENT_LOW_INT_MASK | INT_TX_MASK); 1207 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX4, 1208 TX_COHERENT_HIGH_INT_MASK); 1209 1210 /* setup irq binding */ 1211 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1212 if (!qdma->q_tx[i].ndesc) 1213 continue; 1214 1215 if (TX_RING_IRQ_BLOCKING_MAP_MASK & BIT(i)) 1216 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(i), 1217 TX_RING_IRQ_BLOCKING_CFG_MASK); 1218 else 1219 airoha_qdma_clear(qdma, REG_TX_RING_BLOCKING(i), 1220 TX_RING_IRQ_BLOCKING_CFG_MASK); 1221 } 1222 1223 airoha_qdma_wr(qdma, REG_QDMA_GLOBAL_CFG, 1224 FIELD_PREP(GLOBAL_CFG_DMA_PREFERENCE_MASK, 3) | 1225 GLOBAL_CFG_CPU_TXR_RR_MASK | 1226 GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK | 1227 GLOBAL_CFG_MULTICAST_MODIFY_FP_MASK | 1228 GLOBAL_CFG_MULTICAST_EN_MASK | 1229 GLOBAL_CFG_IRQ0_EN_MASK | GLOBAL_CFG_IRQ1_EN_MASK | 1230 GLOBAL_CFG_TX_WB_DONE_MASK | 1231 FIELD_PREP(GLOBAL_CFG_MAX_ISSUE_NUM_MASK, 2)); 1232 1233 airoha_qdma_init_qos(qdma); 1234 1235 /* disable qdma rx delay interrupt */ 1236 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1237 if (!qdma->q_rx[i].ndesc) 1238 continue; 1239 1240 airoha_qdma_clear(qdma, REG_RX_DELAY_INT_IDX(i), 1241 RX_DELAY_INT_MASK); 1242 } 1243 1244 airoha_qdma_set(qdma, REG_TXQ_CNGST_CFG, 1245 TXQ_CNGST_DROP_EN | TXQ_CNGST_DEI_DROP_EN); 1246 airoha_qdma_init_qos_stats(qdma); 1247 1248 return 0; 1249 } 1250 1251 static irqreturn_t airoha_irq_handler(int irq, void *dev_instance) 1252 { 1253 struct airoha_irq_bank *irq_bank = dev_instance; 1254 struct airoha_qdma *qdma = irq_bank->qdma; 1255 u32 rx_intr_mask = 0, rx_intr1, rx_intr2; 1256 u32 intr[ARRAY_SIZE(irq_bank->irqmask)]; 1257 int i; 1258 1259 for (i = 0; i < ARRAY_SIZE(intr); i++) { 1260 intr[i] = airoha_qdma_rr(qdma, REG_INT_STATUS(i)); 1261 intr[i] &= irq_bank->irqmask[i]; 1262 airoha_qdma_wr(qdma, REG_INT_STATUS(i), intr[i]); 1263 } 1264 1265 if (!test_bit(DEV_STATE_INITIALIZED, &qdma->eth->state)) 1266 return IRQ_NONE; 1267 1268 rx_intr1 = intr[1] & RX_DONE_LOW_INT_MASK; 1269 if (rx_intr1) { 1270 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX1, rx_intr1); 1271 rx_intr_mask |= rx_intr1; 1272 } 1273 1274 rx_intr2 = intr[2] & RX_DONE_HIGH_INT_MASK; 1275 if (rx_intr2) { 1276 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX2, rx_intr2); 1277 rx_intr_mask |= (rx_intr2 << 16); 1278 } 1279 1280 for (i = 0; rx_intr_mask && i < ARRAY_SIZE(qdma->q_rx); i++) { 1281 if (!qdma->q_rx[i].ndesc) 1282 continue; 1283 1284 if (rx_intr_mask & BIT(i)) 1285 napi_schedule(&qdma->q_rx[i].napi); 1286 } 1287 1288 if (intr[0] & INT_TX_MASK) { 1289 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) { 1290 if (!(intr[0] & TX_DONE_INT_MASK(i))) 1291 continue; 1292 1293 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX0, 1294 TX_DONE_INT_MASK(i)); 1295 napi_schedule(&qdma->q_tx_irq[i].napi); 1296 } 1297 } 1298 1299 return IRQ_HANDLED; 1300 } 1301 1302 static int airoha_qdma_init_irq_banks(struct platform_device *pdev, 1303 struct airoha_qdma *qdma) 1304 { 1305 struct airoha_eth *eth = qdma->eth; 1306 int i, id = qdma - ð->qdma[0]; 1307 1308 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 1309 struct airoha_irq_bank *irq_bank = &qdma->irq_banks[i]; 1310 int err, irq_index = 4 * id + i; 1311 const char *name; 1312 1313 spin_lock_init(&irq_bank->irq_lock); 1314 irq_bank->qdma = qdma; 1315 1316 irq_bank->irq = platform_get_irq(pdev, irq_index); 1317 if (irq_bank->irq < 0) 1318 return irq_bank->irq; 1319 1320 name = devm_kasprintf(eth->dev, GFP_KERNEL, 1321 KBUILD_MODNAME ".%d", irq_index); 1322 if (!name) 1323 return -ENOMEM; 1324 1325 err = devm_request_irq(eth->dev, irq_bank->irq, 1326 airoha_irq_handler, IRQF_SHARED, name, 1327 irq_bank); 1328 if (err) 1329 return err; 1330 } 1331 1332 return 0; 1333 } 1334 1335 static int airoha_qdma_init(struct platform_device *pdev, 1336 struct airoha_eth *eth, 1337 struct airoha_qdma *qdma) 1338 { 1339 int err, id = qdma - ð->qdma[0]; 1340 const char *res; 1341 1342 qdma->eth = eth; 1343 res = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d", id); 1344 if (!res) 1345 return -ENOMEM; 1346 1347 qdma->regs = devm_platform_ioremap_resource_byname(pdev, res); 1348 if (IS_ERR(qdma->regs)) 1349 return dev_err_probe(eth->dev, PTR_ERR(qdma->regs), 1350 "failed to iomap qdma%d regs\n", id); 1351 1352 err = airoha_qdma_init_irq_banks(pdev, qdma); 1353 if (err) 1354 return err; 1355 1356 err = airoha_qdma_init_rx(qdma); 1357 if (err) 1358 return err; 1359 1360 err = airoha_qdma_init_tx(qdma); 1361 if (err) 1362 return err; 1363 1364 err = airoha_qdma_init_hfwd_queues(qdma); 1365 if (err) 1366 return err; 1367 1368 return airoha_qdma_hw_init(qdma); 1369 } 1370 1371 static int airoha_hw_init(struct platform_device *pdev, 1372 struct airoha_eth *eth) 1373 { 1374 int err, i; 1375 1376 /* disable xsi */ 1377 err = reset_control_bulk_assert(eth->soc->num_xsi_rsts, eth->xsi_rsts); 1378 if (err) 1379 return err; 1380 1381 err = reset_control_bulk_assert(ARRAY_SIZE(eth->rsts), eth->rsts); 1382 if (err) 1383 return err; 1384 1385 msleep(20); 1386 err = reset_control_bulk_deassert(ARRAY_SIZE(eth->rsts), eth->rsts); 1387 if (err) 1388 return err; 1389 1390 msleep(20); 1391 err = airoha_fe_init(eth); 1392 if (err) 1393 return err; 1394 1395 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) { 1396 err = airoha_qdma_init(pdev, eth, ð->qdma[i]); 1397 if (err) 1398 return err; 1399 } 1400 1401 err = airoha_ppe_init(eth); 1402 if (err) 1403 return err; 1404 1405 set_bit(DEV_STATE_INITIALIZED, ð->state); 1406 1407 return 0; 1408 } 1409 1410 static void airoha_hw_cleanup(struct airoha_qdma *qdma) 1411 { 1412 int i; 1413 1414 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1415 if (!qdma->q_rx[i].ndesc) 1416 continue; 1417 1418 netif_napi_del(&qdma->q_rx[i].napi); 1419 airoha_qdma_cleanup_rx_queue(&qdma->q_rx[i]); 1420 if (qdma->q_rx[i].page_pool) 1421 page_pool_destroy(qdma->q_rx[i].page_pool); 1422 } 1423 1424 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1425 netif_napi_del(&qdma->q_tx_irq[i].napi); 1426 1427 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1428 if (!qdma->q_tx[i].ndesc) 1429 continue; 1430 1431 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]); 1432 } 1433 } 1434 1435 static void airoha_qdma_start_napi(struct airoha_qdma *qdma) 1436 { 1437 int i; 1438 1439 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1440 napi_enable(&qdma->q_tx_irq[i].napi); 1441 1442 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1443 if (!qdma->q_rx[i].ndesc) 1444 continue; 1445 1446 napi_enable(&qdma->q_rx[i].napi); 1447 } 1448 } 1449 1450 static void airoha_qdma_stop_napi(struct airoha_qdma *qdma) 1451 { 1452 int i; 1453 1454 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1455 napi_disable(&qdma->q_tx_irq[i].napi); 1456 1457 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1458 if (!qdma->q_rx[i].ndesc) 1459 continue; 1460 1461 napi_disable(&qdma->q_rx[i].napi); 1462 } 1463 } 1464 1465 static void airoha_update_hw_stats(struct airoha_gdm_port *port) 1466 { 1467 struct airoha_eth *eth = port->qdma->eth; 1468 u32 val, i = 0; 1469 1470 spin_lock(&port->stats.lock); 1471 u64_stats_update_begin(&port->stats.syncp); 1472 1473 /* TX */ 1474 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_H(port->id)); 1475 port->stats.tx_ok_pkts += ((u64)val << 32); 1476 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_L(port->id)); 1477 port->stats.tx_ok_pkts += val; 1478 1479 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_H(port->id)); 1480 port->stats.tx_ok_bytes += ((u64)val << 32); 1481 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_L(port->id)); 1482 port->stats.tx_ok_bytes += val; 1483 1484 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_DROP_CNT(port->id)); 1485 port->stats.tx_drops += val; 1486 1487 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_BC_CNT(port->id)); 1488 port->stats.tx_broadcast += val; 1489 1490 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_MC_CNT(port->id)); 1491 port->stats.tx_multicast += val; 1492 1493 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_RUNT_CNT(port->id)); 1494 port->stats.tx_len[i] += val; 1495 1496 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_H(port->id)); 1497 port->stats.tx_len[i] += ((u64)val << 32); 1498 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_L(port->id)); 1499 port->stats.tx_len[i++] += val; 1500 1501 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_H(port->id)); 1502 port->stats.tx_len[i] += ((u64)val << 32); 1503 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_L(port->id)); 1504 port->stats.tx_len[i++] += val; 1505 1506 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_H(port->id)); 1507 port->stats.tx_len[i] += ((u64)val << 32); 1508 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_L(port->id)); 1509 port->stats.tx_len[i++] += val; 1510 1511 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_H(port->id)); 1512 port->stats.tx_len[i] += ((u64)val << 32); 1513 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_L(port->id)); 1514 port->stats.tx_len[i++] += val; 1515 1516 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_H(port->id)); 1517 port->stats.tx_len[i] += ((u64)val << 32); 1518 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_L(port->id)); 1519 port->stats.tx_len[i++] += val; 1520 1521 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_H(port->id)); 1522 port->stats.tx_len[i] += ((u64)val << 32); 1523 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_L(port->id)); 1524 port->stats.tx_len[i++] += val; 1525 1526 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_LONG_CNT(port->id)); 1527 port->stats.tx_len[i++] += val; 1528 1529 /* RX */ 1530 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_H(port->id)); 1531 port->stats.rx_ok_pkts += ((u64)val << 32); 1532 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_L(port->id)); 1533 port->stats.rx_ok_pkts += val; 1534 1535 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_H(port->id)); 1536 port->stats.rx_ok_bytes += ((u64)val << 32); 1537 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_L(port->id)); 1538 port->stats.rx_ok_bytes += val; 1539 1540 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_DROP_CNT(port->id)); 1541 port->stats.rx_drops += val; 1542 1543 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_BC_CNT(port->id)); 1544 port->stats.rx_broadcast += val; 1545 1546 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_MC_CNT(port->id)); 1547 port->stats.rx_multicast += val; 1548 1549 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ERROR_DROP_CNT(port->id)); 1550 port->stats.rx_errors += val; 1551 1552 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_CRC_ERR_CNT(port->id)); 1553 port->stats.rx_crc_error += val; 1554 1555 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OVERFLOW_DROP_CNT(port->id)); 1556 port->stats.rx_over_errors += val; 1557 1558 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_FRAG_CNT(port->id)); 1559 port->stats.rx_fragment += val; 1560 1561 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_JABBER_CNT(port->id)); 1562 port->stats.rx_jabber += val; 1563 1564 i = 0; 1565 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_RUNT_CNT(port->id)); 1566 port->stats.rx_len[i] += val; 1567 1568 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_H(port->id)); 1569 port->stats.rx_len[i] += ((u64)val << 32); 1570 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_L(port->id)); 1571 port->stats.rx_len[i++] += val; 1572 1573 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_H(port->id)); 1574 port->stats.rx_len[i] += ((u64)val << 32); 1575 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_L(port->id)); 1576 port->stats.rx_len[i++] += val; 1577 1578 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_H(port->id)); 1579 port->stats.rx_len[i] += ((u64)val << 32); 1580 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_L(port->id)); 1581 port->stats.rx_len[i++] += val; 1582 1583 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_H(port->id)); 1584 port->stats.rx_len[i] += ((u64)val << 32); 1585 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_L(port->id)); 1586 port->stats.rx_len[i++] += val; 1587 1588 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_H(port->id)); 1589 port->stats.rx_len[i] += ((u64)val << 32); 1590 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_L(port->id)); 1591 port->stats.rx_len[i++] += val; 1592 1593 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_H(port->id)); 1594 port->stats.rx_len[i] += ((u64)val << 32); 1595 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_L(port->id)); 1596 port->stats.rx_len[i++] += val; 1597 1598 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_LONG_CNT(port->id)); 1599 port->stats.rx_len[i++] += val; 1600 1601 /* reset mib counters */ 1602 airoha_fe_set(eth, REG_FE_GDM_MIB_CLEAR(port->id), 1603 FE_GDM_MIB_RX_CLEAR_MASK | FE_GDM_MIB_TX_CLEAR_MASK); 1604 1605 u64_stats_update_end(&port->stats.syncp); 1606 spin_unlock(&port->stats.lock); 1607 } 1608 1609 static int airoha_dev_open(struct net_device *dev) 1610 { 1611 int err, len = ETH_HLEN + dev->mtu + ETH_FCS_LEN; 1612 struct airoha_gdm_port *port = netdev_priv(dev); 1613 struct airoha_qdma *qdma = port->qdma; 1614 1615 netif_tx_start_all_queues(dev); 1616 err = airoha_set_vip_for_gdm_port(port, true); 1617 if (err) 1618 return err; 1619 1620 if (netdev_uses_dsa(dev)) 1621 airoha_fe_set(qdma->eth, REG_GDM_INGRESS_CFG(port->id), 1622 GDM_STAG_EN_MASK); 1623 else 1624 airoha_fe_clear(qdma->eth, REG_GDM_INGRESS_CFG(port->id), 1625 GDM_STAG_EN_MASK); 1626 1627 airoha_fe_rmw(qdma->eth, REG_GDM_LEN_CFG(port->id), 1628 GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK, 1629 FIELD_PREP(GDM_SHORT_LEN_MASK, 60) | 1630 FIELD_PREP(GDM_LONG_LEN_MASK, len)); 1631 1632 airoha_qdma_set(qdma, REG_QDMA_GLOBAL_CFG, 1633 GLOBAL_CFG_TX_DMA_EN_MASK | 1634 GLOBAL_CFG_RX_DMA_EN_MASK); 1635 atomic_inc(&qdma->users); 1636 1637 return 0; 1638 } 1639 1640 static int airoha_dev_stop(struct net_device *dev) 1641 { 1642 struct airoha_gdm_port *port = netdev_priv(dev); 1643 struct airoha_qdma *qdma = port->qdma; 1644 int i, err; 1645 1646 netif_tx_disable(dev); 1647 err = airoha_set_vip_for_gdm_port(port, false); 1648 if (err) 1649 return err; 1650 1651 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) 1652 netdev_tx_reset_subqueue(dev, i); 1653 1654 if (atomic_dec_and_test(&qdma->users)) { 1655 airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG, 1656 GLOBAL_CFG_TX_DMA_EN_MASK | 1657 GLOBAL_CFG_RX_DMA_EN_MASK); 1658 1659 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1660 if (!qdma->q_tx[i].ndesc) 1661 continue; 1662 1663 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]); 1664 } 1665 } 1666 1667 return 0; 1668 } 1669 1670 static int airoha_dev_set_macaddr(struct net_device *dev, void *p) 1671 { 1672 struct airoha_gdm_port *port = netdev_priv(dev); 1673 int err; 1674 1675 err = eth_mac_addr(dev, p); 1676 if (err) 1677 return err; 1678 1679 airoha_set_macaddr(port, dev->dev_addr); 1680 1681 return 0; 1682 } 1683 1684 static int airhoha_set_gdm2_loopback(struct airoha_gdm_port *port) 1685 { 1686 struct airoha_eth *eth = port->qdma->eth; 1687 u32 val, pse_port, chan, nbq; 1688 int src_port; 1689 1690 /* Forward the traffic to the proper GDM port */ 1691 pse_port = port->id == AIROHA_GDM3_IDX ? FE_PSE_PORT_GDM3 1692 : FE_PSE_PORT_GDM4; 1693 airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(AIROHA_GDM2_IDX), 1694 pse_port); 1695 airoha_fe_clear(eth, REG_GDM_FWD_CFG(AIROHA_GDM2_IDX), 1696 GDM_STRIP_CRC_MASK); 1697 1698 /* Enable GDM2 loopback */ 1699 airoha_fe_wr(eth, REG_GDM_TXCHN_EN(AIROHA_GDM2_IDX), 0xffffffff); 1700 airoha_fe_wr(eth, REG_GDM_RXCHN_EN(AIROHA_GDM2_IDX), 0xffff); 1701 1702 chan = port->id == AIROHA_GDM3_IDX ? airoha_is_7581(eth) ? 4 : 3 : 0; 1703 airoha_fe_rmw(eth, REG_GDM_LPBK_CFG(AIROHA_GDM2_IDX), 1704 LPBK_CHAN_MASK | LPBK_MODE_MASK | LPBK_EN_MASK, 1705 FIELD_PREP(LPBK_CHAN_MASK, chan) | 1706 LBK_GAP_MODE_MASK | LBK_LEN_MODE_MASK | 1707 LBK_CHAN_MODE_MASK | LPBK_EN_MASK); 1708 airoha_fe_rmw(eth, REG_GDM_LEN_CFG(AIROHA_GDM2_IDX), 1709 GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK, 1710 FIELD_PREP(GDM_SHORT_LEN_MASK, 60) | 1711 FIELD_PREP(GDM_LONG_LEN_MASK, AIROHA_MAX_MTU)); 1712 1713 /* Disable VIP and IFC for GDM2 */ 1714 airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, BIT(AIROHA_GDM2_IDX)); 1715 airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, BIT(AIROHA_GDM2_IDX)); 1716 1717 /* XXX: handle XSI_USB_PORT and XSI_PCE1_PORT */ 1718 nbq = port->id == AIROHA_GDM3_IDX && airoha_is_7581(eth) ? 4 : 0; 1719 src_port = eth->soc->ops.get_src_port_id(port, nbq); 1720 if (src_port < 0) 1721 return src_port; 1722 1723 airoha_fe_rmw(eth, REG_FE_WAN_PORT, 1724 WAN1_EN_MASK | WAN1_MASK | WAN0_MASK, 1725 FIELD_PREP(WAN0_MASK, src_port)); 1726 val = src_port & SP_CPORT_DFT_MASK; 1727 airoha_fe_rmw(eth, 1728 REG_SP_DFT_CPORT(src_port >> fls(SP_CPORT_DFT_MASK)), 1729 SP_CPORT_MASK(val), 1730 FE_PSE_PORT_CDM2 << __ffs(SP_CPORT_MASK(val))); 1731 1732 if (port->id != AIROHA_GDM3_IDX && airoha_is_7581(eth)) 1733 airoha_fe_rmw(eth, REG_SRC_PORT_FC_MAP6, 1734 FC_ID_OF_SRC_PORT24_MASK, 1735 FIELD_PREP(FC_ID_OF_SRC_PORT24_MASK, 2)); 1736 1737 return 0; 1738 } 1739 1740 static int airoha_dev_init(struct net_device *dev) 1741 { 1742 struct airoha_gdm_port *port = netdev_priv(dev); 1743 struct airoha_qdma *qdma = port->qdma; 1744 struct airoha_eth *eth = qdma->eth; 1745 u32 pse_port, fe_cpu_port; 1746 u8 ppe_id; 1747 1748 airoha_set_macaddr(port, dev->dev_addr); 1749 1750 switch (port->id) { 1751 case AIROHA_GDM3_IDX: 1752 case AIROHA_GDM4_IDX: 1753 /* If GDM2 is active we can't enable loopback */ 1754 if (!eth->ports[1]) { 1755 int err; 1756 1757 err = airhoha_set_gdm2_loopback(port); 1758 if (err) 1759 return err; 1760 } 1761 fallthrough; 1762 case AIROHA_GDM2_IDX: 1763 if (airoha_ppe_is_enabled(eth, 1)) { 1764 /* For PPE2 always use secondary cpu port. */ 1765 fe_cpu_port = FE_PSE_PORT_CDM2; 1766 pse_port = FE_PSE_PORT_PPE2; 1767 break; 1768 } 1769 fallthrough; 1770 default: { 1771 u8 qdma_id = qdma - ð->qdma[0]; 1772 1773 /* For PPE1 select cpu port according to the running QDMA. */ 1774 fe_cpu_port = qdma_id ? FE_PSE_PORT_CDM2 : FE_PSE_PORT_CDM1; 1775 pse_port = FE_PSE_PORT_PPE1; 1776 break; 1777 } 1778 } 1779 1780 airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(port->id), pse_port); 1781 ppe_id = pse_port == FE_PSE_PORT_PPE2 ? 1 : 0; 1782 airoha_fe_rmw(eth, REG_PPE_DFT_CPORT0(ppe_id), 1783 DFT_CPORT_MASK(port->id), 1784 fe_cpu_port << __ffs(DFT_CPORT_MASK(port->id))); 1785 1786 return 0; 1787 } 1788 1789 static void airoha_dev_get_stats64(struct net_device *dev, 1790 struct rtnl_link_stats64 *storage) 1791 { 1792 struct airoha_gdm_port *port = netdev_priv(dev); 1793 unsigned int start; 1794 1795 airoha_update_hw_stats(port); 1796 do { 1797 start = u64_stats_fetch_begin(&port->stats.syncp); 1798 storage->rx_packets = port->stats.rx_ok_pkts; 1799 storage->tx_packets = port->stats.tx_ok_pkts; 1800 storage->rx_bytes = port->stats.rx_ok_bytes; 1801 storage->tx_bytes = port->stats.tx_ok_bytes; 1802 storage->multicast = port->stats.rx_multicast; 1803 storage->rx_errors = port->stats.rx_errors; 1804 storage->rx_dropped = port->stats.rx_drops; 1805 storage->tx_dropped = port->stats.tx_drops; 1806 storage->rx_crc_errors = port->stats.rx_crc_error; 1807 storage->rx_over_errors = port->stats.rx_over_errors; 1808 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 1809 } 1810 1811 static int airoha_dev_change_mtu(struct net_device *dev, int mtu) 1812 { 1813 struct airoha_gdm_port *port = netdev_priv(dev); 1814 struct airoha_eth *eth = port->qdma->eth; 1815 u32 len = ETH_HLEN + mtu + ETH_FCS_LEN; 1816 1817 airoha_fe_rmw(eth, REG_GDM_LEN_CFG(port->id), 1818 GDM_LONG_LEN_MASK, 1819 FIELD_PREP(GDM_LONG_LEN_MASK, len)); 1820 WRITE_ONCE(dev->mtu, mtu); 1821 1822 return 0; 1823 } 1824 1825 static u16 airoha_dev_select_queue(struct net_device *dev, struct sk_buff *skb, 1826 struct net_device *sb_dev) 1827 { 1828 struct airoha_gdm_port *port = netdev_priv(dev); 1829 int queue, channel; 1830 1831 /* For dsa device select QoS channel according to the dsa user port 1832 * index, rely on port id otherwise. Select QoS queue based on the 1833 * skb priority. 1834 */ 1835 channel = netdev_uses_dsa(dev) ? skb_get_queue_mapping(skb) : port->id; 1836 channel = channel % AIROHA_NUM_QOS_CHANNELS; 1837 queue = (skb->priority - 1) % AIROHA_NUM_QOS_QUEUES; /* QoS queue */ 1838 queue = channel * AIROHA_NUM_QOS_QUEUES + queue; 1839 1840 return queue < dev->num_tx_queues ? queue : 0; 1841 } 1842 1843 static u32 airoha_get_dsa_tag(struct sk_buff *skb, struct net_device *dev) 1844 { 1845 #if IS_ENABLED(CONFIG_NET_DSA) 1846 struct ethhdr *ehdr; 1847 u8 xmit_tpid; 1848 u16 tag; 1849 1850 if (!netdev_uses_dsa(dev)) 1851 return 0; 1852 1853 if (dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK) 1854 return 0; 1855 1856 if (skb_cow_head(skb, 0)) 1857 return 0; 1858 1859 ehdr = (struct ethhdr *)skb->data; 1860 tag = be16_to_cpu(ehdr->h_proto); 1861 xmit_tpid = tag >> 8; 1862 1863 switch (xmit_tpid) { 1864 case MTK_HDR_XMIT_TAGGED_TPID_8100: 1865 ehdr->h_proto = cpu_to_be16(ETH_P_8021Q); 1866 tag &= ~(MTK_HDR_XMIT_TAGGED_TPID_8100 << 8); 1867 break; 1868 case MTK_HDR_XMIT_TAGGED_TPID_88A8: 1869 ehdr->h_proto = cpu_to_be16(ETH_P_8021AD); 1870 tag &= ~(MTK_HDR_XMIT_TAGGED_TPID_88A8 << 8); 1871 break; 1872 default: 1873 /* PPE module requires untagged DSA packets to work properly, 1874 * so move DSA tag to DMA descriptor. 1875 */ 1876 memmove(skb->data + MTK_HDR_LEN, skb->data, 2 * ETH_ALEN); 1877 __skb_pull(skb, MTK_HDR_LEN); 1878 break; 1879 } 1880 1881 return tag; 1882 #else 1883 return 0; 1884 #endif 1885 } 1886 1887 static int airoha_get_fe_port(struct airoha_gdm_port *port) 1888 { 1889 struct airoha_qdma *qdma = port->qdma; 1890 struct airoha_eth *eth = qdma->eth; 1891 1892 switch (eth->soc->version) { 1893 case 0x7583: 1894 return port->id == AIROHA_GDM3_IDX ? FE_PSE_PORT_GDM3 1895 : port->id; 1896 case 0x7581: 1897 default: 1898 return port->id == AIROHA_GDM4_IDX ? FE_PSE_PORT_GDM4 1899 : port->id; 1900 } 1901 } 1902 1903 static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb, 1904 struct net_device *dev) 1905 { 1906 struct airoha_gdm_port *port = netdev_priv(dev); 1907 struct airoha_qdma *qdma = port->qdma; 1908 u32 nr_frags, tag, msg0, msg1, len; 1909 struct airoha_queue_entry *e; 1910 struct netdev_queue *txq; 1911 struct airoha_queue *q; 1912 LIST_HEAD(tx_list); 1913 void *data; 1914 int i, qid; 1915 u16 index; 1916 u8 fport; 1917 1918 qid = skb_get_queue_mapping(skb) % ARRAY_SIZE(qdma->q_tx); 1919 tag = airoha_get_dsa_tag(skb, dev); 1920 1921 msg0 = FIELD_PREP(QDMA_ETH_TXMSG_CHAN_MASK, 1922 qid / AIROHA_NUM_QOS_QUEUES) | 1923 FIELD_PREP(QDMA_ETH_TXMSG_QUEUE_MASK, 1924 qid % AIROHA_NUM_QOS_QUEUES) | 1925 FIELD_PREP(QDMA_ETH_TXMSG_SP_TAG_MASK, tag); 1926 if (skb->ip_summed == CHECKSUM_PARTIAL) 1927 msg0 |= FIELD_PREP(QDMA_ETH_TXMSG_TCO_MASK, 1) | 1928 FIELD_PREP(QDMA_ETH_TXMSG_UCO_MASK, 1) | 1929 FIELD_PREP(QDMA_ETH_TXMSG_ICO_MASK, 1); 1930 1931 /* TSO: fill MSS info in tcp checksum field */ 1932 if (skb_is_gso(skb)) { 1933 if (skb_cow_head(skb, 0)) 1934 goto error; 1935 1936 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | 1937 SKB_GSO_TCPV6)) { 1938 __be16 csum = cpu_to_be16(skb_shinfo(skb)->gso_size); 1939 1940 tcp_hdr(skb)->check = (__force __sum16)csum; 1941 msg0 |= FIELD_PREP(QDMA_ETH_TXMSG_TSO_MASK, 1); 1942 } 1943 } 1944 1945 fport = airoha_get_fe_port(port); 1946 msg1 = FIELD_PREP(QDMA_ETH_TXMSG_FPORT_MASK, fport) | 1947 FIELD_PREP(QDMA_ETH_TXMSG_METER_MASK, 0x7f); 1948 1949 q = &qdma->q_tx[qid]; 1950 if (WARN_ON_ONCE(!q->ndesc)) 1951 goto error; 1952 1953 spin_lock_bh(&q->lock); 1954 1955 txq = netdev_get_tx_queue(dev, qid); 1956 nr_frags = 1 + skb_shinfo(skb)->nr_frags; 1957 1958 if (q->queued + nr_frags >= q->ndesc) { 1959 /* not enough space in the queue */ 1960 netif_tx_stop_queue(txq); 1961 spin_unlock_bh(&q->lock); 1962 return NETDEV_TX_BUSY; 1963 } 1964 1965 len = skb_headlen(skb); 1966 data = skb->data; 1967 1968 e = list_first_entry(&q->tx_list, struct airoha_queue_entry, 1969 list); 1970 index = e - q->entry; 1971 1972 for (i = 0; i < nr_frags; i++) { 1973 struct airoha_qdma_desc *desc = &q->desc[index]; 1974 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1975 dma_addr_t addr; 1976 u32 val; 1977 1978 addr = dma_map_single(dev->dev.parent, data, len, 1979 DMA_TO_DEVICE); 1980 if (unlikely(dma_mapping_error(dev->dev.parent, addr))) 1981 goto error_unmap; 1982 1983 list_move_tail(&e->list, &tx_list); 1984 e->skb = i ? NULL : skb; 1985 e->dma_addr = addr; 1986 e->dma_len = len; 1987 1988 e = list_first_entry(&q->tx_list, struct airoha_queue_entry, 1989 list); 1990 index = e - q->entry; 1991 1992 val = FIELD_PREP(QDMA_DESC_LEN_MASK, len); 1993 if (i < nr_frags - 1) 1994 val |= FIELD_PREP(QDMA_DESC_MORE_MASK, 1); 1995 WRITE_ONCE(desc->ctrl, cpu_to_le32(val)); 1996 WRITE_ONCE(desc->addr, cpu_to_le32(addr)); 1997 val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, index); 1998 WRITE_ONCE(desc->data, cpu_to_le32(val)); 1999 WRITE_ONCE(desc->msg0, cpu_to_le32(msg0)); 2000 WRITE_ONCE(desc->msg1, cpu_to_le32(msg1)); 2001 WRITE_ONCE(desc->msg2, cpu_to_le32(0xffff)); 2002 2003 data = skb_frag_address(frag); 2004 len = skb_frag_size(frag); 2005 } 2006 q->queued += i; 2007 2008 skb_tx_timestamp(skb); 2009 netdev_tx_sent_queue(txq, skb->len); 2010 2011 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) 2012 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), 2013 TX_RING_CPU_IDX_MASK, 2014 FIELD_PREP(TX_RING_CPU_IDX_MASK, index)); 2015 2016 if (q->ndesc - q->queued < q->free_thr) 2017 netif_tx_stop_queue(txq); 2018 2019 spin_unlock_bh(&q->lock); 2020 2021 return NETDEV_TX_OK; 2022 2023 error_unmap: 2024 while (!list_empty(&tx_list)) { 2025 e = list_first_entry(&tx_list, struct airoha_queue_entry, 2026 list); 2027 dma_unmap_single(dev->dev.parent, e->dma_addr, e->dma_len, 2028 DMA_TO_DEVICE); 2029 e->dma_addr = 0; 2030 list_move_tail(&e->list, &q->tx_list); 2031 } 2032 2033 spin_unlock_bh(&q->lock); 2034 error: 2035 dev_kfree_skb_any(skb); 2036 dev->stats.tx_dropped++; 2037 2038 return NETDEV_TX_OK; 2039 } 2040 2041 static void airoha_ethtool_get_drvinfo(struct net_device *dev, 2042 struct ethtool_drvinfo *info) 2043 { 2044 struct airoha_gdm_port *port = netdev_priv(dev); 2045 struct airoha_eth *eth = port->qdma->eth; 2046 2047 strscpy(info->driver, eth->dev->driver->name, sizeof(info->driver)); 2048 strscpy(info->bus_info, dev_name(eth->dev), sizeof(info->bus_info)); 2049 } 2050 2051 static void airoha_ethtool_get_mac_stats(struct net_device *dev, 2052 struct ethtool_eth_mac_stats *stats) 2053 { 2054 struct airoha_gdm_port *port = netdev_priv(dev); 2055 unsigned int start; 2056 2057 airoha_update_hw_stats(port); 2058 do { 2059 start = u64_stats_fetch_begin(&port->stats.syncp); 2060 stats->FramesTransmittedOK = port->stats.tx_ok_pkts; 2061 stats->OctetsTransmittedOK = port->stats.tx_ok_bytes; 2062 stats->MulticastFramesXmittedOK = port->stats.tx_multicast; 2063 stats->BroadcastFramesXmittedOK = port->stats.tx_broadcast; 2064 stats->FramesReceivedOK = port->stats.rx_ok_pkts; 2065 stats->OctetsReceivedOK = port->stats.rx_ok_bytes; 2066 stats->BroadcastFramesReceivedOK = port->stats.rx_broadcast; 2067 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 2068 } 2069 2070 static const struct ethtool_rmon_hist_range airoha_ethtool_rmon_ranges[] = { 2071 { 0, 64 }, 2072 { 65, 127 }, 2073 { 128, 255 }, 2074 { 256, 511 }, 2075 { 512, 1023 }, 2076 { 1024, 1518 }, 2077 { 1519, 10239 }, 2078 {}, 2079 }; 2080 2081 static void 2082 airoha_ethtool_get_rmon_stats(struct net_device *dev, 2083 struct ethtool_rmon_stats *stats, 2084 const struct ethtool_rmon_hist_range **ranges) 2085 { 2086 struct airoha_gdm_port *port = netdev_priv(dev); 2087 struct airoha_hw_stats *hw_stats = &port->stats; 2088 unsigned int start; 2089 2090 BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) != 2091 ARRAY_SIZE(hw_stats->tx_len) + 1); 2092 BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) != 2093 ARRAY_SIZE(hw_stats->rx_len) + 1); 2094 2095 *ranges = airoha_ethtool_rmon_ranges; 2096 airoha_update_hw_stats(port); 2097 do { 2098 int i; 2099 2100 start = u64_stats_fetch_begin(&port->stats.syncp); 2101 stats->fragments = hw_stats->rx_fragment; 2102 stats->jabbers = hw_stats->rx_jabber; 2103 for (i = 0; i < ARRAY_SIZE(airoha_ethtool_rmon_ranges) - 1; 2104 i++) { 2105 stats->hist[i] = hw_stats->rx_len[i]; 2106 stats->hist_tx[i] = hw_stats->tx_len[i]; 2107 } 2108 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 2109 } 2110 2111 static int airoha_qdma_set_chan_tx_sched(struct airoha_gdm_port *port, 2112 int channel, enum tx_sched_mode mode, 2113 const u16 *weights, u8 n_weights) 2114 { 2115 int i; 2116 2117 for (i = 0; i < AIROHA_NUM_TX_RING; i++) 2118 airoha_qdma_clear(port->qdma, REG_QUEUE_CLOSE_CFG(channel), 2119 TXQ_DISABLE_CHAN_QUEUE_MASK(channel, i)); 2120 2121 for (i = 0; i < n_weights; i++) { 2122 u32 status; 2123 int err; 2124 2125 airoha_qdma_wr(port->qdma, REG_TXWRR_WEIGHT_CFG, 2126 TWRR_RW_CMD_MASK | 2127 FIELD_PREP(TWRR_CHAN_IDX_MASK, channel) | 2128 FIELD_PREP(TWRR_QUEUE_IDX_MASK, i) | 2129 FIELD_PREP(TWRR_VALUE_MASK, weights[i])); 2130 err = read_poll_timeout(airoha_qdma_rr, status, 2131 status & TWRR_RW_CMD_DONE, 2132 USEC_PER_MSEC, 10 * USEC_PER_MSEC, 2133 true, port->qdma, 2134 REG_TXWRR_WEIGHT_CFG); 2135 if (err) 2136 return err; 2137 } 2138 2139 airoha_qdma_rmw(port->qdma, REG_CHAN_QOS_MODE(channel >> 3), 2140 CHAN_QOS_MODE_MASK(channel), 2141 mode << __ffs(CHAN_QOS_MODE_MASK(channel))); 2142 2143 return 0; 2144 } 2145 2146 static int airoha_qdma_set_tx_prio_sched(struct airoha_gdm_port *port, 2147 int channel) 2148 { 2149 static const u16 w[AIROHA_NUM_QOS_QUEUES] = {}; 2150 2151 return airoha_qdma_set_chan_tx_sched(port, channel, TC_SCH_SP, w, 2152 ARRAY_SIZE(w)); 2153 } 2154 2155 static int airoha_qdma_set_tx_ets_sched(struct airoha_gdm_port *port, 2156 int channel, 2157 struct tc_ets_qopt_offload *opt) 2158 { 2159 struct tc_ets_qopt_offload_replace_params *p = &opt->replace_params; 2160 enum tx_sched_mode mode = TC_SCH_SP; 2161 u16 w[AIROHA_NUM_QOS_QUEUES] = {}; 2162 int i, nstrict = 0; 2163 2164 if (p->bands > AIROHA_NUM_QOS_QUEUES) 2165 return -EINVAL; 2166 2167 for (i = 0; i < p->bands; i++) { 2168 if (!p->quanta[i]) 2169 nstrict++; 2170 } 2171 2172 /* this configuration is not supported by the hw */ 2173 if (nstrict == AIROHA_NUM_QOS_QUEUES - 1) 2174 return -EINVAL; 2175 2176 /* EN7581 SoC supports fixed QoS band priority where WRR queues have 2177 * lowest priorities with respect to SP ones. 2178 * e.g: WRR0, WRR1, .., WRRm, SP0, SP1, .., SPn 2179 */ 2180 for (i = 0; i < nstrict; i++) { 2181 if (p->priomap[p->bands - i - 1] != i) 2182 return -EINVAL; 2183 } 2184 2185 for (i = 0; i < p->bands - nstrict; i++) { 2186 if (p->priomap[i] != nstrict + i) 2187 return -EINVAL; 2188 2189 w[i] = p->weights[nstrict + i]; 2190 } 2191 2192 if (!nstrict) 2193 mode = TC_SCH_WRR8; 2194 else if (nstrict < AIROHA_NUM_QOS_QUEUES - 1) 2195 mode = nstrict + 1; 2196 2197 return airoha_qdma_set_chan_tx_sched(port, channel, mode, w, 2198 ARRAY_SIZE(w)); 2199 } 2200 2201 static int airoha_qdma_get_tx_ets_stats(struct airoha_gdm_port *port, 2202 int channel, 2203 struct tc_ets_qopt_offload *opt) 2204 { 2205 u64 cpu_tx_packets = airoha_qdma_rr(port->qdma, 2206 REG_CNTR_VAL(channel << 1)); 2207 u64 fwd_tx_packets = airoha_qdma_rr(port->qdma, 2208 REG_CNTR_VAL((channel << 1) + 1)); 2209 u64 tx_packets = (cpu_tx_packets - port->cpu_tx_packets) + 2210 (fwd_tx_packets - port->fwd_tx_packets); 2211 _bstats_update(opt->stats.bstats, 0, tx_packets); 2212 2213 port->cpu_tx_packets = cpu_tx_packets; 2214 port->fwd_tx_packets = fwd_tx_packets; 2215 2216 return 0; 2217 } 2218 2219 static int airoha_tc_setup_qdisc_ets(struct airoha_gdm_port *port, 2220 struct tc_ets_qopt_offload *opt) 2221 { 2222 int channel; 2223 2224 if (opt->parent == TC_H_ROOT) 2225 return -EINVAL; 2226 2227 channel = TC_H_MAJ(opt->handle) >> 16; 2228 channel = channel % AIROHA_NUM_QOS_CHANNELS; 2229 2230 switch (opt->command) { 2231 case TC_ETS_REPLACE: 2232 return airoha_qdma_set_tx_ets_sched(port, channel, opt); 2233 case TC_ETS_DESTROY: 2234 /* PRIO is default qdisc scheduler */ 2235 return airoha_qdma_set_tx_prio_sched(port, channel); 2236 case TC_ETS_STATS: 2237 return airoha_qdma_get_tx_ets_stats(port, channel, opt); 2238 default: 2239 return -EOPNOTSUPP; 2240 } 2241 } 2242 2243 static int airoha_qdma_get_rl_param(struct airoha_qdma *qdma, int queue_id, 2244 u32 addr, enum trtcm_param_type param, 2245 u32 *val_low, u32 *val_high) 2246 { 2247 u32 idx = QDMA_METER_IDX(queue_id), group = QDMA_METER_GROUP(queue_id); 2248 u32 val, config = FIELD_PREP(RATE_LIMIT_PARAM_TYPE_MASK, param) | 2249 FIELD_PREP(RATE_LIMIT_METER_GROUP_MASK, group) | 2250 FIELD_PREP(RATE_LIMIT_PARAM_INDEX_MASK, idx); 2251 2252 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2253 if (read_poll_timeout(airoha_qdma_rr, val, 2254 val & RATE_LIMIT_PARAM_RW_DONE_MASK, 2255 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, qdma, 2256 REG_TRTCM_CFG_PARAM(addr))) 2257 return -ETIMEDOUT; 2258 2259 *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr)); 2260 if (val_high) 2261 *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr)); 2262 2263 return 0; 2264 } 2265 2266 static int airoha_qdma_set_rl_param(struct airoha_qdma *qdma, int queue_id, 2267 u32 addr, enum trtcm_param_type param, 2268 u32 val) 2269 { 2270 u32 idx = QDMA_METER_IDX(queue_id), group = QDMA_METER_GROUP(queue_id); 2271 u32 config = RATE_LIMIT_PARAM_RW_MASK | 2272 FIELD_PREP(RATE_LIMIT_PARAM_TYPE_MASK, param) | 2273 FIELD_PREP(RATE_LIMIT_METER_GROUP_MASK, group) | 2274 FIELD_PREP(RATE_LIMIT_PARAM_INDEX_MASK, idx); 2275 2276 airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val); 2277 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2278 2279 return read_poll_timeout(airoha_qdma_rr, val, 2280 val & RATE_LIMIT_PARAM_RW_DONE_MASK, 2281 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2282 qdma, REG_TRTCM_CFG_PARAM(addr)); 2283 } 2284 2285 static int airoha_qdma_set_rl_config(struct airoha_qdma *qdma, int queue_id, 2286 u32 addr, bool enable, u32 enable_mask) 2287 { 2288 u32 val; 2289 int err; 2290 2291 err = airoha_qdma_get_rl_param(qdma, queue_id, addr, TRTCM_MISC_MODE, 2292 &val, NULL); 2293 if (err) 2294 return err; 2295 2296 val = enable ? val | enable_mask : val & ~enable_mask; 2297 2298 return airoha_qdma_set_rl_param(qdma, queue_id, addr, TRTCM_MISC_MODE, 2299 val); 2300 } 2301 2302 static int airoha_qdma_set_rl_token_bucket(struct airoha_qdma *qdma, 2303 int queue_id, u32 rate_val, 2304 u32 bucket_size) 2305 { 2306 u32 val, config, tick, unit, rate, rate_frac; 2307 int err; 2308 2309 err = airoha_qdma_get_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2310 TRTCM_MISC_MODE, &config, NULL); 2311 if (err) 2312 return err; 2313 2314 val = airoha_qdma_rr(qdma, REG_INGRESS_TRTCM_CFG); 2315 tick = FIELD_GET(INGRESS_FAST_TICK_MASK, val); 2316 if (config & TRTCM_TICK_SEL) 2317 tick *= FIELD_GET(INGRESS_SLOW_TICK_RATIO_MASK, val); 2318 if (!tick) 2319 return -EINVAL; 2320 2321 unit = (config & TRTCM_PKT_MODE) ? 1000000 / tick : 8000 / tick; 2322 if (!unit) 2323 return -EINVAL; 2324 2325 rate = rate_val / unit; 2326 rate_frac = rate_val % unit; 2327 rate_frac = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate_frac) / unit; 2328 rate = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate) | 2329 FIELD_PREP(TRTCM_TOKEN_RATE_FRACTION_MASK, rate_frac); 2330 2331 err = airoha_qdma_set_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2332 TRTCM_TOKEN_RATE_MODE, rate); 2333 if (err) 2334 return err; 2335 2336 val = bucket_size; 2337 if (!(config & TRTCM_PKT_MODE)) 2338 val = max_t(u32, val, MIN_TOKEN_SIZE); 2339 val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET); 2340 2341 return airoha_qdma_set_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2342 TRTCM_BUCKETSIZE_SHIFT_MODE, val); 2343 } 2344 2345 static int airoha_qdma_init_rl_config(struct airoha_qdma *qdma, int queue_id, 2346 bool enable, enum trtcm_unit_type unit) 2347 { 2348 bool tick_sel = queue_id == 0 || queue_id == 2 || queue_id == 8; 2349 enum trtcm_param mode = TRTCM_METER_MODE; 2350 int err; 2351 2352 mode |= unit == TRTCM_PACKET_UNIT ? TRTCM_PKT_MODE : 0; 2353 err = airoha_qdma_set_rl_config(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2354 enable, mode); 2355 if (err) 2356 return err; 2357 2358 return airoha_qdma_set_rl_config(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2359 tick_sel, TRTCM_TICK_SEL); 2360 } 2361 2362 static int airoha_qdma_get_trtcm_param(struct airoha_qdma *qdma, int channel, 2363 u32 addr, enum trtcm_param_type param, 2364 enum trtcm_mode_type mode, 2365 u32 *val_low, u32 *val_high) 2366 { 2367 u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel); 2368 u32 val, config = FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) | 2369 FIELD_PREP(TRTCM_METER_GROUP_MASK, group) | 2370 FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) | 2371 FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode); 2372 2373 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2374 if (read_poll_timeout(airoha_qdma_rr, val, 2375 val & TRTCM_PARAM_RW_DONE_MASK, 2376 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2377 qdma, REG_TRTCM_CFG_PARAM(addr))) 2378 return -ETIMEDOUT; 2379 2380 *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr)); 2381 if (val_high) 2382 *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr)); 2383 2384 return 0; 2385 } 2386 2387 static int airoha_qdma_set_trtcm_param(struct airoha_qdma *qdma, int channel, 2388 u32 addr, enum trtcm_param_type param, 2389 enum trtcm_mode_type mode, u32 val) 2390 { 2391 u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel); 2392 u32 config = TRTCM_PARAM_RW_MASK | 2393 FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) | 2394 FIELD_PREP(TRTCM_METER_GROUP_MASK, group) | 2395 FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) | 2396 FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode); 2397 2398 airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val); 2399 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2400 2401 return read_poll_timeout(airoha_qdma_rr, val, 2402 val & TRTCM_PARAM_RW_DONE_MASK, 2403 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2404 qdma, REG_TRTCM_CFG_PARAM(addr)); 2405 } 2406 2407 static int airoha_qdma_set_trtcm_config(struct airoha_qdma *qdma, int channel, 2408 u32 addr, enum trtcm_mode_type mode, 2409 bool enable, u32 enable_mask) 2410 { 2411 u32 val; 2412 2413 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2414 mode, &val, NULL)) 2415 return -EINVAL; 2416 2417 val = enable ? val | enable_mask : val & ~enable_mask; 2418 2419 return airoha_qdma_set_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2420 mode, val); 2421 } 2422 2423 static int airoha_qdma_set_trtcm_token_bucket(struct airoha_qdma *qdma, 2424 int channel, u32 addr, 2425 enum trtcm_mode_type mode, 2426 u32 rate_val, u32 bucket_size) 2427 { 2428 u32 val, config, tick, unit, rate, rate_frac; 2429 int err; 2430 2431 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2432 mode, &config, NULL)) 2433 return -EINVAL; 2434 2435 val = airoha_qdma_rr(qdma, addr); 2436 tick = FIELD_GET(INGRESS_FAST_TICK_MASK, val); 2437 if (config & TRTCM_TICK_SEL) 2438 tick *= FIELD_GET(INGRESS_SLOW_TICK_RATIO_MASK, val); 2439 if (!tick) 2440 return -EINVAL; 2441 2442 unit = (config & TRTCM_PKT_MODE) ? 1000000 / tick : 8000 / tick; 2443 if (!unit) 2444 return -EINVAL; 2445 2446 rate = rate_val / unit; 2447 rate_frac = rate_val % unit; 2448 rate_frac = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate_frac) / unit; 2449 rate = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate) | 2450 FIELD_PREP(TRTCM_TOKEN_RATE_FRACTION_MASK, rate_frac); 2451 2452 err = airoha_qdma_set_trtcm_param(qdma, channel, addr, 2453 TRTCM_TOKEN_RATE_MODE, mode, rate); 2454 if (err) 2455 return err; 2456 2457 val = max_t(u32, bucket_size, MIN_TOKEN_SIZE); 2458 val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET); 2459 2460 return airoha_qdma_set_trtcm_param(qdma, channel, addr, 2461 TRTCM_BUCKETSIZE_SHIFT_MODE, 2462 mode, val); 2463 } 2464 2465 static int airoha_qdma_set_tx_rate_limit(struct airoha_gdm_port *port, 2466 int channel, u32 rate, 2467 u32 bucket_size) 2468 { 2469 int i, err; 2470 2471 for (i = 0; i <= TRTCM_PEAK_MODE; i++) { 2472 err = airoha_qdma_set_trtcm_config(port->qdma, channel, 2473 REG_EGRESS_TRTCM_CFG, i, 2474 !!rate, TRTCM_METER_MODE); 2475 if (err) 2476 return err; 2477 2478 err = airoha_qdma_set_trtcm_token_bucket(port->qdma, channel, 2479 REG_EGRESS_TRTCM_CFG, 2480 i, rate, bucket_size); 2481 if (err) 2482 return err; 2483 } 2484 2485 return 0; 2486 } 2487 2488 static int airoha_tc_htb_alloc_leaf_queue(struct airoha_gdm_port *port, 2489 struct tc_htb_qopt_offload *opt) 2490 { 2491 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2492 u32 rate = div_u64(opt->rate, 1000) << 3; /* kbps */ 2493 struct net_device *dev = port->dev; 2494 int num_tx_queues = dev->real_num_tx_queues; 2495 int err; 2496 2497 if (opt->parent_classid != TC_HTB_CLASSID_ROOT) { 2498 NL_SET_ERR_MSG_MOD(opt->extack, "invalid parent classid"); 2499 return -EINVAL; 2500 } 2501 2502 err = airoha_qdma_set_tx_rate_limit(port, channel, rate, opt->quantum); 2503 if (err) { 2504 NL_SET_ERR_MSG_MOD(opt->extack, 2505 "failed configuring htb offload"); 2506 return err; 2507 } 2508 2509 if (opt->command == TC_HTB_NODE_MODIFY) 2510 return 0; 2511 2512 err = netif_set_real_num_tx_queues(dev, num_tx_queues + 1); 2513 if (err) { 2514 airoha_qdma_set_tx_rate_limit(port, channel, 0, opt->quantum); 2515 NL_SET_ERR_MSG_MOD(opt->extack, 2516 "failed setting real_num_tx_queues"); 2517 return err; 2518 } 2519 2520 set_bit(channel, port->qos_sq_bmap); 2521 opt->qid = AIROHA_NUM_TX_RING + channel; 2522 2523 return 0; 2524 } 2525 2526 static int airoha_qdma_set_rx_meter(struct airoha_gdm_port *port, 2527 u32 rate, u32 bucket_size, 2528 enum trtcm_unit_type unit_type) 2529 { 2530 struct airoha_qdma *qdma = port->qdma; 2531 int i; 2532 2533 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 2534 int err; 2535 2536 if (!qdma->q_rx[i].ndesc) 2537 continue; 2538 2539 err = airoha_qdma_init_rl_config(qdma, i, !!rate, unit_type); 2540 if (err) 2541 return err; 2542 2543 err = airoha_qdma_set_rl_token_bucket(qdma, i, rate, 2544 bucket_size); 2545 if (err) 2546 return err; 2547 } 2548 2549 return 0; 2550 } 2551 2552 static int airoha_tc_matchall_act_validate(struct tc_cls_matchall_offload *f) 2553 { 2554 const struct flow_action *actions = &f->rule->action; 2555 const struct flow_action_entry *act; 2556 2557 if (!flow_action_has_entries(actions)) { 2558 NL_SET_ERR_MSG_MOD(f->common.extack, 2559 "filter run with no actions"); 2560 return -EINVAL; 2561 } 2562 2563 if (!flow_offload_has_one_action(actions)) { 2564 NL_SET_ERR_MSG_MOD(f->common.extack, 2565 "only once action per filter is supported"); 2566 return -EOPNOTSUPP; 2567 } 2568 2569 act = &actions->entries[0]; 2570 if (act->id != FLOW_ACTION_POLICE) { 2571 NL_SET_ERR_MSG_MOD(f->common.extack, "unsupported action"); 2572 return -EOPNOTSUPP; 2573 } 2574 2575 if (act->police.exceed.act_id != FLOW_ACTION_DROP) { 2576 NL_SET_ERR_MSG_MOD(f->common.extack, 2577 "invalid exceed action id"); 2578 return -EOPNOTSUPP; 2579 } 2580 2581 if (act->police.notexceed.act_id != FLOW_ACTION_ACCEPT) { 2582 NL_SET_ERR_MSG_MOD(f->common.extack, 2583 "invalid notexceed action id"); 2584 return -EOPNOTSUPP; 2585 } 2586 2587 if (act->police.notexceed.act_id == FLOW_ACTION_ACCEPT && 2588 !flow_action_is_last_entry(actions, act)) { 2589 NL_SET_ERR_MSG_MOD(f->common.extack, 2590 "action accept must be last"); 2591 return -EOPNOTSUPP; 2592 } 2593 2594 if (act->police.peakrate_bytes_ps || act->police.avrate || 2595 act->police.overhead || act->police.mtu) { 2596 NL_SET_ERR_MSG_MOD(f->common.extack, 2597 "peakrate/avrate/overhead/mtu unsupported"); 2598 return -EOPNOTSUPP; 2599 } 2600 2601 return 0; 2602 } 2603 2604 static int airoha_dev_tc_matchall(struct net_device *dev, 2605 struct tc_cls_matchall_offload *f) 2606 { 2607 enum trtcm_unit_type unit_type = TRTCM_BYTE_UNIT; 2608 struct airoha_gdm_port *port = netdev_priv(dev); 2609 u32 rate = 0, bucket_size = 0; 2610 2611 switch (f->command) { 2612 case TC_CLSMATCHALL_REPLACE: { 2613 const struct flow_action_entry *act; 2614 int err; 2615 2616 err = airoha_tc_matchall_act_validate(f); 2617 if (err) 2618 return err; 2619 2620 act = &f->rule->action.entries[0]; 2621 if (act->police.rate_pkt_ps) { 2622 rate = act->police.rate_pkt_ps; 2623 bucket_size = act->police.burst_pkt; 2624 unit_type = TRTCM_PACKET_UNIT; 2625 } else { 2626 rate = div_u64(act->police.rate_bytes_ps, 1000); 2627 rate = rate << 3; /* Kbps */ 2628 bucket_size = act->police.burst; 2629 } 2630 fallthrough; 2631 } 2632 case TC_CLSMATCHALL_DESTROY: 2633 return airoha_qdma_set_rx_meter(port, rate, bucket_size, 2634 unit_type); 2635 default: 2636 return -EOPNOTSUPP; 2637 } 2638 } 2639 2640 static int airoha_dev_setup_tc_block_cb(enum tc_setup_type type, 2641 void *type_data, void *cb_priv) 2642 { 2643 struct net_device *dev = cb_priv; 2644 struct airoha_gdm_port *port = netdev_priv(dev); 2645 struct airoha_eth *eth = port->qdma->eth; 2646 2647 if (!tc_can_offload(dev)) 2648 return -EOPNOTSUPP; 2649 2650 switch (type) { 2651 case TC_SETUP_CLSFLOWER: 2652 return airoha_ppe_setup_tc_block_cb(ð->ppe->dev, type_data); 2653 case TC_SETUP_CLSMATCHALL: 2654 return airoha_dev_tc_matchall(dev, type_data); 2655 default: 2656 return -EOPNOTSUPP; 2657 } 2658 } 2659 2660 static int airoha_dev_setup_tc_block(struct airoha_gdm_port *port, 2661 struct flow_block_offload *f) 2662 { 2663 flow_setup_cb_t *cb = airoha_dev_setup_tc_block_cb; 2664 static LIST_HEAD(block_cb_list); 2665 struct flow_block_cb *block_cb; 2666 2667 if (f->binder_type != FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 2668 return -EOPNOTSUPP; 2669 2670 f->driver_block_list = &block_cb_list; 2671 switch (f->command) { 2672 case FLOW_BLOCK_BIND: 2673 block_cb = flow_block_cb_lookup(f->block, cb, port->dev); 2674 if (block_cb) { 2675 flow_block_cb_incref(block_cb); 2676 return 0; 2677 } 2678 block_cb = flow_block_cb_alloc(cb, port->dev, port->dev, NULL); 2679 if (IS_ERR(block_cb)) 2680 return PTR_ERR(block_cb); 2681 2682 flow_block_cb_incref(block_cb); 2683 flow_block_cb_add(block_cb, f); 2684 list_add_tail(&block_cb->driver_list, &block_cb_list); 2685 return 0; 2686 case FLOW_BLOCK_UNBIND: 2687 block_cb = flow_block_cb_lookup(f->block, cb, port->dev); 2688 if (!block_cb) 2689 return -ENOENT; 2690 2691 if (!flow_block_cb_decref(block_cb)) { 2692 flow_block_cb_remove(block_cb, f); 2693 list_del(&block_cb->driver_list); 2694 } 2695 return 0; 2696 default: 2697 return -EOPNOTSUPP; 2698 } 2699 } 2700 2701 static void airoha_tc_remove_htb_queue(struct airoha_gdm_port *port, int queue) 2702 { 2703 struct net_device *dev = port->dev; 2704 2705 netif_set_real_num_tx_queues(dev, dev->real_num_tx_queues - 1); 2706 airoha_qdma_set_tx_rate_limit(port, queue + 1, 0, 0); 2707 clear_bit(queue, port->qos_sq_bmap); 2708 } 2709 2710 static int airoha_tc_htb_delete_leaf_queue(struct airoha_gdm_port *port, 2711 struct tc_htb_qopt_offload *opt) 2712 { 2713 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2714 2715 if (!test_bit(channel, port->qos_sq_bmap)) { 2716 NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id"); 2717 return -EINVAL; 2718 } 2719 2720 airoha_tc_remove_htb_queue(port, channel); 2721 2722 return 0; 2723 } 2724 2725 static int airoha_tc_htb_destroy(struct airoha_gdm_port *port) 2726 { 2727 int q; 2728 2729 for_each_set_bit(q, port->qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS) 2730 airoha_tc_remove_htb_queue(port, q); 2731 2732 return 0; 2733 } 2734 2735 static int airoha_tc_get_htb_get_leaf_queue(struct airoha_gdm_port *port, 2736 struct tc_htb_qopt_offload *opt) 2737 { 2738 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2739 2740 if (!test_bit(channel, port->qos_sq_bmap)) { 2741 NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id"); 2742 return -EINVAL; 2743 } 2744 2745 opt->qid = AIROHA_NUM_TX_RING + channel; 2746 2747 return 0; 2748 } 2749 2750 static int airoha_tc_setup_qdisc_htb(struct airoha_gdm_port *port, 2751 struct tc_htb_qopt_offload *opt) 2752 { 2753 switch (opt->command) { 2754 case TC_HTB_CREATE: 2755 break; 2756 case TC_HTB_DESTROY: 2757 return airoha_tc_htb_destroy(port); 2758 case TC_HTB_NODE_MODIFY: 2759 case TC_HTB_LEAF_ALLOC_QUEUE: 2760 return airoha_tc_htb_alloc_leaf_queue(port, opt); 2761 case TC_HTB_LEAF_DEL: 2762 case TC_HTB_LEAF_DEL_LAST: 2763 case TC_HTB_LEAF_DEL_LAST_FORCE: 2764 return airoha_tc_htb_delete_leaf_queue(port, opt); 2765 case TC_HTB_LEAF_QUERY_QUEUE: 2766 return airoha_tc_get_htb_get_leaf_queue(port, opt); 2767 default: 2768 return -EOPNOTSUPP; 2769 } 2770 2771 return 0; 2772 } 2773 2774 static int airoha_dev_tc_setup(struct net_device *dev, enum tc_setup_type type, 2775 void *type_data) 2776 { 2777 struct airoha_gdm_port *port = netdev_priv(dev); 2778 2779 switch (type) { 2780 case TC_SETUP_QDISC_ETS: 2781 return airoha_tc_setup_qdisc_ets(port, type_data); 2782 case TC_SETUP_QDISC_HTB: 2783 return airoha_tc_setup_qdisc_htb(port, type_data); 2784 case TC_SETUP_BLOCK: 2785 case TC_SETUP_FT: 2786 return airoha_dev_setup_tc_block(port, type_data); 2787 default: 2788 return -EOPNOTSUPP; 2789 } 2790 } 2791 2792 static const struct net_device_ops airoha_netdev_ops = { 2793 .ndo_init = airoha_dev_init, 2794 .ndo_open = airoha_dev_open, 2795 .ndo_stop = airoha_dev_stop, 2796 .ndo_change_mtu = airoha_dev_change_mtu, 2797 .ndo_select_queue = airoha_dev_select_queue, 2798 .ndo_start_xmit = airoha_dev_xmit, 2799 .ndo_get_stats64 = airoha_dev_get_stats64, 2800 .ndo_set_mac_address = airoha_dev_set_macaddr, 2801 .ndo_setup_tc = airoha_dev_tc_setup, 2802 }; 2803 2804 static const struct ethtool_ops airoha_ethtool_ops = { 2805 .get_drvinfo = airoha_ethtool_get_drvinfo, 2806 .get_eth_mac_stats = airoha_ethtool_get_mac_stats, 2807 .get_rmon_stats = airoha_ethtool_get_rmon_stats, 2808 .get_link_ksettings = phy_ethtool_get_link_ksettings, 2809 .get_link = ethtool_op_get_link, 2810 }; 2811 2812 static int airoha_metadata_dst_alloc(struct airoha_gdm_port *port) 2813 { 2814 int i; 2815 2816 for (i = 0; i < ARRAY_SIZE(port->dsa_meta); i++) { 2817 struct metadata_dst *md_dst; 2818 2819 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, 2820 GFP_KERNEL); 2821 if (!md_dst) 2822 return -ENOMEM; 2823 2824 md_dst->u.port_info.port_id = i; 2825 port->dsa_meta[i] = md_dst; 2826 } 2827 2828 return 0; 2829 } 2830 2831 static void airoha_metadata_dst_free(struct airoha_gdm_port *port) 2832 { 2833 int i; 2834 2835 for (i = 0; i < ARRAY_SIZE(port->dsa_meta); i++) { 2836 if (!port->dsa_meta[i]) 2837 continue; 2838 2839 metadata_dst_free(port->dsa_meta[i]); 2840 } 2841 } 2842 2843 bool airoha_is_valid_gdm_port(struct airoha_eth *eth, 2844 struct airoha_gdm_port *port) 2845 { 2846 int i; 2847 2848 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 2849 if (eth->ports[i] == port) 2850 return true; 2851 } 2852 2853 return false; 2854 } 2855 2856 static int airoha_alloc_gdm_port(struct airoha_eth *eth, 2857 struct device_node *np, int index) 2858 { 2859 const __be32 *id_ptr = of_get_property(np, "reg", NULL); 2860 struct airoha_gdm_port *port; 2861 struct airoha_qdma *qdma; 2862 struct net_device *dev; 2863 int err, p; 2864 u32 id; 2865 2866 if (!id_ptr) { 2867 dev_err(eth->dev, "missing gdm port id\n"); 2868 return -EINVAL; 2869 } 2870 2871 id = be32_to_cpup(id_ptr); 2872 p = id - 1; 2873 2874 if (!id || id > ARRAY_SIZE(eth->ports)) { 2875 dev_err(eth->dev, "invalid gdm port id: %d\n", id); 2876 return -EINVAL; 2877 } 2878 2879 if (eth->ports[p]) { 2880 dev_err(eth->dev, "duplicate gdm port id: %d\n", id); 2881 return -EINVAL; 2882 } 2883 2884 dev = devm_alloc_etherdev_mqs(eth->dev, sizeof(*port), 2885 AIROHA_NUM_NETDEV_TX_RINGS, 2886 AIROHA_NUM_RX_RING); 2887 if (!dev) { 2888 dev_err(eth->dev, "alloc_etherdev failed\n"); 2889 return -ENOMEM; 2890 } 2891 2892 qdma = ð->qdma[index % AIROHA_MAX_NUM_QDMA]; 2893 dev->netdev_ops = &airoha_netdev_ops; 2894 dev->ethtool_ops = &airoha_ethtool_ops; 2895 dev->max_mtu = AIROHA_MAX_MTU; 2896 dev->watchdog_timeo = 5 * HZ; 2897 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 2898 NETIF_F_TSO6 | NETIF_F_IPV6_CSUM | 2899 NETIF_F_SG | NETIF_F_TSO | 2900 NETIF_F_HW_TC; 2901 dev->features |= dev->hw_features; 2902 dev->vlan_features = dev->hw_features; 2903 dev->dev.of_node = np; 2904 dev->irq = qdma->irq_banks[0].irq; 2905 SET_NETDEV_DEV(dev, eth->dev); 2906 2907 /* reserve hw queues for HTB offloading */ 2908 err = netif_set_real_num_tx_queues(dev, AIROHA_NUM_TX_RING); 2909 if (err) 2910 return err; 2911 2912 err = of_get_ethdev_address(np, dev); 2913 if (err) { 2914 if (err == -EPROBE_DEFER) 2915 return err; 2916 2917 eth_hw_addr_random(dev); 2918 dev_info(eth->dev, "generated random MAC address %pM\n", 2919 dev->dev_addr); 2920 } 2921 2922 port = netdev_priv(dev); 2923 u64_stats_init(&port->stats.syncp); 2924 spin_lock_init(&port->stats.lock); 2925 port->qdma = qdma; 2926 port->dev = dev; 2927 port->id = id; 2928 eth->ports[p] = port; 2929 2930 return airoha_metadata_dst_alloc(port); 2931 } 2932 2933 static int airoha_register_gdm_devices(struct airoha_eth *eth) 2934 { 2935 int i; 2936 2937 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 2938 struct airoha_gdm_port *port = eth->ports[i]; 2939 int err; 2940 2941 if (!port) 2942 continue; 2943 2944 err = register_netdev(port->dev); 2945 if (err) 2946 return err; 2947 } 2948 2949 return 0; 2950 } 2951 2952 static int airoha_probe(struct platform_device *pdev) 2953 { 2954 struct reset_control_bulk_data *xsi_rsts; 2955 struct device_node *np; 2956 struct airoha_eth *eth; 2957 int i, err; 2958 2959 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 2960 if (!eth) 2961 return -ENOMEM; 2962 2963 eth->soc = of_device_get_match_data(&pdev->dev); 2964 if (!eth->soc) 2965 return -EINVAL; 2966 2967 eth->dev = &pdev->dev; 2968 2969 err = dma_set_mask_and_coherent(eth->dev, DMA_BIT_MASK(32)); 2970 if (err) { 2971 dev_err(eth->dev, "failed configuring DMA mask\n"); 2972 return err; 2973 } 2974 2975 eth->fe_regs = devm_platform_ioremap_resource_byname(pdev, "fe"); 2976 if (IS_ERR(eth->fe_regs)) 2977 return dev_err_probe(eth->dev, PTR_ERR(eth->fe_regs), 2978 "failed to iomap fe regs\n"); 2979 2980 eth->rsts[0].id = "fe"; 2981 eth->rsts[1].id = "pdma"; 2982 eth->rsts[2].id = "qdma"; 2983 err = devm_reset_control_bulk_get_exclusive(eth->dev, 2984 ARRAY_SIZE(eth->rsts), 2985 eth->rsts); 2986 if (err) { 2987 dev_err(eth->dev, "failed to get bulk reset lines\n"); 2988 return err; 2989 } 2990 2991 xsi_rsts = devm_kcalloc(eth->dev, 2992 eth->soc->num_xsi_rsts, sizeof(*xsi_rsts), 2993 GFP_KERNEL); 2994 if (!xsi_rsts) 2995 return -ENOMEM; 2996 2997 eth->xsi_rsts = xsi_rsts; 2998 for (i = 0; i < eth->soc->num_xsi_rsts; i++) 2999 eth->xsi_rsts[i].id = eth->soc->xsi_rsts_names[i]; 3000 3001 err = devm_reset_control_bulk_get_exclusive(eth->dev, 3002 eth->soc->num_xsi_rsts, 3003 eth->xsi_rsts); 3004 if (err) { 3005 dev_err(eth->dev, "failed to get bulk xsi reset lines\n"); 3006 return err; 3007 } 3008 3009 eth->napi_dev = alloc_netdev_dummy(0); 3010 if (!eth->napi_dev) 3011 return -ENOMEM; 3012 3013 /* Enable threaded NAPI by default */ 3014 eth->napi_dev->threaded = true; 3015 strscpy(eth->napi_dev->name, "qdma_eth", sizeof(eth->napi_dev->name)); 3016 platform_set_drvdata(pdev, eth); 3017 3018 err = airoha_hw_init(pdev, eth); 3019 if (err) 3020 goto error_hw_cleanup; 3021 3022 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 3023 airoha_qdma_start_napi(ð->qdma[i]); 3024 3025 i = 0; 3026 for_each_child_of_node(pdev->dev.of_node, np) { 3027 if (!of_device_is_compatible(np, "airoha,eth-mac")) 3028 continue; 3029 3030 if (!of_device_is_available(np)) 3031 continue; 3032 3033 err = airoha_alloc_gdm_port(eth, np, i++); 3034 if (err) { 3035 of_node_put(np); 3036 goto error_napi_stop; 3037 } 3038 } 3039 3040 err = airoha_register_gdm_devices(eth); 3041 if (err) 3042 goto error_napi_stop; 3043 3044 return 0; 3045 3046 error_napi_stop: 3047 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 3048 airoha_qdma_stop_napi(ð->qdma[i]); 3049 airoha_ppe_deinit(eth); 3050 error_hw_cleanup: 3051 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 3052 airoha_hw_cleanup(ð->qdma[i]); 3053 3054 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 3055 struct airoha_gdm_port *port = eth->ports[i]; 3056 3057 if (!port) 3058 continue; 3059 3060 if (port->dev->reg_state == NETREG_REGISTERED) 3061 unregister_netdev(port->dev); 3062 airoha_metadata_dst_free(port); 3063 } 3064 free_netdev(eth->napi_dev); 3065 platform_set_drvdata(pdev, NULL); 3066 3067 return err; 3068 } 3069 3070 static void airoha_remove(struct platform_device *pdev) 3071 { 3072 struct airoha_eth *eth = platform_get_drvdata(pdev); 3073 int i; 3074 3075 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) { 3076 airoha_qdma_stop_napi(ð->qdma[i]); 3077 airoha_hw_cleanup(ð->qdma[i]); 3078 } 3079 3080 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 3081 struct airoha_gdm_port *port = eth->ports[i]; 3082 3083 if (!port) 3084 continue; 3085 3086 airoha_dev_stop(port->dev); 3087 unregister_netdev(port->dev); 3088 airoha_metadata_dst_free(port); 3089 } 3090 free_netdev(eth->napi_dev); 3091 3092 airoha_ppe_deinit(eth); 3093 platform_set_drvdata(pdev, NULL); 3094 } 3095 3096 static const char * const en7581_xsi_rsts_names[] = { 3097 "xsi-mac", 3098 "hsi0-mac", 3099 "hsi1-mac", 3100 "hsi-mac", 3101 "xfp-mac", 3102 }; 3103 3104 static int airoha_en7581_get_src_port_id(struct airoha_gdm_port *port, int nbq) 3105 { 3106 switch (port->id) { 3107 case AIROHA_GDM3_IDX: 3108 /* 7581 SoC supports PCIe serdes on GDM3 port */ 3109 if (nbq == 4) 3110 return HSGMII_LAN_7581_PCIE0_SRCPORT; 3111 if (nbq == 5) 3112 return HSGMII_LAN_7581_PCIE1_SRCPORT; 3113 break; 3114 case AIROHA_GDM4_IDX: 3115 /* 7581 SoC supports eth and usb serdes on GDM4 port */ 3116 if (!nbq) 3117 return HSGMII_LAN_7581_ETH_SRCPORT; 3118 if (nbq == 1) 3119 return HSGMII_LAN_7581_USB_SRCPORT; 3120 break; 3121 default: 3122 break; 3123 } 3124 3125 return -EINVAL; 3126 } 3127 3128 static const char * const an7583_xsi_rsts_names[] = { 3129 "xsi-mac", 3130 "hsi0-mac", 3131 "hsi1-mac", 3132 "xfp-mac", 3133 }; 3134 3135 static int airoha_an7583_get_src_port_id(struct airoha_gdm_port *port, int nbq) 3136 { 3137 switch (port->id) { 3138 case AIROHA_GDM3_IDX: 3139 /* 7583 SoC supports eth serdes on GDM3 port */ 3140 if (!nbq) 3141 return HSGMII_LAN_7583_ETH_SRCPORT; 3142 break; 3143 case AIROHA_GDM4_IDX: 3144 /* 7583 SoC supports PCIe and USB serdes on GDM4 port */ 3145 if (!nbq) 3146 return HSGMII_LAN_7583_PCIE_SRCPORT; 3147 if (nbq == 1) 3148 return HSGMII_LAN_7583_USB_SRCPORT; 3149 break; 3150 default: 3151 break; 3152 } 3153 3154 return -EINVAL; 3155 } 3156 3157 static const struct airoha_eth_soc_data en7581_soc_data = { 3158 .version = 0x7581, 3159 .xsi_rsts_names = en7581_xsi_rsts_names, 3160 .num_xsi_rsts = ARRAY_SIZE(en7581_xsi_rsts_names), 3161 .num_ppe = 2, 3162 .ops = { 3163 .get_src_port_id = airoha_en7581_get_src_port_id, 3164 }, 3165 }; 3166 3167 static const struct airoha_eth_soc_data an7583_soc_data = { 3168 .version = 0x7583, 3169 .xsi_rsts_names = an7583_xsi_rsts_names, 3170 .num_xsi_rsts = ARRAY_SIZE(an7583_xsi_rsts_names), 3171 .num_ppe = 1, 3172 .ops = { 3173 .get_src_port_id = airoha_an7583_get_src_port_id, 3174 }, 3175 }; 3176 3177 static const struct of_device_id of_airoha_match[] = { 3178 { .compatible = "airoha,en7581-eth", .data = &en7581_soc_data }, 3179 { .compatible = "airoha,an7583-eth", .data = &an7583_soc_data }, 3180 { /* sentinel */ } 3181 }; 3182 MODULE_DEVICE_TABLE(of, of_airoha_match); 3183 3184 static struct platform_driver airoha_driver = { 3185 .probe = airoha_probe, 3186 .remove = airoha_remove, 3187 .driver = { 3188 .name = KBUILD_MODNAME, 3189 .of_match_table = of_airoha_match, 3190 }, 3191 }; 3192 module_platform_driver(airoha_driver); 3193 3194 MODULE_LICENSE("GPL"); 3195 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 3196 MODULE_DESCRIPTION("Ethernet driver for Airoha SoC"); 3197