1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024 AIROHA Inc 4 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 5 */ 6 #include <linux/of.h> 7 #include <linux/of_net.h> 8 #include <linux/of_reserved_mem.h> 9 #include <linux/platform_device.h> 10 #include <linux/tcp.h> 11 #include <linux/u64_stats_sync.h> 12 #include <net/dst_metadata.h> 13 #include <net/page_pool/helpers.h> 14 #include <net/pkt_cls.h> 15 #include <uapi/linux/ppp_defs.h> 16 17 #include "airoha_regs.h" 18 #include "airoha_eth.h" 19 20 u32 airoha_rr(void __iomem *base, u32 offset) 21 { 22 return readl(base + offset); 23 } 24 25 void airoha_wr(void __iomem *base, u32 offset, u32 val) 26 { 27 writel(val, base + offset); 28 } 29 30 u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val) 31 { 32 val |= (airoha_rr(base, offset) & ~mask); 33 airoha_wr(base, offset, val); 34 35 return val; 36 } 37 38 static void airoha_qdma_set_irqmask(struct airoha_irq_bank *irq_bank, 39 int index, u32 clear, u32 set) 40 { 41 struct airoha_qdma *qdma = irq_bank->qdma; 42 int bank = irq_bank - &qdma->irq_banks[0]; 43 unsigned long flags; 44 45 if (WARN_ON_ONCE(index >= ARRAY_SIZE(irq_bank->irqmask))) 46 return; 47 48 spin_lock_irqsave(&irq_bank->irq_lock, flags); 49 50 irq_bank->irqmask[index] &= ~clear; 51 irq_bank->irqmask[index] |= set; 52 airoha_qdma_wr(qdma, REG_INT_ENABLE(bank, index), 53 irq_bank->irqmask[index]); 54 /* Read irq_enable register in order to guarantee the update above 55 * completes in the spinlock critical section. 56 */ 57 airoha_qdma_rr(qdma, REG_INT_ENABLE(bank, index)); 58 59 spin_unlock_irqrestore(&irq_bank->irq_lock, flags); 60 } 61 62 static void airoha_qdma_irq_enable(struct airoha_irq_bank *irq_bank, 63 int index, u32 mask) 64 { 65 airoha_qdma_set_irqmask(irq_bank, index, 0, mask); 66 } 67 68 static void airoha_qdma_irq_disable(struct airoha_irq_bank *irq_bank, 69 int index, u32 mask) 70 { 71 airoha_qdma_set_irqmask(irq_bank, index, mask, 0); 72 } 73 74 static void airoha_set_macaddr(struct airoha_gdm_port *port, const u8 *addr) 75 { 76 struct airoha_eth *eth = port->qdma->eth; 77 u32 val, reg; 78 79 reg = airhoa_is_lan_gdm_port(port) ? REG_FE_LAN_MAC_H 80 : REG_FE_WAN_MAC_H; 81 val = (addr[0] << 16) | (addr[1] << 8) | addr[2]; 82 airoha_fe_wr(eth, reg, val); 83 84 val = (addr[3] << 16) | (addr[4] << 8) | addr[5]; 85 airoha_fe_wr(eth, REG_FE_MAC_LMIN(reg), val); 86 airoha_fe_wr(eth, REG_FE_MAC_LMAX(reg), val); 87 88 airoha_ppe_init_upd_mem(port); 89 } 90 91 static void airoha_set_gdm_port_fwd_cfg(struct airoha_eth *eth, u32 addr, 92 u32 val) 93 { 94 airoha_fe_rmw(eth, addr, GDM_OCFQ_MASK, 95 FIELD_PREP(GDM_OCFQ_MASK, val)); 96 airoha_fe_rmw(eth, addr, GDM_MCFQ_MASK, 97 FIELD_PREP(GDM_MCFQ_MASK, val)); 98 airoha_fe_rmw(eth, addr, GDM_BCFQ_MASK, 99 FIELD_PREP(GDM_BCFQ_MASK, val)); 100 airoha_fe_rmw(eth, addr, GDM_UCFQ_MASK, 101 FIELD_PREP(GDM_UCFQ_MASK, val)); 102 } 103 104 static int airoha_set_vip_for_gdm_port(struct airoha_gdm_port *port, 105 bool enable) 106 { 107 struct airoha_eth *eth = port->qdma->eth; 108 u32 vip_port; 109 110 switch (port->id) { 111 case 3: 112 /* FIXME: handle XSI_PCIE1_PORT */ 113 vip_port = XSI_PCIE0_VIP_PORT_MASK; 114 break; 115 case 4: 116 /* FIXME: handle XSI_USB_PORT */ 117 vip_port = XSI_ETH_VIP_PORT_MASK; 118 break; 119 default: 120 return 0; 121 } 122 123 if (enable) { 124 airoha_fe_set(eth, REG_FE_VIP_PORT_EN, vip_port); 125 airoha_fe_set(eth, REG_FE_IFC_PORT_EN, vip_port); 126 } else { 127 airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, vip_port); 128 airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, vip_port); 129 } 130 131 return 0; 132 } 133 134 static void airoha_fe_maccr_init(struct airoha_eth *eth) 135 { 136 int p; 137 138 for (p = 1; p <= ARRAY_SIZE(eth->ports); p++) 139 airoha_fe_set(eth, REG_GDM_FWD_CFG(p), 140 GDM_TCP_CKSUM_MASK | GDM_UDP_CKSUM_MASK | 141 GDM_IP4_CKSUM_MASK | GDM_DROP_CRC_ERR_MASK); 142 143 airoha_fe_rmw(eth, REG_CDM_VLAN_CTRL(1), CDM_VLAN_MASK, 144 FIELD_PREP(CDM_VLAN_MASK, 0x8100)); 145 146 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PAD); 147 } 148 149 static void airoha_fe_vip_setup(struct airoha_eth *eth) 150 { 151 airoha_fe_wr(eth, REG_FE_VIP_PATN(3), ETH_P_PPP_DISC); 152 airoha_fe_wr(eth, REG_FE_VIP_EN(3), PATN_FCPU_EN_MASK | PATN_EN_MASK); 153 154 airoha_fe_wr(eth, REG_FE_VIP_PATN(4), PPP_LCP); 155 airoha_fe_wr(eth, REG_FE_VIP_EN(4), 156 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 157 PATN_EN_MASK); 158 159 airoha_fe_wr(eth, REG_FE_VIP_PATN(6), PPP_IPCP); 160 airoha_fe_wr(eth, REG_FE_VIP_EN(6), 161 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 162 PATN_EN_MASK); 163 164 airoha_fe_wr(eth, REG_FE_VIP_PATN(7), PPP_CHAP); 165 airoha_fe_wr(eth, REG_FE_VIP_EN(7), 166 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 167 PATN_EN_MASK); 168 169 /* BOOTP (0x43) */ 170 airoha_fe_wr(eth, REG_FE_VIP_PATN(8), 0x43); 171 airoha_fe_wr(eth, REG_FE_VIP_EN(8), 172 PATN_FCPU_EN_MASK | PATN_SP_EN_MASK | 173 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 174 175 /* BOOTP (0x44) */ 176 airoha_fe_wr(eth, REG_FE_VIP_PATN(9), 0x44); 177 airoha_fe_wr(eth, REG_FE_VIP_EN(9), 178 PATN_FCPU_EN_MASK | PATN_SP_EN_MASK | 179 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 180 181 /* ISAKMP */ 182 airoha_fe_wr(eth, REG_FE_VIP_PATN(10), 0x1f401f4); 183 airoha_fe_wr(eth, REG_FE_VIP_EN(10), 184 PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK | 185 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 186 187 airoha_fe_wr(eth, REG_FE_VIP_PATN(11), PPP_IPV6CP); 188 airoha_fe_wr(eth, REG_FE_VIP_EN(11), 189 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 190 PATN_EN_MASK); 191 192 /* DHCPv6 */ 193 airoha_fe_wr(eth, REG_FE_VIP_PATN(12), 0x2220223); 194 airoha_fe_wr(eth, REG_FE_VIP_EN(12), 195 PATN_FCPU_EN_MASK | PATN_DP_EN_MASK | PATN_SP_EN_MASK | 196 FIELD_PREP(PATN_TYPE_MASK, 4) | PATN_EN_MASK); 197 198 airoha_fe_wr(eth, REG_FE_VIP_PATN(19), PPP_PAP); 199 airoha_fe_wr(eth, REG_FE_VIP_EN(19), 200 PATN_FCPU_EN_MASK | FIELD_PREP(PATN_TYPE_MASK, 1) | 201 PATN_EN_MASK); 202 203 /* ETH->ETH_P_1905 (0x893a) */ 204 airoha_fe_wr(eth, REG_FE_VIP_PATN(20), 0x893a); 205 airoha_fe_wr(eth, REG_FE_VIP_EN(20), 206 PATN_FCPU_EN_MASK | PATN_EN_MASK); 207 208 airoha_fe_wr(eth, REG_FE_VIP_PATN(21), ETH_P_LLDP); 209 airoha_fe_wr(eth, REG_FE_VIP_EN(21), 210 PATN_FCPU_EN_MASK | PATN_EN_MASK); 211 } 212 213 static u32 airoha_fe_get_pse_queue_rsv_pages(struct airoha_eth *eth, 214 u32 port, u32 queue) 215 { 216 u32 val; 217 218 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR, 219 PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK, 220 FIELD_PREP(PSE_CFG_PORT_ID_MASK, port) | 221 FIELD_PREP(PSE_CFG_QUEUE_ID_MASK, queue)); 222 val = airoha_fe_rr(eth, REG_FE_PSE_QUEUE_CFG_VAL); 223 224 return FIELD_GET(PSE_CFG_OQ_RSV_MASK, val); 225 } 226 227 static void airoha_fe_set_pse_queue_rsv_pages(struct airoha_eth *eth, 228 u32 port, u32 queue, u32 val) 229 { 230 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_VAL, PSE_CFG_OQ_RSV_MASK, 231 FIELD_PREP(PSE_CFG_OQ_RSV_MASK, val)); 232 airoha_fe_rmw(eth, REG_FE_PSE_QUEUE_CFG_WR, 233 PSE_CFG_PORT_ID_MASK | PSE_CFG_QUEUE_ID_MASK | 234 PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK, 235 FIELD_PREP(PSE_CFG_PORT_ID_MASK, port) | 236 FIELD_PREP(PSE_CFG_QUEUE_ID_MASK, queue) | 237 PSE_CFG_WR_EN_MASK | PSE_CFG_OQRSV_SEL_MASK); 238 } 239 240 static u32 airoha_fe_get_pse_all_rsv(struct airoha_eth *eth) 241 { 242 u32 val = airoha_fe_rr(eth, REG_FE_PSE_BUF_SET); 243 244 return FIELD_GET(PSE_ALLRSV_MASK, val); 245 } 246 247 static int airoha_fe_set_pse_oq_rsv(struct airoha_eth *eth, 248 u32 port, u32 queue, u32 val) 249 { 250 u32 orig_val = airoha_fe_get_pse_queue_rsv_pages(eth, port, queue); 251 u32 tmp, all_rsv, fq_limit; 252 253 airoha_fe_set_pse_queue_rsv_pages(eth, port, queue, val); 254 255 /* modify all rsv */ 256 all_rsv = airoha_fe_get_pse_all_rsv(eth); 257 all_rsv += (val - orig_val); 258 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, PSE_ALLRSV_MASK, 259 FIELD_PREP(PSE_ALLRSV_MASK, all_rsv)); 260 261 /* modify hthd */ 262 tmp = airoha_fe_rr(eth, PSE_FQ_CFG); 263 fq_limit = FIELD_GET(PSE_FQ_LIMIT_MASK, tmp); 264 tmp = fq_limit - all_rsv - 0x20; 265 airoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD, 266 PSE_SHARE_USED_HTHD_MASK, 267 FIELD_PREP(PSE_SHARE_USED_HTHD_MASK, tmp)); 268 269 tmp = fq_limit - all_rsv - 0x100; 270 airoha_fe_rmw(eth, REG_PSE_SHARE_USED_THD, 271 PSE_SHARE_USED_MTHD_MASK, 272 FIELD_PREP(PSE_SHARE_USED_MTHD_MASK, tmp)); 273 tmp = (3 * tmp) >> 2; 274 airoha_fe_rmw(eth, REG_FE_PSE_BUF_SET, 275 PSE_SHARE_USED_LTHD_MASK, 276 FIELD_PREP(PSE_SHARE_USED_LTHD_MASK, tmp)); 277 278 return 0; 279 } 280 281 static void airoha_fe_pse_ports_init(struct airoha_eth *eth) 282 { 283 const u32 pse_port_num_queues[] = { 284 [FE_PSE_PORT_CDM1] = 6, 285 [FE_PSE_PORT_GDM1] = 6, 286 [FE_PSE_PORT_GDM2] = 32, 287 [FE_PSE_PORT_GDM3] = 6, 288 [FE_PSE_PORT_PPE1] = 4, 289 [FE_PSE_PORT_CDM2] = 6, 290 [FE_PSE_PORT_CDM3] = 8, 291 [FE_PSE_PORT_CDM4] = 10, 292 [FE_PSE_PORT_PPE2] = 4, 293 [FE_PSE_PORT_GDM4] = 2, 294 [FE_PSE_PORT_CDM5] = 2, 295 }; 296 u32 all_rsv; 297 int q; 298 299 all_rsv = airoha_fe_get_pse_all_rsv(eth); 300 if (airoha_ppe_is_enabled(eth, 1)) { 301 /* hw misses PPE2 oq rsv */ 302 all_rsv += PSE_RSV_PAGES * 303 pse_port_num_queues[FE_PSE_PORT_PPE2]; 304 } 305 airoha_fe_set(eth, REG_FE_PSE_BUF_SET, all_rsv); 306 307 /* CMD1 */ 308 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM1]; q++) 309 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM1, q, 310 PSE_QUEUE_RSV_PAGES); 311 /* GMD1 */ 312 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM1]; q++) 313 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM1, q, 314 PSE_QUEUE_RSV_PAGES); 315 /* GMD2 */ 316 for (q = 6; q < pse_port_num_queues[FE_PSE_PORT_GDM2]; q++) 317 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM2, q, 0); 318 /* GMD3 */ 319 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM3]; q++) 320 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM3, q, 321 PSE_QUEUE_RSV_PAGES); 322 /* PPE1 */ 323 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE1]; q++) { 324 if (q < pse_port_num_queues[FE_PSE_PORT_PPE1]) 325 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 326 PSE_QUEUE_RSV_PAGES); 327 else 328 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE1, q, 0); 329 } 330 /* CDM2 */ 331 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM2]; q++) 332 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM2, q, 333 PSE_QUEUE_RSV_PAGES); 334 /* CDM3 */ 335 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM3] - 1; q++) 336 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM3, q, 0); 337 /* CDM4 */ 338 for (q = 4; q < pse_port_num_queues[FE_PSE_PORT_CDM4]; q++) 339 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM4, q, 340 PSE_QUEUE_RSV_PAGES); 341 if (airoha_ppe_is_enabled(eth, 1)) { 342 /* PPE2 */ 343 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE2]; q++) { 344 if (q < pse_port_num_queues[FE_PSE_PORT_PPE2] / 2) 345 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, 346 q, 347 PSE_QUEUE_RSV_PAGES); 348 else 349 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, 350 q, 0); 351 } 352 } 353 /* GMD4 */ 354 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM4]; q++) 355 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_GDM4, q, 356 PSE_QUEUE_RSV_PAGES); 357 /* CDM5 */ 358 for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_CDM5]; q++) 359 airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM5, q, 360 PSE_QUEUE_RSV_PAGES); 361 } 362 363 static int airoha_fe_mc_vlan_clear(struct airoha_eth *eth) 364 { 365 int i; 366 367 for (i = 0; i < AIROHA_FE_MC_MAX_VLAN_TABLE; i++) { 368 int err, j; 369 u32 val; 370 371 airoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0); 372 373 val = FIELD_PREP(MC_VLAN_CFG_TABLE_ID_MASK, i) | 374 MC_VLAN_CFG_TABLE_SEL_MASK | MC_VLAN_CFG_RW_MASK; 375 airoha_fe_wr(eth, REG_MC_VLAN_CFG, val); 376 err = read_poll_timeout(airoha_fe_rr, val, 377 val & MC_VLAN_CFG_CMD_DONE_MASK, 378 USEC_PER_MSEC, 5 * USEC_PER_MSEC, 379 false, eth, REG_MC_VLAN_CFG); 380 if (err) 381 return err; 382 383 for (j = 0; j < AIROHA_FE_MC_MAX_VLAN_PORT; j++) { 384 airoha_fe_wr(eth, REG_MC_VLAN_DATA, 0x0); 385 386 val = FIELD_PREP(MC_VLAN_CFG_TABLE_ID_MASK, i) | 387 FIELD_PREP(MC_VLAN_CFG_PORT_ID_MASK, j) | 388 MC_VLAN_CFG_RW_MASK; 389 airoha_fe_wr(eth, REG_MC_VLAN_CFG, val); 390 err = read_poll_timeout(airoha_fe_rr, val, 391 val & MC_VLAN_CFG_CMD_DONE_MASK, 392 USEC_PER_MSEC, 393 5 * USEC_PER_MSEC, false, eth, 394 REG_MC_VLAN_CFG); 395 if (err) 396 return err; 397 } 398 } 399 400 return 0; 401 } 402 403 static void airoha_fe_crsn_qsel_init(struct airoha_eth *eth) 404 { 405 /* CDM1_CRSN_QSEL */ 406 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_22 >> 2), 407 CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 408 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 409 CDM_CRSN_QSEL_Q1)); 410 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_08 >> 2), 411 CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 412 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 413 CDM_CRSN_QSEL_Q1)); 414 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_21 >> 2), 415 CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 416 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 417 CDM_CRSN_QSEL_Q1)); 418 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_24 >> 2), 419 CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 420 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 421 CDM_CRSN_QSEL_Q6)); 422 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(1, CRSN_25 >> 2), 423 CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 424 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 425 CDM_CRSN_QSEL_Q1)); 426 /* CDM2_CRSN_QSEL */ 427 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_08 >> 2), 428 CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 429 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_08), 430 CDM_CRSN_QSEL_Q1)); 431 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_21 >> 2), 432 CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 433 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_21), 434 CDM_CRSN_QSEL_Q1)); 435 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_22 >> 2), 436 CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 437 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_22), 438 CDM_CRSN_QSEL_Q1)); 439 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_24 >> 2), 440 CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 441 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_24), 442 CDM_CRSN_QSEL_Q6)); 443 airoha_fe_rmw(eth, REG_CDM_CRSN_QSEL(2, CRSN_25 >> 2), 444 CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 445 FIELD_PREP(CDM_CRSN_QSEL_REASON_MASK(CRSN_25), 446 CDM_CRSN_QSEL_Q1)); 447 } 448 449 static int airoha_fe_init(struct airoha_eth *eth) 450 { 451 airoha_fe_maccr_init(eth); 452 453 /* PSE IQ reserve */ 454 airoha_fe_rmw(eth, REG_PSE_IQ_REV1, PSE_IQ_RES1_P2_MASK, 455 FIELD_PREP(PSE_IQ_RES1_P2_MASK, 0x10)); 456 airoha_fe_rmw(eth, REG_PSE_IQ_REV2, 457 PSE_IQ_RES2_P5_MASK | PSE_IQ_RES2_P4_MASK, 458 FIELD_PREP(PSE_IQ_RES2_P5_MASK, 0x40) | 459 FIELD_PREP(PSE_IQ_RES2_P4_MASK, 0x34)); 460 461 /* enable FE copy engine for MC/KA/DPI */ 462 airoha_fe_wr(eth, REG_FE_PCE_CFG, 463 PCE_DPI_EN_MASK | PCE_KA_EN_MASK | PCE_MC_EN_MASK); 464 /* set vip queue selection to ring 1 */ 465 airoha_fe_rmw(eth, REG_CDM_FWD_CFG(1), CDM_VIP_QSEL_MASK, 466 FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4)); 467 airoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_VIP_QSEL_MASK, 468 FIELD_PREP(CDM_VIP_QSEL_MASK, 0x4)); 469 /* set GDM4 source interface offset to 8 */ 470 airoha_fe_rmw(eth, REG_GDM_SRC_PORT_SET(4), 471 GDM_SPORT_OFF2_MASK | 472 GDM_SPORT_OFF1_MASK | 473 GDM_SPORT_OFF0_MASK, 474 FIELD_PREP(GDM_SPORT_OFF2_MASK, 8) | 475 FIELD_PREP(GDM_SPORT_OFF1_MASK, 8) | 476 FIELD_PREP(GDM_SPORT_OFF0_MASK, 8)); 477 478 /* set PSE Page as 128B */ 479 airoha_fe_rmw(eth, REG_FE_DMA_GLO_CFG, 480 FE_DMA_GLO_L2_SPACE_MASK | FE_DMA_GLO_PG_SZ_MASK, 481 FIELD_PREP(FE_DMA_GLO_L2_SPACE_MASK, 2) | 482 FE_DMA_GLO_PG_SZ_MASK); 483 airoha_fe_wr(eth, REG_FE_RST_GLO_CFG, 484 FE_RST_CORE_MASK | FE_RST_GDM3_MBI_ARB_MASK | 485 FE_RST_GDM4_MBI_ARB_MASK); 486 usleep_range(1000, 2000); 487 488 /* connect RxRing1 and RxRing15 to PSE Port0 OQ-1 489 * connect other rings to PSE Port0 OQ-0 490 */ 491 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP0, BIT(4)); 492 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP1, BIT(28)); 493 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP2, BIT(4)); 494 airoha_fe_wr(eth, REG_FE_CDM1_OQ_MAP3, BIT(28)); 495 496 airoha_fe_vip_setup(eth); 497 airoha_fe_pse_ports_init(eth); 498 499 airoha_fe_set(eth, REG_GDM_MISC_CFG, 500 GDM2_RDM_ACK_WAIT_PREF_MASK | 501 GDM2_CHN_VLD_MODE_MASK); 502 airoha_fe_rmw(eth, REG_CDM_FWD_CFG(2), CDM_OAM_QSEL_MASK, 503 FIELD_PREP(CDM_OAM_QSEL_MASK, 15)); 504 505 /* init fragment and assemble Force Port */ 506 /* NPU Core-3, NPU Bridge Channel-3 */ 507 airoha_fe_rmw(eth, REG_IP_FRAG_FP, 508 IP_FRAGMENT_PORT_MASK | IP_FRAGMENT_NBQ_MASK, 509 FIELD_PREP(IP_FRAGMENT_PORT_MASK, 6) | 510 FIELD_PREP(IP_FRAGMENT_NBQ_MASK, 3)); 511 /* QDMA LAN, RX Ring-22 */ 512 airoha_fe_rmw(eth, REG_IP_FRAG_FP, 513 IP_ASSEMBLE_PORT_MASK | IP_ASSEMBLE_NBQ_MASK, 514 FIELD_PREP(IP_ASSEMBLE_PORT_MASK, 0) | 515 FIELD_PREP(IP_ASSEMBLE_NBQ_MASK, 22)); 516 517 airoha_fe_set(eth, REG_GDM_FWD_CFG(3), GDM_PAD_EN_MASK); 518 airoha_fe_set(eth, REG_GDM_FWD_CFG(4), GDM_PAD_EN_MASK); 519 520 airoha_fe_crsn_qsel_init(eth); 521 522 airoha_fe_clear(eth, REG_FE_CPORT_CFG, FE_CPORT_QUEUE_XFC_MASK); 523 airoha_fe_set(eth, REG_FE_CPORT_CFG, FE_CPORT_PORT_XFC_MASK); 524 525 /* default aging mode for mbi unlock issue */ 526 airoha_fe_rmw(eth, REG_GDM_CHN_RLS(2), 527 MBI_RX_AGE_SEL_MASK | MBI_TX_AGE_SEL_MASK, 528 FIELD_PREP(MBI_RX_AGE_SEL_MASK, 3) | 529 FIELD_PREP(MBI_TX_AGE_SEL_MASK, 3)); 530 531 /* disable IFC by default */ 532 airoha_fe_clear(eth, REG_FE_CSR_IFC_CFG, FE_IFC_EN_MASK); 533 534 /* enable 1:N vlan action, init vlan table */ 535 airoha_fe_set(eth, REG_MC_VLAN_EN, MC_VLAN_EN_MASK); 536 537 return airoha_fe_mc_vlan_clear(eth); 538 } 539 540 static int airoha_qdma_fill_rx_queue(struct airoha_queue *q) 541 { 542 struct airoha_qdma *qdma = q->qdma; 543 int qid = q - &qdma->q_rx[0]; 544 int nframes = 0; 545 546 while (q->queued < q->ndesc - 1) { 547 struct airoha_queue_entry *e = &q->entry[q->head]; 548 struct airoha_qdma_desc *desc = &q->desc[q->head]; 549 struct page *page; 550 int offset; 551 u32 val; 552 553 page = page_pool_dev_alloc_frag(q->page_pool, &offset, 554 q->buf_size); 555 if (!page) 556 break; 557 558 q->head = (q->head + 1) % q->ndesc; 559 q->queued++; 560 nframes++; 561 562 e->buf = page_address(page) + offset; 563 e->dma_addr = page_pool_get_dma_addr(page) + offset; 564 e->dma_len = SKB_WITH_OVERHEAD(q->buf_size); 565 566 val = FIELD_PREP(QDMA_DESC_LEN_MASK, e->dma_len); 567 WRITE_ONCE(desc->ctrl, cpu_to_le32(val)); 568 WRITE_ONCE(desc->addr, cpu_to_le32(e->dma_addr)); 569 val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, q->head); 570 WRITE_ONCE(desc->data, cpu_to_le32(val)); 571 WRITE_ONCE(desc->msg0, 0); 572 WRITE_ONCE(desc->msg1, 0); 573 WRITE_ONCE(desc->msg2, 0); 574 WRITE_ONCE(desc->msg3, 0); 575 576 airoha_qdma_rmw(qdma, REG_RX_CPU_IDX(qid), 577 RX_RING_CPU_IDX_MASK, 578 FIELD_PREP(RX_RING_CPU_IDX_MASK, q->head)); 579 } 580 581 return nframes; 582 } 583 584 static int airoha_qdma_get_gdm_port(struct airoha_eth *eth, 585 struct airoha_qdma_desc *desc) 586 { 587 u32 port, sport, msg1 = le32_to_cpu(desc->msg1); 588 589 sport = FIELD_GET(QDMA_ETH_RXMSG_SPORT_MASK, msg1); 590 switch (sport) { 591 case 0x10 ... 0x14: 592 port = 0; 593 break; 594 case 0x2 ... 0x4: 595 port = sport - 1; 596 break; 597 default: 598 return -EINVAL; 599 } 600 601 return port >= ARRAY_SIZE(eth->ports) ? -EINVAL : port; 602 } 603 604 static int airoha_qdma_rx_process(struct airoha_queue *q, int budget) 605 { 606 enum dma_data_direction dir = page_pool_get_dma_dir(q->page_pool); 607 struct airoha_qdma *qdma = q->qdma; 608 struct airoha_eth *eth = qdma->eth; 609 int qid = q - &qdma->q_rx[0]; 610 int done = 0; 611 612 while (done < budget) { 613 struct airoha_queue_entry *e = &q->entry[q->tail]; 614 struct airoha_qdma_desc *desc = &q->desc[q->tail]; 615 u32 hash, reason, msg1 = le32_to_cpu(desc->msg1); 616 struct page *page = virt_to_head_page(e->buf); 617 u32 desc_ctrl = le32_to_cpu(desc->ctrl); 618 struct airoha_gdm_port *port; 619 int data_len, len, p; 620 621 if (!(desc_ctrl & QDMA_DESC_DONE_MASK)) 622 break; 623 624 q->tail = (q->tail + 1) % q->ndesc; 625 q->queued--; 626 627 dma_sync_single_for_cpu(eth->dev, e->dma_addr, 628 SKB_WITH_OVERHEAD(q->buf_size), dir); 629 630 len = FIELD_GET(QDMA_DESC_LEN_MASK, desc_ctrl); 631 data_len = q->skb ? q->buf_size 632 : SKB_WITH_OVERHEAD(q->buf_size); 633 if (!len || data_len < len) 634 goto free_frag; 635 636 p = airoha_qdma_get_gdm_port(eth, desc); 637 if (p < 0 || !eth->ports[p]) 638 goto free_frag; 639 640 port = eth->ports[p]; 641 if (!q->skb) { /* first buffer */ 642 q->skb = napi_build_skb(e->buf, q->buf_size); 643 if (!q->skb) 644 goto free_frag; 645 646 __skb_put(q->skb, len); 647 skb_mark_for_recycle(q->skb); 648 q->skb->dev = port->dev; 649 q->skb->protocol = eth_type_trans(q->skb, port->dev); 650 q->skb->ip_summed = CHECKSUM_UNNECESSARY; 651 skb_record_rx_queue(q->skb, qid); 652 } else { /* scattered frame */ 653 struct skb_shared_info *shinfo = skb_shinfo(q->skb); 654 int nr_frags = shinfo->nr_frags; 655 656 if (nr_frags >= ARRAY_SIZE(shinfo->frags)) 657 goto free_frag; 658 659 skb_add_rx_frag(q->skb, nr_frags, page, 660 e->buf - page_address(page), len, 661 q->buf_size); 662 } 663 664 if (FIELD_GET(QDMA_DESC_MORE_MASK, desc_ctrl)) 665 continue; 666 667 if (netdev_uses_dsa(port->dev)) { 668 /* PPE module requires untagged packets to work 669 * properly and it provides DSA port index via the 670 * DMA descriptor. Report DSA tag to the DSA stack 671 * via skb dst info. 672 */ 673 u32 sptag = FIELD_GET(QDMA_ETH_RXMSG_SPTAG, 674 le32_to_cpu(desc->msg0)); 675 676 if (sptag < ARRAY_SIZE(port->dsa_meta) && 677 port->dsa_meta[sptag]) 678 skb_dst_set_noref(q->skb, 679 &port->dsa_meta[sptag]->dst); 680 } 681 682 hash = FIELD_GET(AIROHA_RXD4_FOE_ENTRY, msg1); 683 if (hash != AIROHA_RXD4_FOE_ENTRY) 684 skb_set_hash(q->skb, jhash_1word(hash, 0), 685 PKT_HASH_TYPE_L4); 686 687 reason = FIELD_GET(AIROHA_RXD4_PPE_CPU_REASON, msg1); 688 if (reason == PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED) 689 airoha_ppe_check_skb(ð->ppe->dev, q->skb, hash, 690 false); 691 692 done++; 693 napi_gro_receive(&q->napi, q->skb); 694 q->skb = NULL; 695 continue; 696 free_frag: 697 if (q->skb) { 698 dev_kfree_skb(q->skb); 699 q->skb = NULL; 700 } else { 701 page_pool_put_full_page(q->page_pool, page, true); 702 } 703 } 704 airoha_qdma_fill_rx_queue(q); 705 706 return done; 707 } 708 709 static int airoha_qdma_rx_napi_poll(struct napi_struct *napi, int budget) 710 { 711 struct airoha_queue *q = container_of(napi, struct airoha_queue, napi); 712 int cur, done = 0; 713 714 do { 715 cur = airoha_qdma_rx_process(q, budget - done); 716 done += cur; 717 } while (cur && done < budget); 718 719 if (done < budget && napi_complete(napi)) { 720 struct airoha_qdma *qdma = q->qdma; 721 int i, qid = q - &qdma->q_rx[0]; 722 int intr_reg = qid < RX_DONE_HIGH_OFFSET ? QDMA_INT_REG_IDX1 723 : QDMA_INT_REG_IDX2; 724 725 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 726 if (!(BIT(qid) & RX_IRQ_BANK_PIN_MASK(i))) 727 continue; 728 729 airoha_qdma_irq_enable(&qdma->irq_banks[i], intr_reg, 730 BIT(qid % RX_DONE_HIGH_OFFSET)); 731 } 732 } 733 734 return done; 735 } 736 737 static int airoha_qdma_init_rx_queue(struct airoha_queue *q, 738 struct airoha_qdma *qdma, int ndesc) 739 { 740 const struct page_pool_params pp_params = { 741 .order = 0, 742 .pool_size = 256, 743 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 744 .dma_dir = DMA_FROM_DEVICE, 745 .max_len = PAGE_SIZE, 746 .nid = NUMA_NO_NODE, 747 .dev = qdma->eth->dev, 748 .napi = &q->napi, 749 }; 750 struct airoha_eth *eth = qdma->eth; 751 int qid = q - &qdma->q_rx[0], thr; 752 dma_addr_t dma_addr; 753 754 q->buf_size = PAGE_SIZE / 2; 755 q->ndesc = ndesc; 756 q->qdma = qdma; 757 758 q->entry = devm_kzalloc(eth->dev, q->ndesc * sizeof(*q->entry), 759 GFP_KERNEL); 760 if (!q->entry) 761 return -ENOMEM; 762 763 q->page_pool = page_pool_create(&pp_params); 764 if (IS_ERR(q->page_pool)) { 765 int err = PTR_ERR(q->page_pool); 766 767 q->page_pool = NULL; 768 return err; 769 } 770 771 q->desc = dmam_alloc_coherent(eth->dev, q->ndesc * sizeof(*q->desc), 772 &dma_addr, GFP_KERNEL); 773 if (!q->desc) 774 return -ENOMEM; 775 776 netif_napi_add(eth->napi_dev, &q->napi, airoha_qdma_rx_napi_poll); 777 778 airoha_qdma_wr(qdma, REG_RX_RING_BASE(qid), dma_addr); 779 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), 780 RX_RING_SIZE_MASK, 781 FIELD_PREP(RX_RING_SIZE_MASK, ndesc)); 782 783 thr = clamp(ndesc >> 3, 1, 32); 784 airoha_qdma_rmw(qdma, REG_RX_RING_SIZE(qid), RX_RING_THR_MASK, 785 FIELD_PREP(RX_RING_THR_MASK, thr)); 786 airoha_qdma_rmw(qdma, REG_RX_DMA_IDX(qid), RX_RING_DMA_IDX_MASK, 787 FIELD_PREP(RX_RING_DMA_IDX_MASK, q->head)); 788 airoha_qdma_set(qdma, REG_RX_SCATTER_CFG(qid), RX_RING_SG_EN_MASK); 789 790 airoha_qdma_fill_rx_queue(q); 791 792 return 0; 793 } 794 795 static void airoha_qdma_cleanup_rx_queue(struct airoha_queue *q) 796 { 797 struct airoha_eth *eth = q->qdma->eth; 798 799 while (q->queued) { 800 struct airoha_queue_entry *e = &q->entry[q->tail]; 801 struct page *page = virt_to_head_page(e->buf); 802 803 dma_sync_single_for_cpu(eth->dev, e->dma_addr, e->dma_len, 804 page_pool_get_dma_dir(q->page_pool)); 805 page_pool_put_full_page(q->page_pool, page, false); 806 q->tail = (q->tail + 1) % q->ndesc; 807 q->queued--; 808 } 809 } 810 811 static int airoha_qdma_init_rx(struct airoha_qdma *qdma) 812 { 813 int i; 814 815 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 816 int err; 817 818 if (!(RX_DONE_INT_MASK & BIT(i))) { 819 /* rx-queue not binded to irq */ 820 continue; 821 } 822 823 err = airoha_qdma_init_rx_queue(&qdma->q_rx[i], qdma, 824 RX_DSCP_NUM(i)); 825 if (err) 826 return err; 827 } 828 829 return 0; 830 } 831 832 static int airoha_qdma_tx_napi_poll(struct napi_struct *napi, int budget) 833 { 834 struct airoha_tx_irq_queue *irq_q; 835 int id, done = 0, irq_queued; 836 struct airoha_qdma *qdma; 837 struct airoha_eth *eth; 838 u32 status, head; 839 840 irq_q = container_of(napi, struct airoha_tx_irq_queue, napi); 841 qdma = irq_q->qdma; 842 id = irq_q - &qdma->q_tx_irq[0]; 843 eth = qdma->eth; 844 845 status = airoha_qdma_rr(qdma, REG_IRQ_STATUS(id)); 846 head = FIELD_GET(IRQ_HEAD_IDX_MASK, status); 847 head = head % irq_q->size; 848 irq_queued = FIELD_GET(IRQ_ENTRY_LEN_MASK, status); 849 850 while (irq_queued > 0 && done < budget) { 851 u32 qid, val = irq_q->q[head]; 852 struct airoha_qdma_desc *desc; 853 struct airoha_queue_entry *e; 854 struct airoha_queue *q; 855 u32 index, desc_ctrl; 856 struct sk_buff *skb; 857 858 if (val == 0xff) 859 break; 860 861 irq_q->q[head] = 0xff; /* mark as done */ 862 head = (head + 1) % irq_q->size; 863 irq_queued--; 864 done++; 865 866 qid = FIELD_GET(IRQ_RING_IDX_MASK, val); 867 if (qid >= ARRAY_SIZE(qdma->q_tx)) 868 continue; 869 870 q = &qdma->q_tx[qid]; 871 if (!q->ndesc) 872 continue; 873 874 index = FIELD_GET(IRQ_DESC_IDX_MASK, val); 875 if (index >= q->ndesc) 876 continue; 877 878 spin_lock_bh(&q->lock); 879 880 if (!q->queued) 881 goto unlock; 882 883 desc = &q->desc[index]; 884 desc_ctrl = le32_to_cpu(desc->ctrl); 885 886 if (!(desc_ctrl & QDMA_DESC_DONE_MASK) && 887 !(desc_ctrl & QDMA_DESC_DROP_MASK)) 888 goto unlock; 889 890 e = &q->entry[index]; 891 skb = e->skb; 892 893 dma_unmap_single(eth->dev, e->dma_addr, e->dma_len, 894 DMA_TO_DEVICE); 895 memset(e, 0, sizeof(*e)); 896 WRITE_ONCE(desc->msg0, 0); 897 WRITE_ONCE(desc->msg1, 0); 898 q->queued--; 899 900 /* completion ring can report out-of-order indexes if hw QoS 901 * is enabled and packets with different priority are queued 902 * to same DMA ring. Take into account possible out-of-order 903 * reports incrementing DMA ring tail pointer 904 */ 905 while (q->tail != q->head && !q->entry[q->tail].dma_addr) 906 q->tail = (q->tail + 1) % q->ndesc; 907 908 if (skb) { 909 u16 queue = skb_get_queue_mapping(skb); 910 struct netdev_queue *txq; 911 912 txq = netdev_get_tx_queue(skb->dev, queue); 913 netdev_tx_completed_queue(txq, 1, skb->len); 914 if (netif_tx_queue_stopped(txq) && 915 q->ndesc - q->queued >= q->free_thr) 916 netif_tx_wake_queue(txq); 917 918 dev_kfree_skb_any(skb); 919 } 920 unlock: 921 spin_unlock_bh(&q->lock); 922 } 923 924 if (done) { 925 int i, len = done >> 7; 926 927 for (i = 0; i < len; i++) 928 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id), 929 IRQ_CLEAR_LEN_MASK, 0x80); 930 airoha_qdma_rmw(qdma, REG_IRQ_CLEAR_LEN(id), 931 IRQ_CLEAR_LEN_MASK, (done & 0x7f)); 932 } 933 934 if (done < budget && napi_complete(napi)) 935 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0, 936 TX_DONE_INT_MASK(id)); 937 938 return done; 939 } 940 941 static int airoha_qdma_init_tx_queue(struct airoha_queue *q, 942 struct airoha_qdma *qdma, int size) 943 { 944 struct airoha_eth *eth = qdma->eth; 945 int i, qid = q - &qdma->q_tx[0]; 946 dma_addr_t dma_addr; 947 948 spin_lock_init(&q->lock); 949 q->ndesc = size; 950 q->qdma = qdma; 951 q->free_thr = 1 + MAX_SKB_FRAGS; 952 953 q->entry = devm_kzalloc(eth->dev, q->ndesc * sizeof(*q->entry), 954 GFP_KERNEL); 955 if (!q->entry) 956 return -ENOMEM; 957 958 q->desc = dmam_alloc_coherent(eth->dev, q->ndesc * sizeof(*q->desc), 959 &dma_addr, GFP_KERNEL); 960 if (!q->desc) 961 return -ENOMEM; 962 963 for (i = 0; i < q->ndesc; i++) { 964 u32 val; 965 966 val = FIELD_PREP(QDMA_DESC_DONE_MASK, 1); 967 WRITE_ONCE(q->desc[i].ctrl, cpu_to_le32(val)); 968 } 969 970 /* xmit ring drop default setting */ 971 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(qid), 972 TX_RING_IRQ_BLOCKING_TX_DROP_EN_MASK); 973 974 airoha_qdma_wr(qdma, REG_TX_RING_BASE(qid), dma_addr); 975 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK, 976 FIELD_PREP(TX_RING_CPU_IDX_MASK, q->head)); 977 airoha_qdma_rmw(qdma, REG_TX_DMA_IDX(qid), TX_RING_DMA_IDX_MASK, 978 FIELD_PREP(TX_RING_DMA_IDX_MASK, q->head)); 979 980 return 0; 981 } 982 983 static int airoha_qdma_tx_irq_init(struct airoha_tx_irq_queue *irq_q, 984 struct airoha_qdma *qdma, int size) 985 { 986 int id = irq_q - &qdma->q_tx_irq[0]; 987 struct airoha_eth *eth = qdma->eth; 988 dma_addr_t dma_addr; 989 990 netif_napi_add_tx(eth->napi_dev, &irq_q->napi, 991 airoha_qdma_tx_napi_poll); 992 irq_q->q = dmam_alloc_coherent(eth->dev, size * sizeof(u32), 993 &dma_addr, GFP_KERNEL); 994 if (!irq_q->q) 995 return -ENOMEM; 996 997 memset(irq_q->q, 0xff, size * sizeof(u32)); 998 irq_q->size = size; 999 irq_q->qdma = qdma; 1000 1001 airoha_qdma_wr(qdma, REG_TX_IRQ_BASE(id), dma_addr); 1002 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_DEPTH_MASK, 1003 FIELD_PREP(TX_IRQ_DEPTH_MASK, size)); 1004 airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_THR_MASK, 1005 FIELD_PREP(TX_IRQ_THR_MASK, 1)); 1006 1007 return 0; 1008 } 1009 1010 static int airoha_qdma_init_tx(struct airoha_qdma *qdma) 1011 { 1012 int i, err; 1013 1014 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) { 1015 err = airoha_qdma_tx_irq_init(&qdma->q_tx_irq[i], qdma, 1016 IRQ_QUEUE_LEN(i)); 1017 if (err) 1018 return err; 1019 } 1020 1021 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1022 err = airoha_qdma_init_tx_queue(&qdma->q_tx[i], qdma, 1023 TX_DSCP_NUM); 1024 if (err) 1025 return err; 1026 } 1027 1028 return 0; 1029 } 1030 1031 static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q) 1032 { 1033 struct airoha_eth *eth = q->qdma->eth; 1034 1035 spin_lock_bh(&q->lock); 1036 while (q->queued) { 1037 struct airoha_queue_entry *e = &q->entry[q->tail]; 1038 1039 dma_unmap_single(eth->dev, e->dma_addr, e->dma_len, 1040 DMA_TO_DEVICE); 1041 dev_kfree_skb_any(e->skb); 1042 e->skb = NULL; 1043 1044 q->tail = (q->tail + 1) % q->ndesc; 1045 q->queued--; 1046 } 1047 spin_unlock_bh(&q->lock); 1048 } 1049 1050 static int airoha_qdma_init_hfwd_queues(struct airoha_qdma *qdma) 1051 { 1052 int size, index, num_desc = HW_DSCP_NUM; 1053 struct airoha_eth *eth = qdma->eth; 1054 int id = qdma - ð->qdma[0]; 1055 u32 status, buf_size; 1056 dma_addr_t dma_addr; 1057 const char *name; 1058 1059 name = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d-buf", id); 1060 if (!name) 1061 return -ENOMEM; 1062 1063 buf_size = id ? AIROHA_MAX_PACKET_SIZE / 2 : AIROHA_MAX_PACKET_SIZE; 1064 index = of_property_match_string(eth->dev->of_node, 1065 "memory-region-names", name); 1066 if (index >= 0) { 1067 struct reserved_mem *rmem; 1068 struct device_node *np; 1069 1070 /* Consume reserved memory for hw forwarding buffers queue if 1071 * available in the DTS 1072 */ 1073 np = of_parse_phandle(eth->dev->of_node, "memory-region", 1074 index); 1075 if (!np) 1076 return -ENODEV; 1077 1078 rmem = of_reserved_mem_lookup(np); 1079 of_node_put(np); 1080 dma_addr = rmem->base; 1081 /* Compute the number of hw descriptors according to the 1082 * reserved memory size and the payload buffer size 1083 */ 1084 num_desc = div_u64(rmem->size, buf_size); 1085 } else { 1086 size = buf_size * num_desc; 1087 if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, 1088 GFP_KERNEL)) 1089 return -ENOMEM; 1090 } 1091 1092 airoha_qdma_wr(qdma, REG_FWD_BUF_BASE, dma_addr); 1093 1094 size = num_desc * sizeof(struct airoha_qdma_fwd_desc); 1095 if (!dmam_alloc_coherent(eth->dev, size, &dma_addr, GFP_KERNEL)) 1096 return -ENOMEM; 1097 1098 airoha_qdma_wr(qdma, REG_FWD_DSCP_BASE, dma_addr); 1099 /* QDMA0: 2KB. QDMA1: 1KB */ 1100 airoha_qdma_rmw(qdma, REG_HW_FWD_DSCP_CFG, 1101 HW_FWD_DSCP_PAYLOAD_SIZE_MASK, 1102 FIELD_PREP(HW_FWD_DSCP_PAYLOAD_SIZE_MASK, !!id)); 1103 airoha_qdma_rmw(qdma, REG_FWD_DSCP_LOW_THR, FWD_DSCP_LOW_THR_MASK, 1104 FIELD_PREP(FWD_DSCP_LOW_THR_MASK, 128)); 1105 airoha_qdma_rmw(qdma, REG_LMGR_INIT_CFG, 1106 LMGR_INIT_START | LMGR_SRAM_MODE_MASK | 1107 HW_FWD_DESC_NUM_MASK, 1108 FIELD_PREP(HW_FWD_DESC_NUM_MASK, num_desc) | 1109 LMGR_INIT_START | LMGR_SRAM_MODE_MASK); 1110 1111 return read_poll_timeout(airoha_qdma_rr, status, 1112 !(status & LMGR_INIT_START), USEC_PER_MSEC, 1113 30 * USEC_PER_MSEC, true, qdma, 1114 REG_LMGR_INIT_CFG); 1115 } 1116 1117 static void airoha_qdma_init_qos(struct airoha_qdma *qdma) 1118 { 1119 airoha_qdma_clear(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_SCALE_MASK); 1120 airoha_qdma_set(qdma, REG_TXWRR_MODE_CFG, TWRR_WEIGHT_BASE_MASK); 1121 1122 airoha_qdma_clear(qdma, REG_PSE_BUF_USAGE_CFG, 1123 PSE_BUF_ESTIMATE_EN_MASK); 1124 1125 airoha_qdma_set(qdma, REG_EGRESS_RATE_METER_CFG, 1126 EGRESS_RATE_METER_EN_MASK | 1127 EGRESS_RATE_METER_EQ_RATE_EN_MASK); 1128 /* 2047us x 31 = 63.457ms */ 1129 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG, 1130 EGRESS_RATE_METER_WINDOW_SZ_MASK, 1131 FIELD_PREP(EGRESS_RATE_METER_WINDOW_SZ_MASK, 0x1f)); 1132 airoha_qdma_rmw(qdma, REG_EGRESS_RATE_METER_CFG, 1133 EGRESS_RATE_METER_TIMESLICE_MASK, 1134 FIELD_PREP(EGRESS_RATE_METER_TIMESLICE_MASK, 0x7ff)); 1135 1136 /* ratelimit init */ 1137 airoha_qdma_set(qdma, REG_GLB_TRTCM_CFG, GLB_TRTCM_EN_MASK); 1138 /* fast-tick 25us */ 1139 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_FAST_TICK_MASK, 1140 FIELD_PREP(GLB_FAST_TICK_MASK, 25)); 1141 airoha_qdma_rmw(qdma, REG_GLB_TRTCM_CFG, GLB_SLOW_TICK_RATIO_MASK, 1142 FIELD_PREP(GLB_SLOW_TICK_RATIO_MASK, 40)); 1143 1144 airoha_qdma_set(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_TRTCM_EN_MASK); 1145 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG, EGRESS_FAST_TICK_MASK, 1146 FIELD_PREP(EGRESS_FAST_TICK_MASK, 25)); 1147 airoha_qdma_rmw(qdma, REG_EGRESS_TRTCM_CFG, 1148 EGRESS_SLOW_TICK_RATIO_MASK, 1149 FIELD_PREP(EGRESS_SLOW_TICK_RATIO_MASK, 40)); 1150 1151 airoha_qdma_set(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_TRTCM_EN_MASK); 1152 airoha_qdma_clear(qdma, REG_INGRESS_TRTCM_CFG, 1153 INGRESS_TRTCM_MODE_MASK); 1154 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG, INGRESS_FAST_TICK_MASK, 1155 FIELD_PREP(INGRESS_FAST_TICK_MASK, 125)); 1156 airoha_qdma_rmw(qdma, REG_INGRESS_TRTCM_CFG, 1157 INGRESS_SLOW_TICK_RATIO_MASK, 1158 FIELD_PREP(INGRESS_SLOW_TICK_RATIO_MASK, 8)); 1159 1160 airoha_qdma_set(qdma, REG_SLA_TRTCM_CFG, SLA_TRTCM_EN_MASK); 1161 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_FAST_TICK_MASK, 1162 FIELD_PREP(SLA_FAST_TICK_MASK, 25)); 1163 airoha_qdma_rmw(qdma, REG_SLA_TRTCM_CFG, SLA_SLOW_TICK_RATIO_MASK, 1164 FIELD_PREP(SLA_SLOW_TICK_RATIO_MASK, 40)); 1165 } 1166 1167 static void airoha_qdma_init_qos_stats(struct airoha_qdma *qdma) 1168 { 1169 int i; 1170 1171 for (i = 0; i < AIROHA_NUM_QOS_CHANNELS; i++) { 1172 /* Tx-cpu transferred count */ 1173 airoha_qdma_wr(qdma, REG_CNTR_VAL(i << 1), 0); 1174 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1), 1175 CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK | 1176 CNTR_ALL_DSCP_RING_EN_MASK | 1177 FIELD_PREP(CNTR_CHAN_MASK, i)); 1178 /* Tx-fwd transferred count */ 1179 airoha_qdma_wr(qdma, REG_CNTR_VAL((i << 1) + 1), 0); 1180 airoha_qdma_wr(qdma, REG_CNTR_CFG(i << 1), 1181 CNTR_EN_MASK | CNTR_ALL_QUEUE_EN_MASK | 1182 CNTR_ALL_DSCP_RING_EN_MASK | 1183 FIELD_PREP(CNTR_SRC_MASK, 1) | 1184 FIELD_PREP(CNTR_CHAN_MASK, i)); 1185 } 1186 } 1187 1188 static int airoha_qdma_hw_init(struct airoha_qdma *qdma) 1189 { 1190 int i; 1191 1192 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 1193 /* clear pending irqs */ 1194 airoha_qdma_wr(qdma, REG_INT_STATUS(i), 0xffffffff); 1195 /* setup rx irqs */ 1196 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX0, 1197 INT_RX0_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1198 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX1, 1199 INT_RX1_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1200 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX2, 1201 INT_RX2_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1202 airoha_qdma_irq_enable(&qdma->irq_banks[i], QDMA_INT_REG_IDX3, 1203 INT_RX3_MASK(RX_IRQ_BANK_PIN_MASK(i))); 1204 } 1205 /* setup tx irqs */ 1206 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX0, 1207 TX_COHERENT_LOW_INT_MASK | INT_TX_MASK); 1208 airoha_qdma_irq_enable(&qdma->irq_banks[0], QDMA_INT_REG_IDX4, 1209 TX_COHERENT_HIGH_INT_MASK); 1210 1211 /* setup irq binding */ 1212 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1213 if (!qdma->q_tx[i].ndesc) 1214 continue; 1215 1216 if (TX_RING_IRQ_BLOCKING_MAP_MASK & BIT(i)) 1217 airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(i), 1218 TX_RING_IRQ_BLOCKING_CFG_MASK); 1219 else 1220 airoha_qdma_clear(qdma, REG_TX_RING_BLOCKING(i), 1221 TX_RING_IRQ_BLOCKING_CFG_MASK); 1222 } 1223 1224 airoha_qdma_wr(qdma, REG_QDMA_GLOBAL_CFG, 1225 FIELD_PREP(GLOBAL_CFG_DMA_PREFERENCE_MASK, 3) | 1226 GLOBAL_CFG_CPU_TXR_RR_MASK | 1227 GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK | 1228 GLOBAL_CFG_MULTICAST_MODIFY_FP_MASK | 1229 GLOBAL_CFG_MULTICAST_EN_MASK | 1230 GLOBAL_CFG_IRQ0_EN_MASK | GLOBAL_CFG_IRQ1_EN_MASK | 1231 GLOBAL_CFG_TX_WB_DONE_MASK | 1232 FIELD_PREP(GLOBAL_CFG_MAX_ISSUE_NUM_MASK, 2)); 1233 1234 airoha_qdma_init_qos(qdma); 1235 1236 /* disable qdma rx delay interrupt */ 1237 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1238 if (!qdma->q_rx[i].ndesc) 1239 continue; 1240 1241 airoha_qdma_clear(qdma, REG_RX_DELAY_INT_IDX(i), 1242 RX_DELAY_INT_MASK); 1243 } 1244 1245 airoha_qdma_set(qdma, REG_TXQ_CNGST_CFG, 1246 TXQ_CNGST_DROP_EN | TXQ_CNGST_DEI_DROP_EN); 1247 airoha_qdma_init_qos_stats(qdma); 1248 1249 return 0; 1250 } 1251 1252 static irqreturn_t airoha_irq_handler(int irq, void *dev_instance) 1253 { 1254 struct airoha_irq_bank *irq_bank = dev_instance; 1255 struct airoha_qdma *qdma = irq_bank->qdma; 1256 u32 rx_intr_mask = 0, rx_intr1, rx_intr2; 1257 u32 intr[ARRAY_SIZE(irq_bank->irqmask)]; 1258 int i; 1259 1260 for (i = 0; i < ARRAY_SIZE(intr); i++) { 1261 intr[i] = airoha_qdma_rr(qdma, REG_INT_STATUS(i)); 1262 intr[i] &= irq_bank->irqmask[i]; 1263 airoha_qdma_wr(qdma, REG_INT_STATUS(i), intr[i]); 1264 } 1265 1266 if (!test_bit(DEV_STATE_INITIALIZED, &qdma->eth->state)) 1267 return IRQ_NONE; 1268 1269 rx_intr1 = intr[1] & RX_DONE_LOW_INT_MASK; 1270 if (rx_intr1) { 1271 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX1, rx_intr1); 1272 rx_intr_mask |= rx_intr1; 1273 } 1274 1275 rx_intr2 = intr[2] & RX_DONE_HIGH_INT_MASK; 1276 if (rx_intr2) { 1277 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX2, rx_intr2); 1278 rx_intr_mask |= (rx_intr2 << 16); 1279 } 1280 1281 for (i = 0; rx_intr_mask && i < ARRAY_SIZE(qdma->q_rx); i++) { 1282 if (!qdma->q_rx[i].ndesc) 1283 continue; 1284 1285 if (rx_intr_mask & BIT(i)) 1286 napi_schedule(&qdma->q_rx[i].napi); 1287 } 1288 1289 if (intr[0] & INT_TX_MASK) { 1290 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) { 1291 if (!(intr[0] & TX_DONE_INT_MASK(i))) 1292 continue; 1293 1294 airoha_qdma_irq_disable(irq_bank, QDMA_INT_REG_IDX0, 1295 TX_DONE_INT_MASK(i)); 1296 napi_schedule(&qdma->q_tx_irq[i].napi); 1297 } 1298 } 1299 1300 return IRQ_HANDLED; 1301 } 1302 1303 static int airoha_qdma_init_irq_banks(struct platform_device *pdev, 1304 struct airoha_qdma *qdma) 1305 { 1306 struct airoha_eth *eth = qdma->eth; 1307 int i, id = qdma - ð->qdma[0]; 1308 1309 for (i = 0; i < ARRAY_SIZE(qdma->irq_banks); i++) { 1310 struct airoha_irq_bank *irq_bank = &qdma->irq_banks[i]; 1311 int err, irq_index = 4 * id + i; 1312 const char *name; 1313 1314 spin_lock_init(&irq_bank->irq_lock); 1315 irq_bank->qdma = qdma; 1316 1317 irq_bank->irq = platform_get_irq(pdev, irq_index); 1318 if (irq_bank->irq < 0) 1319 return irq_bank->irq; 1320 1321 name = devm_kasprintf(eth->dev, GFP_KERNEL, 1322 KBUILD_MODNAME ".%d", irq_index); 1323 if (!name) 1324 return -ENOMEM; 1325 1326 err = devm_request_irq(eth->dev, irq_bank->irq, 1327 airoha_irq_handler, IRQF_SHARED, name, 1328 irq_bank); 1329 if (err) 1330 return err; 1331 } 1332 1333 return 0; 1334 } 1335 1336 static int airoha_qdma_init(struct platform_device *pdev, 1337 struct airoha_eth *eth, 1338 struct airoha_qdma *qdma) 1339 { 1340 int err, id = qdma - ð->qdma[0]; 1341 const char *res; 1342 1343 qdma->eth = eth; 1344 res = devm_kasprintf(eth->dev, GFP_KERNEL, "qdma%d", id); 1345 if (!res) 1346 return -ENOMEM; 1347 1348 qdma->regs = devm_platform_ioremap_resource_byname(pdev, res); 1349 if (IS_ERR(qdma->regs)) 1350 return dev_err_probe(eth->dev, PTR_ERR(qdma->regs), 1351 "failed to iomap qdma%d regs\n", id); 1352 1353 err = airoha_qdma_init_irq_banks(pdev, qdma); 1354 if (err) 1355 return err; 1356 1357 err = airoha_qdma_init_rx(qdma); 1358 if (err) 1359 return err; 1360 1361 err = airoha_qdma_init_tx(qdma); 1362 if (err) 1363 return err; 1364 1365 err = airoha_qdma_init_hfwd_queues(qdma); 1366 if (err) 1367 return err; 1368 1369 return airoha_qdma_hw_init(qdma); 1370 } 1371 1372 static int airoha_hw_init(struct platform_device *pdev, 1373 struct airoha_eth *eth) 1374 { 1375 int err, i; 1376 1377 /* disable xsi */ 1378 err = reset_control_bulk_assert(eth->soc->num_xsi_rsts, eth->xsi_rsts); 1379 if (err) 1380 return err; 1381 1382 err = reset_control_bulk_assert(ARRAY_SIZE(eth->rsts), eth->rsts); 1383 if (err) 1384 return err; 1385 1386 msleep(20); 1387 err = reset_control_bulk_deassert(ARRAY_SIZE(eth->rsts), eth->rsts); 1388 if (err) 1389 return err; 1390 1391 msleep(20); 1392 err = airoha_fe_init(eth); 1393 if (err) 1394 return err; 1395 1396 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) { 1397 err = airoha_qdma_init(pdev, eth, ð->qdma[i]); 1398 if (err) 1399 return err; 1400 } 1401 1402 err = airoha_ppe_init(eth); 1403 if (err) 1404 return err; 1405 1406 set_bit(DEV_STATE_INITIALIZED, ð->state); 1407 1408 return 0; 1409 } 1410 1411 static void airoha_hw_cleanup(struct airoha_qdma *qdma) 1412 { 1413 int i; 1414 1415 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1416 if (!qdma->q_rx[i].ndesc) 1417 continue; 1418 1419 netif_napi_del(&qdma->q_rx[i].napi); 1420 airoha_qdma_cleanup_rx_queue(&qdma->q_rx[i]); 1421 if (qdma->q_rx[i].page_pool) 1422 page_pool_destroy(qdma->q_rx[i].page_pool); 1423 } 1424 1425 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1426 netif_napi_del(&qdma->q_tx_irq[i].napi); 1427 1428 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1429 if (!qdma->q_tx[i].ndesc) 1430 continue; 1431 1432 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]); 1433 } 1434 } 1435 1436 static void airoha_qdma_start_napi(struct airoha_qdma *qdma) 1437 { 1438 int i; 1439 1440 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1441 napi_enable(&qdma->q_tx_irq[i].napi); 1442 1443 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1444 if (!qdma->q_rx[i].ndesc) 1445 continue; 1446 1447 napi_enable(&qdma->q_rx[i].napi); 1448 } 1449 } 1450 1451 static void airoha_qdma_stop_napi(struct airoha_qdma *qdma) 1452 { 1453 int i; 1454 1455 for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) 1456 napi_disable(&qdma->q_tx_irq[i].napi); 1457 1458 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 1459 if (!qdma->q_rx[i].ndesc) 1460 continue; 1461 1462 napi_disable(&qdma->q_rx[i].napi); 1463 } 1464 } 1465 1466 static void airoha_update_hw_stats(struct airoha_gdm_port *port) 1467 { 1468 struct airoha_eth *eth = port->qdma->eth; 1469 u32 val, i = 0; 1470 1471 spin_lock(&port->stats.lock); 1472 u64_stats_update_begin(&port->stats.syncp); 1473 1474 /* TX */ 1475 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_H(port->id)); 1476 port->stats.tx_ok_pkts += ((u64)val << 32); 1477 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_L(port->id)); 1478 port->stats.tx_ok_pkts += val; 1479 1480 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_H(port->id)); 1481 port->stats.tx_ok_bytes += ((u64)val << 32); 1482 val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_L(port->id)); 1483 port->stats.tx_ok_bytes += val; 1484 1485 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_DROP_CNT(port->id)); 1486 port->stats.tx_drops += val; 1487 1488 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_BC_CNT(port->id)); 1489 port->stats.tx_broadcast += val; 1490 1491 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_MC_CNT(port->id)); 1492 port->stats.tx_multicast += val; 1493 1494 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_RUNT_CNT(port->id)); 1495 port->stats.tx_len[i] += val; 1496 1497 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_H(port->id)); 1498 port->stats.tx_len[i] += ((u64)val << 32); 1499 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_L(port->id)); 1500 port->stats.tx_len[i++] += val; 1501 1502 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_H(port->id)); 1503 port->stats.tx_len[i] += ((u64)val << 32); 1504 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_L(port->id)); 1505 port->stats.tx_len[i++] += val; 1506 1507 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_H(port->id)); 1508 port->stats.tx_len[i] += ((u64)val << 32); 1509 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_L(port->id)); 1510 port->stats.tx_len[i++] += val; 1511 1512 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_H(port->id)); 1513 port->stats.tx_len[i] += ((u64)val << 32); 1514 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_L(port->id)); 1515 port->stats.tx_len[i++] += val; 1516 1517 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_H(port->id)); 1518 port->stats.tx_len[i] += ((u64)val << 32); 1519 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_L(port->id)); 1520 port->stats.tx_len[i++] += val; 1521 1522 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_H(port->id)); 1523 port->stats.tx_len[i] += ((u64)val << 32); 1524 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_L(port->id)); 1525 port->stats.tx_len[i++] += val; 1526 1527 val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_LONG_CNT(port->id)); 1528 port->stats.tx_len[i++] += val; 1529 1530 /* RX */ 1531 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_H(port->id)); 1532 port->stats.rx_ok_pkts += ((u64)val << 32); 1533 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_L(port->id)); 1534 port->stats.rx_ok_pkts += val; 1535 1536 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_H(port->id)); 1537 port->stats.rx_ok_bytes += ((u64)val << 32); 1538 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_L(port->id)); 1539 port->stats.rx_ok_bytes += val; 1540 1541 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_DROP_CNT(port->id)); 1542 port->stats.rx_drops += val; 1543 1544 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_BC_CNT(port->id)); 1545 port->stats.rx_broadcast += val; 1546 1547 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_MC_CNT(port->id)); 1548 port->stats.rx_multicast += val; 1549 1550 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ERROR_DROP_CNT(port->id)); 1551 port->stats.rx_errors += val; 1552 1553 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_CRC_ERR_CNT(port->id)); 1554 port->stats.rx_crc_error += val; 1555 1556 val = airoha_fe_rr(eth, REG_FE_GDM_RX_OVERFLOW_DROP_CNT(port->id)); 1557 port->stats.rx_over_errors += val; 1558 1559 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_FRAG_CNT(port->id)); 1560 port->stats.rx_fragment += val; 1561 1562 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_JABBER_CNT(port->id)); 1563 port->stats.rx_jabber += val; 1564 1565 i = 0; 1566 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_RUNT_CNT(port->id)); 1567 port->stats.rx_len[i] += val; 1568 1569 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_H(port->id)); 1570 port->stats.rx_len[i] += ((u64)val << 32); 1571 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_L(port->id)); 1572 port->stats.rx_len[i++] += val; 1573 1574 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_H(port->id)); 1575 port->stats.rx_len[i] += ((u64)val << 32); 1576 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_L(port->id)); 1577 port->stats.rx_len[i++] += val; 1578 1579 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_H(port->id)); 1580 port->stats.rx_len[i] += ((u64)val << 32); 1581 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_L(port->id)); 1582 port->stats.rx_len[i++] += val; 1583 1584 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_H(port->id)); 1585 port->stats.rx_len[i] += ((u64)val << 32); 1586 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_L(port->id)); 1587 port->stats.rx_len[i++] += val; 1588 1589 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_H(port->id)); 1590 port->stats.rx_len[i] += ((u64)val << 32); 1591 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_L(port->id)); 1592 port->stats.rx_len[i++] += val; 1593 1594 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_H(port->id)); 1595 port->stats.rx_len[i] += ((u64)val << 32); 1596 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_L(port->id)); 1597 port->stats.rx_len[i++] += val; 1598 1599 val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_LONG_CNT(port->id)); 1600 port->stats.rx_len[i++] += val; 1601 1602 /* reset mib counters */ 1603 airoha_fe_set(eth, REG_FE_GDM_MIB_CLEAR(port->id), 1604 FE_GDM_MIB_RX_CLEAR_MASK | FE_GDM_MIB_TX_CLEAR_MASK); 1605 1606 u64_stats_update_end(&port->stats.syncp); 1607 spin_unlock(&port->stats.lock); 1608 } 1609 1610 static int airoha_dev_open(struct net_device *dev) 1611 { 1612 int err, len = ETH_HLEN + dev->mtu + ETH_FCS_LEN; 1613 struct airoha_gdm_port *port = netdev_priv(dev); 1614 struct airoha_qdma *qdma = port->qdma; 1615 1616 netif_tx_start_all_queues(dev); 1617 err = airoha_set_vip_for_gdm_port(port, true); 1618 if (err) 1619 return err; 1620 1621 if (netdev_uses_dsa(dev)) 1622 airoha_fe_set(qdma->eth, REG_GDM_INGRESS_CFG(port->id), 1623 GDM_STAG_EN_MASK); 1624 else 1625 airoha_fe_clear(qdma->eth, REG_GDM_INGRESS_CFG(port->id), 1626 GDM_STAG_EN_MASK); 1627 1628 airoha_fe_rmw(qdma->eth, REG_GDM_LEN_CFG(port->id), 1629 GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK, 1630 FIELD_PREP(GDM_SHORT_LEN_MASK, 60) | 1631 FIELD_PREP(GDM_LONG_LEN_MASK, len)); 1632 1633 airoha_qdma_set(qdma, REG_QDMA_GLOBAL_CFG, 1634 GLOBAL_CFG_TX_DMA_EN_MASK | 1635 GLOBAL_CFG_RX_DMA_EN_MASK); 1636 atomic_inc(&qdma->users); 1637 1638 return 0; 1639 } 1640 1641 static int airoha_dev_stop(struct net_device *dev) 1642 { 1643 struct airoha_gdm_port *port = netdev_priv(dev); 1644 struct airoha_qdma *qdma = port->qdma; 1645 int i, err; 1646 1647 netif_tx_disable(dev); 1648 err = airoha_set_vip_for_gdm_port(port, false); 1649 if (err) 1650 return err; 1651 1652 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) 1653 netdev_tx_reset_subqueue(dev, i); 1654 1655 if (atomic_dec_and_test(&qdma->users)) { 1656 airoha_qdma_clear(qdma, REG_QDMA_GLOBAL_CFG, 1657 GLOBAL_CFG_TX_DMA_EN_MASK | 1658 GLOBAL_CFG_RX_DMA_EN_MASK); 1659 1660 for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) { 1661 if (!qdma->q_tx[i].ndesc) 1662 continue; 1663 1664 airoha_qdma_cleanup_tx_queue(&qdma->q_tx[i]); 1665 } 1666 } 1667 1668 return 0; 1669 } 1670 1671 static int airoha_dev_set_macaddr(struct net_device *dev, void *p) 1672 { 1673 struct airoha_gdm_port *port = netdev_priv(dev); 1674 int err; 1675 1676 err = eth_mac_addr(dev, p); 1677 if (err) 1678 return err; 1679 1680 airoha_set_macaddr(port, dev->dev_addr); 1681 1682 return 0; 1683 } 1684 1685 static int airhoha_set_gdm2_loopback(struct airoha_gdm_port *port) 1686 { 1687 struct airoha_eth *eth = port->qdma->eth; 1688 u32 val, pse_port, chan, nbq; 1689 int src_port; 1690 1691 /* Forward the traffic to the proper GDM port */ 1692 pse_port = port->id == AIROHA_GDM3_IDX ? FE_PSE_PORT_GDM3 1693 : FE_PSE_PORT_GDM4; 1694 airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(2), pse_port); 1695 airoha_fe_clear(eth, REG_GDM_FWD_CFG(2), GDM_STRIP_CRC_MASK); 1696 1697 /* Enable GDM2 loopback */ 1698 airoha_fe_wr(eth, REG_GDM_TXCHN_EN(2), 0xffffffff); 1699 airoha_fe_wr(eth, REG_GDM_RXCHN_EN(2), 0xffff); 1700 1701 chan = port->id == AIROHA_GDM3_IDX ? airoha_is_7581(eth) ? 4 : 3 : 0; 1702 airoha_fe_rmw(eth, REG_GDM_LPBK_CFG(2), 1703 LPBK_CHAN_MASK | LPBK_MODE_MASK | LPBK_EN_MASK, 1704 FIELD_PREP(LPBK_CHAN_MASK, chan) | 1705 LBK_GAP_MODE_MASK | LBK_LEN_MODE_MASK | 1706 LBK_CHAN_MODE_MASK | LPBK_EN_MASK); 1707 airoha_fe_rmw(eth, REG_GDM_LEN_CFG(2), 1708 GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK, 1709 FIELD_PREP(GDM_SHORT_LEN_MASK, 60) | 1710 FIELD_PREP(GDM_LONG_LEN_MASK, AIROHA_MAX_MTU)); 1711 1712 /* Disable VIP and IFC for GDM2 */ 1713 airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, BIT(2)); 1714 airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, BIT(2)); 1715 1716 /* XXX: handle XSI_USB_PORT and XSI_PCE1_PORT */ 1717 nbq = port->id == AIROHA_GDM3_IDX && airoha_is_7581(eth) ? 4 : 0; 1718 src_port = eth->soc->ops.get_src_port_id(port, nbq); 1719 if (src_port < 0) 1720 return src_port; 1721 1722 airoha_fe_rmw(eth, REG_FE_WAN_PORT, 1723 WAN1_EN_MASK | WAN1_MASK | WAN0_MASK, 1724 FIELD_PREP(WAN0_MASK, src_port)); 1725 val = src_port & SP_CPORT_DFT_MASK; 1726 airoha_fe_rmw(eth, 1727 REG_SP_DFT_CPORT(src_port >> fls(SP_CPORT_DFT_MASK)), 1728 SP_CPORT_MASK(val), 1729 FE_PSE_PORT_CDM2 << __ffs(SP_CPORT_MASK(val))); 1730 1731 if (port->id != AIROHA_GDM3_IDX && airoha_is_7581(eth)) 1732 airoha_fe_rmw(eth, REG_SRC_PORT_FC_MAP6, 1733 FC_ID_OF_SRC_PORT24_MASK, 1734 FIELD_PREP(FC_ID_OF_SRC_PORT24_MASK, 2)); 1735 1736 return 0; 1737 } 1738 1739 static int airoha_dev_init(struct net_device *dev) 1740 { 1741 struct airoha_gdm_port *port = netdev_priv(dev); 1742 struct airoha_qdma *qdma = port->qdma; 1743 struct airoha_eth *eth = qdma->eth; 1744 u32 pse_port, fe_cpu_port; 1745 u8 ppe_id; 1746 1747 airoha_set_macaddr(port, dev->dev_addr); 1748 1749 switch (port->id) { 1750 case 3: 1751 case 4: 1752 /* If GDM2 is active we can't enable loopback */ 1753 if (!eth->ports[1]) { 1754 int err; 1755 1756 err = airhoha_set_gdm2_loopback(port); 1757 if (err) 1758 return err; 1759 } 1760 fallthrough; 1761 case 2: 1762 if (airoha_ppe_is_enabled(eth, 1)) { 1763 /* For PPE2 always use secondary cpu port. */ 1764 fe_cpu_port = FE_PSE_PORT_CDM2; 1765 pse_port = FE_PSE_PORT_PPE2; 1766 break; 1767 } 1768 fallthrough; 1769 default: { 1770 u8 qdma_id = qdma - ð->qdma[0]; 1771 1772 /* For PPE1 select cpu port according to the running QDMA. */ 1773 fe_cpu_port = qdma_id ? FE_PSE_PORT_CDM2 : FE_PSE_PORT_CDM1; 1774 pse_port = FE_PSE_PORT_PPE1; 1775 break; 1776 } 1777 } 1778 1779 airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(port->id), pse_port); 1780 ppe_id = pse_port == FE_PSE_PORT_PPE2 ? 1 : 0; 1781 airoha_fe_rmw(eth, REG_PPE_DFT_CPORT0(ppe_id), 1782 DFT_CPORT_MASK(port->id), 1783 fe_cpu_port << __ffs(DFT_CPORT_MASK(port->id))); 1784 1785 return 0; 1786 } 1787 1788 static void airoha_dev_get_stats64(struct net_device *dev, 1789 struct rtnl_link_stats64 *storage) 1790 { 1791 struct airoha_gdm_port *port = netdev_priv(dev); 1792 unsigned int start; 1793 1794 airoha_update_hw_stats(port); 1795 do { 1796 start = u64_stats_fetch_begin(&port->stats.syncp); 1797 storage->rx_packets = port->stats.rx_ok_pkts; 1798 storage->tx_packets = port->stats.tx_ok_pkts; 1799 storage->rx_bytes = port->stats.rx_ok_bytes; 1800 storage->tx_bytes = port->stats.tx_ok_bytes; 1801 storage->multicast = port->stats.rx_multicast; 1802 storage->rx_errors = port->stats.rx_errors; 1803 storage->rx_dropped = port->stats.rx_drops; 1804 storage->tx_dropped = port->stats.tx_drops; 1805 storage->rx_crc_errors = port->stats.rx_crc_error; 1806 storage->rx_over_errors = port->stats.rx_over_errors; 1807 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 1808 } 1809 1810 static int airoha_dev_change_mtu(struct net_device *dev, int mtu) 1811 { 1812 struct airoha_gdm_port *port = netdev_priv(dev); 1813 struct airoha_eth *eth = port->qdma->eth; 1814 u32 len = ETH_HLEN + mtu + ETH_FCS_LEN; 1815 1816 airoha_fe_rmw(eth, REG_GDM_LEN_CFG(port->id), 1817 GDM_LONG_LEN_MASK, 1818 FIELD_PREP(GDM_LONG_LEN_MASK, len)); 1819 WRITE_ONCE(dev->mtu, mtu); 1820 1821 return 0; 1822 } 1823 1824 static u16 airoha_dev_select_queue(struct net_device *dev, struct sk_buff *skb, 1825 struct net_device *sb_dev) 1826 { 1827 struct airoha_gdm_port *port = netdev_priv(dev); 1828 int queue, channel; 1829 1830 /* For dsa device select QoS channel according to the dsa user port 1831 * index, rely on port id otherwise. Select QoS queue based on the 1832 * skb priority. 1833 */ 1834 channel = netdev_uses_dsa(dev) ? skb_get_queue_mapping(skb) : port->id; 1835 channel = channel % AIROHA_NUM_QOS_CHANNELS; 1836 queue = (skb->priority - 1) % AIROHA_NUM_QOS_QUEUES; /* QoS queue */ 1837 queue = channel * AIROHA_NUM_QOS_QUEUES + queue; 1838 1839 return queue < dev->num_tx_queues ? queue : 0; 1840 } 1841 1842 static u32 airoha_get_dsa_tag(struct sk_buff *skb, struct net_device *dev) 1843 { 1844 #if IS_ENABLED(CONFIG_NET_DSA) 1845 struct ethhdr *ehdr; 1846 u8 xmit_tpid; 1847 u16 tag; 1848 1849 if (!netdev_uses_dsa(dev)) 1850 return 0; 1851 1852 if (dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK) 1853 return 0; 1854 1855 if (skb_cow_head(skb, 0)) 1856 return 0; 1857 1858 ehdr = (struct ethhdr *)skb->data; 1859 tag = be16_to_cpu(ehdr->h_proto); 1860 xmit_tpid = tag >> 8; 1861 1862 switch (xmit_tpid) { 1863 case MTK_HDR_XMIT_TAGGED_TPID_8100: 1864 ehdr->h_proto = cpu_to_be16(ETH_P_8021Q); 1865 tag &= ~(MTK_HDR_XMIT_TAGGED_TPID_8100 << 8); 1866 break; 1867 case MTK_HDR_XMIT_TAGGED_TPID_88A8: 1868 ehdr->h_proto = cpu_to_be16(ETH_P_8021AD); 1869 tag &= ~(MTK_HDR_XMIT_TAGGED_TPID_88A8 << 8); 1870 break; 1871 default: 1872 /* PPE module requires untagged DSA packets to work properly, 1873 * so move DSA tag to DMA descriptor. 1874 */ 1875 memmove(skb->data + MTK_HDR_LEN, skb->data, 2 * ETH_ALEN); 1876 __skb_pull(skb, MTK_HDR_LEN); 1877 break; 1878 } 1879 1880 return tag; 1881 #else 1882 return 0; 1883 #endif 1884 } 1885 1886 static bool airoha_dev_tx_queue_busy(struct airoha_queue *q, u32 nr_frags) 1887 { 1888 u32 tail = q->tail <= q->head ? q->tail + q->ndesc : q->tail; 1889 u32 index = q->head + nr_frags; 1890 1891 /* completion napi can free out-of-order tx descriptors if hw QoS is 1892 * enabled and packets with different priorities are queued to the same 1893 * DMA ring. Take into account possible out-of-order reports checking 1894 * if the tx queue is full using circular buffer head/tail pointers 1895 * instead of the number of queued packets. 1896 */ 1897 return index >= tail; 1898 } 1899 1900 static int airoha_get_fe_port(struct airoha_gdm_port *port) 1901 { 1902 struct airoha_qdma *qdma = port->qdma; 1903 struct airoha_eth *eth = qdma->eth; 1904 1905 switch (eth->soc->version) { 1906 case 0x7583: 1907 return port->id == AIROHA_GDM3_IDX ? FE_PSE_PORT_GDM3 1908 : port->id; 1909 case 0x7581: 1910 default: 1911 return port->id == AIROHA_GDM4_IDX ? FE_PSE_PORT_GDM4 1912 : port->id; 1913 } 1914 } 1915 1916 static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb, 1917 struct net_device *dev) 1918 { 1919 struct airoha_gdm_port *port = netdev_priv(dev); 1920 struct airoha_qdma *qdma = port->qdma; 1921 u32 nr_frags, tag, msg0, msg1, len; 1922 struct netdev_queue *txq; 1923 struct airoha_queue *q; 1924 void *data; 1925 int i, qid; 1926 u16 index; 1927 u8 fport; 1928 1929 qid = skb_get_queue_mapping(skb) % ARRAY_SIZE(qdma->q_tx); 1930 tag = airoha_get_dsa_tag(skb, dev); 1931 1932 msg0 = FIELD_PREP(QDMA_ETH_TXMSG_CHAN_MASK, 1933 qid / AIROHA_NUM_QOS_QUEUES) | 1934 FIELD_PREP(QDMA_ETH_TXMSG_QUEUE_MASK, 1935 qid % AIROHA_NUM_QOS_QUEUES) | 1936 FIELD_PREP(QDMA_ETH_TXMSG_SP_TAG_MASK, tag); 1937 if (skb->ip_summed == CHECKSUM_PARTIAL) 1938 msg0 |= FIELD_PREP(QDMA_ETH_TXMSG_TCO_MASK, 1) | 1939 FIELD_PREP(QDMA_ETH_TXMSG_UCO_MASK, 1) | 1940 FIELD_PREP(QDMA_ETH_TXMSG_ICO_MASK, 1); 1941 1942 /* TSO: fill MSS info in tcp checksum field */ 1943 if (skb_is_gso(skb)) { 1944 if (skb_cow_head(skb, 0)) 1945 goto error; 1946 1947 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | 1948 SKB_GSO_TCPV6)) { 1949 __be16 csum = cpu_to_be16(skb_shinfo(skb)->gso_size); 1950 1951 tcp_hdr(skb)->check = (__force __sum16)csum; 1952 msg0 |= FIELD_PREP(QDMA_ETH_TXMSG_TSO_MASK, 1); 1953 } 1954 } 1955 1956 fport = airoha_get_fe_port(port); 1957 msg1 = FIELD_PREP(QDMA_ETH_TXMSG_FPORT_MASK, fport) | 1958 FIELD_PREP(QDMA_ETH_TXMSG_METER_MASK, 0x7f); 1959 1960 q = &qdma->q_tx[qid]; 1961 if (WARN_ON_ONCE(!q->ndesc)) 1962 goto error; 1963 1964 spin_lock_bh(&q->lock); 1965 1966 txq = netdev_get_tx_queue(dev, qid); 1967 nr_frags = 1 + skb_shinfo(skb)->nr_frags; 1968 1969 if (airoha_dev_tx_queue_busy(q, nr_frags)) { 1970 /* not enough space in the queue */ 1971 netif_tx_stop_queue(txq); 1972 spin_unlock_bh(&q->lock); 1973 return NETDEV_TX_BUSY; 1974 } 1975 1976 len = skb_headlen(skb); 1977 data = skb->data; 1978 index = q->head; 1979 1980 for (i = 0; i < nr_frags; i++) { 1981 struct airoha_qdma_desc *desc = &q->desc[index]; 1982 struct airoha_queue_entry *e = &q->entry[index]; 1983 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1984 dma_addr_t addr; 1985 u32 val; 1986 1987 addr = dma_map_single(dev->dev.parent, data, len, 1988 DMA_TO_DEVICE); 1989 if (unlikely(dma_mapping_error(dev->dev.parent, addr))) 1990 goto error_unmap; 1991 1992 index = (index + 1) % q->ndesc; 1993 1994 val = FIELD_PREP(QDMA_DESC_LEN_MASK, len); 1995 if (i < nr_frags - 1) 1996 val |= FIELD_PREP(QDMA_DESC_MORE_MASK, 1); 1997 WRITE_ONCE(desc->ctrl, cpu_to_le32(val)); 1998 WRITE_ONCE(desc->addr, cpu_to_le32(addr)); 1999 val = FIELD_PREP(QDMA_DESC_NEXT_ID_MASK, index); 2000 WRITE_ONCE(desc->data, cpu_to_le32(val)); 2001 WRITE_ONCE(desc->msg0, cpu_to_le32(msg0)); 2002 WRITE_ONCE(desc->msg1, cpu_to_le32(msg1)); 2003 WRITE_ONCE(desc->msg2, cpu_to_le32(0xffff)); 2004 2005 e->skb = i ? NULL : skb; 2006 e->dma_addr = addr; 2007 e->dma_len = len; 2008 2009 data = skb_frag_address(frag); 2010 len = skb_frag_size(frag); 2011 } 2012 2013 q->head = index; 2014 q->queued += i; 2015 2016 skb_tx_timestamp(skb); 2017 netdev_tx_sent_queue(txq, skb->len); 2018 2019 if (netif_xmit_stopped(txq) || !netdev_xmit_more()) 2020 airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), 2021 TX_RING_CPU_IDX_MASK, 2022 FIELD_PREP(TX_RING_CPU_IDX_MASK, q->head)); 2023 2024 if (q->ndesc - q->queued < q->free_thr) 2025 netif_tx_stop_queue(txq); 2026 2027 spin_unlock_bh(&q->lock); 2028 2029 return NETDEV_TX_OK; 2030 2031 error_unmap: 2032 for (i--; i >= 0; i--) { 2033 index = (q->head + i) % q->ndesc; 2034 dma_unmap_single(dev->dev.parent, q->entry[index].dma_addr, 2035 q->entry[index].dma_len, DMA_TO_DEVICE); 2036 } 2037 2038 spin_unlock_bh(&q->lock); 2039 error: 2040 dev_kfree_skb_any(skb); 2041 dev->stats.tx_dropped++; 2042 2043 return NETDEV_TX_OK; 2044 } 2045 2046 static void airoha_ethtool_get_drvinfo(struct net_device *dev, 2047 struct ethtool_drvinfo *info) 2048 { 2049 struct airoha_gdm_port *port = netdev_priv(dev); 2050 struct airoha_eth *eth = port->qdma->eth; 2051 2052 strscpy(info->driver, eth->dev->driver->name, sizeof(info->driver)); 2053 strscpy(info->bus_info, dev_name(eth->dev), sizeof(info->bus_info)); 2054 } 2055 2056 static void airoha_ethtool_get_mac_stats(struct net_device *dev, 2057 struct ethtool_eth_mac_stats *stats) 2058 { 2059 struct airoha_gdm_port *port = netdev_priv(dev); 2060 unsigned int start; 2061 2062 airoha_update_hw_stats(port); 2063 do { 2064 start = u64_stats_fetch_begin(&port->stats.syncp); 2065 stats->FramesTransmittedOK = port->stats.tx_ok_pkts; 2066 stats->OctetsTransmittedOK = port->stats.tx_ok_bytes; 2067 stats->MulticastFramesXmittedOK = port->stats.tx_multicast; 2068 stats->BroadcastFramesXmittedOK = port->stats.tx_broadcast; 2069 stats->FramesReceivedOK = port->stats.rx_ok_pkts; 2070 stats->OctetsReceivedOK = port->stats.rx_ok_bytes; 2071 stats->BroadcastFramesReceivedOK = port->stats.rx_broadcast; 2072 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 2073 } 2074 2075 static const struct ethtool_rmon_hist_range airoha_ethtool_rmon_ranges[] = { 2076 { 0, 64 }, 2077 { 65, 127 }, 2078 { 128, 255 }, 2079 { 256, 511 }, 2080 { 512, 1023 }, 2081 { 1024, 1518 }, 2082 { 1519, 10239 }, 2083 {}, 2084 }; 2085 2086 static void 2087 airoha_ethtool_get_rmon_stats(struct net_device *dev, 2088 struct ethtool_rmon_stats *stats, 2089 const struct ethtool_rmon_hist_range **ranges) 2090 { 2091 struct airoha_gdm_port *port = netdev_priv(dev); 2092 struct airoha_hw_stats *hw_stats = &port->stats; 2093 unsigned int start; 2094 2095 BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) != 2096 ARRAY_SIZE(hw_stats->tx_len) + 1); 2097 BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) != 2098 ARRAY_SIZE(hw_stats->rx_len) + 1); 2099 2100 *ranges = airoha_ethtool_rmon_ranges; 2101 airoha_update_hw_stats(port); 2102 do { 2103 int i; 2104 2105 start = u64_stats_fetch_begin(&port->stats.syncp); 2106 stats->fragments = hw_stats->rx_fragment; 2107 stats->jabbers = hw_stats->rx_jabber; 2108 for (i = 0; i < ARRAY_SIZE(airoha_ethtool_rmon_ranges) - 1; 2109 i++) { 2110 stats->hist[i] = hw_stats->rx_len[i]; 2111 stats->hist_tx[i] = hw_stats->tx_len[i]; 2112 } 2113 } while (u64_stats_fetch_retry(&port->stats.syncp, start)); 2114 } 2115 2116 static int airoha_qdma_set_chan_tx_sched(struct airoha_gdm_port *port, 2117 int channel, enum tx_sched_mode mode, 2118 const u16 *weights, u8 n_weights) 2119 { 2120 int i; 2121 2122 for (i = 0; i < AIROHA_NUM_TX_RING; i++) 2123 airoha_qdma_clear(port->qdma, REG_QUEUE_CLOSE_CFG(channel), 2124 TXQ_DISABLE_CHAN_QUEUE_MASK(channel, i)); 2125 2126 for (i = 0; i < n_weights; i++) { 2127 u32 status; 2128 int err; 2129 2130 airoha_qdma_wr(port->qdma, REG_TXWRR_WEIGHT_CFG, 2131 TWRR_RW_CMD_MASK | 2132 FIELD_PREP(TWRR_CHAN_IDX_MASK, channel) | 2133 FIELD_PREP(TWRR_QUEUE_IDX_MASK, i) | 2134 FIELD_PREP(TWRR_VALUE_MASK, weights[i])); 2135 err = read_poll_timeout(airoha_qdma_rr, status, 2136 status & TWRR_RW_CMD_DONE, 2137 USEC_PER_MSEC, 10 * USEC_PER_MSEC, 2138 true, port->qdma, 2139 REG_TXWRR_WEIGHT_CFG); 2140 if (err) 2141 return err; 2142 } 2143 2144 airoha_qdma_rmw(port->qdma, REG_CHAN_QOS_MODE(channel >> 3), 2145 CHAN_QOS_MODE_MASK(channel), 2146 mode << __ffs(CHAN_QOS_MODE_MASK(channel))); 2147 2148 return 0; 2149 } 2150 2151 static int airoha_qdma_set_tx_prio_sched(struct airoha_gdm_port *port, 2152 int channel) 2153 { 2154 static const u16 w[AIROHA_NUM_QOS_QUEUES] = {}; 2155 2156 return airoha_qdma_set_chan_tx_sched(port, channel, TC_SCH_SP, w, 2157 ARRAY_SIZE(w)); 2158 } 2159 2160 static int airoha_qdma_set_tx_ets_sched(struct airoha_gdm_port *port, 2161 int channel, 2162 struct tc_ets_qopt_offload *opt) 2163 { 2164 struct tc_ets_qopt_offload_replace_params *p = &opt->replace_params; 2165 enum tx_sched_mode mode = TC_SCH_SP; 2166 u16 w[AIROHA_NUM_QOS_QUEUES] = {}; 2167 int i, nstrict = 0; 2168 2169 if (p->bands > AIROHA_NUM_QOS_QUEUES) 2170 return -EINVAL; 2171 2172 for (i = 0; i < p->bands; i++) { 2173 if (!p->quanta[i]) 2174 nstrict++; 2175 } 2176 2177 /* this configuration is not supported by the hw */ 2178 if (nstrict == AIROHA_NUM_QOS_QUEUES - 1) 2179 return -EINVAL; 2180 2181 /* EN7581 SoC supports fixed QoS band priority where WRR queues have 2182 * lowest priorities with respect to SP ones. 2183 * e.g: WRR0, WRR1, .., WRRm, SP0, SP1, .., SPn 2184 */ 2185 for (i = 0; i < nstrict; i++) { 2186 if (p->priomap[p->bands - i - 1] != i) 2187 return -EINVAL; 2188 } 2189 2190 for (i = 0; i < p->bands - nstrict; i++) { 2191 if (p->priomap[i] != nstrict + i) 2192 return -EINVAL; 2193 2194 w[i] = p->weights[nstrict + i]; 2195 } 2196 2197 if (!nstrict) 2198 mode = TC_SCH_WRR8; 2199 else if (nstrict < AIROHA_NUM_QOS_QUEUES - 1) 2200 mode = nstrict + 1; 2201 2202 return airoha_qdma_set_chan_tx_sched(port, channel, mode, w, 2203 ARRAY_SIZE(w)); 2204 } 2205 2206 static int airoha_qdma_get_tx_ets_stats(struct airoha_gdm_port *port, 2207 int channel, 2208 struct tc_ets_qopt_offload *opt) 2209 { 2210 u64 cpu_tx_packets = airoha_qdma_rr(port->qdma, 2211 REG_CNTR_VAL(channel << 1)); 2212 u64 fwd_tx_packets = airoha_qdma_rr(port->qdma, 2213 REG_CNTR_VAL((channel << 1) + 1)); 2214 u64 tx_packets = (cpu_tx_packets - port->cpu_tx_packets) + 2215 (fwd_tx_packets - port->fwd_tx_packets); 2216 _bstats_update(opt->stats.bstats, 0, tx_packets); 2217 2218 port->cpu_tx_packets = cpu_tx_packets; 2219 port->fwd_tx_packets = fwd_tx_packets; 2220 2221 return 0; 2222 } 2223 2224 static int airoha_tc_setup_qdisc_ets(struct airoha_gdm_port *port, 2225 struct tc_ets_qopt_offload *opt) 2226 { 2227 int channel; 2228 2229 if (opt->parent == TC_H_ROOT) 2230 return -EINVAL; 2231 2232 channel = TC_H_MAJ(opt->handle) >> 16; 2233 channel = channel % AIROHA_NUM_QOS_CHANNELS; 2234 2235 switch (opt->command) { 2236 case TC_ETS_REPLACE: 2237 return airoha_qdma_set_tx_ets_sched(port, channel, opt); 2238 case TC_ETS_DESTROY: 2239 /* PRIO is default qdisc scheduler */ 2240 return airoha_qdma_set_tx_prio_sched(port, channel); 2241 case TC_ETS_STATS: 2242 return airoha_qdma_get_tx_ets_stats(port, channel, opt); 2243 default: 2244 return -EOPNOTSUPP; 2245 } 2246 } 2247 2248 static int airoha_qdma_get_rl_param(struct airoha_qdma *qdma, int queue_id, 2249 u32 addr, enum trtcm_param_type param, 2250 u32 *val_low, u32 *val_high) 2251 { 2252 u32 idx = QDMA_METER_IDX(queue_id), group = QDMA_METER_GROUP(queue_id); 2253 u32 val, config = FIELD_PREP(RATE_LIMIT_PARAM_TYPE_MASK, param) | 2254 FIELD_PREP(RATE_LIMIT_METER_GROUP_MASK, group) | 2255 FIELD_PREP(RATE_LIMIT_PARAM_INDEX_MASK, idx); 2256 2257 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2258 if (read_poll_timeout(airoha_qdma_rr, val, 2259 val & RATE_LIMIT_PARAM_RW_DONE_MASK, 2260 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, qdma, 2261 REG_TRTCM_CFG_PARAM(addr))) 2262 return -ETIMEDOUT; 2263 2264 *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr)); 2265 if (val_high) 2266 *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr)); 2267 2268 return 0; 2269 } 2270 2271 static int airoha_qdma_set_rl_param(struct airoha_qdma *qdma, int queue_id, 2272 u32 addr, enum trtcm_param_type param, 2273 u32 val) 2274 { 2275 u32 idx = QDMA_METER_IDX(queue_id), group = QDMA_METER_GROUP(queue_id); 2276 u32 config = RATE_LIMIT_PARAM_RW_MASK | 2277 FIELD_PREP(RATE_LIMIT_PARAM_TYPE_MASK, param) | 2278 FIELD_PREP(RATE_LIMIT_METER_GROUP_MASK, group) | 2279 FIELD_PREP(RATE_LIMIT_PARAM_INDEX_MASK, idx); 2280 2281 airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val); 2282 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2283 2284 return read_poll_timeout(airoha_qdma_rr, val, 2285 val & RATE_LIMIT_PARAM_RW_DONE_MASK, 2286 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2287 qdma, REG_TRTCM_CFG_PARAM(addr)); 2288 } 2289 2290 static int airoha_qdma_set_rl_config(struct airoha_qdma *qdma, int queue_id, 2291 u32 addr, bool enable, u32 enable_mask) 2292 { 2293 u32 val; 2294 int err; 2295 2296 err = airoha_qdma_get_rl_param(qdma, queue_id, addr, TRTCM_MISC_MODE, 2297 &val, NULL); 2298 if (err) 2299 return err; 2300 2301 val = enable ? val | enable_mask : val & ~enable_mask; 2302 2303 return airoha_qdma_set_rl_param(qdma, queue_id, addr, TRTCM_MISC_MODE, 2304 val); 2305 } 2306 2307 static int airoha_qdma_set_rl_token_bucket(struct airoha_qdma *qdma, 2308 int queue_id, u32 rate_val, 2309 u32 bucket_size) 2310 { 2311 u32 val, config, tick, unit, rate, rate_frac; 2312 int err; 2313 2314 err = airoha_qdma_get_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2315 TRTCM_MISC_MODE, &config, NULL); 2316 if (err) 2317 return err; 2318 2319 val = airoha_qdma_rr(qdma, REG_INGRESS_TRTCM_CFG); 2320 tick = FIELD_GET(INGRESS_FAST_TICK_MASK, val); 2321 if (config & TRTCM_TICK_SEL) 2322 tick *= FIELD_GET(INGRESS_SLOW_TICK_RATIO_MASK, val); 2323 if (!tick) 2324 return -EINVAL; 2325 2326 unit = (config & TRTCM_PKT_MODE) ? 1000000 / tick : 8000 / tick; 2327 if (!unit) 2328 return -EINVAL; 2329 2330 rate = rate_val / unit; 2331 rate_frac = rate_val % unit; 2332 rate_frac = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate_frac) / unit; 2333 rate = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate) | 2334 FIELD_PREP(TRTCM_TOKEN_RATE_FRACTION_MASK, rate_frac); 2335 2336 err = airoha_qdma_set_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2337 TRTCM_TOKEN_RATE_MODE, rate); 2338 if (err) 2339 return err; 2340 2341 val = bucket_size; 2342 if (!(config & TRTCM_PKT_MODE)) 2343 val = max_t(u32, val, MIN_TOKEN_SIZE); 2344 val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET); 2345 2346 return airoha_qdma_set_rl_param(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2347 TRTCM_BUCKETSIZE_SHIFT_MODE, val); 2348 } 2349 2350 static int airoha_qdma_init_rl_config(struct airoha_qdma *qdma, int queue_id, 2351 bool enable, enum trtcm_unit_type unit) 2352 { 2353 bool tick_sel = queue_id == 0 || queue_id == 2 || queue_id == 8; 2354 enum trtcm_param mode = TRTCM_METER_MODE; 2355 int err; 2356 2357 mode |= unit == TRTCM_PACKET_UNIT ? TRTCM_PKT_MODE : 0; 2358 err = airoha_qdma_set_rl_config(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2359 enable, mode); 2360 if (err) 2361 return err; 2362 2363 return airoha_qdma_set_rl_config(qdma, queue_id, REG_INGRESS_TRTCM_CFG, 2364 tick_sel, TRTCM_TICK_SEL); 2365 } 2366 2367 static int airoha_qdma_get_trtcm_param(struct airoha_qdma *qdma, int channel, 2368 u32 addr, enum trtcm_param_type param, 2369 enum trtcm_mode_type mode, 2370 u32 *val_low, u32 *val_high) 2371 { 2372 u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel); 2373 u32 val, config = FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) | 2374 FIELD_PREP(TRTCM_METER_GROUP_MASK, group) | 2375 FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) | 2376 FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode); 2377 2378 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2379 if (read_poll_timeout(airoha_qdma_rr, val, 2380 val & TRTCM_PARAM_RW_DONE_MASK, 2381 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2382 qdma, REG_TRTCM_CFG_PARAM(addr))) 2383 return -ETIMEDOUT; 2384 2385 *val_low = airoha_qdma_rr(qdma, REG_TRTCM_DATA_LOW(addr)); 2386 if (val_high) 2387 *val_high = airoha_qdma_rr(qdma, REG_TRTCM_DATA_HIGH(addr)); 2388 2389 return 0; 2390 } 2391 2392 static int airoha_qdma_set_trtcm_param(struct airoha_qdma *qdma, int channel, 2393 u32 addr, enum trtcm_param_type param, 2394 enum trtcm_mode_type mode, u32 val) 2395 { 2396 u32 idx = QDMA_METER_IDX(channel), group = QDMA_METER_GROUP(channel); 2397 u32 config = TRTCM_PARAM_RW_MASK | 2398 FIELD_PREP(TRTCM_PARAM_TYPE_MASK, param) | 2399 FIELD_PREP(TRTCM_METER_GROUP_MASK, group) | 2400 FIELD_PREP(TRTCM_PARAM_INDEX_MASK, idx) | 2401 FIELD_PREP(TRTCM_PARAM_RATE_TYPE_MASK, mode); 2402 2403 airoha_qdma_wr(qdma, REG_TRTCM_DATA_LOW(addr), val); 2404 airoha_qdma_wr(qdma, REG_TRTCM_CFG_PARAM(addr), config); 2405 2406 return read_poll_timeout(airoha_qdma_rr, val, 2407 val & TRTCM_PARAM_RW_DONE_MASK, 2408 USEC_PER_MSEC, 10 * USEC_PER_MSEC, true, 2409 qdma, REG_TRTCM_CFG_PARAM(addr)); 2410 } 2411 2412 static int airoha_qdma_set_trtcm_config(struct airoha_qdma *qdma, int channel, 2413 u32 addr, enum trtcm_mode_type mode, 2414 bool enable, u32 enable_mask) 2415 { 2416 u32 val; 2417 2418 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2419 mode, &val, NULL)) 2420 return -EINVAL; 2421 2422 val = enable ? val | enable_mask : val & ~enable_mask; 2423 2424 return airoha_qdma_set_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2425 mode, val); 2426 } 2427 2428 static int airoha_qdma_set_trtcm_token_bucket(struct airoha_qdma *qdma, 2429 int channel, u32 addr, 2430 enum trtcm_mode_type mode, 2431 u32 rate_val, u32 bucket_size) 2432 { 2433 u32 val, config, tick, unit, rate, rate_frac; 2434 int err; 2435 2436 if (airoha_qdma_get_trtcm_param(qdma, channel, addr, TRTCM_MISC_MODE, 2437 mode, &config, NULL)) 2438 return -EINVAL; 2439 2440 val = airoha_qdma_rr(qdma, addr); 2441 tick = FIELD_GET(INGRESS_FAST_TICK_MASK, val); 2442 if (config & TRTCM_TICK_SEL) 2443 tick *= FIELD_GET(INGRESS_SLOW_TICK_RATIO_MASK, val); 2444 if (!tick) 2445 return -EINVAL; 2446 2447 unit = (config & TRTCM_PKT_MODE) ? 1000000 / tick : 8000 / tick; 2448 if (!unit) 2449 return -EINVAL; 2450 2451 rate = rate_val / unit; 2452 rate_frac = rate_val % unit; 2453 rate_frac = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate_frac) / unit; 2454 rate = FIELD_PREP(TRTCM_TOKEN_RATE_MASK, rate) | 2455 FIELD_PREP(TRTCM_TOKEN_RATE_FRACTION_MASK, rate_frac); 2456 2457 err = airoha_qdma_set_trtcm_param(qdma, channel, addr, 2458 TRTCM_TOKEN_RATE_MODE, mode, rate); 2459 if (err) 2460 return err; 2461 2462 val = max_t(u32, bucket_size, MIN_TOKEN_SIZE); 2463 val = min_t(u32, __fls(val), MAX_TOKEN_SIZE_OFFSET); 2464 2465 return airoha_qdma_set_trtcm_param(qdma, channel, addr, 2466 TRTCM_BUCKETSIZE_SHIFT_MODE, 2467 mode, val); 2468 } 2469 2470 static int airoha_qdma_set_tx_rate_limit(struct airoha_gdm_port *port, 2471 int channel, u32 rate, 2472 u32 bucket_size) 2473 { 2474 int i, err; 2475 2476 for (i = 0; i <= TRTCM_PEAK_MODE; i++) { 2477 err = airoha_qdma_set_trtcm_config(port->qdma, channel, 2478 REG_EGRESS_TRTCM_CFG, i, 2479 !!rate, TRTCM_METER_MODE); 2480 if (err) 2481 return err; 2482 2483 err = airoha_qdma_set_trtcm_token_bucket(port->qdma, channel, 2484 REG_EGRESS_TRTCM_CFG, 2485 i, rate, bucket_size); 2486 if (err) 2487 return err; 2488 } 2489 2490 return 0; 2491 } 2492 2493 static int airoha_tc_htb_alloc_leaf_queue(struct airoha_gdm_port *port, 2494 struct tc_htb_qopt_offload *opt) 2495 { 2496 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2497 u32 rate = div_u64(opt->rate, 1000) << 3; /* kbps */ 2498 struct net_device *dev = port->dev; 2499 int num_tx_queues = dev->real_num_tx_queues; 2500 int err; 2501 2502 if (opt->parent_classid != TC_HTB_CLASSID_ROOT) { 2503 NL_SET_ERR_MSG_MOD(opt->extack, "invalid parent classid"); 2504 return -EINVAL; 2505 } 2506 2507 err = airoha_qdma_set_tx_rate_limit(port, channel, rate, opt->quantum); 2508 if (err) { 2509 NL_SET_ERR_MSG_MOD(opt->extack, 2510 "failed configuring htb offload"); 2511 return err; 2512 } 2513 2514 if (opt->command == TC_HTB_NODE_MODIFY) 2515 return 0; 2516 2517 err = netif_set_real_num_tx_queues(dev, num_tx_queues + 1); 2518 if (err) { 2519 airoha_qdma_set_tx_rate_limit(port, channel, 0, opt->quantum); 2520 NL_SET_ERR_MSG_MOD(opt->extack, 2521 "failed setting real_num_tx_queues"); 2522 return err; 2523 } 2524 2525 set_bit(channel, port->qos_sq_bmap); 2526 opt->qid = AIROHA_NUM_TX_RING + channel; 2527 2528 return 0; 2529 } 2530 2531 static int airoha_qdma_set_rx_meter(struct airoha_gdm_port *port, 2532 u32 rate, u32 bucket_size, 2533 enum trtcm_unit_type unit_type) 2534 { 2535 struct airoha_qdma *qdma = port->qdma; 2536 int i; 2537 2538 for (i = 0; i < ARRAY_SIZE(qdma->q_rx); i++) { 2539 int err; 2540 2541 if (!qdma->q_rx[i].ndesc) 2542 continue; 2543 2544 err = airoha_qdma_init_rl_config(qdma, i, !!rate, unit_type); 2545 if (err) 2546 return err; 2547 2548 err = airoha_qdma_set_rl_token_bucket(qdma, i, rate, 2549 bucket_size); 2550 if (err) 2551 return err; 2552 } 2553 2554 return 0; 2555 } 2556 2557 static int airoha_tc_matchall_act_validate(struct tc_cls_matchall_offload *f) 2558 { 2559 const struct flow_action *actions = &f->rule->action; 2560 const struct flow_action_entry *act; 2561 2562 if (!flow_action_has_entries(actions)) { 2563 NL_SET_ERR_MSG_MOD(f->common.extack, 2564 "filter run with no actions"); 2565 return -EINVAL; 2566 } 2567 2568 if (!flow_offload_has_one_action(actions)) { 2569 NL_SET_ERR_MSG_MOD(f->common.extack, 2570 "only once action per filter is supported"); 2571 return -EOPNOTSUPP; 2572 } 2573 2574 act = &actions->entries[0]; 2575 if (act->id != FLOW_ACTION_POLICE) { 2576 NL_SET_ERR_MSG_MOD(f->common.extack, "unsupported action"); 2577 return -EOPNOTSUPP; 2578 } 2579 2580 if (act->police.exceed.act_id != FLOW_ACTION_DROP) { 2581 NL_SET_ERR_MSG_MOD(f->common.extack, 2582 "invalid exceed action id"); 2583 return -EOPNOTSUPP; 2584 } 2585 2586 if (act->police.notexceed.act_id != FLOW_ACTION_ACCEPT) { 2587 NL_SET_ERR_MSG_MOD(f->common.extack, 2588 "invalid notexceed action id"); 2589 return -EOPNOTSUPP; 2590 } 2591 2592 if (act->police.notexceed.act_id == FLOW_ACTION_ACCEPT && 2593 !flow_action_is_last_entry(actions, act)) { 2594 NL_SET_ERR_MSG_MOD(f->common.extack, 2595 "action accept must be last"); 2596 return -EOPNOTSUPP; 2597 } 2598 2599 if (act->police.peakrate_bytes_ps || act->police.avrate || 2600 act->police.overhead || act->police.mtu) { 2601 NL_SET_ERR_MSG_MOD(f->common.extack, 2602 "peakrate/avrate/overhead/mtu unsupported"); 2603 return -EOPNOTSUPP; 2604 } 2605 2606 return 0; 2607 } 2608 2609 static int airoha_dev_tc_matchall(struct net_device *dev, 2610 struct tc_cls_matchall_offload *f) 2611 { 2612 enum trtcm_unit_type unit_type = TRTCM_BYTE_UNIT; 2613 struct airoha_gdm_port *port = netdev_priv(dev); 2614 u32 rate = 0, bucket_size = 0; 2615 2616 switch (f->command) { 2617 case TC_CLSMATCHALL_REPLACE: { 2618 const struct flow_action_entry *act; 2619 int err; 2620 2621 err = airoha_tc_matchall_act_validate(f); 2622 if (err) 2623 return err; 2624 2625 act = &f->rule->action.entries[0]; 2626 if (act->police.rate_pkt_ps) { 2627 rate = act->police.rate_pkt_ps; 2628 bucket_size = act->police.burst_pkt; 2629 unit_type = TRTCM_PACKET_UNIT; 2630 } else { 2631 rate = div_u64(act->police.rate_bytes_ps, 1000); 2632 rate = rate << 3; /* Kbps */ 2633 bucket_size = act->police.burst; 2634 } 2635 fallthrough; 2636 } 2637 case TC_CLSMATCHALL_DESTROY: 2638 return airoha_qdma_set_rx_meter(port, rate, bucket_size, 2639 unit_type); 2640 default: 2641 return -EOPNOTSUPP; 2642 } 2643 } 2644 2645 static int airoha_dev_setup_tc_block_cb(enum tc_setup_type type, 2646 void *type_data, void *cb_priv) 2647 { 2648 struct net_device *dev = cb_priv; 2649 struct airoha_gdm_port *port = netdev_priv(dev); 2650 struct airoha_eth *eth = port->qdma->eth; 2651 2652 if (!tc_can_offload(dev)) 2653 return -EOPNOTSUPP; 2654 2655 switch (type) { 2656 case TC_SETUP_CLSFLOWER: 2657 return airoha_ppe_setup_tc_block_cb(ð->ppe->dev, type_data); 2658 case TC_SETUP_CLSMATCHALL: 2659 return airoha_dev_tc_matchall(dev, type_data); 2660 default: 2661 return -EOPNOTSUPP; 2662 } 2663 } 2664 2665 static int airoha_dev_setup_tc_block(struct airoha_gdm_port *port, 2666 struct flow_block_offload *f) 2667 { 2668 flow_setup_cb_t *cb = airoha_dev_setup_tc_block_cb; 2669 static LIST_HEAD(block_cb_list); 2670 struct flow_block_cb *block_cb; 2671 2672 if (f->binder_type != FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 2673 return -EOPNOTSUPP; 2674 2675 f->driver_block_list = &block_cb_list; 2676 switch (f->command) { 2677 case FLOW_BLOCK_BIND: 2678 block_cb = flow_block_cb_lookup(f->block, cb, port->dev); 2679 if (block_cb) { 2680 flow_block_cb_incref(block_cb); 2681 return 0; 2682 } 2683 block_cb = flow_block_cb_alloc(cb, port->dev, port->dev, NULL); 2684 if (IS_ERR(block_cb)) 2685 return PTR_ERR(block_cb); 2686 2687 flow_block_cb_incref(block_cb); 2688 flow_block_cb_add(block_cb, f); 2689 list_add_tail(&block_cb->driver_list, &block_cb_list); 2690 return 0; 2691 case FLOW_BLOCK_UNBIND: 2692 block_cb = flow_block_cb_lookup(f->block, cb, port->dev); 2693 if (!block_cb) 2694 return -ENOENT; 2695 2696 if (!flow_block_cb_decref(block_cb)) { 2697 flow_block_cb_remove(block_cb, f); 2698 list_del(&block_cb->driver_list); 2699 } 2700 return 0; 2701 default: 2702 return -EOPNOTSUPP; 2703 } 2704 } 2705 2706 static void airoha_tc_remove_htb_queue(struct airoha_gdm_port *port, int queue) 2707 { 2708 struct net_device *dev = port->dev; 2709 2710 netif_set_real_num_tx_queues(dev, dev->real_num_tx_queues - 1); 2711 airoha_qdma_set_tx_rate_limit(port, queue + 1, 0, 0); 2712 clear_bit(queue, port->qos_sq_bmap); 2713 } 2714 2715 static int airoha_tc_htb_delete_leaf_queue(struct airoha_gdm_port *port, 2716 struct tc_htb_qopt_offload *opt) 2717 { 2718 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2719 2720 if (!test_bit(channel, port->qos_sq_bmap)) { 2721 NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id"); 2722 return -EINVAL; 2723 } 2724 2725 airoha_tc_remove_htb_queue(port, channel); 2726 2727 return 0; 2728 } 2729 2730 static int airoha_tc_htb_destroy(struct airoha_gdm_port *port) 2731 { 2732 int q; 2733 2734 for_each_set_bit(q, port->qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS) 2735 airoha_tc_remove_htb_queue(port, q); 2736 2737 return 0; 2738 } 2739 2740 static int airoha_tc_get_htb_get_leaf_queue(struct airoha_gdm_port *port, 2741 struct tc_htb_qopt_offload *opt) 2742 { 2743 u32 channel = TC_H_MIN(opt->classid) % AIROHA_NUM_QOS_CHANNELS; 2744 2745 if (!test_bit(channel, port->qos_sq_bmap)) { 2746 NL_SET_ERR_MSG_MOD(opt->extack, "invalid queue id"); 2747 return -EINVAL; 2748 } 2749 2750 opt->qid = AIROHA_NUM_TX_RING + channel; 2751 2752 return 0; 2753 } 2754 2755 static int airoha_tc_setup_qdisc_htb(struct airoha_gdm_port *port, 2756 struct tc_htb_qopt_offload *opt) 2757 { 2758 switch (opt->command) { 2759 case TC_HTB_CREATE: 2760 break; 2761 case TC_HTB_DESTROY: 2762 return airoha_tc_htb_destroy(port); 2763 case TC_HTB_NODE_MODIFY: 2764 case TC_HTB_LEAF_ALLOC_QUEUE: 2765 return airoha_tc_htb_alloc_leaf_queue(port, opt); 2766 case TC_HTB_LEAF_DEL: 2767 case TC_HTB_LEAF_DEL_LAST: 2768 case TC_HTB_LEAF_DEL_LAST_FORCE: 2769 return airoha_tc_htb_delete_leaf_queue(port, opt); 2770 case TC_HTB_LEAF_QUERY_QUEUE: 2771 return airoha_tc_get_htb_get_leaf_queue(port, opt); 2772 default: 2773 return -EOPNOTSUPP; 2774 } 2775 2776 return 0; 2777 } 2778 2779 static int airoha_dev_tc_setup(struct net_device *dev, enum tc_setup_type type, 2780 void *type_data) 2781 { 2782 struct airoha_gdm_port *port = netdev_priv(dev); 2783 2784 switch (type) { 2785 case TC_SETUP_QDISC_ETS: 2786 return airoha_tc_setup_qdisc_ets(port, type_data); 2787 case TC_SETUP_QDISC_HTB: 2788 return airoha_tc_setup_qdisc_htb(port, type_data); 2789 case TC_SETUP_BLOCK: 2790 case TC_SETUP_FT: 2791 return airoha_dev_setup_tc_block(port, type_data); 2792 default: 2793 return -EOPNOTSUPP; 2794 } 2795 } 2796 2797 static const struct net_device_ops airoha_netdev_ops = { 2798 .ndo_init = airoha_dev_init, 2799 .ndo_open = airoha_dev_open, 2800 .ndo_stop = airoha_dev_stop, 2801 .ndo_change_mtu = airoha_dev_change_mtu, 2802 .ndo_select_queue = airoha_dev_select_queue, 2803 .ndo_start_xmit = airoha_dev_xmit, 2804 .ndo_get_stats64 = airoha_dev_get_stats64, 2805 .ndo_set_mac_address = airoha_dev_set_macaddr, 2806 .ndo_setup_tc = airoha_dev_tc_setup, 2807 }; 2808 2809 static const struct ethtool_ops airoha_ethtool_ops = { 2810 .get_drvinfo = airoha_ethtool_get_drvinfo, 2811 .get_eth_mac_stats = airoha_ethtool_get_mac_stats, 2812 .get_rmon_stats = airoha_ethtool_get_rmon_stats, 2813 .get_link = ethtool_op_get_link, 2814 }; 2815 2816 static int airoha_metadata_dst_alloc(struct airoha_gdm_port *port) 2817 { 2818 int i; 2819 2820 for (i = 0; i < ARRAY_SIZE(port->dsa_meta); i++) { 2821 struct metadata_dst *md_dst; 2822 2823 md_dst = metadata_dst_alloc(0, METADATA_HW_PORT_MUX, 2824 GFP_KERNEL); 2825 if (!md_dst) 2826 return -ENOMEM; 2827 2828 md_dst->u.port_info.port_id = i; 2829 port->dsa_meta[i] = md_dst; 2830 } 2831 2832 return 0; 2833 } 2834 2835 static void airoha_metadata_dst_free(struct airoha_gdm_port *port) 2836 { 2837 int i; 2838 2839 for (i = 0; i < ARRAY_SIZE(port->dsa_meta); i++) { 2840 if (!port->dsa_meta[i]) 2841 continue; 2842 2843 metadata_dst_free(port->dsa_meta[i]); 2844 } 2845 } 2846 2847 bool airoha_is_valid_gdm_port(struct airoha_eth *eth, 2848 struct airoha_gdm_port *port) 2849 { 2850 int i; 2851 2852 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 2853 if (eth->ports[i] == port) 2854 return true; 2855 } 2856 2857 return false; 2858 } 2859 2860 static int airoha_alloc_gdm_port(struct airoha_eth *eth, 2861 struct device_node *np, int index) 2862 { 2863 const __be32 *id_ptr = of_get_property(np, "reg", NULL); 2864 struct airoha_gdm_port *port; 2865 struct airoha_qdma *qdma; 2866 struct net_device *dev; 2867 int err, p; 2868 u32 id; 2869 2870 if (!id_ptr) { 2871 dev_err(eth->dev, "missing gdm port id\n"); 2872 return -EINVAL; 2873 } 2874 2875 id = be32_to_cpup(id_ptr); 2876 p = id - 1; 2877 2878 if (!id || id > ARRAY_SIZE(eth->ports)) { 2879 dev_err(eth->dev, "invalid gdm port id: %d\n", id); 2880 return -EINVAL; 2881 } 2882 2883 if (eth->ports[p]) { 2884 dev_err(eth->dev, "duplicate gdm port id: %d\n", id); 2885 return -EINVAL; 2886 } 2887 2888 dev = devm_alloc_etherdev_mqs(eth->dev, sizeof(*port), 2889 AIROHA_NUM_NETDEV_TX_RINGS, 2890 AIROHA_NUM_RX_RING); 2891 if (!dev) { 2892 dev_err(eth->dev, "alloc_etherdev failed\n"); 2893 return -ENOMEM; 2894 } 2895 2896 qdma = ð->qdma[index % AIROHA_MAX_NUM_QDMA]; 2897 dev->netdev_ops = &airoha_netdev_ops; 2898 dev->ethtool_ops = &airoha_ethtool_ops; 2899 dev->max_mtu = AIROHA_MAX_MTU; 2900 dev->watchdog_timeo = 5 * HZ; 2901 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 2902 NETIF_F_TSO6 | NETIF_F_IPV6_CSUM | 2903 NETIF_F_SG | NETIF_F_TSO | 2904 NETIF_F_HW_TC; 2905 dev->features |= dev->hw_features; 2906 dev->vlan_features = dev->hw_features; 2907 dev->dev.of_node = np; 2908 dev->irq = qdma->irq_banks[0].irq; 2909 SET_NETDEV_DEV(dev, eth->dev); 2910 2911 /* reserve hw queues for HTB offloading */ 2912 err = netif_set_real_num_tx_queues(dev, AIROHA_NUM_TX_RING); 2913 if (err) 2914 return err; 2915 2916 err = of_get_ethdev_address(np, dev); 2917 if (err) { 2918 if (err == -EPROBE_DEFER) 2919 return err; 2920 2921 eth_hw_addr_random(dev); 2922 dev_info(eth->dev, "generated random MAC address %pM\n", 2923 dev->dev_addr); 2924 } 2925 2926 port = netdev_priv(dev); 2927 u64_stats_init(&port->stats.syncp); 2928 spin_lock_init(&port->stats.lock); 2929 port->qdma = qdma; 2930 port->dev = dev; 2931 port->id = id; 2932 eth->ports[p] = port; 2933 2934 err = airoha_metadata_dst_alloc(port); 2935 if (err) 2936 return err; 2937 2938 err = register_netdev(dev); 2939 if (err) 2940 goto free_metadata_dst; 2941 2942 return 0; 2943 2944 free_metadata_dst: 2945 airoha_metadata_dst_free(port); 2946 return err; 2947 } 2948 2949 static int airoha_probe(struct platform_device *pdev) 2950 { 2951 struct reset_control_bulk_data *xsi_rsts; 2952 struct device_node *np; 2953 struct airoha_eth *eth; 2954 int i, err; 2955 2956 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); 2957 if (!eth) 2958 return -ENOMEM; 2959 2960 eth->soc = of_device_get_match_data(&pdev->dev); 2961 if (!eth->soc) 2962 return -EINVAL; 2963 2964 eth->dev = &pdev->dev; 2965 2966 err = dma_set_mask_and_coherent(eth->dev, DMA_BIT_MASK(32)); 2967 if (err) { 2968 dev_err(eth->dev, "failed configuring DMA mask\n"); 2969 return err; 2970 } 2971 2972 eth->fe_regs = devm_platform_ioremap_resource_byname(pdev, "fe"); 2973 if (IS_ERR(eth->fe_regs)) 2974 return dev_err_probe(eth->dev, PTR_ERR(eth->fe_regs), 2975 "failed to iomap fe regs\n"); 2976 2977 eth->rsts[0].id = "fe"; 2978 eth->rsts[1].id = "pdma"; 2979 eth->rsts[2].id = "qdma"; 2980 err = devm_reset_control_bulk_get_exclusive(eth->dev, 2981 ARRAY_SIZE(eth->rsts), 2982 eth->rsts); 2983 if (err) { 2984 dev_err(eth->dev, "failed to get bulk reset lines\n"); 2985 return err; 2986 } 2987 2988 xsi_rsts = devm_kcalloc(eth->dev, 2989 eth->soc->num_xsi_rsts, sizeof(*xsi_rsts), 2990 GFP_KERNEL); 2991 if (!xsi_rsts) 2992 return -ENOMEM; 2993 2994 eth->xsi_rsts = xsi_rsts; 2995 for (i = 0; i < eth->soc->num_xsi_rsts; i++) 2996 eth->xsi_rsts[i].id = eth->soc->xsi_rsts_names[i]; 2997 2998 err = devm_reset_control_bulk_get_exclusive(eth->dev, 2999 eth->soc->num_xsi_rsts, 3000 eth->xsi_rsts); 3001 if (err) { 3002 dev_err(eth->dev, "failed to get bulk xsi reset lines\n"); 3003 return err; 3004 } 3005 3006 eth->napi_dev = alloc_netdev_dummy(0); 3007 if (!eth->napi_dev) 3008 return -ENOMEM; 3009 3010 /* Enable threaded NAPI by default */ 3011 eth->napi_dev->threaded = true; 3012 strscpy(eth->napi_dev->name, "qdma_eth", sizeof(eth->napi_dev->name)); 3013 platform_set_drvdata(pdev, eth); 3014 3015 err = airoha_hw_init(pdev, eth); 3016 if (err) 3017 goto error_hw_cleanup; 3018 3019 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 3020 airoha_qdma_start_napi(ð->qdma[i]); 3021 3022 i = 0; 3023 for_each_child_of_node(pdev->dev.of_node, np) { 3024 if (!of_device_is_compatible(np, "airoha,eth-mac")) 3025 continue; 3026 3027 if (!of_device_is_available(np)) 3028 continue; 3029 3030 err = airoha_alloc_gdm_port(eth, np, i++); 3031 if (err) { 3032 of_node_put(np); 3033 goto error_napi_stop; 3034 } 3035 } 3036 3037 return 0; 3038 3039 error_napi_stop: 3040 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 3041 airoha_qdma_stop_napi(ð->qdma[i]); 3042 airoha_ppe_deinit(eth); 3043 error_hw_cleanup: 3044 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) 3045 airoha_hw_cleanup(ð->qdma[i]); 3046 3047 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 3048 struct airoha_gdm_port *port = eth->ports[i]; 3049 3050 if (port && port->dev->reg_state == NETREG_REGISTERED) { 3051 unregister_netdev(port->dev); 3052 airoha_metadata_dst_free(port); 3053 } 3054 } 3055 free_netdev(eth->napi_dev); 3056 platform_set_drvdata(pdev, NULL); 3057 3058 return err; 3059 } 3060 3061 static void airoha_remove(struct platform_device *pdev) 3062 { 3063 struct airoha_eth *eth = platform_get_drvdata(pdev); 3064 int i; 3065 3066 for (i = 0; i < ARRAY_SIZE(eth->qdma); i++) { 3067 airoha_qdma_stop_napi(ð->qdma[i]); 3068 airoha_hw_cleanup(ð->qdma[i]); 3069 } 3070 3071 for (i = 0; i < ARRAY_SIZE(eth->ports); i++) { 3072 struct airoha_gdm_port *port = eth->ports[i]; 3073 3074 if (!port) 3075 continue; 3076 3077 airoha_dev_stop(port->dev); 3078 unregister_netdev(port->dev); 3079 airoha_metadata_dst_free(port); 3080 } 3081 free_netdev(eth->napi_dev); 3082 3083 airoha_ppe_deinit(eth); 3084 platform_set_drvdata(pdev, NULL); 3085 } 3086 3087 static const char * const en7581_xsi_rsts_names[] = { 3088 "xsi-mac", 3089 "hsi0-mac", 3090 "hsi1-mac", 3091 "hsi-mac", 3092 "xfp-mac", 3093 }; 3094 3095 static int airoha_en7581_get_src_port_id(struct airoha_gdm_port *port, int nbq) 3096 { 3097 switch (port->id) { 3098 case 3: 3099 /* 7581 SoC supports PCIe serdes on GDM3 port */ 3100 if (nbq == 4) 3101 return HSGMII_LAN_7581_PCIE0_SRCPORT; 3102 if (nbq == 5) 3103 return HSGMII_LAN_7581_PCIE1_SRCPORT; 3104 break; 3105 case 4: 3106 /* 7581 SoC supports eth and usb serdes on GDM4 port */ 3107 if (!nbq) 3108 return HSGMII_LAN_7581_ETH_SRCPORT; 3109 if (nbq == 1) 3110 return HSGMII_LAN_7581_USB_SRCPORT; 3111 break; 3112 default: 3113 break; 3114 } 3115 3116 return -EINVAL; 3117 } 3118 3119 static const char * const an7583_xsi_rsts_names[] = { 3120 "xsi-mac", 3121 "hsi0-mac", 3122 "hsi1-mac", 3123 "xfp-mac", 3124 }; 3125 3126 static int airoha_an7583_get_src_port_id(struct airoha_gdm_port *port, int nbq) 3127 { 3128 switch (port->id) { 3129 case 3: 3130 /* 7583 SoC supports eth serdes on GDM3 port */ 3131 if (!nbq) 3132 return HSGMII_LAN_7583_ETH_SRCPORT; 3133 break; 3134 case 4: 3135 /* 7583 SoC supports PCIe and USB serdes on GDM4 port */ 3136 if (!nbq) 3137 return HSGMII_LAN_7583_PCIE_SRCPORT; 3138 if (nbq == 1) 3139 return HSGMII_LAN_7583_USB_SRCPORT; 3140 break; 3141 default: 3142 break; 3143 } 3144 3145 return -EINVAL; 3146 } 3147 3148 static const struct airoha_eth_soc_data en7581_soc_data = { 3149 .version = 0x7581, 3150 .xsi_rsts_names = en7581_xsi_rsts_names, 3151 .num_xsi_rsts = ARRAY_SIZE(en7581_xsi_rsts_names), 3152 .num_ppe = 2, 3153 .ops = { 3154 .get_src_port_id = airoha_en7581_get_src_port_id, 3155 }, 3156 }; 3157 3158 static const struct airoha_eth_soc_data an7583_soc_data = { 3159 .version = 0x7583, 3160 .xsi_rsts_names = an7583_xsi_rsts_names, 3161 .num_xsi_rsts = ARRAY_SIZE(an7583_xsi_rsts_names), 3162 .num_ppe = 1, 3163 .ops = { 3164 .get_src_port_id = airoha_an7583_get_src_port_id, 3165 }, 3166 }; 3167 3168 static const struct of_device_id of_airoha_match[] = { 3169 { .compatible = "airoha,en7581-eth", .data = &en7581_soc_data }, 3170 { .compatible = "airoha,an7583-eth", .data = &an7583_soc_data }, 3171 { /* sentinel */ } 3172 }; 3173 MODULE_DEVICE_TABLE(of, of_airoha_match); 3174 3175 static struct platform_driver airoha_driver = { 3176 .probe = airoha_probe, 3177 .remove = airoha_remove, 3178 .driver = { 3179 .name = KBUILD_MODNAME, 3180 .of_match_table = of_airoha_match, 3181 }, 3182 }; 3183 module_platform_driver(airoha_driver); 3184 3185 MODULE_LICENSE("GPL"); 3186 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 3187 MODULE_DESCRIPTION("Ethernet driver for Airoha SoC"); 3188