1 // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 2 /* ADIN1110 Low Power 10BASE-T1L Ethernet MAC-PHY 3 * ADIN2111 2-Port Ethernet Switch with Integrated 10BASE-T1L PHY 4 * 5 * Copyright 2021 Analog Devices Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/cache.h> 11 #include <linux/crc8.h> 12 #include <linux/etherdevice.h> 13 #include <linux/ethtool.h> 14 #include <linux/if_bridge.h> 15 #include <linux/interrupt.h> 16 #include <linux/iopoll.h> 17 #include <linux/gpio.h> 18 #include <linux/kernel.h> 19 #include <linux/mii.h> 20 #include <linux/module.h> 21 #include <linux/netdevice.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/phy.h> 24 #include <linux/property.h> 25 #include <linux/spi/spi.h> 26 27 #include <net/switchdev.h> 28 29 #include <asm/unaligned.h> 30 31 #define ADIN1110_PHY_ID 0x1 32 33 #define ADIN1110_RESET 0x03 34 #define ADIN1110_SWRESET BIT(0) 35 36 #define ADIN1110_CONFIG1 0x04 37 #define ADIN1110_CONFIG1_SYNC BIT(15) 38 39 #define ADIN1110_CONFIG2 0x06 40 #define ADIN2111_P2_FWD_UNK2HOST BIT(12) 41 #define ADIN2111_PORT_CUT_THRU_EN BIT(11) 42 #define ADIN1110_CRC_APPEND BIT(5) 43 #define ADIN1110_FWD_UNK2HOST BIT(2) 44 45 #define ADIN1110_STATUS0 0x08 46 47 #define ADIN1110_STATUS1 0x09 48 #define ADIN2111_P2_RX_RDY BIT(17) 49 #define ADIN1110_SPI_ERR BIT(10) 50 #define ADIN1110_RX_RDY BIT(4) 51 52 #define ADIN1110_IMASK1 0x0D 53 #define ADIN2111_RX_RDY_IRQ BIT(17) 54 #define ADIN1110_SPI_ERR_IRQ BIT(10) 55 #define ADIN1110_RX_RDY_IRQ BIT(4) 56 #define ADIN1110_TX_RDY_IRQ BIT(3) 57 58 #define ADIN1110_MDIOACC 0x20 59 #define ADIN1110_MDIO_TRDONE BIT(31) 60 #define ADIN1110_MDIO_ST GENMASK(29, 28) 61 #define ADIN1110_MDIO_OP GENMASK(27, 26) 62 #define ADIN1110_MDIO_PRTAD GENMASK(25, 21) 63 #define ADIN1110_MDIO_DEVAD GENMASK(20, 16) 64 #define ADIN1110_MDIO_DATA GENMASK(15, 0) 65 66 #define ADIN1110_TX_FSIZE 0x30 67 #define ADIN1110_TX 0x31 68 #define ADIN1110_TX_SPACE 0x32 69 70 #define ADIN1110_MAC_ADDR_FILTER_UPR 0x50 71 #define ADIN2111_MAC_ADDR_APPLY2PORT2 BIT(31) 72 #define ADIN1110_MAC_ADDR_APPLY2PORT BIT(30) 73 #define ADIN2111_MAC_ADDR_TO_OTHER_PORT BIT(17) 74 #define ADIN1110_MAC_ADDR_TO_HOST BIT(16) 75 76 #define ADIN1110_MAC_ADDR_FILTER_LWR 0x51 77 78 #define ADIN1110_MAC_ADDR_MASK_UPR 0x70 79 #define ADIN1110_MAC_ADDR_MASK_LWR 0x71 80 81 #define ADIN1110_RX_FSIZE 0x90 82 #define ADIN1110_RX 0x91 83 84 #define ADIN2111_RX_P2_FSIZE 0xC0 85 #define ADIN2111_RX_P2 0xC1 86 87 #define ADIN1110_CLEAR_STATUS0 0xFFF 88 89 /* MDIO_OP codes */ 90 #define ADIN1110_MDIO_OP_WR 0x1 91 #define ADIN1110_MDIO_OP_RD 0x3 92 93 #define ADIN1110_CD BIT(7) 94 #define ADIN1110_WRITE BIT(5) 95 96 #define ADIN1110_MAX_BUFF 2048 97 #define ADIN1110_MAX_FRAMES_READ 64 98 #define ADIN1110_WR_HEADER_LEN 2 99 #define ADIN1110_FRAME_HEADER_LEN 2 100 #define ADIN1110_INTERNAL_SIZE_HEADER_LEN 2 101 #define ADIN1110_RD_HEADER_LEN 3 102 #define ADIN1110_REG_LEN 4 103 #define ADIN1110_FEC_LEN 4 104 105 #define ADIN1110_PHY_ID_VAL 0x0283BC91 106 #define ADIN2111_PHY_ID_VAL 0x0283BCA1 107 108 #define ADIN_MAC_MAX_PORTS 2 109 #define ADIN_MAC_MAX_ADDR_SLOTS 16 110 111 #define ADIN_MAC_MULTICAST_ADDR_SLOT 0 112 #define ADIN_MAC_BROADCAST_ADDR_SLOT 1 113 #define ADIN_MAC_P1_ADDR_SLOT 2 114 #define ADIN_MAC_P2_ADDR_SLOT 3 115 #define ADIN_MAC_FDB_ADDR_SLOT 4 116 117 DECLARE_CRC8_TABLE(adin1110_crc_table); 118 119 enum adin1110_chips_id { 120 ADIN1110_MAC = 0, 121 ADIN2111_MAC, 122 }; 123 124 struct adin1110_cfg { 125 enum adin1110_chips_id id; 126 char name[MDIO_NAME_SIZE]; 127 u32 phy_ids[PHY_MAX_ADDR]; 128 u32 ports_nr; 129 u32 phy_id_val; 130 }; 131 132 struct adin1110_port_priv { 133 struct adin1110_priv *priv; 134 struct net_device *netdev; 135 struct net_device *bridge; 136 struct phy_device *phydev; 137 struct work_struct tx_work; 138 u64 rx_packets; 139 u64 tx_packets; 140 u64 rx_bytes; 141 u64 tx_bytes; 142 struct work_struct rx_mode_work; 143 u32 flags; 144 struct sk_buff_head txq; 145 u32 nr; 146 u32 state; 147 struct adin1110_cfg *cfg; 148 }; 149 150 struct adin1110_priv { 151 struct mutex lock; /* protect spi */ 152 spinlock_t state_lock; /* protect RX mode */ 153 struct mii_bus *mii_bus; 154 struct spi_device *spidev; 155 bool append_crc; 156 struct adin1110_cfg *cfg; 157 u32 tx_space; 158 u32 irq_mask; 159 bool forwarding; 160 int irq; 161 struct adin1110_port_priv *ports[ADIN_MAC_MAX_PORTS]; 162 char mii_bus_name[MII_BUS_ID_SIZE]; 163 u8 data[ADIN1110_MAX_BUFF] ____cacheline_aligned; 164 }; 165 166 struct adin1110_switchdev_event_work { 167 struct work_struct work; 168 struct switchdev_notifier_fdb_info fdb_info; 169 struct adin1110_port_priv *port_priv; 170 unsigned long event; 171 }; 172 173 static struct adin1110_cfg adin1110_cfgs[] = { 174 { 175 .id = ADIN1110_MAC, 176 .name = "adin1110", 177 .phy_ids = {1}, 178 .ports_nr = 1, 179 .phy_id_val = ADIN1110_PHY_ID_VAL, 180 }, 181 { 182 .id = ADIN2111_MAC, 183 .name = "adin2111", 184 .phy_ids = {1, 2}, 185 .ports_nr = 2, 186 .phy_id_val = ADIN2111_PHY_ID_VAL, 187 }, 188 }; 189 190 static u8 adin1110_crc_data(u8 *data, u32 len) 191 { 192 return crc8(adin1110_crc_table, data, len, 0); 193 } 194 195 static int adin1110_read_reg(struct adin1110_priv *priv, u16 reg, u32 *val) 196 { 197 u32 header_len = ADIN1110_RD_HEADER_LEN; 198 u32 read_len = ADIN1110_REG_LEN; 199 struct spi_transfer t = {0}; 200 int ret; 201 202 priv->data[0] = ADIN1110_CD | FIELD_GET(GENMASK(12, 8), reg); 203 priv->data[1] = FIELD_GET(GENMASK(7, 0), reg); 204 priv->data[2] = 0x00; 205 206 if (priv->append_crc) { 207 priv->data[2] = adin1110_crc_data(&priv->data[0], 2); 208 priv->data[3] = 0x00; 209 header_len++; 210 } 211 212 if (priv->append_crc) 213 read_len++; 214 215 memset(&priv->data[header_len], 0, read_len); 216 t.tx_buf = &priv->data[0]; 217 t.rx_buf = &priv->data[0]; 218 t.len = read_len + header_len; 219 220 ret = spi_sync_transfer(priv->spidev, &t, 1); 221 if (ret) 222 return ret; 223 224 if (priv->append_crc) { 225 u8 recv_crc; 226 u8 crc; 227 228 crc = adin1110_crc_data(&priv->data[header_len], 229 ADIN1110_REG_LEN); 230 recv_crc = priv->data[header_len + ADIN1110_REG_LEN]; 231 232 if (crc != recv_crc) { 233 dev_err_ratelimited(&priv->spidev->dev, "CRC error."); 234 return -EBADMSG; 235 } 236 } 237 238 *val = get_unaligned_be32(&priv->data[header_len]); 239 240 return ret; 241 } 242 243 static int adin1110_write_reg(struct adin1110_priv *priv, u16 reg, u32 val) 244 { 245 u32 header_len = ADIN1110_WR_HEADER_LEN; 246 u32 write_len = ADIN1110_REG_LEN; 247 248 priv->data[0] = ADIN1110_CD | ADIN1110_WRITE | FIELD_GET(GENMASK(12, 8), reg); 249 priv->data[1] = FIELD_GET(GENMASK(7, 0), reg); 250 251 if (priv->append_crc) { 252 priv->data[2] = adin1110_crc_data(&priv->data[0], header_len); 253 header_len++; 254 } 255 256 put_unaligned_be32(val, &priv->data[header_len]); 257 if (priv->append_crc) { 258 priv->data[header_len + write_len] = adin1110_crc_data(&priv->data[header_len], 259 write_len); 260 write_len++; 261 } 262 263 return spi_write(priv->spidev, &priv->data[0], header_len + write_len); 264 } 265 266 static int adin1110_set_bits(struct adin1110_priv *priv, u16 reg, 267 unsigned long mask, unsigned long val) 268 { 269 u32 write_val; 270 int ret; 271 272 ret = adin1110_read_reg(priv, reg, &write_val); 273 if (ret < 0) 274 return ret; 275 276 set_mask_bits(&write_val, mask, val); 277 278 return adin1110_write_reg(priv, reg, write_val); 279 } 280 281 static int adin1110_round_len(int len) 282 { 283 /* can read/write only mutiples of 4 bytes of payload */ 284 len = ALIGN(len, 4); 285 286 /* NOTE: ADIN1110_WR_HEADER_LEN should be used for write ops. */ 287 if (len + ADIN1110_RD_HEADER_LEN > ADIN1110_MAX_BUFF) 288 return -EINVAL; 289 290 return len; 291 } 292 293 static int adin1110_read_fifo(struct adin1110_port_priv *port_priv) 294 { 295 struct adin1110_priv *priv = port_priv->priv; 296 u32 header_len = ADIN1110_RD_HEADER_LEN; 297 struct spi_transfer t; 298 u32 frame_size_no_fcs; 299 struct sk_buff *rxb; 300 u32 frame_size; 301 int round_len; 302 u16 reg; 303 int ret; 304 305 if (!port_priv->nr) { 306 reg = ADIN1110_RX; 307 ret = adin1110_read_reg(priv, ADIN1110_RX_FSIZE, &frame_size); 308 } else { 309 reg = ADIN2111_RX_P2; 310 ret = adin1110_read_reg(priv, ADIN2111_RX_P2_FSIZE, 311 &frame_size); 312 } 313 314 if (ret < 0) 315 return ret; 316 317 /* The read frame size includes the extra 2 bytes 318 * from the ADIN1110 frame header. 319 */ 320 if (frame_size < ADIN1110_FRAME_HEADER_LEN + ADIN1110_FEC_LEN) 321 return ret; 322 323 round_len = adin1110_round_len(frame_size); 324 if (round_len < 0) 325 return ret; 326 327 frame_size_no_fcs = frame_size - ADIN1110_FRAME_HEADER_LEN - ADIN1110_FEC_LEN; 328 memset(priv->data, 0, ADIN1110_RD_HEADER_LEN); 329 330 priv->data[0] = ADIN1110_CD | FIELD_GET(GENMASK(12, 8), reg); 331 priv->data[1] = FIELD_GET(GENMASK(7, 0), reg); 332 333 if (priv->append_crc) { 334 priv->data[2] = adin1110_crc_data(&priv->data[0], 2); 335 header_len++; 336 } 337 338 rxb = netdev_alloc_skb(port_priv->netdev, round_len + header_len); 339 if (!rxb) 340 return -ENOMEM; 341 342 skb_put(rxb, frame_size_no_fcs + header_len + ADIN1110_FRAME_HEADER_LEN); 343 344 t.tx_buf = &priv->data[0]; 345 t.rx_buf = &rxb->data[0]; 346 t.len = header_len + round_len; 347 348 ret = spi_sync_transfer(priv->spidev, &t, 1); 349 if (ret) { 350 kfree_skb(rxb); 351 return ret; 352 } 353 354 skb_pull(rxb, header_len + ADIN1110_FRAME_HEADER_LEN); 355 rxb->protocol = eth_type_trans(rxb, port_priv->netdev); 356 357 if ((port_priv->flags & IFF_ALLMULTI && rxb->pkt_type == PACKET_MULTICAST) || 358 (port_priv->flags & IFF_BROADCAST && rxb->pkt_type == PACKET_BROADCAST)) 359 rxb->offload_fwd_mark = 1; 360 361 netif_rx(rxb); 362 363 port_priv->rx_bytes += frame_size - ADIN1110_FRAME_HEADER_LEN; 364 port_priv->rx_packets++; 365 366 return 0; 367 } 368 369 static int adin1110_write_fifo(struct adin1110_port_priv *port_priv, 370 struct sk_buff *txb) 371 { 372 struct adin1110_priv *priv = port_priv->priv; 373 u32 header_len = ADIN1110_WR_HEADER_LEN; 374 __be16 frame_header; 375 int padding = 0; 376 int padded_len; 377 int round_len; 378 int ret; 379 380 /* Pad frame to 64 byte length, 381 * MAC nor PHY will otherwise add the 382 * required padding. 383 * The FEC will be added by the MAC internally. 384 */ 385 if (txb->len + ADIN1110_FEC_LEN < 64) 386 padding = 64 - (txb->len + ADIN1110_FEC_LEN); 387 388 padded_len = txb->len + padding + ADIN1110_FRAME_HEADER_LEN; 389 390 round_len = adin1110_round_len(padded_len); 391 if (round_len < 0) 392 return round_len; 393 394 ret = adin1110_write_reg(priv, ADIN1110_TX_FSIZE, padded_len); 395 if (ret < 0) 396 return ret; 397 398 memset(priv->data, 0, round_len + ADIN1110_WR_HEADER_LEN); 399 400 priv->data[0] = ADIN1110_CD | ADIN1110_WRITE; 401 priv->data[0] |= FIELD_GET(GENMASK(12, 8), ADIN1110_TX); 402 priv->data[1] = FIELD_GET(GENMASK(7, 0), ADIN1110_TX); 403 if (priv->append_crc) { 404 priv->data[2] = adin1110_crc_data(&priv->data[0], 2); 405 header_len++; 406 } 407 408 /* mention the port on which to send the frame in the frame header */ 409 frame_header = cpu_to_be16(port_priv->nr); 410 memcpy(&priv->data[header_len], &frame_header, 411 ADIN1110_FRAME_HEADER_LEN); 412 413 memcpy(&priv->data[header_len + ADIN1110_FRAME_HEADER_LEN], 414 txb->data, txb->len); 415 416 ret = spi_write(priv->spidev, &priv->data[0], round_len + header_len); 417 if (ret < 0) 418 return ret; 419 420 port_priv->tx_bytes += txb->len; 421 port_priv->tx_packets++; 422 423 return 0; 424 } 425 426 static int adin1110_read_mdio_acc(struct adin1110_priv *priv) 427 { 428 u32 val; 429 int ret; 430 431 mutex_lock(&priv->lock); 432 ret = adin1110_read_reg(priv, ADIN1110_MDIOACC, &val); 433 mutex_unlock(&priv->lock); 434 if (ret < 0) 435 return 0; 436 437 return val; 438 } 439 440 static int adin1110_mdio_read(struct mii_bus *bus, int phy_id, int reg) 441 { 442 struct adin1110_priv *priv = bus->priv; 443 u32 val = 0; 444 int ret; 445 446 if (mdio_phy_id_is_c45(phy_id)) 447 return -EOPNOTSUPP; 448 449 val |= FIELD_PREP(ADIN1110_MDIO_OP, ADIN1110_MDIO_OP_RD); 450 val |= FIELD_PREP(ADIN1110_MDIO_ST, 0x1); 451 val |= FIELD_PREP(ADIN1110_MDIO_PRTAD, phy_id); 452 val |= FIELD_PREP(ADIN1110_MDIO_DEVAD, reg); 453 454 /* write the clause 22 read command to the chip */ 455 mutex_lock(&priv->lock); 456 ret = adin1110_write_reg(priv, ADIN1110_MDIOACC, val); 457 mutex_unlock(&priv->lock); 458 if (ret < 0) 459 return ret; 460 461 /* ADIN1110_MDIO_TRDONE BIT of the ADIN1110_MDIOACC 462 * register is set when the read is done. 463 * After the transaction is done, ADIN1110_MDIO_DATA 464 * bitfield of ADIN1110_MDIOACC register will contain 465 * the requested register value. 466 */ 467 ret = readx_poll_timeout(adin1110_read_mdio_acc, priv, val, 468 (val & ADIN1110_MDIO_TRDONE), 10000, 30000); 469 if (ret < 0) 470 return ret; 471 472 return (val & ADIN1110_MDIO_DATA); 473 } 474 475 static int adin1110_mdio_write(struct mii_bus *bus, int phy_id, 476 int reg, u16 reg_val) 477 { 478 struct adin1110_priv *priv = bus->priv; 479 u32 val = 0; 480 int ret; 481 482 if (mdio_phy_id_is_c45(phy_id)) 483 return -EOPNOTSUPP; 484 485 val |= FIELD_PREP(ADIN1110_MDIO_OP, ADIN1110_MDIO_OP_WR); 486 val |= FIELD_PREP(ADIN1110_MDIO_ST, 0x1); 487 val |= FIELD_PREP(ADIN1110_MDIO_PRTAD, phy_id); 488 val |= FIELD_PREP(ADIN1110_MDIO_DEVAD, reg); 489 val |= FIELD_PREP(ADIN1110_MDIO_DATA, reg_val); 490 491 /* write the clause 22 write command to the chip */ 492 mutex_lock(&priv->lock); 493 ret = adin1110_write_reg(priv, ADIN1110_MDIOACC, val); 494 mutex_unlock(&priv->lock); 495 if (ret < 0) 496 return ret; 497 498 return readx_poll_timeout(adin1110_read_mdio_acc, priv, val, 499 (val & ADIN1110_MDIO_TRDONE), 10000, 30000); 500 } 501 502 /* ADIN1110 MAC-PHY contains an ADIN1100 PHY. 503 * ADIN2111 MAC-PHY contains two ADIN1100 PHYs. 504 * By registering a new MDIO bus we allow the PAL to discover 505 * the encapsulated PHY and probe the ADIN1100 driver. 506 */ 507 static int adin1110_register_mdiobus(struct adin1110_priv *priv, 508 struct device *dev) 509 { 510 struct mii_bus *mii_bus; 511 int ret; 512 513 mii_bus = devm_mdiobus_alloc(dev); 514 if (!mii_bus) 515 return -ENOMEM; 516 517 snprintf(priv->mii_bus_name, MII_BUS_ID_SIZE, "%s-%u", 518 priv->cfg->name, priv->spidev->chip_select); 519 520 mii_bus->name = priv->mii_bus_name; 521 mii_bus->read = adin1110_mdio_read; 522 mii_bus->write = adin1110_mdio_write; 523 mii_bus->priv = priv; 524 mii_bus->parent = dev; 525 mii_bus->phy_mask = ~((u32)GENMASK(2, 0)); 526 mii_bus->probe_capabilities = MDIOBUS_C22; 527 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev)); 528 529 ret = devm_mdiobus_register(dev, mii_bus); 530 if (ret) 531 return ret; 532 533 priv->mii_bus = mii_bus; 534 535 return 0; 536 } 537 538 static bool adin1110_port_rx_ready(struct adin1110_port_priv *port_priv, 539 u32 status) 540 { 541 if (!netif_oper_up(port_priv->netdev)) 542 return false; 543 544 if (!port_priv->nr) 545 return !!(status & ADIN1110_RX_RDY); 546 else 547 return !!(status & ADIN2111_P2_RX_RDY); 548 } 549 550 static void adin1110_read_frames(struct adin1110_port_priv *port_priv, 551 unsigned int budget) 552 { 553 struct adin1110_priv *priv = port_priv->priv; 554 u32 status1; 555 int ret; 556 557 while (budget) { 558 ret = adin1110_read_reg(priv, ADIN1110_STATUS1, &status1); 559 if (ret < 0) 560 return; 561 562 if (!adin1110_port_rx_ready(port_priv, status1)) 563 break; 564 565 ret = adin1110_read_fifo(port_priv); 566 if (ret < 0) 567 return; 568 569 budget--; 570 } 571 } 572 573 static void adin1110_wake_queues(struct adin1110_priv *priv) 574 { 575 int i; 576 577 for (i = 0; i < priv->cfg->ports_nr; i++) 578 netif_wake_queue(priv->ports[i]->netdev); 579 } 580 581 static irqreturn_t adin1110_irq(int irq, void *p) 582 { 583 struct adin1110_priv *priv = p; 584 u32 status1; 585 u32 val; 586 int ret; 587 int i; 588 589 mutex_lock(&priv->lock); 590 591 ret = adin1110_read_reg(priv, ADIN1110_STATUS1, &status1); 592 if (ret < 0) 593 goto out; 594 595 if (priv->append_crc && (status1 & ADIN1110_SPI_ERR)) 596 dev_warn_ratelimited(&priv->spidev->dev, 597 "SPI CRC error on write.\n"); 598 599 ret = adin1110_read_reg(priv, ADIN1110_TX_SPACE, &val); 600 if (ret < 0) 601 goto out; 602 603 /* TX FIFO space is expressed in half-words */ 604 priv->tx_space = 2 * val; 605 606 for (i = 0; i < priv->cfg->ports_nr; i++) { 607 if (adin1110_port_rx_ready(priv->ports[i], status1)) 608 adin1110_read_frames(priv->ports[i], 609 ADIN1110_MAX_FRAMES_READ); 610 } 611 612 /* clear IRQ sources */ 613 adin1110_write_reg(priv, ADIN1110_STATUS0, ADIN1110_CLEAR_STATUS0); 614 adin1110_write_reg(priv, ADIN1110_STATUS1, priv->irq_mask); 615 616 out: 617 mutex_unlock(&priv->lock); 618 619 if (priv->tx_space > 0 && ret >= 0) 620 adin1110_wake_queues(priv); 621 622 return IRQ_HANDLED; 623 } 624 625 /* ADIN1110 can filter up to 16 MAC addresses, mac_nr here is the slot used */ 626 static int adin1110_write_mac_address(struct adin1110_port_priv *port_priv, 627 int mac_nr, const u8 *addr, 628 u8 *mask, u32 port_rules) 629 { 630 struct adin1110_priv *priv = port_priv->priv; 631 u32 offset = mac_nr * 2; 632 u32 port_rules_mask; 633 int ret; 634 u32 val; 635 636 if (!port_priv->nr) 637 port_rules_mask = ADIN1110_MAC_ADDR_APPLY2PORT; 638 else 639 port_rules_mask = ADIN2111_MAC_ADDR_APPLY2PORT2; 640 641 if (port_rules & port_rules_mask) 642 port_rules_mask |= ADIN1110_MAC_ADDR_TO_HOST | ADIN2111_MAC_ADDR_TO_OTHER_PORT; 643 644 port_rules_mask |= GENMASK(15, 0); 645 val = port_rules | get_unaligned_be16(&addr[0]); 646 ret = adin1110_set_bits(priv, ADIN1110_MAC_ADDR_FILTER_UPR + offset, 647 port_rules_mask, val); 648 if (ret < 0) 649 return ret; 650 651 val = get_unaligned_be32(&addr[2]); 652 ret = adin1110_write_reg(priv, 653 ADIN1110_MAC_ADDR_FILTER_LWR + offset, val); 654 if (ret < 0) 655 return ret; 656 657 /* Only the first two MAC address slots support masking. */ 658 if (mac_nr < ADIN_MAC_P1_ADDR_SLOT) { 659 val = get_unaligned_be16(&mask[0]); 660 ret = adin1110_write_reg(priv, 661 ADIN1110_MAC_ADDR_MASK_UPR + offset, 662 val); 663 if (ret < 0) 664 return ret; 665 666 val = get_unaligned_be32(&mask[2]); 667 return adin1110_write_reg(priv, 668 ADIN1110_MAC_ADDR_MASK_LWR + offset, 669 val); 670 } 671 672 return 0; 673 } 674 675 static int adin1110_clear_mac_address(struct adin1110_priv *priv, int mac_nr) 676 { 677 u32 offset = mac_nr * 2; 678 int ret; 679 680 ret = adin1110_write_reg(priv, ADIN1110_MAC_ADDR_FILTER_UPR + offset, 0); 681 if (ret < 0) 682 return ret; 683 684 ret = adin1110_write_reg(priv, ADIN1110_MAC_ADDR_FILTER_LWR + offset, 0); 685 if (ret < 0) 686 return ret; 687 688 /* only the first two MAC address slots are maskable */ 689 if (mac_nr <= 1) { 690 ret = adin1110_write_reg(priv, ADIN1110_MAC_ADDR_MASK_UPR + offset, 0); 691 if (ret < 0) 692 return ret; 693 694 ret = adin1110_write_reg(priv, ADIN1110_MAC_ADDR_MASK_LWR + offset, 0); 695 } 696 697 return ret; 698 } 699 700 static u32 adin1110_port_rules(struct adin1110_port_priv *port_priv, 701 bool fw_to_host, 702 bool fw_to_other_port) 703 { 704 u32 port_rules = 0; 705 706 if (!port_priv->nr) 707 port_rules |= ADIN1110_MAC_ADDR_APPLY2PORT; 708 else 709 port_rules |= ADIN2111_MAC_ADDR_APPLY2PORT2; 710 711 if (fw_to_host) 712 port_rules |= ADIN1110_MAC_ADDR_TO_HOST; 713 714 if (fw_to_other_port && port_priv->priv->forwarding) 715 port_rules |= ADIN2111_MAC_ADDR_TO_OTHER_PORT; 716 717 return port_rules; 718 } 719 720 static int adin1110_multicast_filter(struct adin1110_port_priv *port_priv, 721 int mac_nr, bool accept_multicast) 722 { 723 u8 mask[ETH_ALEN] = {0}; 724 u8 mac[ETH_ALEN] = {0}; 725 u32 port_rules = 0; 726 727 mask[0] = BIT(0); 728 mac[0] = BIT(0); 729 730 if (accept_multicast && port_priv->state == BR_STATE_FORWARDING) 731 port_rules = adin1110_port_rules(port_priv, true, true); 732 733 return adin1110_write_mac_address(port_priv, mac_nr, mac, 734 mask, port_rules); 735 } 736 737 static int adin1110_broadcasts_filter(struct adin1110_port_priv *port_priv, 738 int mac_nr, bool accept_broadcast) 739 { 740 u32 port_rules = 0; 741 u8 mask[ETH_ALEN]; 742 743 memset(mask, 0xFF, ETH_ALEN); 744 745 if (accept_broadcast && port_priv->state == BR_STATE_FORWARDING) 746 port_rules = adin1110_port_rules(port_priv, true, true); 747 748 return adin1110_write_mac_address(port_priv, mac_nr, mask, 749 mask, port_rules); 750 } 751 752 static int adin1110_set_mac_address(struct net_device *netdev, 753 const unsigned char *dev_addr) 754 { 755 struct adin1110_port_priv *port_priv = netdev_priv(netdev); 756 u8 mask[ETH_ALEN]; 757 u32 port_rules; 758 u32 mac_slot; 759 760 if (!is_valid_ether_addr(dev_addr)) 761 return -EADDRNOTAVAIL; 762 763 eth_hw_addr_set(netdev, dev_addr); 764 memset(mask, 0xFF, ETH_ALEN); 765 766 mac_slot = (!port_priv->nr) ? ADIN_MAC_P1_ADDR_SLOT : ADIN_MAC_P2_ADDR_SLOT; 767 port_rules = adin1110_port_rules(port_priv, true, false); 768 769 return adin1110_write_mac_address(port_priv, mac_slot, netdev->dev_addr, 770 mask, port_rules); 771 } 772 773 static int adin1110_ndo_set_mac_address(struct net_device *netdev, void *addr) 774 { 775 struct sockaddr *sa = addr; 776 int ret; 777 778 ret = eth_prepare_mac_addr_change(netdev, addr); 779 if (ret < 0) 780 return ret; 781 782 return adin1110_set_mac_address(netdev, sa->sa_data); 783 } 784 785 static int adin1110_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 786 { 787 if (!netif_running(netdev)) 788 return -EINVAL; 789 790 return phy_do_ioctl(netdev, rq, cmd); 791 } 792 793 static int adin1110_set_promisc_mode(struct adin1110_port_priv *port_priv, 794 bool promisc) 795 { 796 struct adin1110_priv *priv = port_priv->priv; 797 u32 mask; 798 799 if (port_priv->state != BR_STATE_FORWARDING) 800 promisc = false; 801 802 if (!port_priv->nr) 803 mask = ADIN1110_FWD_UNK2HOST; 804 else 805 mask = ADIN2111_P2_FWD_UNK2HOST; 806 807 return adin1110_set_bits(priv, ADIN1110_CONFIG2, 808 mask, promisc ? mask : 0); 809 } 810 811 static int adin1110_setup_rx_mode(struct adin1110_port_priv *port_priv) 812 { 813 int ret; 814 815 ret = adin1110_set_promisc_mode(port_priv, 816 !!(port_priv->flags & IFF_PROMISC)); 817 if (ret < 0) 818 return ret; 819 820 ret = adin1110_multicast_filter(port_priv, ADIN_MAC_MULTICAST_ADDR_SLOT, 821 !!(port_priv->flags & IFF_ALLMULTI)); 822 if (ret < 0) 823 return ret; 824 825 ret = adin1110_broadcasts_filter(port_priv, 826 ADIN_MAC_BROADCAST_ADDR_SLOT, 827 !!(port_priv->flags & IFF_BROADCAST)); 828 if (ret < 0) 829 return ret; 830 831 return adin1110_set_bits(port_priv->priv, ADIN1110_CONFIG1, 832 ADIN1110_CONFIG1_SYNC, ADIN1110_CONFIG1_SYNC); 833 } 834 835 static bool adin1110_can_offload_forwarding(struct adin1110_priv *priv) 836 { 837 int i; 838 839 if (priv->cfg->id != ADIN2111_MAC) 840 return false; 841 842 /* Can't enable forwarding if ports do not belong to the same bridge */ 843 if (priv->ports[0]->bridge != priv->ports[1]->bridge || !priv->ports[0]->bridge) 844 return false; 845 846 /* Can't enable forwarding if there is a port 847 * that has been blocked by STP. 848 */ 849 for (i = 0; i < priv->cfg->ports_nr; i++) { 850 if (priv->ports[i]->state != BR_STATE_FORWARDING) 851 return false; 852 } 853 854 return true; 855 } 856 857 static void adin1110_rx_mode_work(struct work_struct *work) 858 { 859 struct adin1110_port_priv *port_priv; 860 struct adin1110_priv *priv; 861 862 port_priv = container_of(work, struct adin1110_port_priv, rx_mode_work); 863 priv = port_priv->priv; 864 865 mutex_lock(&priv->lock); 866 adin1110_setup_rx_mode(port_priv); 867 mutex_unlock(&priv->lock); 868 } 869 870 static void adin1110_set_rx_mode(struct net_device *dev) 871 { 872 struct adin1110_port_priv *port_priv = netdev_priv(dev); 873 struct adin1110_priv *priv = port_priv->priv; 874 875 spin_lock(&priv->state_lock); 876 877 port_priv->flags = dev->flags; 878 schedule_work(&port_priv->rx_mode_work); 879 880 spin_unlock(&priv->state_lock); 881 } 882 883 static int adin1110_net_open(struct net_device *net_dev) 884 { 885 struct adin1110_port_priv *port_priv = netdev_priv(net_dev); 886 struct adin1110_priv *priv = port_priv->priv; 887 u32 val; 888 int ret; 889 890 mutex_lock(&priv->lock); 891 892 /* Configure MAC to compute and append the FCS itself. */ 893 ret = adin1110_write_reg(priv, ADIN1110_CONFIG2, ADIN1110_CRC_APPEND); 894 if (ret < 0) 895 goto out; 896 897 val = ADIN1110_TX_RDY_IRQ | ADIN1110_RX_RDY_IRQ | ADIN1110_SPI_ERR_IRQ; 898 if (priv->cfg->id == ADIN2111_MAC) 899 val |= ADIN2111_RX_RDY_IRQ; 900 901 priv->irq_mask = val; 902 ret = adin1110_write_reg(priv, ADIN1110_IMASK1, ~val); 903 if (ret < 0) { 904 netdev_err(net_dev, "Failed to enable chip IRQs: %d\n", ret); 905 goto out; 906 } 907 908 ret = adin1110_read_reg(priv, ADIN1110_TX_SPACE, &val); 909 if (ret < 0) { 910 netdev_err(net_dev, "Failed to read TX FIFO space: %d\n", ret); 911 goto out; 912 } 913 914 priv->tx_space = 2 * val; 915 916 port_priv->state = BR_STATE_FORWARDING; 917 ret = adin1110_set_mac_address(net_dev, net_dev->dev_addr); 918 if (ret < 0) { 919 netdev_err(net_dev, "Could not set MAC address: %pM, %d\n", 920 net_dev->dev_addr, ret); 921 goto out; 922 } 923 924 ret = adin1110_set_bits(priv, ADIN1110_CONFIG1, ADIN1110_CONFIG1_SYNC, 925 ADIN1110_CONFIG1_SYNC); 926 927 out: 928 mutex_unlock(&priv->lock); 929 930 if (ret < 0) 931 return ret; 932 933 phy_start(port_priv->phydev); 934 935 netif_start_queue(net_dev); 936 937 return 0; 938 } 939 940 static int adin1110_net_stop(struct net_device *net_dev) 941 { 942 struct adin1110_port_priv *port_priv = netdev_priv(net_dev); 943 struct adin1110_priv *priv = port_priv->priv; 944 u32 mask; 945 int ret; 946 947 mask = !port_priv->nr ? ADIN2111_RX_RDY_IRQ : ADIN1110_RX_RDY_IRQ; 948 949 /* Disable RX RDY IRQs */ 950 mutex_lock(&priv->lock); 951 ret = adin1110_set_bits(priv, ADIN1110_IMASK1, mask, mask); 952 mutex_unlock(&priv->lock); 953 if (ret < 0) 954 return ret; 955 956 netif_stop_queue(port_priv->netdev); 957 flush_work(&port_priv->tx_work); 958 phy_stop(port_priv->phydev); 959 960 return 0; 961 } 962 963 static void adin1110_tx_work(struct work_struct *work) 964 { 965 struct adin1110_port_priv *port_priv; 966 struct adin1110_priv *priv; 967 struct sk_buff *txb; 968 int ret; 969 970 port_priv = container_of(work, struct adin1110_port_priv, tx_work); 971 priv = port_priv->priv; 972 973 mutex_lock(&priv->lock); 974 975 while ((txb = skb_dequeue(&port_priv->txq))) { 976 ret = adin1110_write_fifo(port_priv, txb); 977 if (ret < 0) 978 dev_err_ratelimited(&priv->spidev->dev, 979 "Frame write error: %d\n", ret); 980 981 dev_kfree_skb(txb); 982 } 983 984 mutex_unlock(&priv->lock); 985 } 986 987 static netdev_tx_t adin1110_start_xmit(struct sk_buff *skb, struct net_device *dev) 988 { 989 struct adin1110_port_priv *port_priv = netdev_priv(dev); 990 struct adin1110_priv *priv = port_priv->priv; 991 netdev_tx_t netdev_ret = NETDEV_TX_OK; 992 u32 tx_space_needed; 993 994 tx_space_needed = skb->len + ADIN1110_FRAME_HEADER_LEN + ADIN1110_INTERNAL_SIZE_HEADER_LEN; 995 if (tx_space_needed > priv->tx_space) { 996 netif_stop_queue(dev); 997 netdev_ret = NETDEV_TX_BUSY; 998 } else { 999 priv->tx_space -= tx_space_needed; 1000 skb_queue_tail(&port_priv->txq, skb); 1001 } 1002 1003 schedule_work(&port_priv->tx_work); 1004 1005 return netdev_ret; 1006 } 1007 1008 static void adin1110_ndo_get_stats64(struct net_device *dev, 1009 struct rtnl_link_stats64 *storage) 1010 { 1011 struct adin1110_port_priv *port_priv = netdev_priv(dev); 1012 1013 storage->rx_packets = port_priv->rx_packets; 1014 storage->tx_packets = port_priv->tx_packets; 1015 1016 storage->rx_bytes = port_priv->rx_bytes; 1017 storage->tx_bytes = port_priv->tx_bytes; 1018 } 1019 1020 static int adin1110_port_get_port_parent_id(struct net_device *dev, 1021 struct netdev_phys_item_id *ppid) 1022 { 1023 struct adin1110_port_priv *port_priv = netdev_priv(dev); 1024 struct adin1110_priv *priv = port_priv->priv; 1025 1026 ppid->id_len = strnlen(priv->mii_bus_name, MAX_PHYS_ITEM_ID_LEN); 1027 memcpy(ppid->id, priv->mii_bus_name, ppid->id_len); 1028 1029 return 0; 1030 } 1031 1032 static int adin1110_ndo_get_phys_port_name(struct net_device *dev, 1033 char *name, size_t len) 1034 { 1035 struct adin1110_port_priv *port_priv = netdev_priv(dev); 1036 int err; 1037 1038 err = snprintf(name, len, "p%d", port_priv->nr); 1039 if (err >= len) 1040 return -EINVAL; 1041 1042 return 0; 1043 } 1044 1045 static const struct net_device_ops adin1110_netdev_ops = { 1046 .ndo_open = adin1110_net_open, 1047 .ndo_stop = adin1110_net_stop, 1048 .ndo_eth_ioctl = adin1110_ioctl, 1049 .ndo_start_xmit = adin1110_start_xmit, 1050 .ndo_set_mac_address = adin1110_ndo_set_mac_address, 1051 .ndo_set_rx_mode = adin1110_set_rx_mode, 1052 .ndo_validate_addr = eth_validate_addr, 1053 .ndo_get_stats64 = adin1110_ndo_get_stats64, 1054 .ndo_get_port_parent_id = adin1110_port_get_port_parent_id, 1055 .ndo_get_phys_port_name = adin1110_ndo_get_phys_port_name, 1056 }; 1057 1058 static void adin1110_get_drvinfo(struct net_device *dev, 1059 struct ethtool_drvinfo *di) 1060 { 1061 strscpy(di->driver, "ADIN1110", sizeof(di->driver)); 1062 strscpy(di->bus_info, dev_name(dev->dev.parent), sizeof(di->bus_info)); 1063 } 1064 1065 static const struct ethtool_ops adin1110_ethtool_ops = { 1066 .get_drvinfo = adin1110_get_drvinfo, 1067 .get_link = ethtool_op_get_link, 1068 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1069 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1070 }; 1071 1072 static void adin1110_adjust_link(struct net_device *dev) 1073 { 1074 struct phy_device *phydev = dev->phydev; 1075 1076 if (!phydev->link) 1077 phy_print_status(phydev); 1078 } 1079 1080 /* PHY ID is stored in the MAC registers too, 1081 * check spi connection by reading it. 1082 */ 1083 static int adin1110_check_spi(struct adin1110_priv *priv) 1084 { 1085 struct gpio_desc *reset_gpio; 1086 int ret; 1087 u32 val; 1088 1089 reset_gpio = devm_gpiod_get_optional(&priv->spidev->dev, "reset", 1090 GPIOD_OUT_LOW); 1091 if (reset_gpio) { 1092 /* MISO pin is used for internal configuration, can't have 1093 * anyone else disturbing the SDO line. 1094 */ 1095 spi_bus_lock(priv->spidev->controller); 1096 1097 gpiod_set_value(reset_gpio, 1); 1098 fsleep(10000); 1099 gpiod_set_value(reset_gpio, 0); 1100 1101 /* Need to wait 90 ms before interacting with 1102 * the MAC after a HW reset. 1103 */ 1104 fsleep(90000); 1105 1106 spi_bus_unlock(priv->spidev->controller); 1107 } 1108 1109 ret = adin1110_read_reg(priv, ADIN1110_PHY_ID, &val); 1110 if (ret < 0) 1111 return ret; 1112 1113 if (val != priv->cfg->phy_id_val) { 1114 dev_err(&priv->spidev->dev, "PHY ID expected: %x, read: %x\n", 1115 priv->cfg->phy_id_val, val); 1116 return -EIO; 1117 } 1118 1119 return 0; 1120 } 1121 1122 static int adin1110_hw_forwarding(struct adin1110_priv *priv, bool enable) 1123 { 1124 int ret; 1125 int i; 1126 1127 priv->forwarding = enable; 1128 1129 if (!priv->forwarding) { 1130 for (i = ADIN_MAC_FDB_ADDR_SLOT; i < ADIN_MAC_MAX_ADDR_SLOTS; i++) { 1131 ret = adin1110_clear_mac_address(priv, i); 1132 if (ret < 0) 1133 return ret; 1134 } 1135 } 1136 1137 /* Forwarding is optimised when MAC runs in Cut Through mode. */ 1138 ret = adin1110_set_bits(priv, ADIN1110_CONFIG2, 1139 ADIN2111_PORT_CUT_THRU_EN, 1140 priv->forwarding ? ADIN2111_PORT_CUT_THRU_EN : 0); 1141 if (ret < 0) 1142 return ret; 1143 1144 for (i = 0; i < priv->cfg->ports_nr; i++) { 1145 ret = adin1110_setup_rx_mode(priv->ports[i]); 1146 if (ret < 0) 1147 return ret; 1148 } 1149 1150 return ret; 1151 } 1152 1153 static int adin1110_port_bridge_join(struct adin1110_port_priv *port_priv, 1154 struct net_device *bridge) 1155 { 1156 struct adin1110_priv *priv = port_priv->priv; 1157 int ret; 1158 1159 port_priv->bridge = bridge; 1160 1161 if (adin1110_can_offload_forwarding(priv)) { 1162 mutex_lock(&priv->lock); 1163 ret = adin1110_hw_forwarding(priv, true); 1164 mutex_unlock(&priv->lock); 1165 1166 if (ret < 0) 1167 return ret; 1168 } 1169 1170 return adin1110_set_mac_address(port_priv->netdev, bridge->dev_addr); 1171 } 1172 1173 static int adin1110_port_bridge_leave(struct adin1110_port_priv *port_priv, 1174 struct net_device *bridge) 1175 { 1176 struct adin1110_priv *priv = port_priv->priv; 1177 int ret; 1178 1179 port_priv->bridge = NULL; 1180 1181 mutex_lock(&priv->lock); 1182 ret = adin1110_hw_forwarding(priv, false); 1183 mutex_unlock(&priv->lock); 1184 1185 return ret; 1186 } 1187 1188 static bool adin1110_port_dev_check(const struct net_device *dev) 1189 { 1190 return dev->netdev_ops == &adin1110_netdev_ops; 1191 } 1192 1193 static int adin1110_netdevice_event(struct notifier_block *unused, 1194 unsigned long event, void *ptr) 1195 { 1196 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 1197 struct adin1110_port_priv *port_priv = netdev_priv(dev); 1198 struct netdev_notifier_changeupper_info *info = ptr; 1199 int ret = 0; 1200 1201 if (!adin1110_port_dev_check(dev)) 1202 return NOTIFY_DONE; 1203 1204 switch (event) { 1205 case NETDEV_CHANGEUPPER: 1206 if (netif_is_bridge_master(info->upper_dev)) { 1207 if (info->linking) 1208 ret = adin1110_port_bridge_join(port_priv, info->upper_dev); 1209 else 1210 ret = adin1110_port_bridge_leave(port_priv, info->upper_dev); 1211 } 1212 break; 1213 default: 1214 break; 1215 } 1216 1217 return notifier_from_errno(ret); 1218 } 1219 1220 static struct notifier_block adin1110_netdevice_nb = { 1221 .notifier_call = adin1110_netdevice_event, 1222 }; 1223 1224 static void adin1110_disconnect_phy(void *data) 1225 { 1226 phy_disconnect(data); 1227 } 1228 1229 static int adin1110_port_set_forwarding_state(struct adin1110_port_priv *port_priv) 1230 { 1231 struct adin1110_priv *priv = port_priv->priv; 1232 int ret; 1233 1234 port_priv->state = BR_STATE_FORWARDING; 1235 1236 mutex_lock(&priv->lock); 1237 ret = adin1110_set_mac_address(port_priv->netdev, 1238 port_priv->netdev->dev_addr); 1239 if (ret < 0) 1240 goto out; 1241 1242 if (adin1110_can_offload_forwarding(priv)) 1243 ret = adin1110_hw_forwarding(priv, true); 1244 else 1245 ret = adin1110_setup_rx_mode(port_priv); 1246 out: 1247 mutex_unlock(&priv->lock); 1248 1249 return ret; 1250 } 1251 1252 static int adin1110_port_set_blocking_state(struct adin1110_port_priv *port_priv) 1253 { 1254 u8 mac[ETH_ALEN] = {0x01, 0x80, 0xC2, 0x00, 0x00, 0x00}; 1255 struct adin1110_priv *priv = port_priv->priv; 1256 u8 mask[ETH_ALEN]; 1257 u32 port_rules; 1258 int mac_slot; 1259 int ret; 1260 1261 port_priv->state = BR_STATE_BLOCKING; 1262 1263 mutex_lock(&priv->lock); 1264 1265 mac_slot = (!port_priv->nr) ? ADIN_MAC_P1_ADDR_SLOT : ADIN_MAC_P2_ADDR_SLOT; 1266 ret = adin1110_clear_mac_address(priv, mac_slot); 1267 if (ret < 0) 1268 goto out; 1269 1270 ret = adin1110_hw_forwarding(priv, false); 1271 if (ret < 0) 1272 goto out; 1273 1274 /* Allow only BPDUs to be passed to the CPU */ 1275 memset(mask, 0xFF, ETH_ALEN); 1276 port_rules = adin1110_port_rules(port_priv, true, false); 1277 ret = adin1110_write_mac_address(port_priv, mac_slot, mac, 1278 mask, port_rules); 1279 out: 1280 mutex_unlock(&priv->lock); 1281 1282 return ret; 1283 } 1284 1285 /* ADIN1110/2111 does not have any native STP support. 1286 * Listen for bridge core state changes and 1287 * allow all frames to pass or only the BPDUs. 1288 */ 1289 static int adin1110_port_attr_stp_state_set(struct adin1110_port_priv *port_priv, 1290 u8 state) 1291 { 1292 switch (state) { 1293 case BR_STATE_FORWARDING: 1294 return adin1110_port_set_forwarding_state(port_priv); 1295 case BR_STATE_LEARNING: 1296 case BR_STATE_LISTENING: 1297 case BR_STATE_DISABLED: 1298 case BR_STATE_BLOCKING: 1299 return adin1110_port_set_blocking_state(port_priv); 1300 default: 1301 return -EINVAL; 1302 } 1303 } 1304 1305 static int adin1110_port_attr_set(struct net_device *dev, const void *ctx, 1306 const struct switchdev_attr *attr, 1307 struct netlink_ext_ack *extack) 1308 { 1309 struct adin1110_port_priv *port_priv = netdev_priv(dev); 1310 1311 switch (attr->id) { 1312 case SWITCHDEV_ATTR_ID_PORT_STP_STATE: 1313 return adin1110_port_attr_stp_state_set(port_priv, 1314 attr->u.stp_state); 1315 default: 1316 return -EOPNOTSUPP; 1317 } 1318 } 1319 1320 static int adin1110_switchdev_blocking_event(struct notifier_block *unused, 1321 unsigned long event, 1322 void *ptr) 1323 { 1324 struct net_device *netdev = switchdev_notifier_info_to_dev(ptr); 1325 int ret; 1326 1327 if (event == SWITCHDEV_PORT_ATTR_SET) { 1328 ret = switchdev_handle_port_attr_set(netdev, ptr, 1329 adin1110_port_dev_check, 1330 adin1110_port_attr_set); 1331 1332 return notifier_from_errno(ret); 1333 } 1334 1335 return NOTIFY_DONE; 1336 } 1337 1338 static struct notifier_block adin1110_switchdev_blocking_notifier = { 1339 .notifier_call = adin1110_switchdev_blocking_event, 1340 }; 1341 1342 static void adin1110_fdb_offload_notify(struct net_device *netdev, 1343 struct switchdev_notifier_fdb_info *rcv) 1344 { 1345 struct switchdev_notifier_fdb_info info = {}; 1346 1347 info.addr = rcv->addr; 1348 info.vid = rcv->vid; 1349 info.offloaded = true; 1350 call_switchdev_notifiers(SWITCHDEV_FDB_OFFLOADED, 1351 netdev, &info.info, NULL); 1352 } 1353 1354 static int adin1110_fdb_add(struct adin1110_port_priv *port_priv, 1355 struct switchdev_notifier_fdb_info *fdb) 1356 { 1357 struct adin1110_priv *priv = port_priv->priv; 1358 struct adin1110_port_priv *other_port; 1359 u8 mask[ETH_ALEN]; 1360 u32 port_rules; 1361 int mac_nr; 1362 u32 val; 1363 int ret; 1364 1365 netdev_dbg(port_priv->netdev, 1366 "DEBUG: %s: MACID = %pM vid = %u flags = %u %u -- port %d\n", 1367 __func__, fdb->addr, fdb->vid, fdb->added_by_user, 1368 fdb->offloaded, port_priv->nr); 1369 1370 if (!priv->forwarding) 1371 return 0; 1372 1373 if (fdb->is_local) 1374 return -EINVAL; 1375 1376 /* Find free FDB slot on device. */ 1377 for (mac_nr = ADIN_MAC_FDB_ADDR_SLOT; mac_nr < ADIN_MAC_MAX_ADDR_SLOTS; mac_nr++) { 1378 ret = adin1110_read_reg(priv, ADIN1110_MAC_ADDR_FILTER_UPR + (mac_nr * 2), &val); 1379 if (ret < 0) 1380 return ret; 1381 if (!val) 1382 break; 1383 } 1384 1385 if (mac_nr == ADIN_MAC_MAX_ADDR_SLOTS) 1386 return -ENOMEM; 1387 1388 other_port = priv->ports[!port_priv->nr]; 1389 port_rules = adin1110_port_rules(port_priv, false, true); 1390 memset(mask, 0xFF, ETH_ALEN); 1391 1392 return adin1110_write_mac_address(other_port, mac_nr, (u8 *)fdb->addr, 1393 mask, port_rules); 1394 } 1395 1396 static int adin1110_read_mac(struct adin1110_priv *priv, int mac_nr, u8 *addr) 1397 { 1398 u32 val; 1399 int ret; 1400 1401 ret = adin1110_read_reg(priv, ADIN1110_MAC_ADDR_FILTER_UPR + (mac_nr * 2), &val); 1402 if (ret < 0) 1403 return ret; 1404 1405 put_unaligned_be16(val, addr); 1406 1407 ret = adin1110_read_reg(priv, ADIN1110_MAC_ADDR_FILTER_LWR + (mac_nr * 2), &val); 1408 if (ret < 0) 1409 return ret; 1410 1411 put_unaligned_be32(val, addr + 2); 1412 1413 return 0; 1414 } 1415 1416 static int adin1110_fdb_del(struct adin1110_port_priv *port_priv, 1417 struct switchdev_notifier_fdb_info *fdb) 1418 { 1419 struct adin1110_priv *priv = port_priv->priv; 1420 u8 addr[ETH_ALEN]; 1421 int mac_nr; 1422 int ret; 1423 1424 netdev_dbg(port_priv->netdev, 1425 "DEBUG: %s: MACID = %pM vid = %u flags = %u %u -- port %d\n", 1426 __func__, fdb->addr, fdb->vid, fdb->added_by_user, 1427 fdb->offloaded, port_priv->nr); 1428 1429 if (fdb->is_local) 1430 return -EINVAL; 1431 1432 for (mac_nr = ADIN_MAC_FDB_ADDR_SLOT; mac_nr < ADIN_MAC_MAX_ADDR_SLOTS; mac_nr++) { 1433 ret = adin1110_read_mac(priv, mac_nr, addr); 1434 if (ret < 0) 1435 return ret; 1436 1437 if (ether_addr_equal(addr, fdb->addr)) { 1438 ret = adin1110_clear_mac_address(priv, mac_nr); 1439 if (ret < 0) 1440 return ret; 1441 } 1442 } 1443 1444 return 0; 1445 } 1446 1447 static void adin1110_switchdev_event_work(struct work_struct *work) 1448 { 1449 struct adin1110_switchdev_event_work *switchdev_work; 1450 struct adin1110_port_priv *port_priv; 1451 int ret; 1452 1453 switchdev_work = container_of(work, struct adin1110_switchdev_event_work, work); 1454 port_priv = switchdev_work->port_priv; 1455 1456 mutex_lock(&port_priv->priv->lock); 1457 1458 switch (switchdev_work->event) { 1459 case SWITCHDEV_FDB_ADD_TO_DEVICE: 1460 ret = adin1110_fdb_add(port_priv, &switchdev_work->fdb_info); 1461 if (!ret) 1462 adin1110_fdb_offload_notify(port_priv->netdev, 1463 &switchdev_work->fdb_info); 1464 break; 1465 case SWITCHDEV_FDB_DEL_TO_DEVICE: 1466 adin1110_fdb_del(port_priv, &switchdev_work->fdb_info); 1467 break; 1468 default: 1469 break; 1470 } 1471 1472 mutex_unlock(&port_priv->priv->lock); 1473 1474 kfree(switchdev_work->fdb_info.addr); 1475 kfree(switchdev_work); 1476 dev_put(port_priv->netdev); 1477 } 1478 1479 /* called under rcu_read_lock() */ 1480 static int adin1110_switchdev_event(struct notifier_block *unused, 1481 unsigned long event, void *ptr) 1482 { 1483 struct net_device *netdev = switchdev_notifier_info_to_dev(ptr); 1484 struct adin1110_port_priv *port_priv = netdev_priv(netdev); 1485 struct adin1110_switchdev_event_work *switchdev_work; 1486 struct switchdev_notifier_fdb_info *fdb_info = ptr; 1487 1488 if (!adin1110_port_dev_check(netdev)) 1489 return NOTIFY_DONE; 1490 1491 switchdev_work = kzalloc(sizeof(*switchdev_work), GFP_ATOMIC); 1492 if (WARN_ON(!switchdev_work)) 1493 return NOTIFY_BAD; 1494 1495 INIT_WORK(&switchdev_work->work, adin1110_switchdev_event_work); 1496 switchdev_work->port_priv = port_priv; 1497 switchdev_work->event = event; 1498 1499 switch (event) { 1500 case SWITCHDEV_FDB_ADD_TO_DEVICE: 1501 case SWITCHDEV_FDB_DEL_TO_DEVICE: 1502 memcpy(&switchdev_work->fdb_info, ptr, 1503 sizeof(switchdev_work->fdb_info)); 1504 switchdev_work->fdb_info.addr = kzalloc(ETH_ALEN, GFP_ATOMIC); 1505 1506 if (!switchdev_work->fdb_info.addr) 1507 goto err_addr_alloc; 1508 1509 ether_addr_copy((u8 *)switchdev_work->fdb_info.addr, 1510 fdb_info->addr); 1511 dev_hold(netdev); 1512 break; 1513 default: 1514 kfree(switchdev_work); 1515 return NOTIFY_DONE; 1516 } 1517 1518 queue_work(system_long_wq, &switchdev_work->work); 1519 1520 return NOTIFY_DONE; 1521 1522 err_addr_alloc: 1523 kfree(switchdev_work); 1524 return NOTIFY_BAD; 1525 } 1526 1527 static struct notifier_block adin1110_switchdev_notifier = { 1528 .notifier_call = adin1110_switchdev_event, 1529 }; 1530 1531 static void adin1110_unregister_notifiers(void) 1532 { 1533 unregister_switchdev_blocking_notifier(&adin1110_switchdev_blocking_notifier); 1534 unregister_switchdev_notifier(&adin1110_switchdev_notifier); 1535 unregister_netdevice_notifier(&adin1110_netdevice_nb); 1536 } 1537 1538 static int adin1110_setup_notifiers(void) 1539 { 1540 int ret; 1541 1542 ret = register_netdevice_notifier(&adin1110_netdevice_nb); 1543 if (ret < 0) 1544 return ret; 1545 1546 ret = register_switchdev_notifier(&adin1110_switchdev_notifier); 1547 if (ret < 0) 1548 goto err_netdev; 1549 1550 ret = register_switchdev_blocking_notifier(&adin1110_switchdev_blocking_notifier); 1551 if (ret < 0) 1552 goto err_sdev; 1553 1554 return 0; 1555 1556 err_sdev: 1557 unregister_switchdev_notifier(&adin1110_switchdev_notifier); 1558 1559 err_netdev: 1560 unregister_netdevice_notifier(&adin1110_netdevice_nb); 1561 1562 return ret; 1563 } 1564 1565 static int adin1110_probe_netdevs(struct adin1110_priv *priv) 1566 { 1567 struct device *dev = &priv->spidev->dev; 1568 struct adin1110_port_priv *port_priv; 1569 struct net_device *netdev; 1570 int ret; 1571 int i; 1572 1573 for (i = 0; i < priv->cfg->ports_nr; i++) { 1574 netdev = devm_alloc_etherdev(dev, sizeof(*port_priv)); 1575 if (!netdev) 1576 return -ENOMEM; 1577 1578 port_priv = netdev_priv(netdev); 1579 port_priv->netdev = netdev; 1580 port_priv->priv = priv; 1581 port_priv->cfg = priv->cfg; 1582 port_priv->nr = i; 1583 priv->ports[i] = port_priv; 1584 SET_NETDEV_DEV(netdev, dev); 1585 1586 ret = device_get_ethdev_address(dev, netdev); 1587 if (ret < 0) 1588 return ret; 1589 1590 netdev->irq = priv->spidev->irq; 1591 INIT_WORK(&port_priv->tx_work, adin1110_tx_work); 1592 INIT_WORK(&port_priv->rx_mode_work, adin1110_rx_mode_work); 1593 skb_queue_head_init(&port_priv->txq); 1594 1595 netif_carrier_off(netdev); 1596 1597 netdev->if_port = IF_PORT_10BASET; 1598 netdev->netdev_ops = &adin1110_netdev_ops; 1599 netdev->ethtool_ops = &adin1110_ethtool_ops; 1600 netdev->priv_flags |= IFF_UNICAST_FLT; 1601 netdev->features |= NETIF_F_NETNS_LOCAL; 1602 1603 port_priv->phydev = get_phy_device(priv->mii_bus, i + 1, false); 1604 if (IS_ERR(port_priv->phydev)) { 1605 netdev_err(netdev, "Could not find PHY with device address: %d.\n", i); 1606 return PTR_ERR(port_priv->phydev); 1607 } 1608 1609 port_priv->phydev = phy_connect(netdev, 1610 phydev_name(port_priv->phydev), 1611 adin1110_adjust_link, 1612 PHY_INTERFACE_MODE_INTERNAL); 1613 if (IS_ERR(port_priv->phydev)) { 1614 netdev_err(netdev, "Could not connect PHY with device address: %d.\n", i); 1615 return PTR_ERR(port_priv->phydev); 1616 } 1617 1618 ret = devm_add_action_or_reset(dev, adin1110_disconnect_phy, 1619 port_priv->phydev); 1620 if (ret < 0) 1621 return ret; 1622 } 1623 1624 /* ADIN1110 INT_N pin will be used to signal the host */ 1625 ret = devm_request_threaded_irq(dev, priv->spidev->irq, NULL, 1626 adin1110_irq, 1627 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1628 dev_name(dev), priv); 1629 if (ret < 0) 1630 return ret; 1631 1632 for (i = 0; i < priv->cfg->ports_nr; i++) { 1633 ret = devm_register_netdev(dev, priv->ports[i]->netdev); 1634 if (ret < 0) { 1635 dev_err(dev, "Failed to register network device.\n"); 1636 return ret; 1637 } 1638 } 1639 1640 return 0; 1641 } 1642 1643 static int adin1110_probe(struct spi_device *spi) 1644 { 1645 const struct spi_device_id *dev_id = spi_get_device_id(spi); 1646 struct device *dev = &spi->dev; 1647 struct adin1110_priv *priv; 1648 int ret; 1649 1650 priv = devm_kzalloc(dev, sizeof(struct adin1110_priv), GFP_KERNEL); 1651 if (!priv) 1652 return -ENOMEM; 1653 1654 priv->spidev = spi; 1655 priv->cfg = &adin1110_cfgs[dev_id->driver_data]; 1656 spi->bits_per_word = 8; 1657 spi->mode = SPI_MODE_0; 1658 1659 mutex_init(&priv->lock); 1660 spin_lock_init(&priv->state_lock); 1661 1662 /* use of CRC on control and data transactions is pin dependent */ 1663 priv->append_crc = device_property_read_bool(dev, "adi,spi-crc"); 1664 if (priv->append_crc) 1665 crc8_populate_msb(adin1110_crc_table, 0x7); 1666 1667 ret = adin1110_check_spi(priv); 1668 if (ret < 0) { 1669 dev_err(dev, "Probe SPI Read check failed: %d\n", ret); 1670 return ret; 1671 } 1672 1673 ret = adin1110_write_reg(priv, ADIN1110_RESET, ADIN1110_SWRESET); 1674 if (ret < 0) 1675 return ret; 1676 1677 ret = adin1110_register_mdiobus(priv, dev); 1678 if (ret < 0) { 1679 dev_err(dev, "Could not register MDIO bus %d\n", ret); 1680 return ret; 1681 } 1682 1683 return adin1110_probe_netdevs(priv); 1684 } 1685 1686 static const struct of_device_id adin1110_match_table[] = { 1687 { .compatible = "adi,adin1110" }, 1688 { .compatible = "adi,adin2111" }, 1689 { } 1690 }; 1691 MODULE_DEVICE_TABLE(of, adin1110_match_table); 1692 1693 static const struct spi_device_id adin1110_spi_id[] = { 1694 { .name = "adin1110", .driver_data = ADIN1110_MAC }, 1695 { .name = "adin2111", .driver_data = ADIN2111_MAC }, 1696 { } 1697 }; 1698 MODULE_DEVICE_TABLE(spi, adin1110_spi_id); 1699 1700 static struct spi_driver adin1110_driver = { 1701 .driver = { 1702 .name = "adin1110", 1703 .of_match_table = adin1110_match_table, 1704 }, 1705 .probe = adin1110_probe, 1706 .id_table = adin1110_spi_id, 1707 }; 1708 1709 static int __init adin1110_driver_init(void) 1710 { 1711 int ret; 1712 1713 ret = adin1110_setup_notifiers(); 1714 if (ret < 0) 1715 return ret; 1716 1717 ret = spi_register_driver(&adin1110_driver); 1718 if (ret < 0) { 1719 adin1110_unregister_notifiers(); 1720 return ret; 1721 } 1722 1723 return 0; 1724 } 1725 1726 static void __exit adin1110_exit(void) 1727 { 1728 adin1110_unregister_notifiers(); 1729 spi_unregister_driver(&adin1110_driver); 1730 } 1731 module_init(adin1110_driver_init); 1732 module_exit(adin1110_exit); 1733 1734 MODULE_DESCRIPTION("ADIN1110 Network driver"); 1735 MODULE_AUTHOR("Alexandru Tachici <alexandru.tachici@analog.com>"); 1736 MODULE_LICENSE("Dual BSD/GPL"); 1737