1 // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 2 /* ADIN1110 Low Power 10BASE-T1L Ethernet MAC-PHY 3 * ADIN2111 2-Port Ethernet Switch with Integrated 10BASE-T1L PHY 4 * 5 * Copyright 2021 Analog Devices Inc. 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/bits.h> 10 #include <linux/cache.h> 11 #include <linux/crc8.h> 12 #include <linux/etherdevice.h> 13 #include <linux/ethtool.h> 14 #include <linux/if_bridge.h> 15 #include <linux/interrupt.h> 16 #include <linux/iopoll.h> 17 #include <linux/gpio.h> 18 #include <linux/kernel.h> 19 #include <linux/mii.h> 20 #include <linux/module.h> 21 #include <linux/netdevice.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/phy.h> 24 #include <linux/property.h> 25 #include <linux/spi/spi.h> 26 27 #include <net/switchdev.h> 28 29 #include <asm/unaligned.h> 30 31 #define ADIN1110_PHY_ID 0x1 32 33 #define ADIN1110_RESET 0x03 34 #define ADIN1110_SWRESET BIT(0) 35 36 #define ADIN1110_CONFIG1 0x04 37 #define ADIN1110_CONFIG1_SYNC BIT(15) 38 39 #define ADIN1110_CONFIG2 0x06 40 #define ADIN2111_P2_FWD_UNK2HOST BIT(12) 41 #define ADIN2111_PORT_CUT_THRU_EN BIT(11) 42 #define ADIN1110_CRC_APPEND BIT(5) 43 #define ADIN1110_FWD_UNK2HOST BIT(2) 44 45 #define ADIN1110_STATUS0 0x08 46 47 #define ADIN1110_STATUS1 0x09 48 #define ADIN2111_P2_RX_RDY BIT(17) 49 #define ADIN1110_SPI_ERR BIT(10) 50 #define ADIN1110_RX_RDY BIT(4) 51 52 #define ADIN1110_IMASK1 0x0D 53 #define ADIN2111_RX_RDY_IRQ BIT(17) 54 #define ADIN1110_SPI_ERR_IRQ BIT(10) 55 #define ADIN1110_RX_RDY_IRQ BIT(4) 56 #define ADIN1110_TX_RDY_IRQ BIT(3) 57 58 #define ADIN1110_MDIOACC 0x20 59 #define ADIN1110_MDIO_TRDONE BIT(31) 60 #define ADIN1110_MDIO_ST GENMASK(29, 28) 61 #define ADIN1110_MDIO_OP GENMASK(27, 26) 62 #define ADIN1110_MDIO_PRTAD GENMASK(25, 21) 63 #define ADIN1110_MDIO_DEVAD GENMASK(20, 16) 64 #define ADIN1110_MDIO_DATA GENMASK(15, 0) 65 66 #define ADIN1110_TX_FSIZE 0x30 67 #define ADIN1110_TX 0x31 68 #define ADIN1110_TX_SPACE 0x32 69 70 #define ADIN1110_MAC_ADDR_FILTER_UPR 0x50 71 #define ADIN2111_MAC_ADDR_APPLY2PORT2 BIT(31) 72 #define ADIN1110_MAC_ADDR_APPLY2PORT BIT(30) 73 #define ADIN2111_MAC_ADDR_TO_OTHER_PORT BIT(17) 74 #define ADIN1110_MAC_ADDR_TO_HOST BIT(16) 75 76 #define ADIN1110_MAC_ADDR_FILTER_LWR 0x51 77 78 #define ADIN1110_MAC_ADDR_MASK_UPR 0x70 79 #define ADIN1110_MAC_ADDR_MASK_LWR 0x71 80 81 #define ADIN1110_RX_FSIZE 0x90 82 #define ADIN1110_RX 0x91 83 84 #define ADIN2111_RX_P2_FSIZE 0xC0 85 #define ADIN2111_RX_P2 0xC1 86 87 #define ADIN1110_CLEAR_STATUS0 0xFFF 88 89 /* MDIO_OP codes */ 90 #define ADIN1110_MDIO_OP_WR 0x1 91 #define ADIN1110_MDIO_OP_RD 0x3 92 93 #define ADIN1110_CD BIT(7) 94 #define ADIN1110_WRITE BIT(5) 95 96 #define ADIN1110_MAX_BUFF 2048 97 #define ADIN1110_MAX_FRAMES_READ 64 98 #define ADIN1110_WR_HEADER_LEN 2 99 #define ADIN1110_FRAME_HEADER_LEN 2 100 #define ADIN1110_INTERNAL_SIZE_HEADER_LEN 2 101 #define ADIN1110_RD_HEADER_LEN 3 102 #define ADIN1110_REG_LEN 4 103 #define ADIN1110_FEC_LEN 4 104 105 #define ADIN1110_PHY_ID_VAL 0x0283BC91 106 #define ADIN2111_PHY_ID_VAL 0x0283BCA1 107 108 #define ADIN_MAC_MAX_PORTS 2 109 #define ADIN_MAC_MAX_ADDR_SLOTS 16 110 111 #define ADIN_MAC_MULTICAST_ADDR_SLOT 0 112 #define ADIN_MAC_BROADCAST_ADDR_SLOT 1 113 #define ADIN_MAC_P1_ADDR_SLOT 2 114 #define ADIN_MAC_P2_ADDR_SLOT 3 115 #define ADIN_MAC_FDB_ADDR_SLOT 4 116 117 DECLARE_CRC8_TABLE(adin1110_crc_table); 118 119 enum adin1110_chips_id { 120 ADIN1110_MAC = 0, 121 ADIN2111_MAC, 122 }; 123 124 struct adin1110_cfg { 125 enum adin1110_chips_id id; 126 char name[MDIO_NAME_SIZE]; 127 u32 phy_ids[PHY_MAX_ADDR]; 128 u32 ports_nr; 129 u32 phy_id_val; 130 }; 131 132 struct adin1110_port_priv { 133 struct adin1110_priv *priv; 134 struct net_device *netdev; 135 struct net_device *bridge; 136 struct phy_device *phydev; 137 struct work_struct tx_work; 138 u64 rx_packets; 139 u64 tx_packets; 140 u64 rx_bytes; 141 u64 tx_bytes; 142 struct work_struct rx_mode_work; 143 u32 flags; 144 struct sk_buff_head txq; 145 u32 nr; 146 u32 state; 147 struct adin1110_cfg *cfg; 148 }; 149 150 struct adin1110_priv { 151 struct mutex lock; /* protect spi */ 152 spinlock_t state_lock; /* protect RX mode */ 153 struct mii_bus *mii_bus; 154 struct spi_device *spidev; 155 bool append_crc; 156 struct adin1110_cfg *cfg; 157 u32 tx_space; 158 u32 irq_mask; 159 bool forwarding; 160 int irq; 161 struct adin1110_port_priv *ports[ADIN_MAC_MAX_PORTS]; 162 char mii_bus_name[MII_BUS_ID_SIZE]; 163 u8 data[ADIN1110_MAX_BUFF] ____cacheline_aligned; 164 }; 165 166 struct adin1110_switchdev_event_work { 167 struct work_struct work; 168 struct switchdev_notifier_fdb_info fdb_info; 169 struct adin1110_port_priv *port_priv; 170 unsigned long event; 171 }; 172 173 static struct adin1110_cfg adin1110_cfgs[] = { 174 { 175 .id = ADIN1110_MAC, 176 .name = "adin1110", 177 .phy_ids = {1}, 178 .ports_nr = 1, 179 .phy_id_val = ADIN1110_PHY_ID_VAL, 180 }, 181 { 182 .id = ADIN2111_MAC, 183 .name = "adin2111", 184 .phy_ids = {1, 2}, 185 .ports_nr = 2, 186 .phy_id_val = ADIN2111_PHY_ID_VAL, 187 }, 188 }; 189 190 static u8 adin1110_crc_data(u8 *data, u32 len) 191 { 192 return crc8(adin1110_crc_table, data, len, 0); 193 } 194 195 static int adin1110_read_reg(struct adin1110_priv *priv, u16 reg, u32 *val) 196 { 197 u32 header_len = ADIN1110_RD_HEADER_LEN; 198 u32 read_len = ADIN1110_REG_LEN; 199 struct spi_transfer t[2] = {0}; 200 int ret; 201 202 priv->data[0] = ADIN1110_CD | FIELD_GET(GENMASK(12, 8), reg); 203 priv->data[1] = FIELD_GET(GENMASK(7, 0), reg); 204 priv->data[2] = 0x00; 205 206 if (priv->append_crc) { 207 priv->data[2] = adin1110_crc_data(&priv->data[0], 2); 208 priv->data[3] = 0x00; 209 header_len++; 210 } 211 212 t[0].tx_buf = &priv->data[0]; 213 t[0].len = header_len; 214 215 if (priv->append_crc) 216 read_len++; 217 218 memset(&priv->data[header_len], 0, read_len); 219 t[1].rx_buf = &priv->data[header_len]; 220 t[1].len = read_len; 221 222 ret = spi_sync_transfer(priv->spidev, t, 2); 223 if (ret) 224 return ret; 225 226 if (priv->append_crc) { 227 u8 recv_crc; 228 u8 crc; 229 230 crc = adin1110_crc_data(&priv->data[header_len], 231 ADIN1110_REG_LEN); 232 recv_crc = priv->data[header_len + ADIN1110_REG_LEN]; 233 234 if (crc != recv_crc) { 235 dev_err_ratelimited(&priv->spidev->dev, "CRC error."); 236 return -EBADMSG; 237 } 238 } 239 240 *val = get_unaligned_be32(&priv->data[header_len]); 241 242 return ret; 243 } 244 245 static int adin1110_write_reg(struct adin1110_priv *priv, u16 reg, u32 val) 246 { 247 u32 header_len = ADIN1110_WR_HEADER_LEN; 248 u32 write_len = ADIN1110_REG_LEN; 249 250 priv->data[0] = ADIN1110_CD | ADIN1110_WRITE | FIELD_GET(GENMASK(12, 8), reg); 251 priv->data[1] = FIELD_GET(GENMASK(7, 0), reg); 252 253 if (priv->append_crc) { 254 priv->data[2] = adin1110_crc_data(&priv->data[0], header_len); 255 header_len++; 256 } 257 258 put_unaligned_be32(val, &priv->data[header_len]); 259 if (priv->append_crc) { 260 priv->data[header_len + write_len] = adin1110_crc_data(&priv->data[header_len], 261 write_len); 262 write_len++; 263 } 264 265 return spi_write(priv->spidev, &priv->data[0], header_len + write_len); 266 } 267 268 static int adin1110_set_bits(struct adin1110_priv *priv, u16 reg, 269 unsigned long mask, unsigned long val) 270 { 271 u32 write_val; 272 int ret; 273 274 ret = adin1110_read_reg(priv, reg, &write_val); 275 if (ret < 0) 276 return ret; 277 278 set_mask_bits(&write_val, mask, val); 279 280 return adin1110_write_reg(priv, reg, write_val); 281 } 282 283 static int adin1110_round_len(int len) 284 { 285 /* can read/write only mutiples of 4 bytes of payload */ 286 len = ALIGN(len, 4); 287 288 /* NOTE: ADIN1110_WR_HEADER_LEN should be used for write ops. */ 289 if (len + ADIN1110_RD_HEADER_LEN > ADIN1110_MAX_BUFF) 290 return -EINVAL; 291 292 return len; 293 } 294 295 static int adin1110_read_fifo(struct adin1110_port_priv *port_priv) 296 { 297 struct adin1110_priv *priv = port_priv->priv; 298 u32 header_len = ADIN1110_RD_HEADER_LEN; 299 struct spi_transfer t[2] = {0}; 300 u32 frame_size_no_fcs; 301 struct sk_buff *rxb; 302 u32 frame_size; 303 int round_len; 304 u16 reg; 305 int ret; 306 307 if (!port_priv->nr) { 308 reg = ADIN1110_RX; 309 ret = adin1110_read_reg(priv, ADIN1110_RX_FSIZE, &frame_size); 310 } else { 311 reg = ADIN2111_RX_P2; 312 ret = adin1110_read_reg(priv, ADIN2111_RX_P2_FSIZE, 313 &frame_size); 314 } 315 316 if (ret < 0) 317 return ret; 318 319 /* The read frame size includes the extra 2 bytes 320 * from the ADIN1110 frame header. 321 */ 322 if (frame_size < ADIN1110_FRAME_HEADER_LEN + ADIN1110_FEC_LEN) 323 return ret; 324 325 round_len = adin1110_round_len(frame_size); 326 if (round_len < 0) 327 return ret; 328 329 frame_size_no_fcs = frame_size - ADIN1110_FRAME_HEADER_LEN - ADIN1110_FEC_LEN; 330 331 rxb = netdev_alloc_skb(port_priv->netdev, round_len); 332 if (!rxb) 333 return -ENOMEM; 334 335 memset(priv->data, 0, round_len + ADIN1110_RD_HEADER_LEN); 336 337 priv->data[0] = ADIN1110_CD | FIELD_GET(GENMASK(12, 8), reg); 338 priv->data[1] = FIELD_GET(GENMASK(7, 0), reg); 339 340 if (priv->append_crc) { 341 priv->data[2] = adin1110_crc_data(&priv->data[0], 2); 342 header_len++; 343 } 344 345 skb_put(rxb, frame_size_no_fcs + ADIN1110_FRAME_HEADER_LEN); 346 347 t[0].tx_buf = &priv->data[0]; 348 t[0].len = header_len; 349 350 t[1].rx_buf = &rxb->data[0]; 351 t[1].len = round_len; 352 353 ret = spi_sync_transfer(priv->spidev, t, 2); 354 if (ret) { 355 kfree_skb(rxb); 356 return ret; 357 } 358 359 skb_pull(rxb, ADIN1110_FRAME_HEADER_LEN); 360 rxb->protocol = eth_type_trans(rxb, port_priv->netdev); 361 362 if ((port_priv->flags & IFF_ALLMULTI && rxb->pkt_type == PACKET_MULTICAST) || 363 (port_priv->flags & IFF_BROADCAST && rxb->pkt_type == PACKET_BROADCAST)) 364 rxb->offload_fwd_mark = 1; 365 366 netif_rx(rxb); 367 368 port_priv->rx_bytes += frame_size - ADIN1110_FRAME_HEADER_LEN; 369 port_priv->rx_packets++; 370 371 return 0; 372 } 373 374 static int adin1110_write_fifo(struct adin1110_port_priv *port_priv, 375 struct sk_buff *txb) 376 { 377 struct adin1110_priv *priv = port_priv->priv; 378 u32 header_len = ADIN1110_WR_HEADER_LEN; 379 __be16 frame_header; 380 int padding = 0; 381 int padded_len; 382 int round_len; 383 int ret; 384 385 /* Pad frame to 64 byte length, 386 * MAC nor PHY will otherwise add the 387 * required padding. 388 * The FEC will be added by the MAC internally. 389 */ 390 if (txb->len + ADIN1110_FEC_LEN < 64) 391 padding = 64 - (txb->len + ADIN1110_FEC_LEN); 392 393 padded_len = txb->len + padding + ADIN1110_FRAME_HEADER_LEN; 394 395 round_len = adin1110_round_len(padded_len); 396 if (round_len < 0) 397 return round_len; 398 399 ret = adin1110_write_reg(priv, ADIN1110_TX_FSIZE, padded_len); 400 if (ret < 0) 401 return ret; 402 403 memset(priv->data, 0, round_len + ADIN1110_WR_HEADER_LEN); 404 405 priv->data[0] = ADIN1110_CD | ADIN1110_WRITE; 406 priv->data[0] |= FIELD_GET(GENMASK(12, 8), ADIN1110_TX); 407 priv->data[1] = FIELD_GET(GENMASK(7, 0), ADIN1110_TX); 408 if (priv->append_crc) { 409 priv->data[2] = adin1110_crc_data(&priv->data[0], 2); 410 header_len++; 411 } 412 413 /* mention the port on which to send the frame in the frame header */ 414 frame_header = cpu_to_be16(port_priv->nr); 415 memcpy(&priv->data[header_len], &frame_header, 416 ADIN1110_FRAME_HEADER_LEN); 417 418 memcpy(&priv->data[header_len + ADIN1110_FRAME_HEADER_LEN], 419 txb->data, txb->len); 420 421 ret = spi_write(priv->spidev, &priv->data[0], round_len + header_len); 422 if (ret < 0) 423 return ret; 424 425 port_priv->tx_bytes += txb->len; 426 port_priv->tx_packets++; 427 428 return 0; 429 } 430 431 static int adin1110_read_mdio_acc(struct adin1110_priv *priv) 432 { 433 u32 val; 434 int ret; 435 436 mutex_lock(&priv->lock); 437 ret = adin1110_read_reg(priv, ADIN1110_MDIOACC, &val); 438 mutex_unlock(&priv->lock); 439 if (ret < 0) 440 return 0; 441 442 return val; 443 } 444 445 static int adin1110_mdio_read(struct mii_bus *bus, int phy_id, int reg) 446 { 447 struct adin1110_priv *priv = bus->priv; 448 u32 val = 0; 449 int ret; 450 451 if (mdio_phy_id_is_c45(phy_id)) 452 return -EOPNOTSUPP; 453 454 val |= FIELD_PREP(ADIN1110_MDIO_OP, ADIN1110_MDIO_OP_RD); 455 val |= FIELD_PREP(ADIN1110_MDIO_ST, 0x1); 456 val |= FIELD_PREP(ADIN1110_MDIO_PRTAD, phy_id); 457 val |= FIELD_PREP(ADIN1110_MDIO_DEVAD, reg); 458 459 /* write the clause 22 read command to the chip */ 460 mutex_lock(&priv->lock); 461 ret = adin1110_write_reg(priv, ADIN1110_MDIOACC, val); 462 mutex_unlock(&priv->lock); 463 if (ret < 0) 464 return ret; 465 466 /* ADIN1110_MDIO_TRDONE BIT of the ADIN1110_MDIOACC 467 * register is set when the read is done. 468 * After the transaction is done, ADIN1110_MDIO_DATA 469 * bitfield of ADIN1110_MDIOACC register will contain 470 * the requested register value. 471 */ 472 ret = readx_poll_timeout(adin1110_read_mdio_acc, priv, val, 473 (val & ADIN1110_MDIO_TRDONE), 10000, 30000); 474 if (ret < 0) 475 return ret; 476 477 return (val & ADIN1110_MDIO_DATA); 478 } 479 480 static int adin1110_mdio_write(struct mii_bus *bus, int phy_id, 481 int reg, u16 reg_val) 482 { 483 struct adin1110_priv *priv = bus->priv; 484 u32 val = 0; 485 int ret; 486 487 if (mdio_phy_id_is_c45(phy_id)) 488 return -EOPNOTSUPP; 489 490 val |= FIELD_PREP(ADIN1110_MDIO_OP, ADIN1110_MDIO_OP_WR); 491 val |= FIELD_PREP(ADIN1110_MDIO_ST, 0x1); 492 val |= FIELD_PREP(ADIN1110_MDIO_PRTAD, phy_id); 493 val |= FIELD_PREP(ADIN1110_MDIO_DEVAD, reg); 494 val |= FIELD_PREP(ADIN1110_MDIO_DATA, reg_val); 495 496 /* write the clause 22 write command to the chip */ 497 mutex_lock(&priv->lock); 498 ret = adin1110_write_reg(priv, ADIN1110_MDIOACC, val); 499 mutex_unlock(&priv->lock); 500 if (ret < 0) 501 return ret; 502 503 return readx_poll_timeout(adin1110_read_mdio_acc, priv, val, 504 (val & ADIN1110_MDIO_TRDONE), 10000, 30000); 505 } 506 507 /* ADIN1110 MAC-PHY contains an ADIN1100 PHY. 508 * ADIN2111 MAC-PHY contains two ADIN1100 PHYs. 509 * By registering a new MDIO bus we allow the PAL to discover 510 * the encapsulated PHY and probe the ADIN1100 driver. 511 */ 512 static int adin1110_register_mdiobus(struct adin1110_priv *priv, 513 struct device *dev) 514 { 515 struct mii_bus *mii_bus; 516 int ret; 517 518 mii_bus = devm_mdiobus_alloc(dev); 519 if (!mii_bus) 520 return -ENOMEM; 521 522 snprintf(priv->mii_bus_name, MII_BUS_ID_SIZE, "%s-%u", 523 priv->cfg->name, priv->spidev->chip_select); 524 525 mii_bus->name = priv->mii_bus_name; 526 mii_bus->read = adin1110_mdio_read; 527 mii_bus->write = adin1110_mdio_write; 528 mii_bus->priv = priv; 529 mii_bus->parent = dev; 530 mii_bus->phy_mask = ~((u32)GENMASK(2, 0)); 531 mii_bus->probe_capabilities = MDIOBUS_C22; 532 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev)); 533 534 ret = devm_mdiobus_register(dev, mii_bus); 535 if (ret) 536 return ret; 537 538 priv->mii_bus = mii_bus; 539 540 return 0; 541 } 542 543 static bool adin1110_port_rx_ready(struct adin1110_port_priv *port_priv, 544 u32 status) 545 { 546 if (!netif_oper_up(port_priv->netdev)) 547 return false; 548 549 if (!port_priv->nr) 550 return !!(status & ADIN1110_RX_RDY); 551 else 552 return !!(status & ADIN2111_P2_RX_RDY); 553 } 554 555 static void adin1110_read_frames(struct adin1110_port_priv *port_priv, 556 unsigned int budget) 557 { 558 struct adin1110_priv *priv = port_priv->priv; 559 u32 status1; 560 int ret; 561 562 while (budget) { 563 ret = adin1110_read_reg(priv, ADIN1110_STATUS1, &status1); 564 if (ret < 0) 565 return; 566 567 if (!adin1110_port_rx_ready(port_priv, status1)) 568 break; 569 570 ret = adin1110_read_fifo(port_priv); 571 if (ret < 0) 572 return; 573 574 budget--; 575 } 576 } 577 578 static void adin1110_wake_queues(struct adin1110_priv *priv) 579 { 580 int i; 581 582 for (i = 0; i < priv->cfg->ports_nr; i++) 583 netif_wake_queue(priv->ports[i]->netdev); 584 } 585 586 static irqreturn_t adin1110_irq(int irq, void *p) 587 { 588 struct adin1110_priv *priv = p; 589 u32 status1; 590 u32 val; 591 int ret; 592 int i; 593 594 mutex_lock(&priv->lock); 595 596 ret = adin1110_read_reg(priv, ADIN1110_STATUS1, &status1); 597 if (ret < 0) 598 goto out; 599 600 if (priv->append_crc && (status1 & ADIN1110_SPI_ERR)) 601 dev_warn_ratelimited(&priv->spidev->dev, 602 "SPI CRC error on write.\n"); 603 604 ret = adin1110_read_reg(priv, ADIN1110_TX_SPACE, &val); 605 if (ret < 0) 606 goto out; 607 608 /* TX FIFO space is expressed in half-words */ 609 priv->tx_space = 2 * val; 610 611 for (i = 0; i < priv->cfg->ports_nr; i++) { 612 if (adin1110_port_rx_ready(priv->ports[i], status1)) 613 adin1110_read_frames(priv->ports[i], 614 ADIN1110_MAX_FRAMES_READ); 615 } 616 617 /* clear IRQ sources */ 618 adin1110_write_reg(priv, ADIN1110_STATUS0, ADIN1110_CLEAR_STATUS0); 619 adin1110_write_reg(priv, ADIN1110_STATUS1, priv->irq_mask); 620 621 out: 622 mutex_unlock(&priv->lock); 623 624 if (priv->tx_space > 0 && ret >= 0) 625 adin1110_wake_queues(priv); 626 627 return IRQ_HANDLED; 628 } 629 630 /* ADIN1110 can filter up to 16 MAC addresses, mac_nr here is the slot used */ 631 static int adin1110_write_mac_address(struct adin1110_port_priv *port_priv, 632 int mac_nr, const u8 *addr, 633 u8 *mask, u32 port_rules) 634 { 635 struct adin1110_priv *priv = port_priv->priv; 636 u32 offset = mac_nr * 2; 637 u32 port_rules_mask; 638 int ret; 639 u32 val; 640 641 if (!port_priv->nr) 642 port_rules_mask = ADIN1110_MAC_ADDR_APPLY2PORT; 643 else 644 port_rules_mask = ADIN2111_MAC_ADDR_APPLY2PORT2; 645 646 if (port_rules & port_rules_mask) 647 port_rules_mask |= ADIN1110_MAC_ADDR_TO_HOST | ADIN2111_MAC_ADDR_TO_OTHER_PORT; 648 649 port_rules_mask |= GENMASK(15, 0); 650 val = port_rules | get_unaligned_be16(&addr[0]); 651 ret = adin1110_set_bits(priv, ADIN1110_MAC_ADDR_FILTER_UPR + offset, 652 port_rules_mask, val); 653 if (ret < 0) 654 return ret; 655 656 val = get_unaligned_be32(&addr[2]); 657 ret = adin1110_write_reg(priv, 658 ADIN1110_MAC_ADDR_FILTER_LWR + offset, val); 659 if (ret < 0) 660 return ret; 661 662 /* Only the first two MAC address slots support masking. */ 663 if (mac_nr < ADIN_MAC_P1_ADDR_SLOT) { 664 val = get_unaligned_be16(&mask[0]); 665 ret = adin1110_write_reg(priv, 666 ADIN1110_MAC_ADDR_MASK_UPR + offset, 667 val); 668 if (ret < 0) 669 return ret; 670 671 val = get_unaligned_be32(&mask[2]); 672 return adin1110_write_reg(priv, 673 ADIN1110_MAC_ADDR_MASK_LWR + offset, 674 val); 675 } 676 677 return 0; 678 } 679 680 static int adin1110_clear_mac_address(struct adin1110_priv *priv, int mac_nr) 681 { 682 u32 offset = mac_nr * 2; 683 int ret; 684 685 ret = adin1110_write_reg(priv, ADIN1110_MAC_ADDR_FILTER_UPR + offset, 0); 686 if (ret < 0) 687 return ret; 688 689 ret = adin1110_write_reg(priv, ADIN1110_MAC_ADDR_FILTER_LWR + offset, 0); 690 if (ret < 0) 691 return ret; 692 693 /* only the first two MAC address slots are maskable */ 694 if (mac_nr <= 1) { 695 ret = adin1110_write_reg(priv, ADIN1110_MAC_ADDR_MASK_UPR + offset, 0); 696 if (ret < 0) 697 return ret; 698 699 ret = adin1110_write_reg(priv, ADIN1110_MAC_ADDR_MASK_LWR + offset, 0); 700 } 701 702 return ret; 703 } 704 705 static u32 adin1110_port_rules(struct adin1110_port_priv *port_priv, 706 bool fw_to_host, 707 bool fw_to_other_port) 708 { 709 u32 port_rules = 0; 710 711 if (!port_priv->nr) 712 port_rules |= ADIN1110_MAC_ADDR_APPLY2PORT; 713 else 714 port_rules |= ADIN2111_MAC_ADDR_APPLY2PORT2; 715 716 if (fw_to_host) 717 port_rules |= ADIN1110_MAC_ADDR_TO_HOST; 718 719 if (fw_to_other_port && port_priv->priv->forwarding) 720 port_rules |= ADIN2111_MAC_ADDR_TO_OTHER_PORT; 721 722 return port_rules; 723 } 724 725 static int adin1110_multicast_filter(struct adin1110_port_priv *port_priv, 726 int mac_nr, bool accept_multicast) 727 { 728 u8 mask[ETH_ALEN] = {0}; 729 u8 mac[ETH_ALEN] = {0}; 730 u32 port_rules = 0; 731 732 mask[0] = BIT(0); 733 mac[0] = BIT(0); 734 735 if (accept_multicast && port_priv->state == BR_STATE_FORWARDING) 736 port_rules = adin1110_port_rules(port_priv, true, true); 737 738 return adin1110_write_mac_address(port_priv, mac_nr, mac, 739 mask, port_rules); 740 } 741 742 static int adin1110_broadcasts_filter(struct adin1110_port_priv *port_priv, 743 int mac_nr, bool accept_broadcast) 744 { 745 u32 port_rules = 0; 746 u8 mask[ETH_ALEN]; 747 748 memset(mask, 0xFF, ETH_ALEN); 749 750 if (accept_broadcast && port_priv->state == BR_STATE_FORWARDING) 751 port_rules = adin1110_port_rules(port_priv, true, true); 752 753 return adin1110_write_mac_address(port_priv, mac_nr, mask, 754 mask, port_rules); 755 } 756 757 static int adin1110_set_mac_address(struct net_device *netdev, 758 const unsigned char *dev_addr) 759 { 760 struct adin1110_port_priv *port_priv = netdev_priv(netdev); 761 u8 mask[ETH_ALEN]; 762 u32 port_rules; 763 u32 mac_slot; 764 765 if (!is_valid_ether_addr(dev_addr)) 766 return -EADDRNOTAVAIL; 767 768 eth_hw_addr_set(netdev, dev_addr); 769 memset(mask, 0xFF, ETH_ALEN); 770 771 mac_slot = (!port_priv->nr) ? ADIN_MAC_P1_ADDR_SLOT : ADIN_MAC_P2_ADDR_SLOT; 772 port_rules = adin1110_port_rules(port_priv, true, false); 773 774 return adin1110_write_mac_address(port_priv, mac_slot, netdev->dev_addr, 775 mask, port_rules); 776 } 777 778 static int adin1110_ndo_set_mac_address(struct net_device *netdev, void *addr) 779 { 780 struct sockaddr *sa = addr; 781 int ret; 782 783 ret = eth_prepare_mac_addr_change(netdev, addr); 784 if (ret < 0) 785 return ret; 786 787 return adin1110_set_mac_address(netdev, sa->sa_data); 788 } 789 790 static int adin1110_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 791 { 792 if (!netif_running(netdev)) 793 return -EINVAL; 794 795 return phy_do_ioctl(netdev, rq, cmd); 796 } 797 798 static int adin1110_set_promisc_mode(struct adin1110_port_priv *port_priv, 799 bool promisc) 800 { 801 struct adin1110_priv *priv = port_priv->priv; 802 u32 mask; 803 804 if (port_priv->state != BR_STATE_FORWARDING) 805 promisc = false; 806 807 if (!port_priv->nr) 808 mask = ADIN1110_FWD_UNK2HOST; 809 else 810 mask = ADIN2111_P2_FWD_UNK2HOST; 811 812 return adin1110_set_bits(priv, ADIN1110_CONFIG2, 813 mask, promisc ? mask : 0); 814 } 815 816 static int adin1110_setup_rx_mode(struct adin1110_port_priv *port_priv) 817 { 818 int ret; 819 820 ret = adin1110_set_promisc_mode(port_priv, 821 !!(port_priv->flags & IFF_PROMISC)); 822 if (ret < 0) 823 return ret; 824 825 ret = adin1110_multicast_filter(port_priv, ADIN_MAC_MULTICAST_ADDR_SLOT, 826 !!(port_priv->flags & IFF_ALLMULTI)); 827 if (ret < 0) 828 return ret; 829 830 ret = adin1110_broadcasts_filter(port_priv, 831 ADIN_MAC_BROADCAST_ADDR_SLOT, 832 !!(port_priv->flags & IFF_BROADCAST)); 833 if (ret < 0) 834 return ret; 835 836 return adin1110_set_bits(port_priv->priv, ADIN1110_CONFIG1, 837 ADIN1110_CONFIG1_SYNC, ADIN1110_CONFIG1_SYNC); 838 } 839 840 static bool adin1110_can_offload_forwarding(struct adin1110_priv *priv) 841 { 842 int i; 843 844 if (priv->cfg->id != ADIN2111_MAC) 845 return false; 846 847 /* Can't enable forwarding if ports do not belong to the same bridge */ 848 if (priv->ports[0]->bridge != priv->ports[1]->bridge || !priv->ports[0]->bridge) 849 return false; 850 851 /* Can't enable forwarding if there is a port 852 * that has been blocked by STP. 853 */ 854 for (i = 0; i < priv->cfg->ports_nr; i++) { 855 if (priv->ports[i]->state != BR_STATE_FORWARDING) 856 return false; 857 } 858 859 return true; 860 } 861 862 static void adin1110_rx_mode_work(struct work_struct *work) 863 { 864 struct adin1110_port_priv *port_priv; 865 struct adin1110_priv *priv; 866 867 port_priv = container_of(work, struct adin1110_port_priv, rx_mode_work); 868 priv = port_priv->priv; 869 870 mutex_lock(&priv->lock); 871 adin1110_setup_rx_mode(port_priv); 872 mutex_unlock(&priv->lock); 873 } 874 875 static void adin1110_set_rx_mode(struct net_device *dev) 876 { 877 struct adin1110_port_priv *port_priv = netdev_priv(dev); 878 struct adin1110_priv *priv = port_priv->priv; 879 880 spin_lock(&priv->state_lock); 881 882 port_priv->flags = dev->flags; 883 schedule_work(&port_priv->rx_mode_work); 884 885 spin_unlock(&priv->state_lock); 886 } 887 888 static int adin1110_net_open(struct net_device *net_dev) 889 { 890 struct adin1110_port_priv *port_priv = netdev_priv(net_dev); 891 struct adin1110_priv *priv = port_priv->priv; 892 u32 val; 893 int ret; 894 895 mutex_lock(&priv->lock); 896 897 /* Configure MAC to compute and append the FCS itself. */ 898 ret = adin1110_write_reg(priv, ADIN1110_CONFIG2, ADIN1110_CRC_APPEND); 899 if (ret < 0) 900 goto out; 901 902 val = ADIN1110_TX_RDY_IRQ | ADIN1110_RX_RDY_IRQ | ADIN1110_SPI_ERR_IRQ; 903 if (priv->cfg->id == ADIN2111_MAC) 904 val |= ADIN2111_RX_RDY_IRQ; 905 906 priv->irq_mask = val; 907 ret = adin1110_write_reg(priv, ADIN1110_IMASK1, ~val); 908 if (ret < 0) { 909 netdev_err(net_dev, "Failed to enable chip IRQs: %d\n", ret); 910 goto out; 911 } 912 913 ret = adin1110_read_reg(priv, ADIN1110_TX_SPACE, &val); 914 if (ret < 0) { 915 netdev_err(net_dev, "Failed to read TX FIFO space: %d\n", ret); 916 goto out; 917 } 918 919 priv->tx_space = 2 * val; 920 921 port_priv->state = BR_STATE_FORWARDING; 922 ret = adin1110_set_mac_address(net_dev, net_dev->dev_addr); 923 if (ret < 0) { 924 netdev_err(net_dev, "Could not set MAC address: %pM, %d\n", 925 net_dev->dev_addr, ret); 926 goto out; 927 } 928 929 ret = adin1110_set_bits(priv, ADIN1110_CONFIG1, ADIN1110_CONFIG1_SYNC, 930 ADIN1110_CONFIG1_SYNC); 931 932 out: 933 mutex_unlock(&priv->lock); 934 935 if (ret < 0) 936 return ret; 937 938 phy_start(port_priv->phydev); 939 940 netif_start_queue(net_dev); 941 942 return 0; 943 } 944 945 static int adin1110_net_stop(struct net_device *net_dev) 946 { 947 struct adin1110_port_priv *port_priv = netdev_priv(net_dev); 948 struct adin1110_priv *priv = port_priv->priv; 949 u32 mask; 950 int ret; 951 952 mask = !port_priv->nr ? ADIN2111_RX_RDY_IRQ : ADIN1110_RX_RDY_IRQ; 953 954 /* Disable RX RDY IRQs */ 955 mutex_lock(&priv->lock); 956 ret = adin1110_set_bits(priv, ADIN1110_IMASK1, mask, mask); 957 mutex_unlock(&priv->lock); 958 if (ret < 0) 959 return ret; 960 961 netif_stop_queue(port_priv->netdev); 962 flush_work(&port_priv->tx_work); 963 phy_stop(port_priv->phydev); 964 965 return 0; 966 } 967 968 static void adin1110_tx_work(struct work_struct *work) 969 { 970 struct adin1110_port_priv *port_priv; 971 struct adin1110_priv *priv; 972 struct sk_buff *txb; 973 int ret; 974 975 port_priv = container_of(work, struct adin1110_port_priv, tx_work); 976 priv = port_priv->priv; 977 978 mutex_lock(&priv->lock); 979 980 while ((txb = skb_dequeue(&port_priv->txq))) { 981 ret = adin1110_write_fifo(port_priv, txb); 982 if (ret < 0) 983 dev_err_ratelimited(&priv->spidev->dev, 984 "Frame write error: %d\n", ret); 985 986 dev_kfree_skb(txb); 987 } 988 989 mutex_unlock(&priv->lock); 990 } 991 992 static netdev_tx_t adin1110_start_xmit(struct sk_buff *skb, struct net_device *dev) 993 { 994 struct adin1110_port_priv *port_priv = netdev_priv(dev); 995 struct adin1110_priv *priv = port_priv->priv; 996 netdev_tx_t netdev_ret = NETDEV_TX_OK; 997 u32 tx_space_needed; 998 999 tx_space_needed = skb->len + ADIN1110_FRAME_HEADER_LEN + ADIN1110_INTERNAL_SIZE_HEADER_LEN; 1000 if (tx_space_needed > priv->tx_space) { 1001 netif_stop_queue(dev); 1002 netdev_ret = NETDEV_TX_BUSY; 1003 } else { 1004 priv->tx_space -= tx_space_needed; 1005 skb_queue_tail(&port_priv->txq, skb); 1006 } 1007 1008 schedule_work(&port_priv->tx_work); 1009 1010 return netdev_ret; 1011 } 1012 1013 static void adin1110_ndo_get_stats64(struct net_device *dev, 1014 struct rtnl_link_stats64 *storage) 1015 { 1016 struct adin1110_port_priv *port_priv = netdev_priv(dev); 1017 1018 storage->rx_packets = port_priv->rx_packets; 1019 storage->tx_packets = port_priv->tx_packets; 1020 1021 storage->rx_bytes = port_priv->rx_bytes; 1022 storage->tx_bytes = port_priv->tx_bytes; 1023 } 1024 1025 static int adin1110_port_get_port_parent_id(struct net_device *dev, 1026 struct netdev_phys_item_id *ppid) 1027 { 1028 struct adin1110_port_priv *port_priv = netdev_priv(dev); 1029 struct adin1110_priv *priv = port_priv->priv; 1030 1031 ppid->id_len = strnlen(priv->mii_bus_name, MAX_PHYS_ITEM_ID_LEN); 1032 memcpy(ppid->id, priv->mii_bus_name, ppid->id_len); 1033 1034 return 0; 1035 } 1036 1037 static int adin1110_ndo_get_phys_port_name(struct net_device *dev, 1038 char *name, size_t len) 1039 { 1040 struct adin1110_port_priv *port_priv = netdev_priv(dev); 1041 int err; 1042 1043 err = snprintf(name, len, "p%d", port_priv->nr); 1044 if (err >= len) 1045 return -EINVAL; 1046 1047 return 0; 1048 } 1049 1050 static const struct net_device_ops adin1110_netdev_ops = { 1051 .ndo_open = adin1110_net_open, 1052 .ndo_stop = adin1110_net_stop, 1053 .ndo_eth_ioctl = adin1110_ioctl, 1054 .ndo_start_xmit = adin1110_start_xmit, 1055 .ndo_set_mac_address = adin1110_ndo_set_mac_address, 1056 .ndo_set_rx_mode = adin1110_set_rx_mode, 1057 .ndo_validate_addr = eth_validate_addr, 1058 .ndo_get_stats64 = adin1110_ndo_get_stats64, 1059 .ndo_get_port_parent_id = adin1110_port_get_port_parent_id, 1060 .ndo_get_phys_port_name = adin1110_ndo_get_phys_port_name, 1061 }; 1062 1063 static void adin1110_get_drvinfo(struct net_device *dev, 1064 struct ethtool_drvinfo *di) 1065 { 1066 strscpy(di->driver, "ADIN1110", sizeof(di->driver)); 1067 strscpy(di->bus_info, dev_name(dev->dev.parent), sizeof(di->bus_info)); 1068 } 1069 1070 static const struct ethtool_ops adin1110_ethtool_ops = { 1071 .get_drvinfo = adin1110_get_drvinfo, 1072 .get_link = ethtool_op_get_link, 1073 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1074 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1075 }; 1076 1077 static void adin1110_adjust_link(struct net_device *dev) 1078 { 1079 struct phy_device *phydev = dev->phydev; 1080 1081 if (!phydev->link) 1082 phy_print_status(phydev); 1083 } 1084 1085 /* PHY ID is stored in the MAC registers too, 1086 * check spi connection by reading it. 1087 */ 1088 static int adin1110_check_spi(struct adin1110_priv *priv) 1089 { 1090 int ret; 1091 u32 val; 1092 1093 ret = adin1110_read_reg(priv, ADIN1110_PHY_ID, &val); 1094 if (ret < 0) 1095 return ret; 1096 1097 if (val != priv->cfg->phy_id_val) { 1098 dev_err(&priv->spidev->dev, "PHY ID expected: %x, read: %x\n", 1099 priv->cfg->phy_id_val, val); 1100 return -EIO; 1101 } 1102 1103 return 0; 1104 } 1105 1106 static int adin1110_hw_forwarding(struct adin1110_priv *priv, bool enable) 1107 { 1108 int ret; 1109 int i; 1110 1111 priv->forwarding = enable; 1112 1113 if (!priv->forwarding) { 1114 for (i = ADIN_MAC_FDB_ADDR_SLOT; i < ADIN_MAC_MAX_ADDR_SLOTS; i++) { 1115 ret = adin1110_clear_mac_address(priv, i); 1116 if (ret < 0) 1117 return ret; 1118 } 1119 } 1120 1121 /* Forwarding is optimised when MAC runs in Cut Through mode. */ 1122 ret = adin1110_set_bits(priv, ADIN1110_CONFIG2, 1123 ADIN2111_PORT_CUT_THRU_EN, 1124 priv->forwarding ? ADIN2111_PORT_CUT_THRU_EN : 0); 1125 if (ret < 0) 1126 return ret; 1127 1128 for (i = 0; i < priv->cfg->ports_nr; i++) { 1129 ret = adin1110_setup_rx_mode(priv->ports[i]); 1130 if (ret < 0) 1131 return ret; 1132 } 1133 1134 return ret; 1135 } 1136 1137 static int adin1110_port_bridge_join(struct adin1110_port_priv *port_priv, 1138 struct net_device *bridge) 1139 { 1140 struct adin1110_priv *priv = port_priv->priv; 1141 int ret; 1142 1143 port_priv->bridge = bridge; 1144 1145 if (adin1110_can_offload_forwarding(priv)) { 1146 mutex_lock(&priv->lock); 1147 ret = adin1110_hw_forwarding(priv, true); 1148 mutex_unlock(&priv->lock); 1149 1150 if (ret < 0) 1151 return ret; 1152 } 1153 1154 return adin1110_set_mac_address(port_priv->netdev, bridge->dev_addr); 1155 } 1156 1157 static int adin1110_port_bridge_leave(struct adin1110_port_priv *port_priv, 1158 struct net_device *bridge) 1159 { 1160 struct adin1110_priv *priv = port_priv->priv; 1161 int ret; 1162 1163 port_priv->bridge = NULL; 1164 1165 mutex_lock(&priv->lock); 1166 ret = adin1110_hw_forwarding(priv, false); 1167 mutex_unlock(&priv->lock); 1168 1169 return ret; 1170 } 1171 1172 static int adin1110_netdevice_event(struct notifier_block *unused, 1173 unsigned long event, void *ptr) 1174 { 1175 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 1176 struct adin1110_port_priv *port_priv = netdev_priv(dev); 1177 struct netdev_notifier_changeupper_info *info = ptr; 1178 int ret = 0; 1179 1180 switch (event) { 1181 case NETDEV_CHANGEUPPER: 1182 if (netif_is_bridge_master(info->upper_dev)) { 1183 if (info->linking) 1184 ret = adin1110_port_bridge_join(port_priv, info->upper_dev); 1185 else 1186 ret = adin1110_port_bridge_leave(port_priv, info->upper_dev); 1187 } 1188 break; 1189 default: 1190 break; 1191 } 1192 1193 return notifier_from_errno(ret); 1194 } 1195 1196 static struct notifier_block adin1110_netdevice_nb = { 1197 .notifier_call = adin1110_netdevice_event, 1198 }; 1199 1200 static void adin1110_disconnect_phy(void *data) 1201 { 1202 phy_disconnect(data); 1203 } 1204 1205 static bool adin1110_port_dev_check(const struct net_device *dev) 1206 { 1207 return dev->netdev_ops == &adin1110_netdev_ops; 1208 } 1209 1210 static int adin1110_port_set_forwarding_state(struct adin1110_port_priv *port_priv) 1211 { 1212 struct adin1110_priv *priv = port_priv->priv; 1213 int ret; 1214 1215 port_priv->state = BR_STATE_FORWARDING; 1216 1217 mutex_lock(&priv->lock); 1218 ret = adin1110_set_mac_address(port_priv->netdev, 1219 port_priv->netdev->dev_addr); 1220 if (ret < 0) 1221 goto out; 1222 1223 if (adin1110_can_offload_forwarding(priv)) 1224 ret = adin1110_hw_forwarding(priv, true); 1225 else 1226 ret = adin1110_setup_rx_mode(port_priv); 1227 out: 1228 mutex_unlock(&priv->lock); 1229 1230 return ret; 1231 } 1232 1233 static int adin1110_port_set_blocking_state(struct adin1110_port_priv *port_priv) 1234 { 1235 u8 mac[ETH_ALEN] = {0x01, 0x80, 0xC2, 0x00, 0x00, 0x00}; 1236 struct adin1110_priv *priv = port_priv->priv; 1237 u8 mask[ETH_ALEN]; 1238 u32 port_rules; 1239 int mac_slot; 1240 int ret; 1241 1242 port_priv->state = BR_STATE_BLOCKING; 1243 1244 mutex_lock(&priv->lock); 1245 1246 mac_slot = (!port_priv->nr) ? ADIN_MAC_P1_ADDR_SLOT : ADIN_MAC_P2_ADDR_SLOT; 1247 ret = adin1110_clear_mac_address(priv, mac_slot); 1248 if (ret < 0) 1249 goto out; 1250 1251 ret = adin1110_hw_forwarding(priv, false); 1252 if (ret < 0) 1253 goto out; 1254 1255 /* Allow only BPDUs to be passed to the CPU */ 1256 memset(mask, 0xFF, ETH_ALEN); 1257 port_rules = adin1110_port_rules(port_priv, true, false); 1258 ret = adin1110_write_mac_address(port_priv, mac_slot, mac, 1259 mask, port_rules); 1260 out: 1261 mutex_unlock(&priv->lock); 1262 1263 return ret; 1264 } 1265 1266 /* ADIN1110/2111 does not have any native STP support. 1267 * Listen for bridge core state changes and 1268 * allow all frames to pass or only the BPDUs. 1269 */ 1270 static int adin1110_port_attr_stp_state_set(struct adin1110_port_priv *port_priv, 1271 u8 state) 1272 { 1273 switch (state) { 1274 case BR_STATE_FORWARDING: 1275 return adin1110_port_set_forwarding_state(port_priv); 1276 case BR_STATE_LEARNING: 1277 case BR_STATE_LISTENING: 1278 case BR_STATE_DISABLED: 1279 case BR_STATE_BLOCKING: 1280 return adin1110_port_set_blocking_state(port_priv); 1281 default: 1282 return -EINVAL; 1283 } 1284 } 1285 1286 static int adin1110_port_attr_set(struct net_device *dev, const void *ctx, 1287 const struct switchdev_attr *attr, 1288 struct netlink_ext_ack *extack) 1289 { 1290 struct adin1110_port_priv *port_priv = netdev_priv(dev); 1291 1292 switch (attr->id) { 1293 case SWITCHDEV_ATTR_ID_PORT_STP_STATE: 1294 return adin1110_port_attr_stp_state_set(port_priv, 1295 attr->u.stp_state); 1296 default: 1297 return -EOPNOTSUPP; 1298 } 1299 } 1300 1301 static int adin1110_switchdev_blocking_event(struct notifier_block *unused, 1302 unsigned long event, 1303 void *ptr) 1304 { 1305 struct net_device *netdev = switchdev_notifier_info_to_dev(ptr); 1306 int ret; 1307 1308 if (event == SWITCHDEV_PORT_ATTR_SET) { 1309 ret = switchdev_handle_port_attr_set(netdev, ptr, 1310 adin1110_port_dev_check, 1311 adin1110_port_attr_set); 1312 1313 return notifier_from_errno(ret); 1314 } 1315 1316 return NOTIFY_DONE; 1317 } 1318 1319 static struct notifier_block adin1110_switchdev_blocking_notifier = { 1320 .notifier_call = adin1110_switchdev_blocking_event, 1321 }; 1322 1323 static void adin1110_fdb_offload_notify(struct net_device *netdev, 1324 struct switchdev_notifier_fdb_info *rcv) 1325 { 1326 struct switchdev_notifier_fdb_info info = {}; 1327 1328 info.addr = rcv->addr; 1329 info.vid = rcv->vid; 1330 info.offloaded = true; 1331 call_switchdev_notifiers(SWITCHDEV_FDB_OFFLOADED, 1332 netdev, &info.info, NULL); 1333 } 1334 1335 static int adin1110_fdb_add(struct adin1110_port_priv *port_priv, 1336 struct switchdev_notifier_fdb_info *fdb) 1337 { 1338 struct adin1110_priv *priv = port_priv->priv; 1339 struct adin1110_port_priv *other_port; 1340 u8 mask[ETH_ALEN]; 1341 u32 port_rules; 1342 int mac_nr; 1343 u32 val; 1344 int ret; 1345 1346 netdev_dbg(port_priv->netdev, 1347 "DEBUG: %s: MACID = %pM vid = %u flags = %u %u -- port %d\n", 1348 __func__, fdb->addr, fdb->vid, fdb->added_by_user, 1349 fdb->offloaded, port_priv->nr); 1350 1351 if (!priv->forwarding) 1352 return 0; 1353 1354 if (fdb->is_local) 1355 return -EINVAL; 1356 1357 /* Find free FDB slot on device. */ 1358 for (mac_nr = ADIN_MAC_FDB_ADDR_SLOT; mac_nr < ADIN_MAC_MAX_ADDR_SLOTS; mac_nr++) { 1359 ret = adin1110_read_reg(priv, ADIN1110_MAC_ADDR_FILTER_UPR + (mac_nr * 2), &val); 1360 if (ret < 0) 1361 return ret; 1362 if (!val) 1363 break; 1364 } 1365 1366 if (mac_nr == ADIN_MAC_MAX_ADDR_SLOTS) 1367 return -ENOMEM; 1368 1369 other_port = priv->ports[!port_priv->nr]; 1370 port_rules = adin1110_port_rules(port_priv, false, true); 1371 memset(mask, 0xFF, ETH_ALEN); 1372 1373 return adin1110_write_mac_address(other_port, mac_nr, (u8 *)fdb->addr, 1374 mask, port_rules); 1375 } 1376 1377 static int adin1110_read_mac(struct adin1110_priv *priv, int mac_nr, u8 *addr) 1378 { 1379 u32 val; 1380 int ret; 1381 1382 ret = adin1110_read_reg(priv, ADIN1110_MAC_ADDR_FILTER_UPR + (mac_nr * 2), &val); 1383 if (ret < 0) 1384 return ret; 1385 1386 put_unaligned_be16(val, addr); 1387 1388 ret = adin1110_read_reg(priv, ADIN1110_MAC_ADDR_FILTER_LWR + (mac_nr * 2), &val); 1389 if (ret < 0) 1390 return ret; 1391 1392 put_unaligned_be32(val, addr + 2); 1393 1394 return 0; 1395 } 1396 1397 static int adin1110_fdb_del(struct adin1110_port_priv *port_priv, 1398 struct switchdev_notifier_fdb_info *fdb) 1399 { 1400 struct adin1110_priv *priv = port_priv->priv; 1401 u8 addr[ETH_ALEN]; 1402 int mac_nr; 1403 int ret; 1404 1405 netdev_dbg(port_priv->netdev, 1406 "DEBUG: %s: MACID = %pM vid = %u flags = %u %u -- port %d\n", 1407 __func__, fdb->addr, fdb->vid, fdb->added_by_user, 1408 fdb->offloaded, port_priv->nr); 1409 1410 if (fdb->is_local) 1411 return -EINVAL; 1412 1413 for (mac_nr = ADIN_MAC_FDB_ADDR_SLOT; mac_nr < ADIN_MAC_MAX_ADDR_SLOTS; mac_nr++) { 1414 ret = adin1110_read_mac(priv, mac_nr, addr); 1415 if (ret < 0) 1416 return ret; 1417 1418 if (ether_addr_equal(addr, fdb->addr)) { 1419 ret = adin1110_clear_mac_address(priv, mac_nr); 1420 if (ret < 0) 1421 return ret; 1422 } 1423 } 1424 1425 return 0; 1426 } 1427 1428 static void adin1110_switchdev_event_work(struct work_struct *work) 1429 { 1430 struct adin1110_switchdev_event_work *switchdev_work; 1431 struct adin1110_port_priv *port_priv; 1432 int ret; 1433 1434 switchdev_work = container_of(work, struct adin1110_switchdev_event_work, work); 1435 port_priv = switchdev_work->port_priv; 1436 1437 mutex_lock(&port_priv->priv->lock); 1438 1439 switch (switchdev_work->event) { 1440 case SWITCHDEV_FDB_ADD_TO_DEVICE: 1441 ret = adin1110_fdb_add(port_priv, &switchdev_work->fdb_info); 1442 if (!ret) 1443 adin1110_fdb_offload_notify(port_priv->netdev, 1444 &switchdev_work->fdb_info); 1445 break; 1446 case SWITCHDEV_FDB_DEL_TO_DEVICE: 1447 adin1110_fdb_del(port_priv, &switchdev_work->fdb_info); 1448 break; 1449 default: 1450 break; 1451 } 1452 1453 mutex_unlock(&port_priv->priv->lock); 1454 1455 kfree(switchdev_work->fdb_info.addr); 1456 kfree(switchdev_work); 1457 dev_put(port_priv->netdev); 1458 } 1459 1460 /* called under rcu_read_lock() */ 1461 static int adin1110_switchdev_event(struct notifier_block *unused, 1462 unsigned long event, void *ptr) 1463 { 1464 struct net_device *netdev = switchdev_notifier_info_to_dev(ptr); 1465 struct adin1110_port_priv *port_priv = netdev_priv(netdev); 1466 struct adin1110_switchdev_event_work *switchdev_work; 1467 struct switchdev_notifier_fdb_info *fdb_info = ptr; 1468 1469 if (!adin1110_port_dev_check(netdev)) 1470 return NOTIFY_DONE; 1471 1472 switchdev_work = kzalloc(sizeof(*switchdev_work), GFP_ATOMIC); 1473 if (WARN_ON(!switchdev_work)) 1474 return NOTIFY_BAD; 1475 1476 INIT_WORK(&switchdev_work->work, adin1110_switchdev_event_work); 1477 switchdev_work->port_priv = port_priv; 1478 switchdev_work->event = event; 1479 1480 switch (event) { 1481 case SWITCHDEV_FDB_ADD_TO_DEVICE: 1482 case SWITCHDEV_FDB_DEL_TO_DEVICE: 1483 memcpy(&switchdev_work->fdb_info, ptr, 1484 sizeof(switchdev_work->fdb_info)); 1485 switchdev_work->fdb_info.addr = kzalloc(ETH_ALEN, GFP_ATOMIC); 1486 1487 if (!switchdev_work->fdb_info.addr) 1488 goto err_addr_alloc; 1489 1490 ether_addr_copy((u8 *)switchdev_work->fdb_info.addr, 1491 fdb_info->addr); 1492 dev_hold(netdev); 1493 break; 1494 default: 1495 kfree(switchdev_work); 1496 return NOTIFY_DONE; 1497 } 1498 1499 queue_work(system_long_wq, &switchdev_work->work); 1500 1501 return NOTIFY_DONE; 1502 1503 err_addr_alloc: 1504 kfree(switchdev_work); 1505 return NOTIFY_BAD; 1506 } 1507 1508 static struct notifier_block adin1110_switchdev_notifier = { 1509 .notifier_call = adin1110_switchdev_event, 1510 }; 1511 1512 static void adin1110_unregister_notifiers(void *data) 1513 { 1514 unregister_switchdev_blocking_notifier(&adin1110_switchdev_blocking_notifier); 1515 unregister_switchdev_notifier(&adin1110_switchdev_notifier); 1516 unregister_netdevice_notifier(&adin1110_netdevice_nb); 1517 } 1518 1519 static int adin1110_setup_notifiers(struct adin1110_priv *priv) 1520 { 1521 struct device *dev = &priv->spidev->dev; 1522 int ret; 1523 1524 ret = register_netdevice_notifier(&adin1110_netdevice_nb); 1525 if (ret < 0) 1526 return ret; 1527 1528 ret = register_switchdev_notifier(&adin1110_switchdev_notifier); 1529 if (ret < 0) 1530 goto err_netdev; 1531 1532 ret = register_switchdev_blocking_notifier(&adin1110_switchdev_blocking_notifier); 1533 if (ret < 0) 1534 goto err_sdev; 1535 1536 return devm_add_action_or_reset(dev, adin1110_unregister_notifiers, NULL); 1537 1538 err_sdev: 1539 unregister_switchdev_notifier(&adin1110_switchdev_notifier); 1540 1541 err_netdev: 1542 unregister_netdevice_notifier(&adin1110_netdevice_nb); 1543 return ret; 1544 } 1545 1546 static int adin1110_probe_netdevs(struct adin1110_priv *priv) 1547 { 1548 struct device *dev = &priv->spidev->dev; 1549 struct adin1110_port_priv *port_priv; 1550 struct net_device *netdev; 1551 int ret; 1552 int i; 1553 1554 for (i = 0; i < priv->cfg->ports_nr; i++) { 1555 netdev = devm_alloc_etherdev(dev, sizeof(*port_priv)); 1556 if (!netdev) 1557 return -ENOMEM; 1558 1559 port_priv = netdev_priv(netdev); 1560 port_priv->netdev = netdev; 1561 port_priv->priv = priv; 1562 port_priv->cfg = priv->cfg; 1563 port_priv->nr = i; 1564 priv->ports[i] = port_priv; 1565 SET_NETDEV_DEV(netdev, dev); 1566 1567 ret = device_get_ethdev_address(dev, netdev); 1568 if (ret < 0) 1569 return ret; 1570 1571 netdev->irq = priv->spidev->irq; 1572 INIT_WORK(&port_priv->tx_work, adin1110_tx_work); 1573 INIT_WORK(&port_priv->rx_mode_work, adin1110_rx_mode_work); 1574 skb_queue_head_init(&port_priv->txq); 1575 1576 netif_carrier_off(netdev); 1577 1578 netdev->if_port = IF_PORT_10BASET; 1579 netdev->netdev_ops = &adin1110_netdev_ops; 1580 netdev->ethtool_ops = &adin1110_ethtool_ops; 1581 netdev->priv_flags |= IFF_UNICAST_FLT; 1582 netdev->features |= NETIF_F_NETNS_LOCAL; 1583 1584 port_priv->phydev = get_phy_device(priv->mii_bus, i + 1, false); 1585 if (!port_priv->phydev) { 1586 netdev_err(netdev, "Could not find PHY with device address: %d.\n", i); 1587 return -ENODEV; 1588 } 1589 1590 port_priv->phydev = phy_connect(netdev, 1591 phydev_name(port_priv->phydev), 1592 adin1110_adjust_link, 1593 PHY_INTERFACE_MODE_INTERNAL); 1594 if (IS_ERR(port_priv->phydev)) { 1595 netdev_err(netdev, "Could not connect PHY with device address: %d.\n", i); 1596 return PTR_ERR(port_priv->phydev); 1597 } 1598 1599 ret = devm_add_action_or_reset(dev, adin1110_disconnect_phy, 1600 port_priv->phydev); 1601 if (ret < 0) 1602 return ret; 1603 } 1604 1605 /* ADIN1110 INT_N pin will be used to signal the host */ 1606 ret = devm_request_threaded_irq(dev, priv->spidev->irq, NULL, 1607 adin1110_irq, 1608 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1609 dev_name(dev), priv); 1610 if (ret < 0) 1611 return ret; 1612 1613 ret = adin1110_setup_notifiers(priv); 1614 if (ret < 0) 1615 return ret; 1616 1617 for (i = 0; i < priv->cfg->ports_nr; i++) { 1618 ret = devm_register_netdev(dev, priv->ports[i]->netdev); 1619 if (ret < 0) { 1620 dev_err(dev, "Failed to register network device.\n"); 1621 return ret; 1622 } 1623 } 1624 1625 return 0; 1626 } 1627 1628 static int adin1110_probe(struct spi_device *spi) 1629 { 1630 const struct spi_device_id *dev_id = spi_get_device_id(spi); 1631 struct device *dev = &spi->dev; 1632 struct adin1110_priv *priv; 1633 int ret; 1634 1635 priv = devm_kzalloc(dev, sizeof(struct adin1110_priv), GFP_KERNEL); 1636 if (!priv) 1637 return -ENOMEM; 1638 1639 priv->spidev = spi; 1640 priv->cfg = &adin1110_cfgs[dev_id->driver_data]; 1641 spi->bits_per_word = 8; 1642 spi->mode = SPI_MODE_0; 1643 1644 mutex_init(&priv->lock); 1645 spin_lock_init(&priv->state_lock); 1646 1647 /* use of CRC on control and data transactions is pin dependent */ 1648 priv->append_crc = device_property_read_bool(dev, "adi,spi-crc"); 1649 if (priv->append_crc) 1650 crc8_populate_msb(adin1110_crc_table, 0x7); 1651 1652 ret = adin1110_check_spi(priv); 1653 if (ret < 0) { 1654 dev_err(dev, "Probe SPI Read check failed: %d\n", ret); 1655 return ret; 1656 } 1657 1658 ret = adin1110_write_reg(priv, ADIN1110_RESET, ADIN1110_SWRESET); 1659 if (ret < 0) 1660 return ret; 1661 1662 ret = adin1110_register_mdiobus(priv, dev); 1663 if (ret < 0) { 1664 dev_err(dev, "Could not register MDIO bus %d\n", ret); 1665 return ret; 1666 } 1667 1668 return adin1110_probe_netdevs(priv); 1669 } 1670 1671 static const struct of_device_id adin1110_match_table[] = { 1672 { .compatible = "adi,adin1110" }, 1673 { .compatible = "adi,adin2111" }, 1674 { } 1675 }; 1676 MODULE_DEVICE_TABLE(of, adin1110_match_table); 1677 1678 static const struct spi_device_id adin1110_spi_id[] = { 1679 { .name = "adin1110", .driver_data = ADIN1110_MAC }, 1680 { .name = "adin2111", .driver_data = ADIN2111_MAC }, 1681 { } 1682 }; 1683 1684 static struct spi_driver adin1110_driver = { 1685 .driver = { 1686 .name = "adin1110", 1687 .of_match_table = adin1110_match_table, 1688 }, 1689 .probe = adin1110_probe, 1690 .id_table = adin1110_spi_id, 1691 }; 1692 module_spi_driver(adin1110_driver); 1693 1694 MODULE_DESCRIPTION("ADIN1110 Network driver"); 1695 MODULE_AUTHOR("Alexandru Tachici <alexandru.tachici@analog.com>"); 1696 MODULE_LICENSE("Dual BSD/GPL"); 1697