1 // SPDX-License-Identifier: GPL-2.0 2 /* DSA driver for: 3 * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch 4 * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch 5 * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch 6 * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch 7 * 8 * These switches have a built-in 8051 CPU and can download and execute a 9 * firmware in this CPU. They can also be configured to use an external CPU 10 * handling the switch in a memory-mapped manner by connecting to that external 11 * CPU's memory bus. 12 * 13 * Copyright (C) 2018 Linus Wallej <linus.walleij@linaro.org> 14 * Includes portions of code from the firmware uploader by: 15 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> 16 */ 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/device.h> 20 #include <linux/iopoll.h> 21 #include <linux/of.h> 22 #include <linux/of_mdio.h> 23 #include <linux/bitops.h> 24 #include <linux/if_bridge.h> 25 #include <linux/if_vlan.h> 26 #include <linux/etherdevice.h> 27 #include <linux/gpio/consumer.h> 28 #include <linux/gpio/driver.h> 29 #include <linux/dsa/8021q.h> 30 #include <linux/random.h> 31 #include <net/dsa.h> 32 33 #include "vitesse-vsc73xx.h" 34 35 #define VSC73XX_BLOCK_MAC 0x1 /* Subblocks 0-4, 6 (CPU port) */ 36 #define VSC73XX_BLOCK_ANALYZER 0x2 /* Only subblock 0 */ 37 #define VSC73XX_BLOCK_MII 0x3 /* Subblocks 0 and 1 */ 38 #define VSC73XX_BLOCK_MEMINIT 0x3 /* Only subblock 2 */ 39 #define VSC73XX_BLOCK_CAPTURE 0x4 /* Only subblock 2 */ 40 #define VSC73XX_BLOCK_ARBITER 0x5 /* Only subblock 0 */ 41 #define VSC73XX_BLOCK_SYSTEM 0x7 /* Only subblock 0 */ 42 43 /* MII Block subblock */ 44 #define VSC73XX_BLOCK_MII_INTERNAL 0x0 /* Internal MDIO subblock */ 45 46 #define CPU_PORT 6 /* CPU port */ 47 48 /* MAC Block registers */ 49 #define VSC73XX_MAC_CFG 0x00 50 #define VSC73XX_MACHDXGAP 0x02 51 #define VSC73XX_FCCONF 0x04 52 #define VSC73XX_FCMACHI 0x08 53 #define VSC73XX_FCMACLO 0x0c 54 #define VSC73XX_MAXLEN 0x10 55 #define VSC73XX_ADVPORTM 0x19 56 #define VSC73XX_TXUPDCFG 0x24 57 #define VSC73XX_TXQ_SELECT_CFG 0x28 58 #define VSC73XX_RXOCT 0x50 59 #define VSC73XX_TXOCT 0x51 60 #define VSC73XX_C_RX0 0x52 61 #define VSC73XX_C_RX1 0x53 62 #define VSC73XX_C_RX2 0x54 63 #define VSC73XX_C_TX0 0x55 64 #define VSC73XX_C_TX1 0x56 65 #define VSC73XX_C_TX2 0x57 66 #define VSC73XX_C_CFG 0x58 67 #define VSC73XX_CAT_DROP 0x6e 68 #define VSC73XX_CAT_PR_MISC_L2 0x6f 69 #define VSC73XX_CAT_PR_USR_PRIO 0x75 70 #define VSC73XX_CAT_VLAN_MISC 0x79 71 #define VSC73XX_CAT_PORT_VLAN 0x7a 72 #define VSC73XX_Q_MISC_CONF 0xdf 73 74 /* MAC_CFG register bits */ 75 #define VSC73XX_MAC_CFG_WEXC_DIS BIT(31) 76 #define VSC73XX_MAC_CFG_PORT_RST BIT(29) 77 #define VSC73XX_MAC_CFG_TX_EN BIT(28) 78 #define VSC73XX_MAC_CFG_SEED_LOAD BIT(27) 79 #define VSC73XX_MAC_CFG_SEED_MASK GENMASK(26, 19) 80 #define VSC73XX_MAC_CFG_SEED_OFFSET 19 81 #define VSC73XX_MAC_CFG_FDX BIT(18) 82 #define VSC73XX_MAC_CFG_GIGA_MODE BIT(17) 83 #define VSC73XX_MAC_CFG_RX_EN BIT(16) 84 #define VSC73XX_MAC_CFG_VLAN_DBLAWR BIT(15) 85 #define VSC73XX_MAC_CFG_VLAN_AWR BIT(14) 86 #define VSC73XX_MAC_CFG_100_BASE_T BIT(13) /* Not in manual */ 87 #define VSC73XX_MAC_CFG_TX_IPG_MASK GENMASK(10, 6) 88 #define VSC73XX_MAC_CFG_TX_IPG_OFFSET 6 89 #define VSC73XX_MAC_CFG_TX_IPG_1000M (6 << VSC73XX_MAC_CFG_TX_IPG_OFFSET) 90 #define VSC73XX_MAC_CFG_TX_IPG_100_10M (17 << VSC73XX_MAC_CFG_TX_IPG_OFFSET) 91 #define VSC73XX_MAC_CFG_MAC_RX_RST BIT(5) 92 #define VSC73XX_MAC_CFG_MAC_TX_RST BIT(4) 93 #define VSC73XX_MAC_CFG_CLK_SEL_MASK GENMASK(2, 0) 94 #define VSC73XX_MAC_CFG_CLK_SEL_OFFSET 0 95 #define VSC73XX_MAC_CFG_CLK_SEL_1000M 1 96 #define VSC73XX_MAC_CFG_CLK_SEL_100M 2 97 #define VSC73XX_MAC_CFG_CLK_SEL_10M 3 98 #define VSC73XX_MAC_CFG_CLK_SEL_EXT 4 99 100 #define VSC73XX_MAC_CFG_1000M_F_PHY (VSC73XX_MAC_CFG_FDX | \ 101 VSC73XX_MAC_CFG_GIGA_MODE | \ 102 VSC73XX_MAC_CFG_TX_IPG_1000M | \ 103 VSC73XX_MAC_CFG_CLK_SEL_EXT) 104 #define VSC73XX_MAC_CFG_100_10M_F_PHY (VSC73XX_MAC_CFG_FDX | \ 105 VSC73XX_MAC_CFG_TX_IPG_100_10M | \ 106 VSC73XX_MAC_CFG_CLK_SEL_EXT) 107 #define VSC73XX_MAC_CFG_100_10M_H_PHY (VSC73XX_MAC_CFG_TX_IPG_100_10M | \ 108 VSC73XX_MAC_CFG_CLK_SEL_EXT) 109 #define VSC73XX_MAC_CFG_1000M_F_RGMII (VSC73XX_MAC_CFG_FDX | \ 110 VSC73XX_MAC_CFG_GIGA_MODE | \ 111 VSC73XX_MAC_CFG_TX_IPG_1000M | \ 112 VSC73XX_MAC_CFG_CLK_SEL_1000M) 113 #define VSC73XX_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \ 114 VSC73XX_MAC_CFG_MAC_RX_RST | \ 115 VSC73XX_MAC_CFG_MAC_TX_RST) 116 117 /* Flow control register bits */ 118 #define VSC73XX_FCCONF_ZERO_PAUSE_EN BIT(17) 119 #define VSC73XX_FCCONF_FLOW_CTRL_OBEY BIT(16) 120 #define VSC73XX_FCCONF_PAUSE_VAL_MASK GENMASK(15, 0) 121 122 /* ADVPORTM advanced port setup register bits */ 123 #define VSC73XX_ADVPORTM_IFG_PPM BIT(7) 124 #define VSC73XX_ADVPORTM_EXC_COL_CONT BIT(6) 125 #define VSC73XX_ADVPORTM_EXT_PORT BIT(5) 126 #define VSC73XX_ADVPORTM_INV_GTX BIT(4) 127 #define VSC73XX_ADVPORTM_ENA_GTX BIT(3) 128 #define VSC73XX_ADVPORTM_DDR_MODE BIT(2) 129 #define VSC73XX_ADVPORTM_IO_LOOPBACK BIT(1) 130 #define VSC73XX_ADVPORTM_HOST_LOOPBACK BIT(0) 131 132 /* TXUPDCFG transmit modify setup bits */ 133 #define VSC73XX_TXUPDCFG_DSCP_REWR_MODE GENMASK(20, 19) 134 #define VSC73XX_TXUPDCFG_DSCP_REWR_ENA BIT(18) 135 #define VSC73XX_TXUPDCFG_TX_INT_TO_USRPRIO_ENA BIT(17) 136 #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID GENMASK(15, 4) 137 #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA BIT(3) 138 #define VSC73XX_TXUPDCFG_TX_UPDATE_CRC_CPU_ENA BIT(1) 139 #define VSC73XX_TXUPDCFG_TX_INSERT_TAG BIT(0) 140 141 #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_SHIFT 4 142 143 /* CAT_DROP categorizer frame dropping register bits */ 144 #define VSC73XX_CAT_DROP_DROP_MC_SMAC_ENA BIT(6) 145 #define VSC73XX_CAT_DROP_FWD_CTRL_ENA BIT(4) 146 #define VSC73XX_CAT_DROP_FWD_PAUSE_ENA BIT(3) 147 #define VSC73XX_CAT_DROP_UNTAGGED_ENA BIT(2) 148 #define VSC73XX_CAT_DROP_TAGGED_ENA BIT(1) 149 #define VSC73XX_CAT_DROP_NULL_MAC_ENA BIT(0) 150 151 #define VSC73XX_Q_MISC_CONF_EXTENT_MEM BIT(31) 152 #define VSC73XX_Q_MISC_CONF_EARLY_TX_MASK GENMASK(4, 1) 153 #define VSC73XX_Q_MISC_CONF_EARLY_TX_512 (1 << 1) 154 #define VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE BIT(0) 155 156 /* CAT_VLAN_MISC categorizer VLAN miscellaneous bits */ 157 #define VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA BIT(8) 158 #define VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA BIT(7) 159 160 /* CAT_PORT_VLAN categorizer port VLAN */ 161 #define VSC73XX_CAT_PORT_VLAN_VLAN_CFI BIT(15) 162 #define VSC73XX_CAT_PORT_VLAN_VLAN_USR_PRIO GENMASK(14, 12) 163 #define VSC73XX_CAT_PORT_VLAN_VLAN_VID GENMASK(11, 0) 164 165 /* Frame analyzer block 2 registers */ 166 #define VSC73XX_STORMLIMIT 0x02 167 #define VSC73XX_ADVLEARN 0x03 168 #define VSC73XX_IFLODMSK 0x04 169 #define VSC73XX_VLANMASK 0x05 170 #define VSC73XX_MACHDATA 0x06 171 #define VSC73XX_MACLDATA 0x07 172 #define VSC73XX_ANMOVED 0x08 173 #define VSC73XX_ANAGEFIL 0x09 174 #define VSC73XX_ANEVENTS 0x0a 175 #define VSC73XX_ANCNTMASK 0x0b 176 #define VSC73XX_ANCNTVAL 0x0c 177 #define VSC73XX_LEARNMASK 0x0d 178 #define VSC73XX_UFLODMASK 0x0e 179 #define VSC73XX_MFLODMASK 0x0f 180 #define VSC73XX_RECVMASK 0x10 181 #define VSC73XX_AGGRCTRL 0x20 182 #define VSC73XX_AGGRMSKS 0x30 /* Until 0x3f */ 183 #define VSC73XX_DSTMASKS 0x40 /* Until 0x7f */ 184 #define VSC73XX_SRCMASKS 0x80 /* Until 0x87 */ 185 #define VSC73XX_CAPENAB 0xa0 186 #define VSC73XX_MACACCESS 0xb0 187 #define VSC73XX_IPMCACCESS 0xb1 188 #define VSC73XX_MACTINDX 0xc0 189 #define VSC73XX_VLANACCESS 0xd0 190 #define VSC73XX_VLANTIDX 0xe0 191 #define VSC73XX_AGENCTRL 0xf0 192 #define VSC73XX_CAPRST 0xff 193 194 #define VSC73XX_SRCMASKS_CPU_COPY BIT(27) 195 #define VSC73XX_SRCMASKS_MIRROR BIT(26) 196 #define VSC73XX_SRCMASKS_PORTS_MASK GENMASK(7, 0) 197 198 #define VSC73XX_MACACCESS_CPU_COPY BIT(14) 199 #define VSC73XX_MACACCESS_FWD_KILL BIT(13) 200 #define VSC73XX_MACACCESS_IGNORE_VLAN BIT(12) 201 #define VSC73XX_MACACCESS_AGED_FLAG BIT(11) 202 #define VSC73XX_MACACCESS_VALID BIT(10) 203 #define VSC73XX_MACACCESS_LOCKED BIT(9) 204 #define VSC73XX_MACACCESS_DEST_IDX_MASK GENMASK(8, 3) 205 #define VSC73XX_MACACCESS_CMD_MASK GENMASK(2, 0) 206 #define VSC73XX_MACACCESS_CMD_IDLE 0 207 #define VSC73XX_MACACCESS_CMD_LEARN 1 208 #define VSC73XX_MACACCESS_CMD_FORGET 2 209 #define VSC73XX_MACACCESS_CMD_AGE_TABLE 3 210 #define VSC73XX_MACACCESS_CMD_FLUSH_TABLE 4 211 #define VSC73XX_MACACCESS_CMD_CLEAR_TABLE 5 212 #define VSC73XX_MACACCESS_CMD_READ_ENTRY 6 213 #define VSC73XX_MACACCESS_CMD_WRITE_ENTRY 7 214 215 #define VSC73XX_VLANACCESS_LEARN_DISABLED BIT(30) 216 #define VSC73XX_VLANACCESS_VLAN_MIRROR BIT(29) 217 #define VSC73XX_VLANACCESS_VLAN_SRC_CHECK BIT(28) 218 #define VSC73XX_VLANACCESS_VLAN_PORT_MASK GENMASK(9, 2) 219 #define VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT 2 220 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK GENMASK(1, 0) 221 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE 0 222 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY 1 223 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY 2 224 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE 3 225 226 /* MII block 3 registers */ 227 #define VSC73XX_MII_STAT 0x0 228 #define VSC73XX_MII_CMD 0x1 229 #define VSC73XX_MII_DATA 0x2 230 #define VSC73XX_MII_MPRES 0x3 231 232 #define VSC73XX_MII_MPRES_NOPREAMBLE BIT(6) 233 #define VSC73XX_MII_MPRES_PRESCALEVAL GENMASK(5, 0) 234 #define VSC73XX_MII_PRESCALEVAL_MIN 3 /* min allowed mdio clock prescaler */ 235 236 /* Arbiter block 5 registers */ 237 #define VSC73XX_ARBEMPTY 0x0c 238 #define VSC73XX_ARBDISC 0x0e 239 #define VSC73XX_SBACKWDROP 0x12 240 #define VSC73XX_DBACKWDROP 0x13 241 #define VSC73XX_ARBBURSTPROB 0x15 242 243 /* System block 7 registers */ 244 #define VSC73XX_ICPU_SIPAD 0x01 245 #define VSC73XX_GMIIDELAY 0x05 246 #define VSC73XX_ICPU_CTRL 0x10 247 #define VSC73XX_ICPU_ADDR 0x11 248 #define VSC73XX_ICPU_SRAM 0x12 249 #define VSC73XX_HWSEM 0x13 250 #define VSC73XX_GLORESET 0x14 251 #define VSC73XX_ICPU_MBOX_VAL 0x15 252 #define VSC73XX_ICPU_MBOX_SET 0x16 253 #define VSC73XX_ICPU_MBOX_CLR 0x17 254 #define VSC73XX_CHIPID 0x18 255 #define VSC73XX_GPIO 0x34 256 257 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_NONE 0 258 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_4_NS 1 259 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_7_NS 2 260 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS 3 261 262 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_NONE (0 << 4) 263 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_4_NS (1 << 4) 264 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_7_NS (2 << 4) 265 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS (3 << 4) 266 267 #define VSC73XX_ICPU_CTRL_WATCHDOG_RST BIT(31) 268 #define VSC73XX_ICPU_CTRL_CLK_DIV_MASK GENMASK(12, 8) 269 #define VSC73XX_ICPU_CTRL_SRST_HOLD BIT(7) 270 #define VSC73XX_ICPU_CTRL_ICPU_PI_EN BIT(6) 271 #define VSC73XX_ICPU_CTRL_BOOT_EN BIT(3) 272 #define VSC73XX_ICPU_CTRL_EXT_ACC_EN BIT(2) 273 #define VSC73XX_ICPU_CTRL_CLK_EN BIT(1) 274 #define VSC73XX_ICPU_CTRL_SRST BIT(0) 275 276 #define VSC73XX_CHIPID_ID_SHIFT 12 277 #define VSC73XX_CHIPID_ID_MASK 0xffff 278 #define VSC73XX_CHIPID_REV_SHIFT 28 279 #define VSC73XX_CHIPID_REV_MASK 0xf 280 #define VSC73XX_CHIPID_ID_7385 0x7385 281 #define VSC73XX_CHIPID_ID_7388 0x7388 282 #define VSC73XX_CHIPID_ID_7395 0x7395 283 #define VSC73XX_CHIPID_ID_7398 0x7398 284 285 #define VSC73XX_GLORESET_STROBE BIT(4) 286 #define VSC73XX_GLORESET_ICPU_LOCK BIT(3) 287 #define VSC73XX_GLORESET_MEM_LOCK BIT(2) 288 #define VSC73XX_GLORESET_PHY_RESET BIT(1) 289 #define VSC73XX_GLORESET_MASTER_RESET BIT(0) 290 291 #define VSC7385_CLOCK_DELAY ((3 << 4) | 3) 292 #define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3) 293 294 #define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \ 295 VSC73XX_ICPU_CTRL_BOOT_EN | \ 296 VSC73XX_ICPU_CTRL_EXT_ACC_EN) 297 298 #define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \ 299 VSC73XX_ICPU_CTRL_BOOT_EN | \ 300 VSC73XX_ICPU_CTRL_CLK_EN | \ 301 VSC73XX_ICPU_CTRL_SRST) 302 303 #define IS_7385(a) ((a)->chipid == VSC73XX_CHIPID_ID_7385) 304 #define IS_7388(a) ((a)->chipid == VSC73XX_CHIPID_ID_7388) 305 #define IS_7395(a) ((a)->chipid == VSC73XX_CHIPID_ID_7395) 306 #define IS_7398(a) ((a)->chipid == VSC73XX_CHIPID_ID_7398) 307 #define IS_739X(a) (IS_7395(a) || IS_7398(a)) 308 309 #define VSC73XX_POLL_SLEEP_US 1000 310 #define VSC73XX_POLL_TIMEOUT_US 10000 311 312 struct vsc73xx_counter { 313 u8 counter; 314 const char *name; 315 }; 316 317 /* Counters are named according to the MIB standards where applicable. 318 * Some counters are custom, non-standard. The standard counters are 319 * named in accordance with RFC2819, RFC2021 and IEEE Std 802.3-2002 Annex 320 * 30A Counters. 321 */ 322 static const struct vsc73xx_counter vsc73xx_rx_counters[] = { 323 { 0, "RxEtherStatsPkts" }, 324 { 1, "RxBroadcast+MulticastPkts" }, /* non-standard counter */ 325 { 2, "RxTotalErrorPackets" }, /* non-standard counter */ 326 { 3, "RxEtherStatsBroadcastPkts" }, 327 { 4, "RxEtherStatsMulticastPkts" }, 328 { 5, "RxEtherStatsPkts64Octets" }, 329 { 6, "RxEtherStatsPkts65to127Octets" }, 330 { 7, "RxEtherStatsPkts128to255Octets" }, 331 { 8, "RxEtherStatsPkts256to511Octets" }, 332 { 9, "RxEtherStatsPkts512to1023Octets" }, 333 { 10, "RxEtherStatsPkts1024to1518Octets" }, 334 { 11, "RxJumboFrames" }, /* non-standard counter */ 335 { 12, "RxaPauseMACControlFramesTransmitted" }, 336 { 13, "RxFIFODrops" }, /* non-standard counter */ 337 { 14, "RxBackwardDrops" }, /* non-standard counter */ 338 { 15, "RxClassifierDrops" }, /* non-standard counter */ 339 { 16, "RxEtherStatsCRCAlignErrors" }, 340 { 17, "RxEtherStatsUndersizePkts" }, 341 { 18, "RxEtherStatsOversizePkts" }, 342 { 19, "RxEtherStatsFragments" }, 343 { 20, "RxEtherStatsJabbers" }, 344 { 21, "RxaMACControlFramesReceived" }, 345 /* 22-24 are undefined */ 346 { 25, "RxaFramesReceivedOK" }, 347 { 26, "RxQoSClass0" }, /* non-standard counter */ 348 { 27, "RxQoSClass1" }, /* non-standard counter */ 349 { 28, "RxQoSClass2" }, /* non-standard counter */ 350 { 29, "RxQoSClass3" }, /* non-standard counter */ 351 }; 352 353 static const struct vsc73xx_counter vsc73xx_tx_counters[] = { 354 { 0, "TxEtherStatsPkts" }, 355 { 1, "TxBroadcast+MulticastPkts" }, /* non-standard counter */ 356 { 2, "TxTotalErrorPackets" }, /* non-standard counter */ 357 { 3, "TxEtherStatsBroadcastPkts" }, 358 { 4, "TxEtherStatsMulticastPkts" }, 359 { 5, "TxEtherStatsPkts64Octets" }, 360 { 6, "TxEtherStatsPkts65to127Octets" }, 361 { 7, "TxEtherStatsPkts128to255Octets" }, 362 { 8, "TxEtherStatsPkts256to511Octets" }, 363 { 9, "TxEtherStatsPkts512to1023Octets" }, 364 { 10, "TxEtherStatsPkts1024to1518Octets" }, 365 { 11, "TxJumboFrames" }, /* non-standard counter */ 366 { 12, "TxaPauseMACControlFramesTransmitted" }, 367 { 13, "TxFIFODrops" }, /* non-standard counter */ 368 { 14, "TxDrops" }, /* non-standard counter */ 369 { 15, "TxEtherStatsCollisions" }, 370 { 16, "TxEtherStatsCRCAlignErrors" }, 371 { 17, "TxEtherStatsUndersizePkts" }, 372 { 18, "TxEtherStatsOversizePkts" }, 373 { 19, "TxEtherStatsFragments" }, 374 { 20, "TxEtherStatsJabbers" }, 375 /* 21-24 are undefined */ 376 { 25, "TxaFramesReceivedOK" }, 377 { 26, "TxQoSClass0" }, /* non-standard counter */ 378 { 27, "TxQoSClass1" }, /* non-standard counter */ 379 { 28, "TxQoSClass2" }, /* non-standard counter */ 380 { 29, "TxQoSClass3" }, /* non-standard counter */ 381 }; 382 383 struct vsc73xx_vlan_summary { 384 size_t num_tagged; 385 size_t num_untagged; 386 }; 387 388 enum vsc73xx_port_vlan_conf { 389 VSC73XX_VLAN_FILTER, 390 VSC73XX_VLAN_FILTER_UNTAG_ALL, 391 VSC73XX_VLAN_IGNORE, 392 }; 393 394 int vsc73xx_is_addr_valid(u8 block, u8 subblock) 395 { 396 switch (block) { 397 case VSC73XX_BLOCK_MAC: 398 switch (subblock) { 399 case 0 ... 4: 400 case 6: 401 return 1; 402 } 403 break; 404 405 case VSC73XX_BLOCK_ANALYZER: 406 case VSC73XX_BLOCK_SYSTEM: 407 switch (subblock) { 408 case 0: 409 return 1; 410 } 411 break; 412 413 case VSC73XX_BLOCK_MII: 414 case VSC73XX_BLOCK_CAPTURE: 415 case VSC73XX_BLOCK_ARBITER: 416 switch (subblock) { 417 case 0 ... 1: 418 return 1; 419 } 420 break; 421 } 422 423 return 0; 424 } 425 EXPORT_SYMBOL(vsc73xx_is_addr_valid); 426 427 static int vsc73xx_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, 428 u32 *val) 429 { 430 return vsc->ops->read(vsc, block, subblock, reg, val); 431 } 432 433 static int vsc73xx_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, 434 u32 val) 435 { 436 return vsc->ops->write(vsc, block, subblock, reg, val); 437 } 438 439 static int vsc73xx_update_bits(struct vsc73xx *vsc, u8 block, u8 subblock, 440 u8 reg, u32 mask, u32 val) 441 { 442 u32 tmp, orig; 443 int ret; 444 445 /* Same read-modify-write algorithm as e.g. regmap */ 446 ret = vsc73xx_read(vsc, block, subblock, reg, &orig); 447 if (ret) 448 return ret; 449 tmp = orig & ~mask; 450 tmp |= val & mask; 451 return vsc73xx_write(vsc, block, subblock, reg, tmp); 452 } 453 454 static int vsc73xx_detect(struct vsc73xx *vsc) 455 { 456 bool icpu_si_boot_en; 457 bool icpu_pi_en; 458 u32 val; 459 u32 rev; 460 int ret; 461 u32 id; 462 463 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 464 VSC73XX_ICPU_MBOX_VAL, &val); 465 if (ret) { 466 dev_err(vsc->dev, "unable to read mailbox (%d)\n", ret); 467 return ret; 468 } 469 470 if (val == 0xffffffff) { 471 dev_info(vsc->dev, "chip seems dead.\n"); 472 return -EAGAIN; 473 } 474 475 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 476 VSC73XX_CHIPID, &val); 477 if (ret) { 478 dev_err(vsc->dev, "unable to read chip id (%d)\n", ret); 479 return ret; 480 } 481 482 id = (val >> VSC73XX_CHIPID_ID_SHIFT) & 483 VSC73XX_CHIPID_ID_MASK; 484 switch (id) { 485 case VSC73XX_CHIPID_ID_7385: 486 case VSC73XX_CHIPID_ID_7388: 487 case VSC73XX_CHIPID_ID_7395: 488 case VSC73XX_CHIPID_ID_7398: 489 break; 490 default: 491 dev_err(vsc->dev, "unsupported chip, id=%04x\n", id); 492 return -ENODEV; 493 } 494 495 vsc->chipid = id; 496 rev = (val >> VSC73XX_CHIPID_REV_SHIFT) & 497 VSC73XX_CHIPID_REV_MASK; 498 dev_info(vsc->dev, "VSC%04X (rev: %d) switch found\n", id, rev); 499 500 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 501 VSC73XX_ICPU_CTRL, &val); 502 if (ret) { 503 dev_err(vsc->dev, "unable to read iCPU control\n"); 504 return ret; 505 } 506 507 /* The iCPU can always be used but can boot in different ways. 508 * If it is initially disabled and has no external memory, 509 * we are in control and can do whatever we like, else we 510 * are probably in trouble (we need some way to communicate 511 * with the running firmware) so we bail out for now. 512 */ 513 icpu_pi_en = !!(val & VSC73XX_ICPU_CTRL_ICPU_PI_EN); 514 icpu_si_boot_en = !!(val & VSC73XX_ICPU_CTRL_BOOT_EN); 515 if (icpu_si_boot_en && icpu_pi_en) { 516 dev_err(vsc->dev, 517 "iCPU enabled boots from SI, has external memory\n"); 518 dev_err(vsc->dev, "no idea how to deal with this\n"); 519 return -ENODEV; 520 } 521 if (icpu_si_boot_en && !icpu_pi_en) { 522 dev_err(vsc->dev, 523 "iCPU enabled boots from PI/SI, no external memory\n"); 524 return -EAGAIN; 525 } 526 if (!icpu_si_boot_en && icpu_pi_en) { 527 dev_err(vsc->dev, 528 "iCPU enabled, boots from PI external memory\n"); 529 dev_err(vsc->dev, "no idea how to deal with this\n"); 530 return -ENODEV; 531 } 532 /* !icpu_si_boot_en && !cpu_pi_en */ 533 dev_info(vsc->dev, "iCPU disabled, no external memory\n"); 534 535 return 0; 536 } 537 538 static int vsc73xx_phy_read(struct dsa_switch *ds, int phy, int regnum) 539 { 540 struct vsc73xx *vsc = ds->priv; 541 u32 cmd; 542 u32 val; 543 int ret; 544 545 /* Setting bit 26 means "read" */ 546 cmd = BIT(26) | (phy << 21) | (regnum << 16); 547 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd); 548 if (ret) 549 return ret; 550 msleep(2); 551 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, 0, 2, &val); 552 if (ret) 553 return ret; 554 if (val & BIT(16)) { 555 dev_err(vsc->dev, "reading reg %02x from phy%d failed\n", 556 regnum, phy); 557 return -EIO; 558 } 559 val &= 0xFFFFU; 560 561 dev_dbg(vsc->dev, "read reg %02x from phy%d = %04x\n", 562 regnum, phy, val); 563 564 return val; 565 } 566 567 static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum, 568 u16 val) 569 { 570 struct vsc73xx *vsc = ds->priv; 571 u32 cmd; 572 int ret; 573 574 /* It was found through tedious experiments that this router 575 * chip really hates to have it's PHYs reset. They 576 * never recover if that happens: autonegotiation stops 577 * working after a reset. Just filter out this command. 578 * (Resetting the whole chip is OK.) 579 */ 580 if (regnum == 0 && (val & BIT(15))) { 581 dev_info(vsc->dev, "reset PHY - disallowed\n"); 582 return 0; 583 } 584 585 cmd = (phy << 21) | (regnum << 16); 586 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd); 587 if (ret) 588 return ret; 589 590 dev_dbg(vsc->dev, "write %04x to reg %02x in phy%d\n", 591 val, regnum, phy); 592 return 0; 593 } 594 595 static enum dsa_tag_protocol vsc73xx_get_tag_protocol(struct dsa_switch *ds, 596 int port, 597 enum dsa_tag_protocol mp) 598 { 599 /* The switch internally uses a 8 byte header with length, 600 * source port, tag, LPA and priority. This is supposedly 601 * only accessible when operating the switch using the internal 602 * CPU or with an external CPU mapping the device in, but not 603 * when operating the switch over SPI and putting frames in/out 604 * on port 6 (the CPU port). So far we must assume that we 605 * cannot access the tag. (See "Internal frame header" section 606 * 3.9.1 in the manual.) 607 */ 608 return DSA_TAG_PROTO_VSC73XX_8021Q; 609 } 610 611 static int vsc73xx_wait_for_vlan_table_cmd(struct vsc73xx *vsc) 612 { 613 int ret, err; 614 u32 val; 615 616 ret = read_poll_timeout(vsc73xx_read, err, 617 err < 0 || 618 ((val & VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK) == 619 VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE), 620 VSC73XX_POLL_SLEEP_US, VSC73XX_POLL_TIMEOUT_US, 621 false, vsc, VSC73XX_BLOCK_ANALYZER, 622 0, VSC73XX_VLANACCESS, &val); 623 if (ret) 624 return ret; 625 return err; 626 } 627 628 static int 629 vsc73xx_read_vlan_table_entry(struct vsc73xx *vsc, u16 vid, u8 *portmap) 630 { 631 u32 val; 632 int ret; 633 634 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANTIDX, vid); 635 636 ret = vsc73xx_wait_for_vlan_table_cmd(vsc); 637 if (ret) 638 return ret; 639 640 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS, 641 VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK, 642 VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY); 643 644 ret = vsc73xx_wait_for_vlan_table_cmd(vsc); 645 if (ret) 646 return ret; 647 648 vsc73xx_read(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS, &val); 649 *portmap = (val & VSC73XX_VLANACCESS_VLAN_PORT_MASK) >> 650 VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT; 651 652 return 0; 653 } 654 655 static int 656 vsc73xx_write_vlan_table_entry(struct vsc73xx *vsc, u16 vid, u8 portmap) 657 { 658 int ret; 659 660 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANTIDX, vid); 661 662 ret = vsc73xx_wait_for_vlan_table_cmd(vsc); 663 if (ret) 664 return ret; 665 666 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS, 667 VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK | 668 VSC73XX_VLANACCESS_VLAN_SRC_CHECK | 669 VSC73XX_VLANACCESS_VLAN_PORT_MASK, 670 VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY | 671 VSC73XX_VLANACCESS_VLAN_SRC_CHECK | 672 (portmap << VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT)); 673 674 return vsc73xx_wait_for_vlan_table_cmd(vsc); 675 } 676 677 static int 678 vsc73xx_update_vlan_table(struct vsc73xx *vsc, int port, u16 vid, bool set) 679 { 680 u8 portmap; 681 int ret; 682 683 ret = vsc73xx_read_vlan_table_entry(vsc, vid, &portmap); 684 if (ret) 685 return ret; 686 687 if (set) 688 portmap |= BIT(port); 689 else 690 portmap &= ~BIT(port); 691 692 return vsc73xx_write_vlan_table_entry(vsc, vid, portmap); 693 } 694 695 static int vsc73xx_configure_rgmii_port_delay(struct dsa_switch *ds) 696 { 697 /* Keep 2.0 ns delay for backward complatibility */ 698 u32 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS; 699 u32 rx_delay = VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS; 700 struct dsa_port *dp = dsa_to_port(ds, CPU_PORT); 701 struct device_node *port_dn = dp->dn; 702 struct vsc73xx *vsc = ds->priv; 703 u32 delay; 704 705 if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay)) { 706 switch (delay) { 707 case 0: 708 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_NONE; 709 break; 710 case 1400: 711 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_4_NS; 712 break; 713 case 1700: 714 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_7_NS; 715 break; 716 case 2000: 717 break; 718 default: 719 dev_err(vsc->dev, 720 "Unsupported RGMII Transmit Clock Delay\n"); 721 return -EINVAL; 722 } 723 } else { 724 dev_dbg(vsc->dev, 725 "RGMII Transmit Clock Delay isn't configured, set to 2.0 ns\n"); 726 } 727 728 if (!of_property_read_u32(port_dn, "rx-internal-delay-ps", &delay)) { 729 switch (delay) { 730 case 0: 731 rx_delay = VSC73XX_GMIIDELAY_GMII0_RXDELAY_NONE; 732 break; 733 case 1400: 734 rx_delay = VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_4_NS; 735 break; 736 case 1700: 737 rx_delay = VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_7_NS; 738 break; 739 case 2000: 740 break; 741 default: 742 dev_err(vsc->dev, 743 "Unsupported RGMII Receive Clock Delay value\n"); 744 return -EINVAL; 745 } 746 } else { 747 dev_dbg(vsc->dev, 748 "RGMII Receive Clock Delay isn't configured, set to 2.0 ns\n"); 749 } 750 751 /* MII delay, set both GTX and RX delay */ 752 return vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GMIIDELAY, 753 tx_delay | rx_delay); 754 } 755 756 static int vsc73xx_setup(struct dsa_switch *ds) 757 { 758 struct vsc73xx *vsc = ds->priv; 759 int i, ret, val; 760 761 dev_info(vsc->dev, "set up the switch\n"); 762 763 ds->untag_bridge_pvid = true; 764 ds->max_num_bridges = DSA_TAG_8021Q_MAX_NUM_BRIDGES; 765 766 /* Issue RESET */ 767 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET, 768 VSC73XX_GLORESET_MASTER_RESET); 769 usleep_range(125, 200); 770 771 /* Initialize memory, initialize RAM bank 0..15 except 6 and 7 772 * This sequence appears in the 773 * VSC7385 SparX-G5 datasheet section 6.6.1 774 * VSC7395 SparX-G5e datasheet section 6.6.1 775 * "initialization sequence". 776 * No explanation is given to the 0x1010400 magic number. 777 */ 778 for (i = 0; i <= 15; i++) { 779 if (i != 6 && i != 7) { 780 vsc73xx_write(vsc, VSC73XX_BLOCK_MEMINIT, 781 2, 782 0, 0x1010400 + i); 783 mdelay(1); 784 } 785 } 786 mdelay(30); 787 788 /* Clear MAC table */ 789 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, 790 VSC73XX_MACACCESS, 791 VSC73XX_MACACCESS_CMD_CLEAR_TABLE); 792 793 /* Set VLAN table to default values */ 794 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, 795 VSC73XX_VLANACCESS, 796 VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE); 797 798 msleep(40); 799 800 /* Use 20KiB buffers on all ports on VSC7395 801 * The VSC7385 has 16KiB buffers and that is the 802 * default if we don't set this up explicitly. 803 * Port "31" is "all ports". 804 */ 805 if (IS_739X(vsc)) 806 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 0x1f, 807 VSC73XX_Q_MISC_CONF, 808 VSC73XX_Q_MISC_CONF_EXTENT_MEM); 809 810 /* Put all ports into reset until enabled */ 811 for (i = 0; i < 7; i++) { 812 if (i == 5) 813 continue; 814 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 4, 815 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET); 816 } 817 818 /* Configure RGMII delay */ 819 ret = vsc73xx_configure_rgmii_port_delay(ds); 820 if (ret) 821 return ret; 822 823 /* Ingess VLAN reception mask (table 145) */ 824 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANMASK, 825 0xff); 826 /* IP multicast flood mask (table 144) */ 827 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_IFLODMSK, 828 0xff); 829 830 mdelay(50); 831 832 /* Disable preamble and use maximum allowed clock for the internal 833 * mdio bus, used for communication with internal PHYs only. 834 */ 835 val = VSC73XX_MII_MPRES_NOPREAMBLE | 836 FIELD_PREP(VSC73XX_MII_MPRES_PRESCALEVAL, 837 VSC73XX_MII_PRESCALEVAL_MIN); 838 vsc73xx_write(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL, 839 VSC73XX_MII_MPRES, val); 840 841 /* Release reset from the internal PHYs */ 842 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET, 843 VSC73XX_GLORESET_PHY_RESET); 844 845 udelay(4); 846 847 /* Clear VLAN table */ 848 for (i = 0; i < VLAN_N_VID; i++) 849 vsc73xx_write_vlan_table_entry(vsc, i, 0); 850 851 INIT_LIST_HEAD(&vsc->vlans); 852 853 rtnl_lock(); 854 ret = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q)); 855 rtnl_unlock(); 856 857 return ret; 858 } 859 860 static void vsc73xx_teardown(struct dsa_switch *ds) 861 { 862 rtnl_lock(); 863 dsa_tag_8021q_unregister(ds); 864 rtnl_unlock(); 865 } 866 867 static void vsc73xx_init_port(struct vsc73xx *vsc, int port) 868 { 869 u32 val; 870 871 /* MAC configure, first reset the port and then write defaults */ 872 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 873 port, 874 VSC73XX_MAC_CFG, 875 VSC73XX_MAC_CFG_RESET); 876 877 /* Take up the port in 1Gbit mode by default, this will be 878 * augmented after auto-negotiation on the PHY-facing 879 * ports. 880 */ 881 if (port == CPU_PORT) 882 val = VSC73XX_MAC_CFG_1000M_F_RGMII; 883 else 884 val = VSC73XX_MAC_CFG_1000M_F_PHY; 885 886 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 887 port, 888 VSC73XX_MAC_CFG, 889 val | 890 VSC73XX_MAC_CFG_TX_EN | 891 VSC73XX_MAC_CFG_RX_EN); 892 893 /* Flow control for the CPU port: 894 * Use a zero delay pause frame when pause condition is left 895 * Obey pause control frames 896 */ 897 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 898 port, 899 VSC73XX_FCCONF, 900 VSC73XX_FCCONF_ZERO_PAUSE_EN | 901 VSC73XX_FCCONF_FLOW_CTRL_OBEY); 902 903 /* Issue pause control frames on PHY facing ports. 904 * Allow early initiation of MAC transmission if the amount 905 * of egress data is below 512 bytes on CPU port. 906 * FIXME: enable 20KiB buffers? 907 */ 908 if (port == CPU_PORT) 909 val = VSC73XX_Q_MISC_CONF_EARLY_TX_512; 910 else 911 val = VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE; 912 val |= VSC73XX_Q_MISC_CONF_EXTENT_MEM; 913 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 914 port, 915 VSC73XX_Q_MISC_CONF, 916 val); 917 918 /* Flow control MAC: a MAC address used in flow control frames */ 919 val = (vsc->addr[5] << 16) | (vsc->addr[4] << 8) | (vsc->addr[3]); 920 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 921 port, 922 VSC73XX_FCMACHI, 923 val); 924 val = (vsc->addr[2] << 16) | (vsc->addr[1] << 8) | (vsc->addr[0]); 925 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 926 port, 927 VSC73XX_FCMACLO, 928 val); 929 930 /* Tell the categorizer to forward pause frames, not control 931 * frame. Do not drop anything. 932 */ 933 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 934 port, 935 VSC73XX_CAT_DROP, 936 VSC73XX_CAT_DROP_FWD_PAUSE_ENA); 937 938 /* Clear all counters */ 939 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 940 port, VSC73XX_C_RX0, 0); 941 } 942 943 static void vsc73xx_reset_port(struct vsc73xx *vsc, int port, u32 initval) 944 { 945 int ret, err; 946 u32 val; 947 948 /* Disable RX on this port */ 949 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 950 VSC73XX_MAC_CFG, 951 VSC73XX_MAC_CFG_RX_EN, 0); 952 953 /* Discard packets */ 954 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 955 VSC73XX_ARBDISC, BIT(port), BIT(port)); 956 957 /* Wait until queue is empty */ 958 ret = read_poll_timeout(vsc73xx_read, err, 959 err < 0 || (val & BIT(port)), 960 VSC73XX_POLL_SLEEP_US, 961 VSC73XX_POLL_TIMEOUT_US, false, 962 vsc, VSC73XX_BLOCK_ARBITER, 0, 963 VSC73XX_ARBEMPTY, &val); 964 if (ret) 965 dev_err(vsc->dev, 966 "timeout waiting for block arbiter\n"); 967 else if (err < 0) 968 dev_err(vsc->dev, "error reading arbiter\n"); 969 970 /* Put this port into reset */ 971 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, 972 VSC73XX_MAC_CFG_RESET | initval); 973 } 974 975 static void vsc73xx_mac_config(struct phylink_config *config, unsigned int mode, 976 const struct phylink_link_state *state) 977 { 978 struct dsa_port *dp = dsa_phylink_to_port(config); 979 struct vsc73xx *vsc = dp->ds->priv; 980 int port = dp->index; 981 982 /* Special handling of the CPU-facing port */ 983 if (port == CPU_PORT) { 984 /* Other ports are already initialized but not this one */ 985 vsc73xx_init_port(vsc, CPU_PORT); 986 /* Select the external port for this interface (EXT_PORT) 987 * Enable the GMII GTX external clock 988 * Use double data rate (DDR mode) 989 */ 990 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 991 CPU_PORT, 992 VSC73XX_ADVPORTM, 993 VSC73XX_ADVPORTM_EXT_PORT | 994 VSC73XX_ADVPORTM_ENA_GTX | 995 VSC73XX_ADVPORTM_DDR_MODE); 996 } 997 } 998 999 static void vsc73xx_mac_link_down(struct phylink_config *config, 1000 unsigned int mode, phy_interface_t interface) 1001 { 1002 struct dsa_port *dp = dsa_phylink_to_port(config); 1003 struct vsc73xx *vsc = dp->ds->priv; 1004 int port = dp->index; 1005 1006 /* This routine is described in the datasheet (below ARBDISC register 1007 * description) 1008 */ 1009 vsc73xx_reset_port(vsc, port, 0); 1010 1011 /* Allow backward dropping of frames from this port */ 1012 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 1013 VSC73XX_SBACKWDROP, BIT(port), BIT(port)); 1014 } 1015 1016 static void vsc73xx_mac_link_up(struct phylink_config *config, 1017 struct phy_device *phy, unsigned int mode, 1018 phy_interface_t interface, int speed, 1019 int duplex, bool tx_pause, bool rx_pause) 1020 { 1021 struct dsa_port *dp = dsa_phylink_to_port(config); 1022 struct vsc73xx *vsc = dp->ds->priv; 1023 int port = dp->index; 1024 u32 val; 1025 u8 seed; 1026 1027 if (speed == SPEED_1000) 1028 val = VSC73XX_MAC_CFG_GIGA_MODE | VSC73XX_MAC_CFG_TX_IPG_1000M; 1029 else 1030 val = VSC73XX_MAC_CFG_TX_IPG_100_10M; 1031 1032 if (phy_interface_mode_is_rgmii(interface)) 1033 val |= VSC73XX_MAC_CFG_CLK_SEL_1000M; 1034 else 1035 val |= VSC73XX_MAC_CFG_CLK_SEL_EXT; 1036 1037 if (duplex == DUPLEX_FULL) 1038 val |= VSC73XX_MAC_CFG_FDX; 1039 1040 /* This routine is described in the datasheet (below ARBDISC register 1041 * description) 1042 */ 1043 vsc73xx_reset_port(vsc, port, val); 1044 1045 /* Seed the port randomness with randomness */ 1046 get_random_bytes(&seed, 1); 1047 val |= seed << VSC73XX_MAC_CFG_SEED_OFFSET; 1048 val |= VSC73XX_MAC_CFG_SEED_LOAD; 1049 val |= VSC73XX_MAC_CFG_WEXC_DIS; 1050 1051 /* Those bits are responsible for MTU only. Kernel takes care about MTU, 1052 * let's enable +8 bytes frame length unconditionally. 1053 */ 1054 val |= VSC73XX_MAC_CFG_VLAN_AWR | VSC73XX_MAC_CFG_VLAN_DBLAWR; 1055 1056 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val); 1057 1058 /* Flow control for the PHY facing ports: 1059 * Use a zero delay pause frame when pause condition is left 1060 * Obey pause control frames 1061 * When generating pause frames, use 0xff as pause value 1062 */ 1063 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_FCCONF, 1064 VSC73XX_FCCONF_ZERO_PAUSE_EN | 1065 VSC73XX_FCCONF_FLOW_CTRL_OBEY | 1066 0xff); 1067 1068 /* Accept packets again */ 1069 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 1070 VSC73XX_ARBDISC, BIT(port), 0); 1071 1072 /* Disallow backward dropping of frames from this port */ 1073 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 1074 VSC73XX_SBACKWDROP, BIT(port), 0); 1075 1076 /* Enable TX, RX, deassert reset, stop loading seed */ 1077 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1078 VSC73XX_MAC_CFG, 1079 VSC73XX_MAC_CFG_RESET | VSC73XX_MAC_CFG_SEED_LOAD | 1080 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN, 1081 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN); 1082 } 1083 1084 static bool vsc73xx_tag_8021q_active(struct dsa_port *dp) 1085 { 1086 return !dsa_port_is_vlan_filtering(dp); 1087 } 1088 1089 static struct vsc73xx_bridge_vlan * 1090 vsc73xx_bridge_vlan_find(struct vsc73xx *vsc, u16 vid) 1091 { 1092 struct vsc73xx_bridge_vlan *vlan; 1093 1094 list_for_each_entry(vlan, &vsc->vlans, list) 1095 if (vlan->vid == vid) 1096 return vlan; 1097 1098 return NULL; 1099 } 1100 1101 static void 1102 vsc73xx_bridge_vlan_remove_port(struct vsc73xx_bridge_vlan *vsc73xx_vlan, 1103 int port) 1104 { 1105 vsc73xx_vlan->portmask &= ~BIT(port); 1106 1107 if (vsc73xx_vlan->portmask) 1108 return; 1109 1110 list_del(&vsc73xx_vlan->list); 1111 kfree(vsc73xx_vlan); 1112 } 1113 1114 static void vsc73xx_bridge_vlan_summary(struct vsc73xx *vsc, int port, 1115 struct vsc73xx_vlan_summary *summary, 1116 u16 ignored_vid) 1117 { 1118 size_t num_tagged = 0, num_untagged = 0; 1119 struct vsc73xx_bridge_vlan *vlan; 1120 1121 list_for_each_entry(vlan, &vsc->vlans, list) { 1122 if (!(vlan->portmask & BIT(port)) || vlan->vid == ignored_vid) 1123 continue; 1124 1125 if (vlan->untagged & BIT(port)) 1126 num_untagged++; 1127 else 1128 num_tagged++; 1129 } 1130 1131 summary->num_untagged = num_untagged; 1132 summary->num_tagged = num_tagged; 1133 } 1134 1135 static u16 vsc73xx_find_first_vlan_untagged(struct vsc73xx *vsc, int port) 1136 { 1137 struct vsc73xx_bridge_vlan *vlan; 1138 1139 list_for_each_entry(vlan, &vsc->vlans, list) 1140 if ((vlan->portmask & BIT(port)) && 1141 (vlan->untagged & BIT(port))) 1142 return vlan->vid; 1143 1144 return VLAN_N_VID; 1145 } 1146 1147 static int vsc73xx_set_vlan_conf(struct vsc73xx *vsc, int port, 1148 enum vsc73xx_port_vlan_conf port_vlan_conf) 1149 { 1150 u32 val = 0; 1151 int ret; 1152 1153 if (port_vlan_conf == VSC73XX_VLAN_IGNORE) 1154 val = VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA | 1155 VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA; 1156 1157 ret = vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1158 VSC73XX_CAT_VLAN_MISC, 1159 VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA | 1160 VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA, val); 1161 if (ret) 1162 return ret; 1163 1164 val = (port_vlan_conf == VSC73XX_VLAN_FILTER) ? 1165 VSC73XX_TXUPDCFG_TX_INSERT_TAG : 0; 1166 1167 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1168 VSC73XX_TXUPDCFG, 1169 VSC73XX_TXUPDCFG_TX_INSERT_TAG, val); 1170 } 1171 1172 /** 1173 * vsc73xx_vlan_commit_conf - Update VLAN configuration of a port 1174 * @vsc: Switch private data structure 1175 * @port: Port index on which to operate 1176 * 1177 * Update the VLAN behavior of a port to make sure that when it is under 1178 * a VLAN filtering bridge, the port is either filtering with tag 1179 * preservation, or filtering with all VLANs egress-untagged. Otherwise, 1180 * the port ignores VLAN tags from packets and applies the port-based 1181 * VID. 1182 * 1183 * Must be called when changes are made to: 1184 * - the bridge VLAN filtering state of the port 1185 * - the number or attributes of VLANs from the bridge VLAN table, 1186 * while the port is currently VLAN-aware 1187 * 1188 * Return: 0 on success, or negative errno on error. 1189 */ 1190 static int vsc73xx_vlan_commit_conf(struct vsc73xx *vsc, int port) 1191 { 1192 enum vsc73xx_port_vlan_conf port_vlan_conf = VSC73XX_VLAN_IGNORE; 1193 struct dsa_port *dp = dsa_to_port(vsc->ds, port); 1194 1195 if (port == CPU_PORT) { 1196 port_vlan_conf = VSC73XX_VLAN_FILTER; 1197 } else if (dsa_port_is_vlan_filtering(dp)) { 1198 struct vsc73xx_vlan_summary summary; 1199 1200 port_vlan_conf = VSC73XX_VLAN_FILTER; 1201 1202 vsc73xx_bridge_vlan_summary(vsc, port, &summary, VLAN_N_VID); 1203 if (summary.num_tagged == 0) 1204 port_vlan_conf = VSC73XX_VLAN_FILTER_UNTAG_ALL; 1205 } 1206 1207 return vsc73xx_set_vlan_conf(vsc, port, port_vlan_conf); 1208 } 1209 1210 static int 1211 vsc73xx_vlan_change_untagged(struct vsc73xx *vsc, int port, u16 vid, bool set) 1212 { 1213 u32 val = 0; 1214 1215 if (set) 1216 val = VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA | 1217 ((vid << VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_SHIFT) & 1218 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID); 1219 1220 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1221 VSC73XX_TXUPDCFG, 1222 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA | 1223 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID, val); 1224 } 1225 1226 /** 1227 * vsc73xx_vlan_commit_untagged - Update native VLAN of a port 1228 * @vsc: Switch private data structure 1229 * @port: Port index on which to operate 1230 * 1231 * Update the native VLAN of a port (the one VLAN which is transmitted 1232 * as egress-tagged on a trunk port) when port is in VLAN filtering mode and 1233 * only one untagged vid is configured. 1234 * In other cases no need to configure it because switch can untag all vlans on 1235 * the port. 1236 * 1237 * Return: 0 on success, or negative errno on error. 1238 */ 1239 static int vsc73xx_vlan_commit_untagged(struct vsc73xx *vsc, int port) 1240 { 1241 struct dsa_port *dp = dsa_to_port(vsc->ds, port); 1242 struct vsc73xx_vlan_summary summary; 1243 u16 vid = 0; 1244 bool valid; 1245 1246 if (!dsa_port_is_vlan_filtering(dp)) 1247 /* Port is configured to untag all vlans in that case. 1248 * No need to commit untagged config change. 1249 */ 1250 return 0; 1251 1252 vsc73xx_bridge_vlan_summary(vsc, port, &summary, VLAN_N_VID); 1253 1254 if (summary.num_untagged > 1) 1255 /* Port must untag all vlans in that case. 1256 * No need to commit untagged config change. 1257 */ 1258 return 0; 1259 1260 valid = (summary.num_untagged == 1); 1261 if (valid) 1262 vid = vsc73xx_find_first_vlan_untagged(vsc, port); 1263 1264 return vsc73xx_vlan_change_untagged(vsc, port, vid, valid); 1265 } 1266 1267 static int 1268 vsc73xx_vlan_change_pvid(struct vsc73xx *vsc, int port, u16 vid, bool set) 1269 { 1270 u32 val = 0; 1271 int ret; 1272 1273 val = set ? 0 : VSC73XX_CAT_DROP_UNTAGGED_ENA; 1274 1275 ret = vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1276 VSC73XX_CAT_DROP, 1277 VSC73XX_CAT_DROP_UNTAGGED_ENA, val); 1278 if (!set || ret) 1279 return ret; 1280 1281 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1282 VSC73XX_CAT_PORT_VLAN, 1283 VSC73XX_CAT_PORT_VLAN_VLAN_VID, 1284 vid & VSC73XX_CAT_PORT_VLAN_VLAN_VID); 1285 } 1286 1287 /** 1288 * vsc73xx_vlan_commit_pvid - Update port-based default VLAN of a port 1289 * @vsc: Switch private data structure 1290 * @port: Port index on which to operate 1291 * 1292 * Update the PVID of a port so that it follows either the bridge PVID 1293 * configuration, when the bridge is currently VLAN-aware, or the PVID 1294 * from tag_8021q, when the port is standalone or under a VLAN-unaware 1295 * bridge. A port with no PVID drops all untagged and VID 0 tagged 1296 * traffic. 1297 * 1298 * Must be called when changes are made to: 1299 * - the bridge VLAN filtering state of the port 1300 * - the number or attributes of VLANs from the bridge VLAN table, 1301 * while the port is currently VLAN-aware 1302 * 1303 * Return: 0 on success, or negative errno on error. 1304 */ 1305 static int vsc73xx_vlan_commit_pvid(struct vsc73xx *vsc, int port) 1306 { 1307 struct vsc73xx_portinfo *portinfo = &vsc->portinfo[port]; 1308 bool valid = portinfo->pvid_tag_8021q_configured; 1309 struct dsa_port *dp = dsa_to_port(vsc->ds, port); 1310 u16 vid = portinfo->pvid_tag_8021q; 1311 1312 if (dsa_port_is_vlan_filtering(dp)) { 1313 vid = portinfo->pvid_vlan_filtering; 1314 valid = portinfo->pvid_vlan_filtering_configured; 1315 } 1316 1317 return vsc73xx_vlan_change_pvid(vsc, port, vid, valid); 1318 } 1319 1320 static int vsc73xx_vlan_commit_settings(struct vsc73xx *vsc, int port) 1321 { 1322 int ret; 1323 1324 ret = vsc73xx_vlan_commit_untagged(vsc, port); 1325 if (ret) 1326 return ret; 1327 1328 ret = vsc73xx_vlan_commit_pvid(vsc, port); 1329 if (ret) 1330 return ret; 1331 1332 return vsc73xx_vlan_commit_conf(vsc, port); 1333 } 1334 1335 static int vsc73xx_port_enable(struct dsa_switch *ds, int port, 1336 struct phy_device *phy) 1337 { 1338 struct vsc73xx *vsc = ds->priv; 1339 1340 dev_info(vsc->dev, "enable port %d\n", port); 1341 vsc73xx_init_port(vsc, port); 1342 1343 return vsc73xx_vlan_commit_settings(vsc, port); 1344 } 1345 1346 static void vsc73xx_port_disable(struct dsa_switch *ds, int port) 1347 { 1348 struct vsc73xx *vsc = ds->priv; 1349 1350 /* Just put the port into reset */ 1351 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, 1352 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET); 1353 } 1354 1355 static const struct vsc73xx_counter * 1356 vsc73xx_find_counter(struct vsc73xx *vsc, 1357 u8 counter, 1358 bool tx) 1359 { 1360 const struct vsc73xx_counter *cnts; 1361 int num_cnts; 1362 int i; 1363 1364 if (tx) { 1365 cnts = vsc73xx_tx_counters; 1366 num_cnts = ARRAY_SIZE(vsc73xx_tx_counters); 1367 } else { 1368 cnts = vsc73xx_rx_counters; 1369 num_cnts = ARRAY_SIZE(vsc73xx_rx_counters); 1370 } 1371 1372 for (i = 0; i < num_cnts; i++) { 1373 const struct vsc73xx_counter *cnt; 1374 1375 cnt = &cnts[i]; 1376 if (cnt->counter == counter) 1377 return cnt; 1378 } 1379 1380 return NULL; 1381 } 1382 1383 static void vsc73xx_get_strings(struct dsa_switch *ds, int port, u32 stringset, 1384 uint8_t *data) 1385 { 1386 const struct vsc73xx_counter *cnt; 1387 struct vsc73xx *vsc = ds->priv; 1388 u8 indices[6]; 1389 u8 *buf = data; 1390 int i; 1391 u32 val; 1392 int ret; 1393 1394 if (stringset != ETH_SS_STATS) 1395 return; 1396 1397 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port, 1398 VSC73XX_C_CFG, &val); 1399 if (ret) 1400 return; 1401 1402 indices[0] = (val & 0x1f); /* RX counter 0 */ 1403 indices[1] = ((val >> 5) & 0x1f); /* RX counter 1 */ 1404 indices[2] = ((val >> 10) & 0x1f); /* RX counter 2 */ 1405 indices[3] = ((val >> 16) & 0x1f); /* TX counter 0 */ 1406 indices[4] = ((val >> 21) & 0x1f); /* TX counter 1 */ 1407 indices[5] = ((val >> 26) & 0x1f); /* TX counter 2 */ 1408 1409 /* The first counters is the RX octets */ 1410 ethtool_puts(&buf, "RxEtherStatsOctets"); 1411 1412 /* Each port supports recording 3 RX counters and 3 TX counters, 1413 * figure out what counters we use in this set-up and return the 1414 * names of them. The hardware default counters will be number of 1415 * packets on RX/TX, combined broadcast+multicast packets RX/TX and 1416 * total error packets RX/TX. 1417 */ 1418 for (i = 0; i < 3; i++) { 1419 cnt = vsc73xx_find_counter(vsc, indices[i], false); 1420 ethtool_puts(&buf, cnt ? cnt->name : ""); 1421 } 1422 1423 /* TX stats begins with the number of TX octets */ 1424 ethtool_puts(&buf, "TxEtherStatsOctets"); 1425 1426 for (i = 3; i < 6; i++) { 1427 cnt = vsc73xx_find_counter(vsc, indices[i], true); 1428 ethtool_puts(&buf, cnt ? cnt->name : ""); 1429 1430 } 1431 } 1432 1433 static int vsc73xx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1434 { 1435 /* We only support SS_STATS */ 1436 if (sset != ETH_SS_STATS) 1437 return 0; 1438 /* RX and TX packets, then 3 RX counters, 3 TX counters */ 1439 return 8; 1440 } 1441 1442 static void vsc73xx_get_ethtool_stats(struct dsa_switch *ds, int port, 1443 uint64_t *data) 1444 { 1445 struct vsc73xx *vsc = ds->priv; 1446 u8 regs[] = { 1447 VSC73XX_RXOCT, 1448 VSC73XX_C_RX0, 1449 VSC73XX_C_RX1, 1450 VSC73XX_C_RX2, 1451 VSC73XX_TXOCT, 1452 VSC73XX_C_TX0, 1453 VSC73XX_C_TX1, 1454 VSC73XX_C_TX2, 1455 }; 1456 u32 val; 1457 int ret; 1458 int i; 1459 1460 for (i = 0; i < ARRAY_SIZE(regs); i++) { 1461 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port, 1462 regs[i], &val); 1463 if (ret) { 1464 dev_err(vsc->dev, "error reading counter %d\n", i); 1465 return; 1466 } 1467 data[i] = val; 1468 } 1469 } 1470 1471 static int vsc73xx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1472 { 1473 struct vsc73xx *vsc = ds->priv; 1474 1475 return vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, 1476 VSC73XX_MAXLEN, new_mtu + ETH_HLEN + ETH_FCS_LEN); 1477 } 1478 1479 /* According to application not "VSC7398 Jumbo Frames" setting 1480 * up the frame size to 9.6 KB does not affect the performance on standard 1481 * frames. It is clear from the application note that 1482 * "9.6 kilobytes" == 9600 bytes. 1483 */ 1484 static int vsc73xx_get_max_mtu(struct dsa_switch *ds, int port) 1485 { 1486 return 9600 - ETH_HLEN - ETH_FCS_LEN; 1487 } 1488 1489 static void vsc73xx_phylink_get_caps(struct dsa_switch *dsa, int port, 1490 struct phylink_config *config) 1491 { 1492 unsigned long *interfaces = config->supported_interfaces; 1493 1494 if (port == 5) 1495 return; 1496 1497 if (port == CPU_PORT) { 1498 __set_bit(PHY_INTERFACE_MODE_MII, interfaces); 1499 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces); 1500 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces); 1501 __set_bit(PHY_INTERFACE_MODE_RGMII, interfaces); 1502 } 1503 1504 if (port <= 4) { 1505 /* Internal PHYs */ 1506 __set_bit(PHY_INTERFACE_MODE_INTERNAL, interfaces); 1507 /* phylib default */ 1508 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces); 1509 } 1510 1511 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000; 1512 } 1513 1514 static int 1515 vsc73xx_port_vlan_filtering(struct dsa_switch *ds, int port, 1516 bool vlan_filtering, struct netlink_ext_ack *extack) 1517 { 1518 struct vsc73xx *vsc = ds->priv; 1519 1520 /* The commit to hardware processed below is required because vsc73xx 1521 * is using tag_8021q. When vlan_filtering is disabled, tag_8021q uses 1522 * pvid/untagged vlans for port recognition. The values configured for 1523 * vlans and pvid/untagged states are stored in portinfo structure. 1524 * When vlan_filtering is enabled, we need to restore pvid/untagged from 1525 * portinfo structure. Analogous routine is processed when 1526 * vlan_filtering is disabled, but values used for tag_8021q are 1527 * restored. 1528 */ 1529 1530 return vsc73xx_vlan_commit_settings(vsc, port); 1531 } 1532 1533 static int vsc73xx_port_vlan_add(struct dsa_switch *ds, int port, 1534 const struct switchdev_obj_port_vlan *vlan, 1535 struct netlink_ext_ack *extack) 1536 { 1537 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1538 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1539 struct dsa_port *dp = dsa_to_port(ds, port); 1540 struct vsc73xx_bridge_vlan *vsc73xx_vlan; 1541 struct vsc73xx_vlan_summary summary; 1542 struct vsc73xx_portinfo *portinfo; 1543 struct vsc73xx *vsc = ds->priv; 1544 bool commit_to_hardware; 1545 int ret = 0; 1546 1547 /* Be sure to deny alterations to the configuration done by tag_8021q. 1548 */ 1549 if (vid_is_dsa_8021q(vlan->vid)) { 1550 NL_SET_ERR_MSG_MOD(extack, 1551 "Range 3072-4095 reserved for dsa_8021q operation"); 1552 return -EBUSY; 1553 } 1554 1555 /* The processed vlan->vid is excluded from the search because the VLAN 1556 * can be re-added with a different set of flags, so it's easiest to 1557 * ignore its old flags from the VLAN database software copy. 1558 */ 1559 vsc73xx_bridge_vlan_summary(vsc, port, &summary, vlan->vid); 1560 1561 /* VSC73XX allows only three untagged states: none, one or all */ 1562 if ((untagged && summary.num_tagged > 0 && summary.num_untagged > 0) || 1563 (!untagged && summary.num_untagged > 1)) { 1564 NL_SET_ERR_MSG_MOD(extack, 1565 "Port can have only none, one or all untagged vlan"); 1566 return -EBUSY; 1567 } 1568 1569 vsc73xx_vlan = vsc73xx_bridge_vlan_find(vsc, vlan->vid); 1570 1571 if (!vsc73xx_vlan) { 1572 vsc73xx_vlan = kzalloc(sizeof(*vsc73xx_vlan), GFP_KERNEL); 1573 if (!vsc73xx_vlan) 1574 return -ENOMEM; 1575 1576 vsc73xx_vlan->vid = vlan->vid; 1577 1578 list_add_tail(&vsc73xx_vlan->list, &vsc->vlans); 1579 } 1580 1581 vsc73xx_vlan->portmask |= BIT(port); 1582 1583 /* CPU port must be always tagged because source port identification is 1584 * based on tag_8021q. 1585 */ 1586 if (port == CPU_PORT) 1587 goto update_vlan_table; 1588 1589 if (untagged) 1590 vsc73xx_vlan->untagged |= BIT(port); 1591 else 1592 vsc73xx_vlan->untagged &= ~BIT(port); 1593 1594 portinfo = &vsc->portinfo[port]; 1595 1596 if (pvid) { 1597 portinfo->pvid_vlan_filtering_configured = true; 1598 portinfo->pvid_vlan_filtering = vlan->vid; 1599 } else if (portinfo->pvid_vlan_filtering_configured && 1600 portinfo->pvid_vlan_filtering == vlan->vid) { 1601 portinfo->pvid_vlan_filtering_configured = false; 1602 } 1603 1604 commit_to_hardware = !vsc73xx_tag_8021q_active(dp); 1605 if (commit_to_hardware) { 1606 ret = vsc73xx_vlan_commit_settings(vsc, port); 1607 if (ret) 1608 goto err; 1609 } 1610 1611 update_vlan_table: 1612 ret = vsc73xx_update_vlan_table(vsc, port, vlan->vid, true); 1613 if (!ret) 1614 return 0; 1615 err: 1616 vsc73xx_bridge_vlan_remove_port(vsc73xx_vlan, port); 1617 return ret; 1618 } 1619 1620 static int vsc73xx_port_vlan_del(struct dsa_switch *ds, int port, 1621 const struct switchdev_obj_port_vlan *vlan) 1622 { 1623 struct vsc73xx_bridge_vlan *vsc73xx_vlan; 1624 struct vsc73xx_portinfo *portinfo; 1625 struct vsc73xx *vsc = ds->priv; 1626 bool commit_to_hardware; 1627 int ret; 1628 1629 ret = vsc73xx_update_vlan_table(vsc, port, vlan->vid, false); 1630 if (ret) 1631 return ret; 1632 1633 portinfo = &vsc->portinfo[port]; 1634 1635 if (portinfo->pvid_vlan_filtering_configured && 1636 portinfo->pvid_vlan_filtering == vlan->vid) 1637 portinfo->pvid_vlan_filtering_configured = false; 1638 1639 vsc73xx_vlan = vsc73xx_bridge_vlan_find(vsc, vlan->vid); 1640 1641 if (vsc73xx_vlan) 1642 vsc73xx_bridge_vlan_remove_port(vsc73xx_vlan, port); 1643 1644 commit_to_hardware = !vsc73xx_tag_8021q_active(dsa_to_port(ds, port)); 1645 1646 if (commit_to_hardware) 1647 return vsc73xx_vlan_commit_settings(vsc, port); 1648 1649 return 0; 1650 } 1651 1652 static int vsc73xx_tag_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid, 1653 u16 flags) 1654 { 1655 bool pvid = flags & BRIDGE_VLAN_INFO_PVID; 1656 struct vsc73xx_portinfo *portinfo; 1657 struct vsc73xx *vsc = ds->priv; 1658 bool commit_to_hardware; 1659 int ret; 1660 1661 portinfo = &vsc->portinfo[port]; 1662 1663 if (pvid) { 1664 portinfo->pvid_tag_8021q_configured = true; 1665 portinfo->pvid_tag_8021q = vid; 1666 } 1667 1668 commit_to_hardware = vsc73xx_tag_8021q_active(dsa_to_port(ds, port)); 1669 if (commit_to_hardware) { 1670 ret = vsc73xx_vlan_commit_settings(vsc, port); 1671 if (ret) 1672 return ret; 1673 } 1674 1675 return vsc73xx_update_vlan_table(vsc, port, vid, true); 1676 } 1677 1678 static int vsc73xx_tag_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid) 1679 { 1680 struct vsc73xx_portinfo *portinfo; 1681 struct vsc73xx *vsc = ds->priv; 1682 1683 portinfo = &vsc->portinfo[port]; 1684 1685 if (portinfo->pvid_tag_8021q_configured && 1686 portinfo->pvid_tag_8021q == vid) { 1687 struct dsa_port *dp = dsa_to_port(ds, port); 1688 bool commit_to_hardware; 1689 int err; 1690 1691 portinfo->pvid_tag_8021q_configured = false; 1692 1693 commit_to_hardware = vsc73xx_tag_8021q_active(dp); 1694 if (commit_to_hardware) { 1695 err = vsc73xx_vlan_commit_settings(vsc, port); 1696 if (err) 1697 return err; 1698 } 1699 } 1700 1701 return vsc73xx_update_vlan_table(vsc, port, vid, false); 1702 } 1703 1704 static int vsc73xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1705 struct switchdev_brport_flags flags, 1706 struct netlink_ext_ack *extack) 1707 { 1708 if (flags.mask & ~BR_LEARNING) 1709 return -EINVAL; 1710 1711 return 0; 1712 } 1713 1714 static int vsc73xx_port_bridge_flags(struct dsa_switch *ds, int port, 1715 struct switchdev_brport_flags flags, 1716 struct netlink_ext_ack *extack) 1717 { 1718 if (flags.mask & BR_LEARNING) { 1719 u32 val = flags.val & BR_LEARNING ? BIT(port) : 0; 1720 struct vsc73xx *vsc = ds->priv; 1721 1722 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1723 VSC73XX_LEARNMASK, BIT(port), val); 1724 } 1725 1726 return 0; 1727 } 1728 1729 static void vsc73xx_refresh_fwd_map(struct dsa_switch *ds, int port, u8 state) 1730 { 1731 struct dsa_port *other_dp, *dp = dsa_to_port(ds, port); 1732 struct vsc73xx *vsc = ds->priv; 1733 u16 mask; 1734 1735 if (state != BR_STATE_FORWARDING) { 1736 /* Ports that aren't in the forwarding state must not 1737 * forward packets anywhere. 1738 */ 1739 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1740 VSC73XX_SRCMASKS + port, 1741 VSC73XX_SRCMASKS_PORTS_MASK, 0); 1742 1743 dsa_switch_for_each_available_port(other_dp, ds) { 1744 if (other_dp == dp) 1745 continue; 1746 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1747 VSC73XX_SRCMASKS + other_dp->index, 1748 BIT(port), 0); 1749 } 1750 1751 return; 1752 } 1753 1754 /* Forwarding ports must forward to the CPU and to other ports 1755 * in the same bridge 1756 */ 1757 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1758 VSC73XX_SRCMASKS + CPU_PORT, BIT(port), BIT(port)); 1759 1760 mask = BIT(CPU_PORT); 1761 1762 dsa_switch_for_each_user_port(other_dp, ds) { 1763 int other_port = other_dp->index; 1764 1765 if (port == other_port || !dsa_port_bridge_same(dp, other_dp) || 1766 other_dp->stp_state != BR_STATE_FORWARDING) 1767 continue; 1768 1769 mask |= BIT(other_port); 1770 1771 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1772 VSC73XX_SRCMASKS + other_port, 1773 BIT(port), BIT(port)); 1774 } 1775 1776 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1777 VSC73XX_SRCMASKS + port, 1778 VSC73XX_SRCMASKS_PORTS_MASK, mask); 1779 } 1780 1781 /* FIXME: STP frames aren't forwarded at this moment. BPDU frames are 1782 * forwarded only from and to PI/SI interface. For more info see chapter 1783 * 2.7.1 (CPU Forwarding) in datasheet. 1784 * This function is required for tag_8021q operations. 1785 */ 1786 static void vsc73xx_port_stp_state_set(struct dsa_switch *ds, int port, 1787 u8 state) 1788 { 1789 struct dsa_port *dp = dsa_to_port(ds, port); 1790 struct vsc73xx *vsc = ds->priv; 1791 u32 val = 0; 1792 1793 if (state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) 1794 val = dp->learning ? BIT(port) : 0; 1795 1796 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1797 VSC73XX_LEARNMASK, BIT(port), val); 1798 1799 val = (state == BR_STATE_BLOCKING || state == BR_STATE_DISABLED) ? 1800 0 : BIT(port); 1801 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1802 VSC73XX_RECVMASK, BIT(port), val); 1803 1804 /* CPU Port should always forward packets when user ports are forwarding 1805 * so let's configure it from other ports only. 1806 */ 1807 if (port != CPU_PORT) 1808 vsc73xx_refresh_fwd_map(ds, port, state); 1809 } 1810 1811 static const struct phylink_mac_ops vsc73xx_phylink_mac_ops = { 1812 .mac_config = vsc73xx_mac_config, 1813 .mac_link_down = vsc73xx_mac_link_down, 1814 .mac_link_up = vsc73xx_mac_link_up, 1815 }; 1816 1817 static const struct dsa_switch_ops vsc73xx_ds_ops = { 1818 .get_tag_protocol = vsc73xx_get_tag_protocol, 1819 .setup = vsc73xx_setup, 1820 .teardown = vsc73xx_teardown, 1821 .phy_read = vsc73xx_phy_read, 1822 .phy_write = vsc73xx_phy_write, 1823 .get_strings = vsc73xx_get_strings, 1824 .get_ethtool_stats = vsc73xx_get_ethtool_stats, 1825 .get_sset_count = vsc73xx_get_sset_count, 1826 .port_enable = vsc73xx_port_enable, 1827 .port_disable = vsc73xx_port_disable, 1828 .port_pre_bridge_flags = vsc73xx_port_pre_bridge_flags, 1829 .port_bridge_flags = vsc73xx_port_bridge_flags, 1830 .port_bridge_join = dsa_tag_8021q_bridge_join, 1831 .port_bridge_leave = dsa_tag_8021q_bridge_leave, 1832 .port_change_mtu = vsc73xx_change_mtu, 1833 .port_max_mtu = vsc73xx_get_max_mtu, 1834 .port_stp_state_set = vsc73xx_port_stp_state_set, 1835 .port_vlan_filtering = vsc73xx_port_vlan_filtering, 1836 .port_vlan_add = vsc73xx_port_vlan_add, 1837 .port_vlan_del = vsc73xx_port_vlan_del, 1838 .phylink_get_caps = vsc73xx_phylink_get_caps, 1839 .tag_8021q_vlan_add = vsc73xx_tag_8021q_vlan_add, 1840 .tag_8021q_vlan_del = vsc73xx_tag_8021q_vlan_del, 1841 }; 1842 1843 static int vsc73xx_gpio_get(struct gpio_chip *chip, unsigned int offset) 1844 { 1845 struct vsc73xx *vsc = gpiochip_get_data(chip); 1846 u32 val; 1847 int ret; 1848 1849 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1850 VSC73XX_GPIO, &val); 1851 if (ret) 1852 return ret; 1853 1854 return !!(val & BIT(offset)); 1855 } 1856 1857 static void vsc73xx_gpio_set(struct gpio_chip *chip, unsigned int offset, 1858 int val) 1859 { 1860 struct vsc73xx *vsc = gpiochip_get_data(chip); 1861 u32 tmp = val ? BIT(offset) : 0; 1862 1863 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1864 VSC73XX_GPIO, BIT(offset), tmp); 1865 } 1866 1867 static int vsc73xx_gpio_direction_output(struct gpio_chip *chip, 1868 unsigned int offset, int val) 1869 { 1870 struct vsc73xx *vsc = gpiochip_get_data(chip); 1871 u32 tmp = val ? BIT(offset) : 0; 1872 1873 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1874 VSC73XX_GPIO, BIT(offset + 4) | BIT(offset), 1875 BIT(offset + 4) | tmp); 1876 } 1877 1878 static int vsc73xx_gpio_direction_input(struct gpio_chip *chip, 1879 unsigned int offset) 1880 { 1881 struct vsc73xx *vsc = gpiochip_get_data(chip); 1882 1883 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1884 VSC73XX_GPIO, BIT(offset + 4), 1885 0); 1886 } 1887 1888 static int vsc73xx_gpio_get_direction(struct gpio_chip *chip, 1889 unsigned int offset) 1890 { 1891 struct vsc73xx *vsc = gpiochip_get_data(chip); 1892 u32 val; 1893 int ret; 1894 1895 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1896 VSC73XX_GPIO, &val); 1897 if (ret) 1898 return ret; 1899 1900 return !(val & BIT(offset + 4)); 1901 } 1902 1903 static int vsc73xx_gpio_probe(struct vsc73xx *vsc) 1904 { 1905 int ret; 1906 1907 vsc->gc.label = devm_kasprintf(vsc->dev, GFP_KERNEL, "VSC%04x", 1908 vsc->chipid); 1909 if (!vsc->gc.label) 1910 return -ENOMEM; 1911 vsc->gc.ngpio = 4; 1912 vsc->gc.owner = THIS_MODULE; 1913 vsc->gc.parent = vsc->dev; 1914 vsc->gc.base = -1; 1915 vsc->gc.get = vsc73xx_gpio_get; 1916 vsc->gc.set = vsc73xx_gpio_set; 1917 vsc->gc.direction_input = vsc73xx_gpio_direction_input; 1918 vsc->gc.direction_output = vsc73xx_gpio_direction_output; 1919 vsc->gc.get_direction = vsc73xx_gpio_get_direction; 1920 vsc->gc.can_sleep = true; 1921 ret = devm_gpiochip_add_data(vsc->dev, &vsc->gc, vsc); 1922 if (ret) { 1923 dev_err(vsc->dev, "unable to register GPIO chip\n"); 1924 return ret; 1925 } 1926 return 0; 1927 } 1928 1929 int vsc73xx_probe(struct vsc73xx *vsc) 1930 { 1931 struct device *dev = vsc->dev; 1932 int ret; 1933 1934 /* Release reset, if any */ 1935 vsc->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1936 if (IS_ERR(vsc->reset)) { 1937 dev_err(dev, "failed to get RESET GPIO\n"); 1938 return PTR_ERR(vsc->reset); 1939 } 1940 if (vsc->reset) 1941 /* Wait 20ms according to datasheet table 245 */ 1942 msleep(20); 1943 1944 ret = vsc73xx_detect(vsc); 1945 if (ret == -EAGAIN) { 1946 dev_err(vsc->dev, 1947 "Chip seems to be out of control. Assert reset and try again.\n"); 1948 gpiod_set_value_cansleep(vsc->reset, 1); 1949 /* Reset pulse should be 20ns minimum, according to datasheet 1950 * table 245, so 10us should be fine 1951 */ 1952 usleep_range(10, 100); 1953 gpiod_set_value_cansleep(vsc->reset, 0); 1954 /* Wait 20ms according to datasheet table 245 */ 1955 msleep(20); 1956 ret = vsc73xx_detect(vsc); 1957 } 1958 if (ret) { 1959 dev_err(dev, "no chip found (%d)\n", ret); 1960 return -ENODEV; 1961 } 1962 1963 eth_random_addr(vsc->addr); 1964 dev_info(vsc->dev, 1965 "MAC for control frames: %02X:%02X:%02X:%02X:%02X:%02X\n", 1966 vsc->addr[0], vsc->addr[1], vsc->addr[2], 1967 vsc->addr[3], vsc->addr[4], vsc->addr[5]); 1968 1969 vsc->ds = devm_kzalloc(dev, sizeof(*vsc->ds), GFP_KERNEL); 1970 if (!vsc->ds) 1971 return -ENOMEM; 1972 1973 vsc->ds->dev = dev; 1974 vsc->ds->num_ports = VSC73XX_MAX_NUM_PORTS; 1975 vsc->ds->priv = vsc; 1976 1977 vsc->ds->ops = &vsc73xx_ds_ops; 1978 vsc->ds->phylink_mac_ops = &vsc73xx_phylink_mac_ops; 1979 ret = dsa_register_switch(vsc->ds); 1980 if (ret) { 1981 dev_err(dev, "unable to register switch (%d)\n", ret); 1982 return ret; 1983 } 1984 1985 ret = vsc73xx_gpio_probe(vsc); 1986 if (ret) { 1987 dsa_unregister_switch(vsc->ds); 1988 return ret; 1989 } 1990 1991 return 0; 1992 } 1993 EXPORT_SYMBOL(vsc73xx_probe); 1994 1995 void vsc73xx_remove(struct vsc73xx *vsc) 1996 { 1997 dsa_unregister_switch(vsc->ds); 1998 gpiod_set_value(vsc->reset, 1); 1999 } 2000 EXPORT_SYMBOL(vsc73xx_remove); 2001 2002 void vsc73xx_shutdown(struct vsc73xx *vsc) 2003 { 2004 dsa_switch_shutdown(vsc->ds); 2005 } 2006 EXPORT_SYMBOL(vsc73xx_shutdown); 2007 2008 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>"); 2009 MODULE_DESCRIPTION("Vitesse VSC7385/7388/7395/7398 driver"); 2010 MODULE_LICENSE("GPL v2"); 2011