1 // SPDX-License-Identifier: GPL-2.0 2 /* DSA driver for: 3 * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch 4 * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch 5 * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch 6 * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch 7 * 8 * These switches have a built-in 8051 CPU and can download and execute a 9 * firmware in this CPU. They can also be configured to use an external CPU 10 * handling the switch in a memory-mapped manner by connecting to that external 11 * CPU's memory bus. 12 * 13 * Copyright (C) 2018 Linus Wallej <linus.walleij@linaro.org> 14 * Includes portions of code from the firmware uploader by: 15 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> 16 */ 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/device.h> 20 #include <linux/iopoll.h> 21 #include <linux/of.h> 22 #include <linux/of_mdio.h> 23 #include <linux/bitops.h> 24 #include <linux/if_bridge.h> 25 #include <linux/if_vlan.h> 26 #include <linux/etherdevice.h> 27 #include <linux/gpio/consumer.h> 28 #include <linux/gpio/driver.h> 29 #include <linux/dsa/8021q.h> 30 #include <linux/random.h> 31 #include <net/dsa.h> 32 33 #include "vitesse-vsc73xx.h" 34 35 #define VSC73XX_BLOCK_MAC 0x1 /* Subblocks 0-4, 6 (CPU port) */ 36 #define VSC73XX_BLOCK_ANALYZER 0x2 /* Only subblock 0 */ 37 #define VSC73XX_BLOCK_MII 0x3 /* Subblocks 0 and 1 */ 38 #define VSC73XX_BLOCK_MEMINIT 0x3 /* Only subblock 2 */ 39 #define VSC73XX_BLOCK_CAPTURE 0x4 /* Subblocks 0-4, 6, 7 */ 40 #define VSC73XX_BLOCK_ARBITER 0x5 /* Only subblock 0 */ 41 #define VSC73XX_BLOCK_SYSTEM 0x7 /* Only subblock 0 */ 42 43 /* MII Block subblock */ 44 #define VSC73XX_BLOCK_MII_INTERNAL 0x0 /* Internal MDIO subblock */ 45 #define VSC73XX_BLOCK_MII_EXTERNAL 0x1 /* External MDIO subblock */ 46 47 #define CPU_PORT 6 /* CPU port */ 48 49 /* MAC Block registers */ 50 #define VSC73XX_MAC_CFG 0x00 51 #define VSC73XX_MACHDXGAP 0x02 52 #define VSC73XX_FCCONF 0x04 53 #define VSC73XX_FCMACHI 0x08 54 #define VSC73XX_FCMACLO 0x0c 55 #define VSC73XX_MAXLEN 0x10 56 #define VSC73XX_ADVPORTM 0x19 57 #define VSC73XX_TXUPDCFG 0x24 58 #define VSC73XX_TXQ_SELECT_CFG 0x28 59 #define VSC73XX_RXOCT 0x50 60 #define VSC73XX_TXOCT 0x51 61 #define VSC73XX_C_RX0 0x52 62 #define VSC73XX_C_RX1 0x53 63 #define VSC73XX_C_RX2 0x54 64 #define VSC73XX_C_TX0 0x55 65 #define VSC73XX_C_TX1 0x56 66 #define VSC73XX_C_TX2 0x57 67 #define VSC73XX_C_CFG 0x58 68 #define VSC73XX_CAT_DROP 0x6e 69 #define VSC73XX_CAT_PR_MISC_L2 0x6f 70 #define VSC73XX_CAT_PR_USR_PRIO 0x75 71 #define VSC73XX_CAT_VLAN_MISC 0x79 72 #define VSC73XX_CAT_PORT_VLAN 0x7a 73 #define VSC73XX_Q_MISC_CONF 0xdf 74 75 /* MAC_CFG register bits */ 76 #define VSC73XX_MAC_CFG_WEXC_DIS BIT(31) 77 #define VSC73XX_MAC_CFG_PORT_RST BIT(29) 78 #define VSC73XX_MAC_CFG_TX_EN BIT(28) 79 #define VSC73XX_MAC_CFG_SEED_LOAD BIT(27) 80 #define VSC73XX_MAC_CFG_SEED_MASK GENMASK(26, 19) 81 #define VSC73XX_MAC_CFG_SEED_OFFSET 19 82 #define VSC73XX_MAC_CFG_FDX BIT(18) 83 #define VSC73XX_MAC_CFG_GIGA_MODE BIT(17) 84 #define VSC73XX_MAC_CFG_RX_EN BIT(16) 85 #define VSC73XX_MAC_CFG_VLAN_DBLAWR BIT(15) 86 #define VSC73XX_MAC_CFG_VLAN_AWR BIT(14) 87 #define VSC73XX_MAC_CFG_100_BASE_T BIT(13) /* Not in manual */ 88 #define VSC73XX_MAC_CFG_TX_IPG_MASK GENMASK(10, 6) 89 #define VSC73XX_MAC_CFG_TX_IPG_OFFSET 6 90 #define VSC73XX_MAC_CFG_TX_IPG_1000M (6 << VSC73XX_MAC_CFG_TX_IPG_OFFSET) 91 #define VSC73XX_MAC_CFG_TX_IPG_100_10M (17 << VSC73XX_MAC_CFG_TX_IPG_OFFSET) 92 #define VSC73XX_MAC_CFG_MAC_RX_RST BIT(5) 93 #define VSC73XX_MAC_CFG_MAC_TX_RST BIT(4) 94 #define VSC73XX_MAC_CFG_CLK_SEL_MASK GENMASK(2, 0) 95 #define VSC73XX_MAC_CFG_CLK_SEL_OFFSET 0 96 #define VSC73XX_MAC_CFG_CLK_SEL_1000M 1 97 #define VSC73XX_MAC_CFG_CLK_SEL_100M 2 98 #define VSC73XX_MAC_CFG_CLK_SEL_10M 3 99 #define VSC73XX_MAC_CFG_CLK_SEL_EXT 4 100 101 #define VSC73XX_MAC_CFG_1000M_F_PHY (VSC73XX_MAC_CFG_FDX | \ 102 VSC73XX_MAC_CFG_GIGA_MODE | \ 103 VSC73XX_MAC_CFG_TX_IPG_1000M | \ 104 VSC73XX_MAC_CFG_CLK_SEL_EXT) 105 #define VSC73XX_MAC_CFG_100_10M_F_PHY (VSC73XX_MAC_CFG_FDX | \ 106 VSC73XX_MAC_CFG_TX_IPG_100_10M | \ 107 VSC73XX_MAC_CFG_CLK_SEL_EXT) 108 #define VSC73XX_MAC_CFG_100_10M_H_PHY (VSC73XX_MAC_CFG_TX_IPG_100_10M | \ 109 VSC73XX_MAC_CFG_CLK_SEL_EXT) 110 #define VSC73XX_MAC_CFG_1000M_F_RGMII (VSC73XX_MAC_CFG_FDX | \ 111 VSC73XX_MAC_CFG_GIGA_MODE | \ 112 VSC73XX_MAC_CFG_TX_IPG_1000M | \ 113 VSC73XX_MAC_CFG_CLK_SEL_1000M) 114 #define VSC73XX_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \ 115 VSC73XX_MAC_CFG_MAC_RX_RST | \ 116 VSC73XX_MAC_CFG_MAC_TX_RST) 117 118 /* Flow control register bits */ 119 #define VSC73XX_FCCONF_ZERO_PAUSE_EN BIT(17) 120 #define VSC73XX_FCCONF_FLOW_CTRL_OBEY BIT(16) 121 #define VSC73XX_FCCONF_PAUSE_VAL_MASK GENMASK(15, 0) 122 123 /* ADVPORTM advanced port setup register bits */ 124 #define VSC73XX_ADVPORTM_IFG_PPM BIT(7) 125 #define VSC73XX_ADVPORTM_EXC_COL_CONT BIT(6) 126 #define VSC73XX_ADVPORTM_EXT_PORT BIT(5) 127 #define VSC73XX_ADVPORTM_INV_GTX BIT(4) 128 #define VSC73XX_ADVPORTM_ENA_GTX BIT(3) 129 #define VSC73XX_ADVPORTM_DDR_MODE BIT(2) 130 #define VSC73XX_ADVPORTM_IO_LOOPBACK BIT(1) 131 #define VSC73XX_ADVPORTM_HOST_LOOPBACK BIT(0) 132 133 /* TXUPDCFG transmit modify setup bits */ 134 #define VSC73XX_TXUPDCFG_DSCP_REWR_MODE GENMASK(20, 19) 135 #define VSC73XX_TXUPDCFG_DSCP_REWR_ENA BIT(18) 136 #define VSC73XX_TXUPDCFG_TX_INT_TO_USRPRIO_ENA BIT(17) 137 #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID GENMASK(15, 4) 138 #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA BIT(3) 139 #define VSC73XX_TXUPDCFG_TX_UPDATE_CRC_CPU_ENA BIT(1) 140 #define VSC73XX_TXUPDCFG_TX_INSERT_TAG BIT(0) 141 142 #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_SHIFT 4 143 144 /* CAT_DROP categorizer frame dropping register bits */ 145 #define VSC73XX_CAT_DROP_DROP_MC_SMAC_ENA BIT(6) 146 #define VSC73XX_CAT_DROP_FWD_CTRL_ENA BIT(4) 147 #define VSC73XX_CAT_DROP_FWD_PAUSE_ENA BIT(3) 148 #define VSC73XX_CAT_DROP_UNTAGGED_ENA BIT(2) 149 #define VSC73XX_CAT_DROP_TAGGED_ENA BIT(1) 150 #define VSC73XX_CAT_DROP_NULL_MAC_ENA BIT(0) 151 152 #define VSC73XX_Q_MISC_CONF_EXTENT_MEM BIT(31) 153 #define VSC73XX_Q_MISC_CONF_EARLY_TX_MASK GENMASK(4, 1) 154 #define VSC73XX_Q_MISC_CONF_EARLY_TX_512 (1 << 1) 155 #define VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE BIT(0) 156 157 /* CAT_VLAN_MISC categorizer VLAN miscellaneous bits */ 158 #define VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA BIT(8) 159 #define VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA BIT(7) 160 161 /* CAT_PORT_VLAN categorizer port VLAN */ 162 #define VSC73XX_CAT_PORT_VLAN_VLAN_CFI BIT(15) 163 #define VSC73XX_CAT_PORT_VLAN_VLAN_USR_PRIO GENMASK(14, 12) 164 #define VSC73XX_CAT_PORT_VLAN_VLAN_VID GENMASK(11, 0) 165 166 /* Frame analyzer block 2 registers */ 167 #define VSC73XX_STORMLIMIT 0x02 168 #define VSC73XX_ADVLEARN 0x03 169 #define VSC73XX_IFLODMSK 0x04 170 #define VSC73XX_VLANMASK 0x05 171 #define VSC73XX_MACHDATA 0x06 172 #define VSC73XX_MACLDATA 0x07 173 #define VSC73XX_ANMOVED 0x08 174 #define VSC73XX_ANAGEFIL 0x09 175 #define VSC73XX_ANEVENTS 0x0a 176 #define VSC73XX_ANCNTMASK 0x0b 177 #define VSC73XX_ANCNTVAL 0x0c 178 #define VSC73XX_LEARNMASK 0x0d 179 #define VSC73XX_UFLODMASK 0x0e 180 #define VSC73XX_MFLODMASK 0x0f 181 #define VSC73XX_RECVMASK 0x10 182 #define VSC73XX_AGGRCTRL 0x20 183 #define VSC73XX_AGGRMSKS 0x30 /* Until 0x3f */ 184 #define VSC73XX_DSTMASKS 0x40 /* Until 0x7f */ 185 #define VSC73XX_SRCMASKS 0x80 /* Until 0x87 */ 186 #define VSC73XX_CAPENAB 0xa0 187 #define VSC73XX_MACACCESS 0xb0 188 #define VSC73XX_IPMCACCESS 0xb1 189 #define VSC73XX_MACTINDX 0xc0 190 #define VSC73XX_VLANACCESS 0xd0 191 #define VSC73XX_VLANTIDX 0xe0 192 #define VSC73XX_AGENCTRL 0xf0 193 #define VSC73XX_CAPRST 0xff 194 195 #define VSC73XX_SRCMASKS_CPU_COPY BIT(27) 196 #define VSC73XX_SRCMASKS_MIRROR BIT(26) 197 #define VSC73XX_SRCMASKS_PORTS_MASK GENMASK(7, 0) 198 199 #define VSC73XX_MACACCESS_CPU_COPY BIT(14) 200 #define VSC73XX_MACACCESS_FWD_KILL BIT(13) 201 #define VSC73XX_MACACCESS_IGNORE_VLAN BIT(12) 202 #define VSC73XX_MACACCESS_AGED_FLAG BIT(11) 203 #define VSC73XX_MACACCESS_VALID BIT(10) 204 #define VSC73XX_MACACCESS_LOCKED BIT(9) 205 #define VSC73XX_MACACCESS_DEST_IDX_MASK GENMASK(8, 3) 206 #define VSC73XX_MACACCESS_CMD_MASK GENMASK(2, 0) 207 #define VSC73XX_MACACCESS_CMD_IDLE 0 208 #define VSC73XX_MACACCESS_CMD_LEARN 1 209 #define VSC73XX_MACACCESS_CMD_FORGET 2 210 #define VSC73XX_MACACCESS_CMD_AGE_TABLE 3 211 #define VSC73XX_MACACCESS_CMD_FLUSH_TABLE 4 212 #define VSC73XX_MACACCESS_CMD_CLEAR_TABLE 5 213 #define VSC73XX_MACACCESS_CMD_READ_ENTRY 6 214 #define VSC73XX_MACACCESS_CMD_WRITE_ENTRY 7 215 216 #define VSC73XX_VLANACCESS_LEARN_DISABLED BIT(30) 217 #define VSC73XX_VLANACCESS_VLAN_MIRROR BIT(29) 218 #define VSC73XX_VLANACCESS_VLAN_SRC_CHECK BIT(28) 219 #define VSC73XX_VLANACCESS_VLAN_PORT_MASK GENMASK(9, 2) 220 #define VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT 2 221 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK GENMASK(1, 0) 222 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE 0 223 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY 1 224 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY 2 225 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE 3 226 227 /* MII block 3 registers */ 228 #define VSC73XX_MII_STAT 0x0 229 #define VSC73XX_MII_CMD 0x1 230 #define VSC73XX_MII_DATA 0x2 231 232 #define VSC73XX_MII_STAT_BUSY BIT(3) 233 234 /* Arbiter block 5 registers */ 235 #define VSC73XX_ARBEMPTY 0x0c 236 #define VSC73XX_ARBDISC 0x0e 237 #define VSC73XX_SBACKWDROP 0x12 238 #define VSC73XX_DBACKWDROP 0x13 239 #define VSC73XX_ARBBURSTPROB 0x15 240 241 /* System block 7 registers */ 242 #define VSC73XX_ICPU_SIPAD 0x01 243 #define VSC73XX_GMIIDELAY 0x05 244 #define VSC73XX_ICPU_CTRL 0x10 245 #define VSC73XX_ICPU_ADDR 0x11 246 #define VSC73XX_ICPU_SRAM 0x12 247 #define VSC73XX_HWSEM 0x13 248 #define VSC73XX_GLORESET 0x14 249 #define VSC73XX_ICPU_MBOX_VAL 0x15 250 #define VSC73XX_ICPU_MBOX_SET 0x16 251 #define VSC73XX_ICPU_MBOX_CLR 0x17 252 #define VSC73XX_CHIPID 0x18 253 #define VSC73XX_GPIO 0x34 254 255 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_NONE 0 256 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_4_NS 1 257 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_7_NS 2 258 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS 3 259 260 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_NONE (0 << 4) 261 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_4_NS (1 << 4) 262 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_7_NS (2 << 4) 263 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS (3 << 4) 264 265 #define VSC73XX_ICPU_CTRL_WATCHDOG_RST BIT(31) 266 #define VSC73XX_ICPU_CTRL_CLK_DIV_MASK GENMASK(12, 8) 267 #define VSC73XX_ICPU_CTRL_SRST_HOLD BIT(7) 268 #define VSC73XX_ICPU_CTRL_ICPU_PI_EN BIT(6) 269 #define VSC73XX_ICPU_CTRL_BOOT_EN BIT(3) 270 #define VSC73XX_ICPU_CTRL_EXT_ACC_EN BIT(2) 271 #define VSC73XX_ICPU_CTRL_CLK_EN BIT(1) 272 #define VSC73XX_ICPU_CTRL_SRST BIT(0) 273 274 #define VSC73XX_CHIPID_ID_SHIFT 12 275 #define VSC73XX_CHIPID_ID_MASK 0xffff 276 #define VSC73XX_CHIPID_REV_SHIFT 28 277 #define VSC73XX_CHIPID_REV_MASK 0xf 278 #define VSC73XX_CHIPID_ID_7385 0x7385 279 #define VSC73XX_CHIPID_ID_7388 0x7388 280 #define VSC73XX_CHIPID_ID_7395 0x7395 281 #define VSC73XX_CHIPID_ID_7398 0x7398 282 283 #define VSC73XX_GLORESET_STROBE BIT(4) 284 #define VSC73XX_GLORESET_ICPU_LOCK BIT(3) 285 #define VSC73XX_GLORESET_MEM_LOCK BIT(2) 286 #define VSC73XX_GLORESET_PHY_RESET BIT(1) 287 #define VSC73XX_GLORESET_MASTER_RESET BIT(0) 288 289 #define VSC7385_CLOCK_DELAY ((3 << 4) | 3) 290 #define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3) 291 292 #define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \ 293 VSC73XX_ICPU_CTRL_BOOT_EN | \ 294 VSC73XX_ICPU_CTRL_EXT_ACC_EN) 295 296 #define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \ 297 VSC73XX_ICPU_CTRL_BOOT_EN | \ 298 VSC73XX_ICPU_CTRL_CLK_EN | \ 299 VSC73XX_ICPU_CTRL_SRST) 300 301 #define IS_7385(a) ((a)->chipid == VSC73XX_CHIPID_ID_7385) 302 #define IS_7388(a) ((a)->chipid == VSC73XX_CHIPID_ID_7388) 303 #define IS_7395(a) ((a)->chipid == VSC73XX_CHIPID_ID_7395) 304 #define IS_7398(a) ((a)->chipid == VSC73XX_CHIPID_ID_7398) 305 #define IS_739X(a) (IS_7395(a) || IS_7398(a)) 306 307 #define VSC73XX_POLL_SLEEP_US 1000 308 #define VSC73XX_MDIO_POLL_SLEEP_US 5 309 #define VSC73XX_POLL_TIMEOUT_US 10000 310 311 struct vsc73xx_counter { 312 u8 counter; 313 const char *name; 314 }; 315 316 /* Counters are named according to the MIB standards where applicable. 317 * Some counters are custom, non-standard. The standard counters are 318 * named in accordance with RFC2819, RFC2021 and IEEE Std 802.3-2002 Annex 319 * 30A Counters. 320 */ 321 static const struct vsc73xx_counter vsc73xx_rx_counters[] = { 322 { 0, "RxEtherStatsPkts" }, 323 { 1, "RxBroadcast+MulticastPkts" }, /* non-standard counter */ 324 { 2, "RxTotalErrorPackets" }, /* non-standard counter */ 325 { 3, "RxEtherStatsBroadcastPkts" }, 326 { 4, "RxEtherStatsMulticastPkts" }, 327 { 5, "RxEtherStatsPkts64Octets" }, 328 { 6, "RxEtherStatsPkts65to127Octets" }, 329 { 7, "RxEtherStatsPkts128to255Octets" }, 330 { 8, "RxEtherStatsPkts256to511Octets" }, 331 { 9, "RxEtherStatsPkts512to1023Octets" }, 332 { 10, "RxEtherStatsPkts1024to1518Octets" }, 333 { 11, "RxJumboFrames" }, /* non-standard counter */ 334 { 12, "RxaPauseMACControlFramesTransmitted" }, 335 { 13, "RxFIFODrops" }, /* non-standard counter */ 336 { 14, "RxBackwardDrops" }, /* non-standard counter */ 337 { 15, "RxClassifierDrops" }, /* non-standard counter */ 338 { 16, "RxEtherStatsCRCAlignErrors" }, 339 { 17, "RxEtherStatsUndersizePkts" }, 340 { 18, "RxEtherStatsOversizePkts" }, 341 { 19, "RxEtherStatsFragments" }, 342 { 20, "RxEtherStatsJabbers" }, 343 { 21, "RxaMACControlFramesReceived" }, 344 /* 22-24 are undefined */ 345 { 25, "RxaFramesReceivedOK" }, 346 { 26, "RxQoSClass0" }, /* non-standard counter */ 347 { 27, "RxQoSClass1" }, /* non-standard counter */ 348 { 28, "RxQoSClass2" }, /* non-standard counter */ 349 { 29, "RxQoSClass3" }, /* non-standard counter */ 350 }; 351 352 static const struct vsc73xx_counter vsc73xx_tx_counters[] = { 353 { 0, "TxEtherStatsPkts" }, 354 { 1, "TxBroadcast+MulticastPkts" }, /* non-standard counter */ 355 { 2, "TxTotalErrorPackets" }, /* non-standard counter */ 356 { 3, "TxEtherStatsBroadcastPkts" }, 357 { 4, "TxEtherStatsMulticastPkts" }, 358 { 5, "TxEtherStatsPkts64Octets" }, 359 { 6, "TxEtherStatsPkts65to127Octets" }, 360 { 7, "TxEtherStatsPkts128to255Octets" }, 361 { 8, "TxEtherStatsPkts256to511Octets" }, 362 { 9, "TxEtherStatsPkts512to1023Octets" }, 363 { 10, "TxEtherStatsPkts1024to1518Octets" }, 364 { 11, "TxJumboFrames" }, /* non-standard counter */ 365 { 12, "TxaPauseMACControlFramesTransmitted" }, 366 { 13, "TxFIFODrops" }, /* non-standard counter */ 367 { 14, "TxDrops" }, /* non-standard counter */ 368 { 15, "TxEtherStatsCollisions" }, 369 { 16, "TxEtherStatsCRCAlignErrors" }, 370 { 17, "TxEtherStatsUndersizePkts" }, 371 { 18, "TxEtherStatsOversizePkts" }, 372 { 19, "TxEtherStatsFragments" }, 373 { 20, "TxEtherStatsJabbers" }, 374 /* 21-24 are undefined */ 375 { 25, "TxaFramesReceivedOK" }, 376 { 26, "TxQoSClass0" }, /* non-standard counter */ 377 { 27, "TxQoSClass1" }, /* non-standard counter */ 378 { 28, "TxQoSClass2" }, /* non-standard counter */ 379 { 29, "TxQoSClass3" }, /* non-standard counter */ 380 }; 381 382 struct vsc73xx_vlan_summary { 383 size_t num_tagged; 384 size_t num_untagged; 385 }; 386 387 enum vsc73xx_port_vlan_conf { 388 VSC73XX_VLAN_FILTER, 389 VSC73XX_VLAN_FILTER_UNTAG_ALL, 390 VSC73XX_VLAN_IGNORE, 391 }; 392 393 int vsc73xx_is_addr_valid(u8 block, u8 subblock) 394 { 395 switch (block) { 396 case VSC73XX_BLOCK_MAC: 397 switch (subblock) { 398 case 0 ... 4: 399 case 6: 400 return 1; 401 } 402 break; 403 404 case VSC73XX_BLOCK_ANALYZER: 405 case VSC73XX_BLOCK_SYSTEM: 406 switch (subblock) { 407 case 0: 408 return 1; 409 } 410 break; 411 412 case VSC73XX_BLOCK_MII: 413 case VSC73XX_BLOCK_ARBITER: 414 switch (subblock) { 415 case 0 ... 1: 416 return 1; 417 } 418 break; 419 case VSC73XX_BLOCK_CAPTURE: 420 switch (subblock) { 421 case 0 ... 4: 422 case 6 ... 7: 423 return 1; 424 } 425 break; 426 } 427 428 return 0; 429 } 430 EXPORT_SYMBOL(vsc73xx_is_addr_valid); 431 432 static int vsc73xx_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, 433 u32 *val) 434 { 435 return vsc->ops->read(vsc, block, subblock, reg, val); 436 } 437 438 static int vsc73xx_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, 439 u32 val) 440 { 441 return vsc->ops->write(vsc, block, subblock, reg, val); 442 } 443 444 static int vsc73xx_update_bits(struct vsc73xx *vsc, u8 block, u8 subblock, 445 u8 reg, u32 mask, u32 val) 446 { 447 u32 tmp, orig; 448 int ret; 449 450 /* Same read-modify-write algorithm as e.g. regmap */ 451 ret = vsc73xx_read(vsc, block, subblock, reg, &orig); 452 if (ret) 453 return ret; 454 tmp = orig & ~mask; 455 tmp |= val & mask; 456 return vsc73xx_write(vsc, block, subblock, reg, tmp); 457 } 458 459 static int vsc73xx_detect(struct vsc73xx *vsc) 460 { 461 bool icpu_si_boot_en; 462 bool icpu_pi_en; 463 u32 val; 464 u32 rev; 465 int ret; 466 u32 id; 467 468 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 469 VSC73XX_ICPU_MBOX_VAL, &val); 470 if (ret) { 471 dev_err(vsc->dev, "unable to read mailbox (%d)\n", ret); 472 return ret; 473 } 474 475 if (val == 0xffffffff) { 476 dev_info(vsc->dev, "chip seems dead.\n"); 477 return -EAGAIN; 478 } 479 480 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 481 VSC73XX_CHIPID, &val); 482 if (ret) { 483 dev_err(vsc->dev, "unable to read chip id (%d)\n", ret); 484 return ret; 485 } 486 487 id = (val >> VSC73XX_CHIPID_ID_SHIFT) & 488 VSC73XX_CHIPID_ID_MASK; 489 switch (id) { 490 case VSC73XX_CHIPID_ID_7385: 491 case VSC73XX_CHIPID_ID_7388: 492 case VSC73XX_CHIPID_ID_7395: 493 case VSC73XX_CHIPID_ID_7398: 494 break; 495 default: 496 dev_err(vsc->dev, "unsupported chip, id=%04x\n", id); 497 return -ENODEV; 498 } 499 500 vsc->chipid = id; 501 rev = (val >> VSC73XX_CHIPID_REV_SHIFT) & 502 VSC73XX_CHIPID_REV_MASK; 503 dev_info(vsc->dev, "VSC%04X (rev: %d) switch found\n", id, rev); 504 505 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 506 VSC73XX_ICPU_CTRL, &val); 507 if (ret) { 508 dev_err(vsc->dev, "unable to read iCPU control\n"); 509 return ret; 510 } 511 512 /* The iCPU can always be used but can boot in different ways. 513 * If it is initially disabled and has no external memory, 514 * we are in control and can do whatever we like, else we 515 * are probably in trouble (we need some way to communicate 516 * with the running firmware) so we bail out for now. 517 */ 518 icpu_pi_en = !!(val & VSC73XX_ICPU_CTRL_ICPU_PI_EN); 519 icpu_si_boot_en = !!(val & VSC73XX_ICPU_CTRL_BOOT_EN); 520 if (icpu_si_boot_en && icpu_pi_en) { 521 dev_err(vsc->dev, 522 "iCPU enabled boots from SI, has external memory\n"); 523 dev_err(vsc->dev, "no idea how to deal with this\n"); 524 return -ENODEV; 525 } 526 if (icpu_si_boot_en && !icpu_pi_en) { 527 dev_err(vsc->dev, 528 "iCPU enabled boots from PI/SI, no external memory\n"); 529 return -EAGAIN; 530 } 531 if (!icpu_si_boot_en && icpu_pi_en) { 532 dev_err(vsc->dev, 533 "iCPU enabled, boots from PI external memory\n"); 534 dev_err(vsc->dev, "no idea how to deal with this\n"); 535 return -ENODEV; 536 } 537 /* !icpu_si_boot_en && !cpu_pi_en */ 538 dev_info(vsc->dev, "iCPU disabled, no external memory\n"); 539 540 return 0; 541 } 542 543 static int vsc73xx_mdio_busy_check(struct vsc73xx *vsc) 544 { 545 int ret, err; 546 u32 val; 547 548 ret = read_poll_timeout(vsc73xx_read, err, 549 err < 0 || !(val & VSC73XX_MII_STAT_BUSY), 550 VSC73XX_MDIO_POLL_SLEEP_US, 551 VSC73XX_POLL_TIMEOUT_US, false, vsc, 552 VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL, 553 VSC73XX_MII_STAT, &val); 554 if (ret) 555 return ret; 556 return err; 557 } 558 559 static int vsc73xx_phy_read(struct dsa_switch *ds, int phy, int regnum) 560 { 561 struct vsc73xx *vsc = ds->priv; 562 u32 cmd; 563 u32 val; 564 int ret; 565 566 ret = vsc73xx_mdio_busy_check(vsc); 567 if (ret) 568 return ret; 569 570 /* Setting bit 26 means "read" */ 571 cmd = BIT(26) | (phy << 21) | (regnum << 16); 572 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd); 573 if (ret) 574 return ret; 575 576 ret = vsc73xx_mdio_busy_check(vsc); 577 if (ret) 578 return ret; 579 580 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, 0, 2, &val); 581 if (ret) 582 return ret; 583 if (val & BIT(16)) { 584 dev_err(vsc->dev, "reading reg %02x from phy%d failed\n", 585 regnum, phy); 586 return -EIO; 587 } 588 val &= 0xFFFFU; 589 590 dev_dbg(vsc->dev, "read reg %02x from phy%d = %04x\n", 591 regnum, phy, val); 592 593 return val; 594 } 595 596 static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum, 597 u16 val) 598 { 599 struct vsc73xx *vsc = ds->priv; 600 u32 cmd; 601 int ret; 602 603 ret = vsc73xx_mdio_busy_check(vsc); 604 if (ret) 605 return ret; 606 607 cmd = (phy << 21) | (regnum << 16) | val; 608 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd); 609 if (ret) 610 return ret; 611 612 dev_dbg(vsc->dev, "write %04x to reg %02x in phy%d\n", 613 val, regnum, phy); 614 return 0; 615 } 616 617 static enum dsa_tag_protocol vsc73xx_get_tag_protocol(struct dsa_switch *ds, 618 int port, 619 enum dsa_tag_protocol mp) 620 { 621 /* The switch internally uses a 8 byte header with length, 622 * source port, tag, LPA and priority. This is supposedly 623 * only accessible when operating the switch using the internal 624 * CPU or with an external CPU mapping the device in, but not 625 * when operating the switch over SPI and putting frames in/out 626 * on port 6 (the CPU port). So far we must assume that we 627 * cannot access the tag. (See "Internal frame header" section 628 * 3.9.1 in the manual.) 629 */ 630 return DSA_TAG_PROTO_VSC73XX_8021Q; 631 } 632 633 static int vsc73xx_wait_for_vlan_table_cmd(struct vsc73xx *vsc) 634 { 635 int ret, err; 636 u32 val; 637 638 ret = read_poll_timeout(vsc73xx_read, err, 639 err < 0 || 640 ((val & VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK) == 641 VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE), 642 VSC73XX_POLL_SLEEP_US, VSC73XX_POLL_TIMEOUT_US, 643 false, vsc, VSC73XX_BLOCK_ANALYZER, 644 0, VSC73XX_VLANACCESS, &val); 645 if (ret) 646 return ret; 647 return err; 648 } 649 650 static int 651 vsc73xx_read_vlan_table_entry(struct vsc73xx *vsc, u16 vid, u8 *portmap) 652 { 653 u32 val; 654 int ret; 655 656 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANTIDX, vid); 657 658 ret = vsc73xx_wait_for_vlan_table_cmd(vsc); 659 if (ret) 660 return ret; 661 662 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS, 663 VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK, 664 VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY); 665 666 ret = vsc73xx_wait_for_vlan_table_cmd(vsc); 667 if (ret) 668 return ret; 669 670 vsc73xx_read(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS, &val); 671 *portmap = (val & VSC73XX_VLANACCESS_VLAN_PORT_MASK) >> 672 VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT; 673 674 return 0; 675 } 676 677 static int 678 vsc73xx_write_vlan_table_entry(struct vsc73xx *vsc, u16 vid, u8 portmap) 679 { 680 int ret; 681 682 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANTIDX, vid); 683 684 ret = vsc73xx_wait_for_vlan_table_cmd(vsc); 685 if (ret) 686 return ret; 687 688 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS, 689 VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK | 690 VSC73XX_VLANACCESS_VLAN_SRC_CHECK | 691 VSC73XX_VLANACCESS_VLAN_PORT_MASK, 692 VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY | 693 VSC73XX_VLANACCESS_VLAN_SRC_CHECK | 694 (portmap << VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT)); 695 696 return vsc73xx_wait_for_vlan_table_cmd(vsc); 697 } 698 699 static int 700 vsc73xx_update_vlan_table(struct vsc73xx *vsc, int port, u16 vid, bool set) 701 { 702 u8 portmap; 703 int ret; 704 705 ret = vsc73xx_read_vlan_table_entry(vsc, vid, &portmap); 706 if (ret) 707 return ret; 708 709 if (set) 710 portmap |= BIT(port); 711 else 712 portmap &= ~BIT(port); 713 714 return vsc73xx_write_vlan_table_entry(vsc, vid, portmap); 715 } 716 717 static int vsc73xx_setup(struct dsa_switch *ds) 718 { 719 struct vsc73xx *vsc = ds->priv; 720 int i, ret; 721 722 dev_info(vsc->dev, "set up the switch\n"); 723 724 ds->untag_bridge_pvid = true; 725 ds->max_num_bridges = DSA_TAG_8021Q_MAX_NUM_BRIDGES; 726 727 /* Issue RESET */ 728 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET, 729 VSC73XX_GLORESET_MASTER_RESET); 730 usleep_range(125, 200); 731 732 /* Initialize memory, initialize RAM bank 0..15 except 6 and 7 733 * This sequence appears in the 734 * VSC7385 SparX-G5 datasheet section 6.6.1 735 * VSC7395 SparX-G5e datasheet section 6.6.1 736 * "initialization sequence". 737 * No explanation is given to the 0x1010400 magic number. 738 */ 739 for (i = 0; i <= 15; i++) { 740 if (i != 6 && i != 7) { 741 vsc73xx_write(vsc, VSC73XX_BLOCK_MEMINIT, 742 2, 743 0, 0x1010400 + i); 744 mdelay(1); 745 } 746 } 747 mdelay(30); 748 749 /* Clear MAC table */ 750 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, 751 VSC73XX_MACACCESS, 752 VSC73XX_MACACCESS_CMD_CLEAR_TABLE); 753 754 /* Set VLAN table to default values */ 755 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, 756 VSC73XX_VLANACCESS, 757 VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE); 758 759 msleep(40); 760 761 /* Use 20KiB buffers on all ports on VSC7395 762 * The VSC7385 has 16KiB buffers and that is the 763 * default if we don't set this up explicitly. 764 * Port "31" is "all ports". 765 */ 766 if (IS_739X(vsc)) 767 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 0x1f, 768 VSC73XX_Q_MISC_CONF, 769 VSC73XX_Q_MISC_CONF_EXTENT_MEM); 770 771 /* Put all ports into reset until enabled */ 772 for (i = 0; i < 7; i++) { 773 if (i == 5) 774 continue; 775 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 4, 776 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET); 777 } 778 779 /* MII delay, set both GTX and RX delay to 2 ns */ 780 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GMIIDELAY, 781 VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS | 782 VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS); 783 /* Ingess VLAN reception mask (table 145) */ 784 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANMASK, 785 0xff); 786 /* IP multicast flood mask (table 144) */ 787 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_IFLODMSK, 788 0xff); 789 790 mdelay(50); 791 792 /* Release reset from the internal PHYs */ 793 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET, 794 VSC73XX_GLORESET_PHY_RESET); 795 796 udelay(4); 797 798 /* Clear VLAN table */ 799 for (i = 0; i < VLAN_N_VID; i++) 800 vsc73xx_write_vlan_table_entry(vsc, i, 0); 801 802 INIT_LIST_HEAD(&vsc->vlans); 803 804 rtnl_lock(); 805 ret = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q)); 806 rtnl_unlock(); 807 808 return ret; 809 } 810 811 static void vsc73xx_teardown(struct dsa_switch *ds) 812 { 813 rtnl_lock(); 814 dsa_tag_8021q_unregister(ds); 815 rtnl_unlock(); 816 } 817 818 static void vsc73xx_init_port(struct vsc73xx *vsc, int port) 819 { 820 u32 val; 821 822 /* MAC configure, first reset the port and then write defaults */ 823 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 824 port, 825 VSC73XX_MAC_CFG, 826 VSC73XX_MAC_CFG_RESET); 827 828 /* Take up the port in 1Gbit mode by default, this will be 829 * augmented after auto-negotiation on the PHY-facing 830 * ports. 831 */ 832 if (port == CPU_PORT) 833 val = VSC73XX_MAC_CFG_1000M_F_RGMII; 834 else 835 val = VSC73XX_MAC_CFG_1000M_F_PHY; 836 837 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 838 port, 839 VSC73XX_MAC_CFG, 840 val | 841 VSC73XX_MAC_CFG_TX_EN | 842 VSC73XX_MAC_CFG_RX_EN); 843 844 /* Flow control for the CPU port: 845 * Use a zero delay pause frame when pause condition is left 846 * Obey pause control frames 847 */ 848 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 849 port, 850 VSC73XX_FCCONF, 851 VSC73XX_FCCONF_ZERO_PAUSE_EN | 852 VSC73XX_FCCONF_FLOW_CTRL_OBEY); 853 854 /* Issue pause control frames on PHY facing ports. 855 * Allow early initiation of MAC transmission if the amount 856 * of egress data is below 512 bytes on CPU port. 857 * FIXME: enable 20KiB buffers? 858 */ 859 if (port == CPU_PORT) 860 val = VSC73XX_Q_MISC_CONF_EARLY_TX_512; 861 else 862 val = VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE; 863 val |= VSC73XX_Q_MISC_CONF_EXTENT_MEM; 864 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 865 port, 866 VSC73XX_Q_MISC_CONF, 867 val); 868 869 /* Flow control MAC: a MAC address used in flow control frames */ 870 val = (vsc->addr[5] << 16) | (vsc->addr[4] << 8) | (vsc->addr[3]); 871 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 872 port, 873 VSC73XX_FCMACHI, 874 val); 875 val = (vsc->addr[2] << 16) | (vsc->addr[1] << 8) | (vsc->addr[0]); 876 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 877 port, 878 VSC73XX_FCMACLO, 879 val); 880 881 /* Tell the categorizer to forward pause frames, not control 882 * frame. Do not drop anything. 883 */ 884 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 885 port, 886 VSC73XX_CAT_DROP, 887 VSC73XX_CAT_DROP_FWD_PAUSE_ENA); 888 889 /* Clear all counters */ 890 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 891 port, VSC73XX_C_RX0, 0); 892 } 893 894 static void vsc73xx_reset_port(struct vsc73xx *vsc, int port, u32 initval) 895 { 896 int ret, err; 897 u32 val; 898 899 /* Disable RX on this port */ 900 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 901 VSC73XX_MAC_CFG, 902 VSC73XX_MAC_CFG_RX_EN, 0); 903 904 /* Discard packets */ 905 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 906 VSC73XX_ARBDISC, BIT(port), BIT(port)); 907 908 /* Wait until queue is empty */ 909 ret = read_poll_timeout(vsc73xx_read, err, 910 err < 0 || (val & BIT(port)), 911 VSC73XX_POLL_SLEEP_US, 912 VSC73XX_POLL_TIMEOUT_US, false, 913 vsc, VSC73XX_BLOCK_ARBITER, 0, 914 VSC73XX_ARBEMPTY, &val); 915 if (ret) 916 dev_err(vsc->dev, 917 "timeout waiting for block arbiter\n"); 918 else if (err < 0) 919 dev_err(vsc->dev, "error reading arbiter\n"); 920 921 /* Put this port into reset */ 922 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, 923 VSC73XX_MAC_CFG_RESET | initval); 924 } 925 926 static void vsc73xx_mac_config(struct phylink_config *config, unsigned int mode, 927 const struct phylink_link_state *state) 928 { 929 struct dsa_port *dp = dsa_phylink_to_port(config); 930 struct vsc73xx *vsc = dp->ds->priv; 931 int port = dp->index; 932 933 /* Special handling of the CPU-facing port */ 934 if (port == CPU_PORT) { 935 /* Other ports are already initialized but not this one */ 936 vsc73xx_init_port(vsc, CPU_PORT); 937 /* Select the external port for this interface (EXT_PORT) 938 * Enable the GMII GTX external clock 939 * Use double data rate (DDR mode) 940 */ 941 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 942 CPU_PORT, 943 VSC73XX_ADVPORTM, 944 VSC73XX_ADVPORTM_EXT_PORT | 945 VSC73XX_ADVPORTM_ENA_GTX | 946 VSC73XX_ADVPORTM_DDR_MODE); 947 } 948 } 949 950 static void vsc73xx_mac_link_down(struct phylink_config *config, 951 unsigned int mode, phy_interface_t interface) 952 { 953 struct dsa_port *dp = dsa_phylink_to_port(config); 954 struct vsc73xx *vsc = dp->ds->priv; 955 int port = dp->index; 956 957 /* This routine is described in the datasheet (below ARBDISC register 958 * description) 959 */ 960 vsc73xx_reset_port(vsc, port, 0); 961 962 /* Allow backward dropping of frames from this port */ 963 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 964 VSC73XX_SBACKWDROP, BIT(port), BIT(port)); 965 } 966 967 static void vsc73xx_mac_link_up(struct phylink_config *config, 968 struct phy_device *phy, unsigned int mode, 969 phy_interface_t interface, int speed, 970 int duplex, bool tx_pause, bool rx_pause) 971 { 972 struct dsa_port *dp = dsa_phylink_to_port(config); 973 struct vsc73xx *vsc = dp->ds->priv; 974 int port = dp->index; 975 u32 val; 976 u8 seed; 977 978 if (speed == SPEED_1000) 979 val = VSC73XX_MAC_CFG_GIGA_MODE | VSC73XX_MAC_CFG_TX_IPG_1000M; 980 else 981 val = VSC73XX_MAC_CFG_TX_IPG_100_10M; 982 983 if (phy_interface_mode_is_rgmii(interface)) 984 val |= VSC73XX_MAC_CFG_CLK_SEL_1000M; 985 else 986 val |= VSC73XX_MAC_CFG_CLK_SEL_EXT; 987 988 if (duplex == DUPLEX_FULL) 989 val |= VSC73XX_MAC_CFG_FDX; 990 else 991 /* In datasheet description ("Port Mode Procedure" in 5.6.2) 992 * this bit is configured only for half duplex. 993 */ 994 val |= VSC73XX_MAC_CFG_WEXC_DIS; 995 996 /* This routine is described in the datasheet (below ARBDISC register 997 * description) 998 */ 999 vsc73xx_reset_port(vsc, port, val); 1000 1001 /* Seed the port randomness with randomness */ 1002 get_random_bytes(&seed, 1); 1003 val |= seed << VSC73XX_MAC_CFG_SEED_OFFSET; 1004 val |= VSC73XX_MAC_CFG_SEED_LOAD; 1005 1006 /* Those bits are responsible for MTU only. Kernel takes care about MTU, 1007 * let's enable +8 bytes frame length unconditionally. 1008 */ 1009 val |= VSC73XX_MAC_CFG_VLAN_AWR | VSC73XX_MAC_CFG_VLAN_DBLAWR; 1010 1011 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val); 1012 1013 /* Flow control for the PHY facing ports: 1014 * Use a zero delay pause frame when pause condition is left 1015 * Obey pause control frames 1016 * When generating pause frames, use 0xff as pause value 1017 */ 1018 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_FCCONF, 1019 VSC73XX_FCCONF_ZERO_PAUSE_EN | 1020 VSC73XX_FCCONF_FLOW_CTRL_OBEY | 1021 0xff); 1022 1023 /* Accept packets again */ 1024 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 1025 VSC73XX_ARBDISC, BIT(port), 0); 1026 1027 /* Disallow backward dropping of frames from this port */ 1028 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 1029 VSC73XX_SBACKWDROP, BIT(port), 0); 1030 1031 /* Enable TX, RX, deassert reset, stop loading seed */ 1032 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1033 VSC73XX_MAC_CFG, 1034 VSC73XX_MAC_CFG_RESET | VSC73XX_MAC_CFG_SEED_LOAD | 1035 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN, 1036 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN); 1037 } 1038 1039 static bool vsc73xx_tag_8021q_active(struct dsa_port *dp) 1040 { 1041 return !dsa_port_is_vlan_filtering(dp); 1042 } 1043 1044 static struct vsc73xx_bridge_vlan * 1045 vsc73xx_bridge_vlan_find(struct vsc73xx *vsc, u16 vid) 1046 { 1047 struct vsc73xx_bridge_vlan *vlan; 1048 1049 list_for_each_entry(vlan, &vsc->vlans, list) 1050 if (vlan->vid == vid) 1051 return vlan; 1052 1053 return NULL; 1054 } 1055 1056 static void 1057 vsc73xx_bridge_vlan_remove_port(struct vsc73xx_bridge_vlan *vsc73xx_vlan, 1058 int port) 1059 { 1060 vsc73xx_vlan->portmask &= ~BIT(port); 1061 1062 if (vsc73xx_vlan->portmask) 1063 return; 1064 1065 list_del(&vsc73xx_vlan->list); 1066 kfree(vsc73xx_vlan); 1067 } 1068 1069 static void vsc73xx_bridge_vlan_summary(struct vsc73xx *vsc, int port, 1070 struct vsc73xx_vlan_summary *summary, 1071 u16 ignored_vid) 1072 { 1073 size_t num_tagged = 0, num_untagged = 0; 1074 struct vsc73xx_bridge_vlan *vlan; 1075 1076 list_for_each_entry(vlan, &vsc->vlans, list) { 1077 if (!(vlan->portmask & BIT(port)) || vlan->vid == ignored_vid) 1078 continue; 1079 1080 if (vlan->untagged & BIT(port)) 1081 num_untagged++; 1082 else 1083 num_tagged++; 1084 } 1085 1086 summary->num_untagged = num_untagged; 1087 summary->num_tagged = num_tagged; 1088 } 1089 1090 static u16 vsc73xx_find_first_vlan_untagged(struct vsc73xx *vsc, int port) 1091 { 1092 struct vsc73xx_bridge_vlan *vlan; 1093 1094 list_for_each_entry(vlan, &vsc->vlans, list) 1095 if ((vlan->portmask & BIT(port)) && 1096 (vlan->untagged & BIT(port))) 1097 return vlan->vid; 1098 1099 return VLAN_N_VID; 1100 } 1101 1102 static int vsc73xx_set_vlan_conf(struct vsc73xx *vsc, int port, 1103 enum vsc73xx_port_vlan_conf port_vlan_conf) 1104 { 1105 u32 val = 0; 1106 int ret; 1107 1108 if (port_vlan_conf == VSC73XX_VLAN_IGNORE) 1109 val = VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA | 1110 VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA; 1111 1112 ret = vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1113 VSC73XX_CAT_VLAN_MISC, 1114 VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA | 1115 VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA, val); 1116 if (ret) 1117 return ret; 1118 1119 val = (port_vlan_conf == VSC73XX_VLAN_FILTER) ? 1120 VSC73XX_TXUPDCFG_TX_INSERT_TAG : 0; 1121 1122 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1123 VSC73XX_TXUPDCFG, 1124 VSC73XX_TXUPDCFG_TX_INSERT_TAG, val); 1125 } 1126 1127 /** 1128 * vsc73xx_vlan_commit_conf - Update VLAN configuration of a port 1129 * @vsc: Switch private data structure 1130 * @port: Port index on which to operate 1131 * 1132 * Update the VLAN behavior of a port to make sure that when it is under 1133 * a VLAN filtering bridge, the port is either filtering with tag 1134 * preservation, or filtering with all VLANs egress-untagged. Otherwise, 1135 * the port ignores VLAN tags from packets and applies the port-based 1136 * VID. 1137 * 1138 * Must be called when changes are made to: 1139 * - the bridge VLAN filtering state of the port 1140 * - the number or attributes of VLANs from the bridge VLAN table, 1141 * while the port is currently VLAN-aware 1142 * 1143 * Return: 0 on success, or negative errno on error. 1144 */ 1145 static int vsc73xx_vlan_commit_conf(struct vsc73xx *vsc, int port) 1146 { 1147 enum vsc73xx_port_vlan_conf port_vlan_conf = VSC73XX_VLAN_IGNORE; 1148 struct dsa_port *dp = dsa_to_port(vsc->ds, port); 1149 1150 if (port == CPU_PORT) { 1151 port_vlan_conf = VSC73XX_VLAN_FILTER; 1152 } else if (dsa_port_is_vlan_filtering(dp)) { 1153 struct vsc73xx_vlan_summary summary; 1154 1155 port_vlan_conf = VSC73XX_VLAN_FILTER; 1156 1157 vsc73xx_bridge_vlan_summary(vsc, port, &summary, VLAN_N_VID); 1158 if (summary.num_tagged == 0) 1159 port_vlan_conf = VSC73XX_VLAN_FILTER_UNTAG_ALL; 1160 } 1161 1162 return vsc73xx_set_vlan_conf(vsc, port, port_vlan_conf); 1163 } 1164 1165 static int 1166 vsc73xx_vlan_change_untagged(struct vsc73xx *vsc, int port, u16 vid, bool set) 1167 { 1168 u32 val = 0; 1169 1170 if (set) 1171 val = VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA | 1172 ((vid << VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_SHIFT) & 1173 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID); 1174 1175 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1176 VSC73XX_TXUPDCFG, 1177 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA | 1178 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID, val); 1179 } 1180 1181 /** 1182 * vsc73xx_vlan_commit_untagged - Update native VLAN of a port 1183 * @vsc: Switch private data structure 1184 * @port: Port index on which to operate 1185 * 1186 * Update the native VLAN of a port (the one VLAN which is transmitted 1187 * as egress-tagged on a trunk port) when port is in VLAN filtering mode and 1188 * only one untagged vid is configured. 1189 * In other cases no need to configure it because switch can untag all vlans on 1190 * the port. 1191 * 1192 * Return: 0 on success, or negative errno on error. 1193 */ 1194 static int vsc73xx_vlan_commit_untagged(struct vsc73xx *vsc, int port) 1195 { 1196 struct dsa_port *dp = dsa_to_port(vsc->ds, port); 1197 struct vsc73xx_vlan_summary summary; 1198 u16 vid = 0; 1199 bool valid; 1200 1201 if (!dsa_port_is_vlan_filtering(dp)) 1202 /* Port is configured to untag all vlans in that case. 1203 * No need to commit untagged config change. 1204 */ 1205 return 0; 1206 1207 vsc73xx_bridge_vlan_summary(vsc, port, &summary, VLAN_N_VID); 1208 1209 if (summary.num_untagged > 1) 1210 /* Port must untag all vlans in that case. 1211 * No need to commit untagged config change. 1212 */ 1213 return 0; 1214 1215 valid = (summary.num_untagged == 1); 1216 if (valid) 1217 vid = vsc73xx_find_first_vlan_untagged(vsc, port); 1218 1219 return vsc73xx_vlan_change_untagged(vsc, port, vid, valid); 1220 } 1221 1222 static int 1223 vsc73xx_vlan_change_pvid(struct vsc73xx *vsc, int port, u16 vid, bool set) 1224 { 1225 u32 val = 0; 1226 int ret; 1227 1228 val = set ? 0 : VSC73XX_CAT_DROP_UNTAGGED_ENA; 1229 1230 ret = vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1231 VSC73XX_CAT_DROP, 1232 VSC73XX_CAT_DROP_UNTAGGED_ENA, val); 1233 if (!set || ret) 1234 return ret; 1235 1236 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1237 VSC73XX_CAT_PORT_VLAN, 1238 VSC73XX_CAT_PORT_VLAN_VLAN_VID, 1239 vid & VSC73XX_CAT_PORT_VLAN_VLAN_VID); 1240 } 1241 1242 /** 1243 * vsc73xx_vlan_commit_pvid - Update port-based default VLAN of a port 1244 * @vsc: Switch private data structure 1245 * @port: Port index on which to operate 1246 * 1247 * Update the PVID of a port so that it follows either the bridge PVID 1248 * configuration, when the bridge is currently VLAN-aware, or the PVID 1249 * from tag_8021q, when the port is standalone or under a VLAN-unaware 1250 * bridge. A port with no PVID drops all untagged and VID 0 tagged 1251 * traffic. 1252 * 1253 * Must be called when changes are made to: 1254 * - the bridge VLAN filtering state of the port 1255 * - the number or attributes of VLANs from the bridge VLAN table, 1256 * while the port is currently VLAN-aware 1257 * 1258 * Return: 0 on success, or negative errno on error. 1259 */ 1260 static int vsc73xx_vlan_commit_pvid(struct vsc73xx *vsc, int port) 1261 { 1262 struct vsc73xx_portinfo *portinfo = &vsc->portinfo[port]; 1263 bool valid = portinfo->pvid_tag_8021q_configured; 1264 struct dsa_port *dp = dsa_to_port(vsc->ds, port); 1265 u16 vid = portinfo->pvid_tag_8021q; 1266 1267 if (dsa_port_is_vlan_filtering(dp)) { 1268 vid = portinfo->pvid_vlan_filtering; 1269 valid = portinfo->pvid_vlan_filtering_configured; 1270 } 1271 1272 return vsc73xx_vlan_change_pvid(vsc, port, vid, valid); 1273 } 1274 1275 static int vsc73xx_vlan_commit_settings(struct vsc73xx *vsc, int port) 1276 { 1277 int ret; 1278 1279 ret = vsc73xx_vlan_commit_untagged(vsc, port); 1280 if (ret) 1281 return ret; 1282 1283 ret = vsc73xx_vlan_commit_pvid(vsc, port); 1284 if (ret) 1285 return ret; 1286 1287 return vsc73xx_vlan_commit_conf(vsc, port); 1288 } 1289 1290 static int vsc73xx_port_enable(struct dsa_switch *ds, int port, 1291 struct phy_device *phy) 1292 { 1293 struct vsc73xx *vsc = ds->priv; 1294 1295 dev_info(vsc->dev, "enable port %d\n", port); 1296 vsc73xx_init_port(vsc, port); 1297 1298 return vsc73xx_vlan_commit_settings(vsc, port); 1299 } 1300 1301 static void vsc73xx_port_disable(struct dsa_switch *ds, int port) 1302 { 1303 struct vsc73xx *vsc = ds->priv; 1304 1305 /* Just put the port into reset */ 1306 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, 1307 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET); 1308 } 1309 1310 static const struct vsc73xx_counter * 1311 vsc73xx_find_counter(struct vsc73xx *vsc, 1312 u8 counter, 1313 bool tx) 1314 { 1315 const struct vsc73xx_counter *cnts; 1316 int num_cnts; 1317 int i; 1318 1319 if (tx) { 1320 cnts = vsc73xx_tx_counters; 1321 num_cnts = ARRAY_SIZE(vsc73xx_tx_counters); 1322 } else { 1323 cnts = vsc73xx_rx_counters; 1324 num_cnts = ARRAY_SIZE(vsc73xx_rx_counters); 1325 } 1326 1327 for (i = 0; i < num_cnts; i++) { 1328 const struct vsc73xx_counter *cnt; 1329 1330 cnt = &cnts[i]; 1331 if (cnt->counter == counter) 1332 return cnt; 1333 } 1334 1335 return NULL; 1336 } 1337 1338 static void vsc73xx_get_strings(struct dsa_switch *ds, int port, u32 stringset, 1339 uint8_t *data) 1340 { 1341 const struct vsc73xx_counter *cnt; 1342 struct vsc73xx *vsc = ds->priv; 1343 u8 indices[6]; 1344 u8 *buf = data; 1345 int i; 1346 u32 val; 1347 int ret; 1348 1349 if (stringset != ETH_SS_STATS) 1350 return; 1351 1352 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port, 1353 VSC73XX_C_CFG, &val); 1354 if (ret) 1355 return; 1356 1357 indices[0] = (val & 0x1f); /* RX counter 0 */ 1358 indices[1] = ((val >> 5) & 0x1f); /* RX counter 1 */ 1359 indices[2] = ((val >> 10) & 0x1f); /* RX counter 2 */ 1360 indices[3] = ((val >> 16) & 0x1f); /* TX counter 0 */ 1361 indices[4] = ((val >> 21) & 0x1f); /* TX counter 1 */ 1362 indices[5] = ((val >> 26) & 0x1f); /* TX counter 2 */ 1363 1364 /* The first counters is the RX octets */ 1365 ethtool_puts(&buf, "RxEtherStatsOctets"); 1366 1367 /* Each port supports recording 3 RX counters and 3 TX counters, 1368 * figure out what counters we use in this set-up and return the 1369 * names of them. The hardware default counters will be number of 1370 * packets on RX/TX, combined broadcast+multicast packets RX/TX and 1371 * total error packets RX/TX. 1372 */ 1373 for (i = 0; i < 3; i++) { 1374 cnt = vsc73xx_find_counter(vsc, indices[i], false); 1375 ethtool_puts(&buf, cnt ? cnt->name : ""); 1376 } 1377 1378 /* TX stats begins with the number of TX octets */ 1379 ethtool_puts(&buf, "TxEtherStatsOctets"); 1380 1381 for (i = 3; i < 6; i++) { 1382 cnt = vsc73xx_find_counter(vsc, indices[i], true); 1383 ethtool_puts(&buf, cnt ? cnt->name : ""); 1384 1385 } 1386 } 1387 1388 static int vsc73xx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1389 { 1390 /* We only support SS_STATS */ 1391 if (sset != ETH_SS_STATS) 1392 return 0; 1393 /* RX and TX packets, then 3 RX counters, 3 TX counters */ 1394 return 8; 1395 } 1396 1397 static void vsc73xx_get_ethtool_stats(struct dsa_switch *ds, int port, 1398 uint64_t *data) 1399 { 1400 struct vsc73xx *vsc = ds->priv; 1401 u8 regs[] = { 1402 VSC73XX_RXOCT, 1403 VSC73XX_C_RX0, 1404 VSC73XX_C_RX1, 1405 VSC73XX_C_RX2, 1406 VSC73XX_TXOCT, 1407 VSC73XX_C_TX0, 1408 VSC73XX_C_TX1, 1409 VSC73XX_C_TX2, 1410 }; 1411 u32 val; 1412 int ret; 1413 int i; 1414 1415 for (i = 0; i < ARRAY_SIZE(regs); i++) { 1416 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port, 1417 regs[i], &val); 1418 if (ret) { 1419 dev_err(vsc->dev, "error reading counter %d\n", i); 1420 return; 1421 } 1422 data[i] = val; 1423 } 1424 } 1425 1426 static int vsc73xx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1427 { 1428 struct vsc73xx *vsc = ds->priv; 1429 1430 return vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, 1431 VSC73XX_MAXLEN, new_mtu + ETH_HLEN + ETH_FCS_LEN); 1432 } 1433 1434 /* According to application not "VSC7398 Jumbo Frames" setting 1435 * up the frame size to 9.6 KB does not affect the performance on standard 1436 * frames. It is clear from the application note that 1437 * "9.6 kilobytes" == 9600 bytes. 1438 */ 1439 static int vsc73xx_get_max_mtu(struct dsa_switch *ds, int port) 1440 { 1441 return 9600 - ETH_HLEN - ETH_FCS_LEN; 1442 } 1443 1444 static void vsc73xx_phylink_get_caps(struct dsa_switch *dsa, int port, 1445 struct phylink_config *config) 1446 { 1447 unsigned long *interfaces = config->supported_interfaces; 1448 1449 if (port == 5) 1450 return; 1451 1452 if (port == CPU_PORT) { 1453 __set_bit(PHY_INTERFACE_MODE_MII, interfaces); 1454 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces); 1455 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces); 1456 __set_bit(PHY_INTERFACE_MODE_RGMII, interfaces); 1457 } 1458 1459 if (port <= 4) { 1460 /* Internal PHYs */ 1461 __set_bit(PHY_INTERFACE_MODE_INTERNAL, interfaces); 1462 /* phylib default */ 1463 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces); 1464 } 1465 1466 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000; 1467 } 1468 1469 static int 1470 vsc73xx_port_vlan_filtering(struct dsa_switch *ds, int port, 1471 bool vlan_filtering, struct netlink_ext_ack *extack) 1472 { 1473 struct vsc73xx *vsc = ds->priv; 1474 1475 /* The commit to hardware processed below is required because vsc73xx 1476 * is using tag_8021q. When vlan_filtering is disabled, tag_8021q uses 1477 * pvid/untagged vlans for port recognition. The values configured for 1478 * vlans and pvid/untagged states are stored in portinfo structure. 1479 * When vlan_filtering is enabled, we need to restore pvid/untagged from 1480 * portinfo structure. Analogous routine is processed when 1481 * vlan_filtering is disabled, but values used for tag_8021q are 1482 * restored. 1483 */ 1484 1485 return vsc73xx_vlan_commit_settings(vsc, port); 1486 } 1487 1488 static int vsc73xx_port_vlan_add(struct dsa_switch *ds, int port, 1489 const struct switchdev_obj_port_vlan *vlan, 1490 struct netlink_ext_ack *extack) 1491 { 1492 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1493 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1494 struct dsa_port *dp = dsa_to_port(ds, port); 1495 struct vsc73xx_bridge_vlan *vsc73xx_vlan; 1496 struct vsc73xx_vlan_summary summary; 1497 struct vsc73xx_portinfo *portinfo; 1498 struct vsc73xx *vsc = ds->priv; 1499 bool commit_to_hardware; 1500 int ret = 0; 1501 1502 /* Be sure to deny alterations to the configuration done by tag_8021q. 1503 */ 1504 if (vid_is_dsa_8021q(vlan->vid)) { 1505 NL_SET_ERR_MSG_MOD(extack, 1506 "Range 3072-4095 reserved for dsa_8021q operation"); 1507 return -EBUSY; 1508 } 1509 1510 /* The processed vlan->vid is excluded from the search because the VLAN 1511 * can be re-added with a different set of flags, so it's easiest to 1512 * ignore its old flags from the VLAN database software copy. 1513 */ 1514 vsc73xx_bridge_vlan_summary(vsc, port, &summary, vlan->vid); 1515 1516 /* VSC73XX allows only three untagged states: none, one or all */ 1517 if ((untagged && summary.num_tagged > 0 && summary.num_untagged > 0) || 1518 (!untagged && summary.num_untagged > 1)) { 1519 NL_SET_ERR_MSG_MOD(extack, 1520 "Port can have only none, one or all untagged vlan"); 1521 return -EBUSY; 1522 } 1523 1524 vsc73xx_vlan = vsc73xx_bridge_vlan_find(vsc, vlan->vid); 1525 1526 if (!vsc73xx_vlan) { 1527 vsc73xx_vlan = kzalloc(sizeof(*vsc73xx_vlan), GFP_KERNEL); 1528 if (!vsc73xx_vlan) 1529 return -ENOMEM; 1530 1531 vsc73xx_vlan->vid = vlan->vid; 1532 1533 list_add_tail(&vsc73xx_vlan->list, &vsc->vlans); 1534 } 1535 1536 vsc73xx_vlan->portmask |= BIT(port); 1537 1538 /* CPU port must be always tagged because source port identification is 1539 * based on tag_8021q. 1540 */ 1541 if (port == CPU_PORT) 1542 goto update_vlan_table; 1543 1544 if (untagged) 1545 vsc73xx_vlan->untagged |= BIT(port); 1546 else 1547 vsc73xx_vlan->untagged &= ~BIT(port); 1548 1549 portinfo = &vsc->portinfo[port]; 1550 1551 if (pvid) { 1552 portinfo->pvid_vlan_filtering_configured = true; 1553 portinfo->pvid_vlan_filtering = vlan->vid; 1554 } else if (portinfo->pvid_vlan_filtering_configured && 1555 portinfo->pvid_vlan_filtering == vlan->vid) { 1556 portinfo->pvid_vlan_filtering_configured = false; 1557 } 1558 1559 commit_to_hardware = !vsc73xx_tag_8021q_active(dp); 1560 if (commit_to_hardware) { 1561 ret = vsc73xx_vlan_commit_settings(vsc, port); 1562 if (ret) 1563 goto err; 1564 } 1565 1566 update_vlan_table: 1567 ret = vsc73xx_update_vlan_table(vsc, port, vlan->vid, true); 1568 if (!ret) 1569 return 0; 1570 err: 1571 vsc73xx_bridge_vlan_remove_port(vsc73xx_vlan, port); 1572 return ret; 1573 } 1574 1575 static int vsc73xx_port_vlan_del(struct dsa_switch *ds, int port, 1576 const struct switchdev_obj_port_vlan *vlan) 1577 { 1578 struct vsc73xx_bridge_vlan *vsc73xx_vlan; 1579 struct vsc73xx_portinfo *portinfo; 1580 struct vsc73xx *vsc = ds->priv; 1581 bool commit_to_hardware; 1582 int ret; 1583 1584 ret = vsc73xx_update_vlan_table(vsc, port, vlan->vid, false); 1585 if (ret) 1586 return ret; 1587 1588 portinfo = &vsc->portinfo[port]; 1589 1590 if (portinfo->pvid_vlan_filtering_configured && 1591 portinfo->pvid_vlan_filtering == vlan->vid) 1592 portinfo->pvid_vlan_filtering_configured = false; 1593 1594 vsc73xx_vlan = vsc73xx_bridge_vlan_find(vsc, vlan->vid); 1595 1596 if (vsc73xx_vlan) 1597 vsc73xx_bridge_vlan_remove_port(vsc73xx_vlan, port); 1598 1599 commit_to_hardware = !vsc73xx_tag_8021q_active(dsa_to_port(ds, port)); 1600 1601 if (commit_to_hardware) 1602 return vsc73xx_vlan_commit_settings(vsc, port); 1603 1604 return 0; 1605 } 1606 1607 static int vsc73xx_tag_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid, 1608 u16 flags) 1609 { 1610 bool pvid = flags & BRIDGE_VLAN_INFO_PVID; 1611 struct vsc73xx_portinfo *portinfo; 1612 struct vsc73xx *vsc = ds->priv; 1613 bool commit_to_hardware; 1614 int ret; 1615 1616 portinfo = &vsc->portinfo[port]; 1617 1618 if (pvid) { 1619 portinfo->pvid_tag_8021q_configured = true; 1620 portinfo->pvid_tag_8021q = vid; 1621 } 1622 1623 commit_to_hardware = vsc73xx_tag_8021q_active(dsa_to_port(ds, port)); 1624 if (commit_to_hardware) { 1625 ret = vsc73xx_vlan_commit_settings(vsc, port); 1626 if (ret) 1627 return ret; 1628 } 1629 1630 return vsc73xx_update_vlan_table(vsc, port, vid, true); 1631 } 1632 1633 static int vsc73xx_tag_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid) 1634 { 1635 struct vsc73xx_portinfo *portinfo; 1636 struct vsc73xx *vsc = ds->priv; 1637 1638 portinfo = &vsc->portinfo[port]; 1639 1640 if (portinfo->pvid_tag_8021q_configured && 1641 portinfo->pvid_tag_8021q == vid) { 1642 struct dsa_port *dp = dsa_to_port(ds, port); 1643 bool commit_to_hardware; 1644 int err; 1645 1646 portinfo->pvid_tag_8021q_configured = false; 1647 1648 commit_to_hardware = vsc73xx_tag_8021q_active(dp); 1649 if (commit_to_hardware) { 1650 err = vsc73xx_vlan_commit_settings(vsc, port); 1651 if (err) 1652 return err; 1653 } 1654 } 1655 1656 return vsc73xx_update_vlan_table(vsc, port, vid, false); 1657 } 1658 1659 static int vsc73xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1660 struct switchdev_brport_flags flags, 1661 struct netlink_ext_ack *extack) 1662 { 1663 if (flags.mask & ~BR_LEARNING) 1664 return -EINVAL; 1665 1666 return 0; 1667 } 1668 1669 static int vsc73xx_port_bridge_flags(struct dsa_switch *ds, int port, 1670 struct switchdev_brport_flags flags, 1671 struct netlink_ext_ack *extack) 1672 { 1673 if (flags.mask & BR_LEARNING) { 1674 u32 val = flags.val & BR_LEARNING ? BIT(port) : 0; 1675 struct vsc73xx *vsc = ds->priv; 1676 1677 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1678 VSC73XX_LEARNMASK, BIT(port), val); 1679 } 1680 1681 return 0; 1682 } 1683 1684 static void vsc73xx_refresh_fwd_map(struct dsa_switch *ds, int port, u8 state) 1685 { 1686 struct dsa_port *other_dp, *dp = dsa_to_port(ds, port); 1687 struct vsc73xx *vsc = ds->priv; 1688 u16 mask; 1689 1690 if (state != BR_STATE_FORWARDING) { 1691 /* Ports that aren't in the forwarding state must not 1692 * forward packets anywhere. 1693 */ 1694 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1695 VSC73XX_SRCMASKS + port, 1696 VSC73XX_SRCMASKS_PORTS_MASK, 0); 1697 1698 dsa_switch_for_each_available_port(other_dp, ds) { 1699 if (other_dp == dp) 1700 continue; 1701 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1702 VSC73XX_SRCMASKS + other_dp->index, 1703 BIT(port), 0); 1704 } 1705 1706 return; 1707 } 1708 1709 /* Forwarding ports must forward to the CPU and to other ports 1710 * in the same bridge 1711 */ 1712 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1713 VSC73XX_SRCMASKS + CPU_PORT, BIT(port), BIT(port)); 1714 1715 mask = BIT(CPU_PORT); 1716 1717 dsa_switch_for_each_user_port(other_dp, ds) { 1718 int other_port = other_dp->index; 1719 1720 if (port == other_port || !dsa_port_bridge_same(dp, other_dp) || 1721 other_dp->stp_state != BR_STATE_FORWARDING) 1722 continue; 1723 1724 mask |= BIT(other_port); 1725 1726 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1727 VSC73XX_SRCMASKS + other_port, 1728 BIT(port), BIT(port)); 1729 } 1730 1731 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1732 VSC73XX_SRCMASKS + port, 1733 VSC73XX_SRCMASKS_PORTS_MASK, mask); 1734 } 1735 1736 /* FIXME: STP frames aren't forwarded at this moment. BPDU frames are 1737 * forwarded only from and to PI/SI interface. For more info see chapter 1738 * 2.7.1 (CPU Forwarding) in datasheet. 1739 * This function is required for tag_8021q operations. 1740 */ 1741 static void vsc73xx_port_stp_state_set(struct dsa_switch *ds, int port, 1742 u8 state) 1743 { 1744 struct dsa_port *dp = dsa_to_port(ds, port); 1745 struct vsc73xx *vsc = ds->priv; 1746 u32 val = 0; 1747 1748 if (state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) 1749 val = dp->learning ? BIT(port) : 0; 1750 1751 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1752 VSC73XX_LEARNMASK, BIT(port), val); 1753 1754 val = (state == BR_STATE_BLOCKING || state == BR_STATE_DISABLED) ? 1755 0 : BIT(port); 1756 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1757 VSC73XX_RECVMASK, BIT(port), val); 1758 1759 /* CPU Port should always forward packets when user ports are forwarding 1760 * so let's configure it from other ports only. 1761 */ 1762 if (port != CPU_PORT) 1763 vsc73xx_refresh_fwd_map(ds, port, state); 1764 } 1765 1766 static const struct phylink_mac_ops vsc73xx_phylink_mac_ops = { 1767 .mac_config = vsc73xx_mac_config, 1768 .mac_link_down = vsc73xx_mac_link_down, 1769 .mac_link_up = vsc73xx_mac_link_up, 1770 }; 1771 1772 static const struct dsa_switch_ops vsc73xx_ds_ops = { 1773 .get_tag_protocol = vsc73xx_get_tag_protocol, 1774 .setup = vsc73xx_setup, 1775 .teardown = vsc73xx_teardown, 1776 .phy_read = vsc73xx_phy_read, 1777 .phy_write = vsc73xx_phy_write, 1778 .get_strings = vsc73xx_get_strings, 1779 .get_ethtool_stats = vsc73xx_get_ethtool_stats, 1780 .get_sset_count = vsc73xx_get_sset_count, 1781 .port_enable = vsc73xx_port_enable, 1782 .port_disable = vsc73xx_port_disable, 1783 .port_pre_bridge_flags = vsc73xx_port_pre_bridge_flags, 1784 .port_bridge_flags = vsc73xx_port_bridge_flags, 1785 .port_bridge_join = dsa_tag_8021q_bridge_join, 1786 .port_bridge_leave = dsa_tag_8021q_bridge_leave, 1787 .port_change_mtu = vsc73xx_change_mtu, 1788 .port_max_mtu = vsc73xx_get_max_mtu, 1789 .port_stp_state_set = vsc73xx_port_stp_state_set, 1790 .port_vlan_filtering = vsc73xx_port_vlan_filtering, 1791 .port_vlan_add = vsc73xx_port_vlan_add, 1792 .port_vlan_del = vsc73xx_port_vlan_del, 1793 .phylink_get_caps = vsc73xx_phylink_get_caps, 1794 .tag_8021q_vlan_add = vsc73xx_tag_8021q_vlan_add, 1795 .tag_8021q_vlan_del = vsc73xx_tag_8021q_vlan_del, 1796 }; 1797 1798 static int vsc73xx_gpio_get(struct gpio_chip *chip, unsigned int offset) 1799 { 1800 struct vsc73xx *vsc = gpiochip_get_data(chip); 1801 u32 val; 1802 int ret; 1803 1804 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1805 VSC73XX_GPIO, &val); 1806 if (ret) 1807 return ret; 1808 1809 return !!(val & BIT(offset)); 1810 } 1811 1812 static void vsc73xx_gpio_set(struct gpio_chip *chip, unsigned int offset, 1813 int val) 1814 { 1815 struct vsc73xx *vsc = gpiochip_get_data(chip); 1816 u32 tmp = val ? BIT(offset) : 0; 1817 1818 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1819 VSC73XX_GPIO, BIT(offset), tmp); 1820 } 1821 1822 static int vsc73xx_gpio_direction_output(struct gpio_chip *chip, 1823 unsigned int offset, int val) 1824 { 1825 struct vsc73xx *vsc = gpiochip_get_data(chip); 1826 u32 tmp = val ? BIT(offset) : 0; 1827 1828 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1829 VSC73XX_GPIO, BIT(offset + 4) | BIT(offset), 1830 BIT(offset + 4) | tmp); 1831 } 1832 1833 static int vsc73xx_gpio_direction_input(struct gpio_chip *chip, 1834 unsigned int offset) 1835 { 1836 struct vsc73xx *vsc = gpiochip_get_data(chip); 1837 1838 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1839 VSC73XX_GPIO, BIT(offset + 4), 1840 0); 1841 } 1842 1843 static int vsc73xx_gpio_get_direction(struct gpio_chip *chip, 1844 unsigned int offset) 1845 { 1846 struct vsc73xx *vsc = gpiochip_get_data(chip); 1847 u32 val; 1848 int ret; 1849 1850 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1851 VSC73XX_GPIO, &val); 1852 if (ret) 1853 return ret; 1854 1855 return !(val & BIT(offset + 4)); 1856 } 1857 1858 static int vsc73xx_gpio_probe(struct vsc73xx *vsc) 1859 { 1860 int ret; 1861 1862 vsc->gc.label = devm_kasprintf(vsc->dev, GFP_KERNEL, "VSC%04x", 1863 vsc->chipid); 1864 if (!vsc->gc.label) 1865 return -ENOMEM; 1866 vsc->gc.ngpio = 4; 1867 vsc->gc.owner = THIS_MODULE; 1868 vsc->gc.parent = vsc->dev; 1869 vsc->gc.base = -1; 1870 vsc->gc.get = vsc73xx_gpio_get; 1871 vsc->gc.set = vsc73xx_gpio_set; 1872 vsc->gc.direction_input = vsc73xx_gpio_direction_input; 1873 vsc->gc.direction_output = vsc73xx_gpio_direction_output; 1874 vsc->gc.get_direction = vsc73xx_gpio_get_direction; 1875 vsc->gc.can_sleep = true; 1876 ret = devm_gpiochip_add_data(vsc->dev, &vsc->gc, vsc); 1877 if (ret) { 1878 dev_err(vsc->dev, "unable to register GPIO chip\n"); 1879 return ret; 1880 } 1881 return 0; 1882 } 1883 1884 int vsc73xx_probe(struct vsc73xx *vsc) 1885 { 1886 struct device *dev = vsc->dev; 1887 int ret; 1888 1889 /* Release reset, if any */ 1890 vsc->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1891 if (IS_ERR(vsc->reset)) { 1892 dev_err(dev, "failed to get RESET GPIO\n"); 1893 return PTR_ERR(vsc->reset); 1894 } 1895 if (vsc->reset) 1896 /* Wait 20ms according to datasheet table 245 */ 1897 msleep(20); 1898 1899 ret = vsc73xx_detect(vsc); 1900 if (ret == -EAGAIN) { 1901 dev_err(vsc->dev, 1902 "Chip seems to be out of control. Assert reset and try again.\n"); 1903 gpiod_set_value_cansleep(vsc->reset, 1); 1904 /* Reset pulse should be 20ns minimum, according to datasheet 1905 * table 245, so 10us should be fine 1906 */ 1907 usleep_range(10, 100); 1908 gpiod_set_value_cansleep(vsc->reset, 0); 1909 /* Wait 20ms according to datasheet table 245 */ 1910 msleep(20); 1911 ret = vsc73xx_detect(vsc); 1912 } 1913 if (ret) { 1914 dev_err(dev, "no chip found (%d)\n", ret); 1915 return -ENODEV; 1916 } 1917 1918 eth_random_addr(vsc->addr); 1919 dev_info(vsc->dev, 1920 "MAC for control frames: %02X:%02X:%02X:%02X:%02X:%02X\n", 1921 vsc->addr[0], vsc->addr[1], vsc->addr[2], 1922 vsc->addr[3], vsc->addr[4], vsc->addr[5]); 1923 1924 vsc->ds = devm_kzalloc(dev, sizeof(*vsc->ds), GFP_KERNEL); 1925 if (!vsc->ds) 1926 return -ENOMEM; 1927 1928 vsc->ds->dev = dev; 1929 vsc->ds->num_ports = VSC73XX_MAX_NUM_PORTS; 1930 vsc->ds->priv = vsc; 1931 1932 vsc->ds->ops = &vsc73xx_ds_ops; 1933 vsc->ds->phylink_mac_ops = &vsc73xx_phylink_mac_ops; 1934 ret = dsa_register_switch(vsc->ds); 1935 if (ret) { 1936 dev_err(dev, "unable to register switch (%d)\n", ret); 1937 return ret; 1938 } 1939 1940 ret = vsc73xx_gpio_probe(vsc); 1941 if (ret) { 1942 dsa_unregister_switch(vsc->ds); 1943 return ret; 1944 } 1945 1946 return 0; 1947 } 1948 EXPORT_SYMBOL(vsc73xx_probe); 1949 1950 void vsc73xx_remove(struct vsc73xx *vsc) 1951 { 1952 dsa_unregister_switch(vsc->ds); 1953 gpiod_set_value(vsc->reset, 1); 1954 } 1955 EXPORT_SYMBOL(vsc73xx_remove); 1956 1957 void vsc73xx_shutdown(struct vsc73xx *vsc) 1958 { 1959 dsa_switch_shutdown(vsc->ds); 1960 } 1961 EXPORT_SYMBOL(vsc73xx_shutdown); 1962 1963 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>"); 1964 MODULE_DESCRIPTION("Vitesse VSC7385/7388/7395/7398 driver"); 1965 MODULE_LICENSE("GPL v2"); 1966