1 // SPDX-License-Identifier: GPL-2.0 2 /* DSA driver for: 3 * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch 4 * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch 5 * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch 6 * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch 7 * 8 * These switches have a built-in 8051 CPU and can download and execute a 9 * firmware in this CPU. They can also be configured to use an external CPU 10 * handling the switch in a memory-mapped manner by connecting to that external 11 * CPU's memory bus. 12 * 13 * Copyright (C) 2018 Linus Wallej <linus.walleij@linaro.org> 14 * Includes portions of code from the firmware uploader by: 15 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> 16 */ 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/device.h> 20 #include <linux/iopoll.h> 21 #include <linux/of.h> 22 #include <linux/of_mdio.h> 23 #include <linux/bitops.h> 24 #include <linux/if_bridge.h> 25 #include <linux/etherdevice.h> 26 #include <linux/gpio/consumer.h> 27 #include <linux/gpio/driver.h> 28 #include <linux/random.h> 29 #include <net/dsa.h> 30 31 #include "vitesse-vsc73xx.h" 32 33 #define VSC73XX_BLOCK_MAC 0x1 /* Subblocks 0-4, 6 (CPU port) */ 34 #define VSC73XX_BLOCK_ANALYZER 0x2 /* Only subblock 0 */ 35 #define VSC73XX_BLOCK_MII 0x3 /* Subblocks 0 and 1 */ 36 #define VSC73XX_BLOCK_MEMINIT 0x3 /* Only subblock 2 */ 37 #define VSC73XX_BLOCK_CAPTURE 0x4 /* Only subblock 2 */ 38 #define VSC73XX_BLOCK_ARBITER 0x5 /* Only subblock 0 */ 39 #define VSC73XX_BLOCK_SYSTEM 0x7 /* Only subblock 0 */ 40 41 #define CPU_PORT 6 /* CPU port */ 42 43 /* MAC Block registers */ 44 #define VSC73XX_MAC_CFG 0x00 45 #define VSC73XX_MACHDXGAP 0x02 46 #define VSC73XX_FCCONF 0x04 47 #define VSC73XX_FCMACHI 0x08 48 #define VSC73XX_FCMACLO 0x0c 49 #define VSC73XX_MAXLEN 0x10 50 #define VSC73XX_ADVPORTM 0x19 51 #define VSC73XX_TXUPDCFG 0x24 52 #define VSC73XX_TXQ_SELECT_CFG 0x28 53 #define VSC73XX_RXOCT 0x50 54 #define VSC73XX_TXOCT 0x51 55 #define VSC73XX_C_RX0 0x52 56 #define VSC73XX_C_RX1 0x53 57 #define VSC73XX_C_RX2 0x54 58 #define VSC73XX_C_TX0 0x55 59 #define VSC73XX_C_TX1 0x56 60 #define VSC73XX_C_TX2 0x57 61 #define VSC73XX_C_CFG 0x58 62 #define VSC73XX_CAT_DROP 0x6e 63 #define VSC73XX_CAT_PR_MISC_L2 0x6f 64 #define VSC73XX_CAT_PR_USR_PRIO 0x75 65 #define VSC73XX_Q_MISC_CONF 0xdf 66 67 /* MAC_CFG register bits */ 68 #define VSC73XX_MAC_CFG_WEXC_DIS BIT(31) 69 #define VSC73XX_MAC_CFG_PORT_RST BIT(29) 70 #define VSC73XX_MAC_CFG_TX_EN BIT(28) 71 #define VSC73XX_MAC_CFG_SEED_LOAD BIT(27) 72 #define VSC73XX_MAC_CFG_SEED_MASK GENMASK(26, 19) 73 #define VSC73XX_MAC_CFG_SEED_OFFSET 19 74 #define VSC73XX_MAC_CFG_FDX BIT(18) 75 #define VSC73XX_MAC_CFG_GIGA_MODE BIT(17) 76 #define VSC73XX_MAC_CFG_RX_EN BIT(16) 77 #define VSC73XX_MAC_CFG_VLAN_DBLAWR BIT(15) 78 #define VSC73XX_MAC_CFG_VLAN_AWR BIT(14) 79 #define VSC73XX_MAC_CFG_100_BASE_T BIT(13) /* Not in manual */ 80 #define VSC73XX_MAC_CFG_TX_IPG_MASK GENMASK(10, 6) 81 #define VSC73XX_MAC_CFG_TX_IPG_OFFSET 6 82 #define VSC73XX_MAC_CFG_TX_IPG_1000M (6 << VSC73XX_MAC_CFG_TX_IPG_OFFSET) 83 #define VSC73XX_MAC_CFG_TX_IPG_100_10M (17 << VSC73XX_MAC_CFG_TX_IPG_OFFSET) 84 #define VSC73XX_MAC_CFG_MAC_RX_RST BIT(5) 85 #define VSC73XX_MAC_CFG_MAC_TX_RST BIT(4) 86 #define VSC73XX_MAC_CFG_CLK_SEL_MASK GENMASK(2, 0) 87 #define VSC73XX_MAC_CFG_CLK_SEL_OFFSET 0 88 #define VSC73XX_MAC_CFG_CLK_SEL_1000M 1 89 #define VSC73XX_MAC_CFG_CLK_SEL_100M 2 90 #define VSC73XX_MAC_CFG_CLK_SEL_10M 3 91 #define VSC73XX_MAC_CFG_CLK_SEL_EXT 4 92 93 #define VSC73XX_MAC_CFG_1000M_F_PHY (VSC73XX_MAC_CFG_FDX | \ 94 VSC73XX_MAC_CFG_GIGA_MODE | \ 95 VSC73XX_MAC_CFG_TX_IPG_1000M | \ 96 VSC73XX_MAC_CFG_CLK_SEL_EXT) 97 #define VSC73XX_MAC_CFG_100_10M_F_PHY (VSC73XX_MAC_CFG_FDX | \ 98 VSC73XX_MAC_CFG_TX_IPG_100_10M | \ 99 VSC73XX_MAC_CFG_CLK_SEL_EXT) 100 #define VSC73XX_MAC_CFG_100_10M_H_PHY (VSC73XX_MAC_CFG_TX_IPG_100_10M | \ 101 VSC73XX_MAC_CFG_CLK_SEL_EXT) 102 #define VSC73XX_MAC_CFG_1000M_F_RGMII (VSC73XX_MAC_CFG_FDX | \ 103 VSC73XX_MAC_CFG_GIGA_MODE | \ 104 VSC73XX_MAC_CFG_TX_IPG_1000M | \ 105 VSC73XX_MAC_CFG_CLK_SEL_1000M) 106 #define VSC73XX_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \ 107 VSC73XX_MAC_CFG_MAC_RX_RST | \ 108 VSC73XX_MAC_CFG_MAC_TX_RST) 109 110 /* Flow control register bits */ 111 #define VSC73XX_FCCONF_ZERO_PAUSE_EN BIT(17) 112 #define VSC73XX_FCCONF_FLOW_CTRL_OBEY BIT(16) 113 #define VSC73XX_FCCONF_PAUSE_VAL_MASK GENMASK(15, 0) 114 115 /* ADVPORTM advanced port setup register bits */ 116 #define VSC73XX_ADVPORTM_IFG_PPM BIT(7) 117 #define VSC73XX_ADVPORTM_EXC_COL_CONT BIT(6) 118 #define VSC73XX_ADVPORTM_EXT_PORT BIT(5) 119 #define VSC73XX_ADVPORTM_INV_GTX BIT(4) 120 #define VSC73XX_ADVPORTM_ENA_GTX BIT(3) 121 #define VSC73XX_ADVPORTM_DDR_MODE BIT(2) 122 #define VSC73XX_ADVPORTM_IO_LOOPBACK BIT(1) 123 #define VSC73XX_ADVPORTM_HOST_LOOPBACK BIT(0) 124 125 /* CAT_DROP categorizer frame dropping register bits */ 126 #define VSC73XX_CAT_DROP_DROP_MC_SMAC_ENA BIT(6) 127 #define VSC73XX_CAT_DROP_FWD_CTRL_ENA BIT(4) 128 #define VSC73XX_CAT_DROP_FWD_PAUSE_ENA BIT(3) 129 #define VSC73XX_CAT_DROP_UNTAGGED_ENA BIT(2) 130 #define VSC73XX_CAT_DROP_TAGGED_ENA BIT(1) 131 #define VSC73XX_CAT_DROP_NULL_MAC_ENA BIT(0) 132 133 #define VSC73XX_Q_MISC_CONF_EXTENT_MEM BIT(31) 134 #define VSC73XX_Q_MISC_CONF_EARLY_TX_MASK GENMASK(4, 1) 135 #define VSC73XX_Q_MISC_CONF_EARLY_TX_512 (1 << 1) 136 #define VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE BIT(0) 137 138 /* Frame analyzer block 2 registers */ 139 #define VSC73XX_STORMLIMIT 0x02 140 #define VSC73XX_ADVLEARN 0x03 141 #define VSC73XX_IFLODMSK 0x04 142 #define VSC73XX_VLANMASK 0x05 143 #define VSC73XX_MACHDATA 0x06 144 #define VSC73XX_MACLDATA 0x07 145 #define VSC73XX_ANMOVED 0x08 146 #define VSC73XX_ANAGEFIL 0x09 147 #define VSC73XX_ANEVENTS 0x0a 148 #define VSC73XX_ANCNTMASK 0x0b 149 #define VSC73XX_ANCNTVAL 0x0c 150 #define VSC73XX_LEARNMASK 0x0d 151 #define VSC73XX_UFLODMASK 0x0e 152 #define VSC73XX_MFLODMASK 0x0f 153 #define VSC73XX_RECVMASK 0x10 154 #define VSC73XX_AGGRCTRL 0x20 155 #define VSC73XX_AGGRMSKS 0x30 /* Until 0x3f */ 156 #define VSC73XX_DSTMASKS 0x40 /* Until 0x7f */ 157 #define VSC73XX_SRCMASKS 0x80 /* Until 0x87 */ 158 #define VSC73XX_CAPENAB 0xa0 159 #define VSC73XX_MACACCESS 0xb0 160 #define VSC73XX_IPMCACCESS 0xb1 161 #define VSC73XX_MACTINDX 0xc0 162 #define VSC73XX_VLANACCESS 0xd0 163 #define VSC73XX_VLANTIDX 0xe0 164 #define VSC73XX_AGENCTRL 0xf0 165 #define VSC73XX_CAPRST 0xff 166 167 #define VSC73XX_MACACCESS_CPU_COPY BIT(14) 168 #define VSC73XX_MACACCESS_FWD_KILL BIT(13) 169 #define VSC73XX_MACACCESS_IGNORE_VLAN BIT(12) 170 #define VSC73XX_MACACCESS_AGED_FLAG BIT(11) 171 #define VSC73XX_MACACCESS_VALID BIT(10) 172 #define VSC73XX_MACACCESS_LOCKED BIT(9) 173 #define VSC73XX_MACACCESS_DEST_IDX_MASK GENMASK(8, 3) 174 #define VSC73XX_MACACCESS_CMD_MASK GENMASK(2, 0) 175 #define VSC73XX_MACACCESS_CMD_IDLE 0 176 #define VSC73XX_MACACCESS_CMD_LEARN 1 177 #define VSC73XX_MACACCESS_CMD_FORGET 2 178 #define VSC73XX_MACACCESS_CMD_AGE_TABLE 3 179 #define VSC73XX_MACACCESS_CMD_FLUSH_TABLE 4 180 #define VSC73XX_MACACCESS_CMD_CLEAR_TABLE 5 181 #define VSC73XX_MACACCESS_CMD_READ_ENTRY 6 182 #define VSC73XX_MACACCESS_CMD_WRITE_ENTRY 7 183 184 #define VSC73XX_VLANACCESS_LEARN_DISABLED BIT(30) 185 #define VSC73XX_VLANACCESS_VLAN_MIRROR BIT(29) 186 #define VSC73XX_VLANACCESS_VLAN_SRC_CHECK BIT(28) 187 #define VSC73XX_VLANACCESS_VLAN_PORT_MASK GENMASK(9, 2) 188 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK GENMASK(2, 0) 189 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE 0 190 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY 1 191 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY 2 192 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE 3 193 194 /* MII block 3 registers */ 195 #define VSC73XX_MII_STAT 0x0 196 #define VSC73XX_MII_CMD 0x1 197 #define VSC73XX_MII_DATA 0x2 198 199 /* Arbiter block 5 registers */ 200 #define VSC73XX_ARBEMPTY 0x0c 201 #define VSC73XX_ARBDISC 0x0e 202 #define VSC73XX_SBACKWDROP 0x12 203 #define VSC73XX_DBACKWDROP 0x13 204 #define VSC73XX_ARBBURSTPROB 0x15 205 206 /* System block 7 registers */ 207 #define VSC73XX_ICPU_SIPAD 0x01 208 #define VSC73XX_GMIIDELAY 0x05 209 #define VSC73XX_ICPU_CTRL 0x10 210 #define VSC73XX_ICPU_ADDR 0x11 211 #define VSC73XX_ICPU_SRAM 0x12 212 #define VSC73XX_HWSEM 0x13 213 #define VSC73XX_GLORESET 0x14 214 #define VSC73XX_ICPU_MBOX_VAL 0x15 215 #define VSC73XX_ICPU_MBOX_SET 0x16 216 #define VSC73XX_ICPU_MBOX_CLR 0x17 217 #define VSC73XX_CHIPID 0x18 218 #define VSC73XX_GPIO 0x34 219 220 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_NONE 0 221 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_4_NS 1 222 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_7_NS 2 223 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS 3 224 225 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_NONE (0 << 4) 226 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_4_NS (1 << 4) 227 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_7_NS (2 << 4) 228 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS (3 << 4) 229 230 #define VSC73XX_ICPU_CTRL_WATCHDOG_RST BIT(31) 231 #define VSC73XX_ICPU_CTRL_CLK_DIV_MASK GENMASK(12, 8) 232 #define VSC73XX_ICPU_CTRL_SRST_HOLD BIT(7) 233 #define VSC73XX_ICPU_CTRL_ICPU_PI_EN BIT(6) 234 #define VSC73XX_ICPU_CTRL_BOOT_EN BIT(3) 235 #define VSC73XX_ICPU_CTRL_EXT_ACC_EN BIT(2) 236 #define VSC73XX_ICPU_CTRL_CLK_EN BIT(1) 237 #define VSC73XX_ICPU_CTRL_SRST BIT(0) 238 239 #define VSC73XX_CHIPID_ID_SHIFT 12 240 #define VSC73XX_CHIPID_ID_MASK 0xffff 241 #define VSC73XX_CHIPID_REV_SHIFT 28 242 #define VSC73XX_CHIPID_REV_MASK 0xf 243 #define VSC73XX_CHIPID_ID_7385 0x7385 244 #define VSC73XX_CHIPID_ID_7388 0x7388 245 #define VSC73XX_CHIPID_ID_7395 0x7395 246 #define VSC73XX_CHIPID_ID_7398 0x7398 247 248 #define VSC73XX_GLORESET_STROBE BIT(4) 249 #define VSC73XX_GLORESET_ICPU_LOCK BIT(3) 250 #define VSC73XX_GLORESET_MEM_LOCK BIT(2) 251 #define VSC73XX_GLORESET_PHY_RESET BIT(1) 252 #define VSC73XX_GLORESET_MASTER_RESET BIT(0) 253 254 #define VSC7385_CLOCK_DELAY ((3 << 4) | 3) 255 #define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3) 256 257 #define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \ 258 VSC73XX_ICPU_CTRL_BOOT_EN | \ 259 VSC73XX_ICPU_CTRL_EXT_ACC_EN) 260 261 #define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \ 262 VSC73XX_ICPU_CTRL_BOOT_EN | \ 263 VSC73XX_ICPU_CTRL_CLK_EN | \ 264 VSC73XX_ICPU_CTRL_SRST) 265 266 #define IS_7385(a) ((a)->chipid == VSC73XX_CHIPID_ID_7385) 267 #define IS_7388(a) ((a)->chipid == VSC73XX_CHIPID_ID_7388) 268 #define IS_7395(a) ((a)->chipid == VSC73XX_CHIPID_ID_7395) 269 #define IS_7398(a) ((a)->chipid == VSC73XX_CHIPID_ID_7398) 270 #define IS_739X(a) (IS_7395(a) || IS_7398(a)) 271 272 #define VSC73XX_POLL_SLEEP_US 1000 273 #define VSC73XX_POLL_TIMEOUT_US 10000 274 275 struct vsc73xx_counter { 276 u8 counter; 277 const char *name; 278 }; 279 280 /* Counters are named according to the MIB standards where applicable. 281 * Some counters are custom, non-standard. The standard counters are 282 * named in accordance with RFC2819, RFC2021 and IEEE Std 802.3-2002 Annex 283 * 30A Counters. 284 */ 285 static const struct vsc73xx_counter vsc73xx_rx_counters[] = { 286 { 0, "RxEtherStatsPkts" }, 287 { 1, "RxBroadcast+MulticastPkts" }, /* non-standard counter */ 288 { 2, "RxTotalErrorPackets" }, /* non-standard counter */ 289 { 3, "RxEtherStatsBroadcastPkts" }, 290 { 4, "RxEtherStatsMulticastPkts" }, 291 { 5, "RxEtherStatsPkts64Octets" }, 292 { 6, "RxEtherStatsPkts65to127Octets" }, 293 { 7, "RxEtherStatsPkts128to255Octets" }, 294 { 8, "RxEtherStatsPkts256to511Octets" }, 295 { 9, "RxEtherStatsPkts512to1023Octets" }, 296 { 10, "RxEtherStatsPkts1024to1518Octets" }, 297 { 11, "RxJumboFrames" }, /* non-standard counter */ 298 { 12, "RxaPauseMACControlFramesTransmitted" }, 299 { 13, "RxFIFODrops" }, /* non-standard counter */ 300 { 14, "RxBackwardDrops" }, /* non-standard counter */ 301 { 15, "RxClassifierDrops" }, /* non-standard counter */ 302 { 16, "RxEtherStatsCRCAlignErrors" }, 303 { 17, "RxEtherStatsUndersizePkts" }, 304 { 18, "RxEtherStatsOversizePkts" }, 305 { 19, "RxEtherStatsFragments" }, 306 { 20, "RxEtherStatsJabbers" }, 307 { 21, "RxaMACControlFramesReceived" }, 308 /* 22-24 are undefined */ 309 { 25, "RxaFramesReceivedOK" }, 310 { 26, "RxQoSClass0" }, /* non-standard counter */ 311 { 27, "RxQoSClass1" }, /* non-standard counter */ 312 { 28, "RxQoSClass2" }, /* non-standard counter */ 313 { 29, "RxQoSClass3" }, /* non-standard counter */ 314 }; 315 316 static const struct vsc73xx_counter vsc73xx_tx_counters[] = { 317 { 0, "TxEtherStatsPkts" }, 318 { 1, "TxBroadcast+MulticastPkts" }, /* non-standard counter */ 319 { 2, "TxTotalErrorPackets" }, /* non-standard counter */ 320 { 3, "TxEtherStatsBroadcastPkts" }, 321 { 4, "TxEtherStatsMulticastPkts" }, 322 { 5, "TxEtherStatsPkts64Octets" }, 323 { 6, "TxEtherStatsPkts65to127Octets" }, 324 { 7, "TxEtherStatsPkts128to255Octets" }, 325 { 8, "TxEtherStatsPkts256to511Octets" }, 326 { 9, "TxEtherStatsPkts512to1023Octets" }, 327 { 10, "TxEtherStatsPkts1024to1518Octets" }, 328 { 11, "TxJumboFrames" }, /* non-standard counter */ 329 { 12, "TxaPauseMACControlFramesTransmitted" }, 330 { 13, "TxFIFODrops" }, /* non-standard counter */ 331 { 14, "TxDrops" }, /* non-standard counter */ 332 { 15, "TxEtherStatsCollisions" }, 333 { 16, "TxEtherStatsCRCAlignErrors" }, 334 { 17, "TxEtherStatsUndersizePkts" }, 335 { 18, "TxEtherStatsOversizePkts" }, 336 { 19, "TxEtherStatsFragments" }, 337 { 20, "TxEtherStatsJabbers" }, 338 /* 21-24 are undefined */ 339 { 25, "TxaFramesReceivedOK" }, 340 { 26, "TxQoSClass0" }, /* non-standard counter */ 341 { 27, "TxQoSClass1" }, /* non-standard counter */ 342 { 28, "TxQoSClass2" }, /* non-standard counter */ 343 { 29, "TxQoSClass3" }, /* non-standard counter */ 344 }; 345 346 int vsc73xx_is_addr_valid(u8 block, u8 subblock) 347 { 348 switch (block) { 349 case VSC73XX_BLOCK_MAC: 350 switch (subblock) { 351 case 0 ... 4: 352 case 6: 353 return 1; 354 } 355 break; 356 357 case VSC73XX_BLOCK_ANALYZER: 358 case VSC73XX_BLOCK_SYSTEM: 359 switch (subblock) { 360 case 0: 361 return 1; 362 } 363 break; 364 365 case VSC73XX_BLOCK_MII: 366 case VSC73XX_BLOCK_CAPTURE: 367 case VSC73XX_BLOCK_ARBITER: 368 switch (subblock) { 369 case 0 ... 1: 370 return 1; 371 } 372 break; 373 } 374 375 return 0; 376 } 377 EXPORT_SYMBOL(vsc73xx_is_addr_valid); 378 379 static int vsc73xx_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, 380 u32 *val) 381 { 382 return vsc->ops->read(vsc, block, subblock, reg, val); 383 } 384 385 static int vsc73xx_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, 386 u32 val) 387 { 388 return vsc->ops->write(vsc, block, subblock, reg, val); 389 } 390 391 static int vsc73xx_update_bits(struct vsc73xx *vsc, u8 block, u8 subblock, 392 u8 reg, u32 mask, u32 val) 393 { 394 u32 tmp, orig; 395 int ret; 396 397 /* Same read-modify-write algorithm as e.g. regmap */ 398 ret = vsc73xx_read(vsc, block, subblock, reg, &orig); 399 if (ret) 400 return ret; 401 tmp = orig & ~mask; 402 tmp |= val & mask; 403 return vsc73xx_write(vsc, block, subblock, reg, tmp); 404 } 405 406 static int vsc73xx_detect(struct vsc73xx *vsc) 407 { 408 bool icpu_si_boot_en; 409 bool icpu_pi_en; 410 u32 val; 411 u32 rev; 412 int ret; 413 u32 id; 414 415 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 416 VSC73XX_ICPU_MBOX_VAL, &val); 417 if (ret) { 418 dev_err(vsc->dev, "unable to read mailbox (%d)\n", ret); 419 return ret; 420 } 421 422 if (val == 0xffffffff) { 423 dev_info(vsc->dev, "chip seems dead.\n"); 424 return -EAGAIN; 425 } 426 427 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 428 VSC73XX_CHIPID, &val); 429 if (ret) { 430 dev_err(vsc->dev, "unable to read chip id (%d)\n", ret); 431 return ret; 432 } 433 434 id = (val >> VSC73XX_CHIPID_ID_SHIFT) & 435 VSC73XX_CHIPID_ID_MASK; 436 switch (id) { 437 case VSC73XX_CHIPID_ID_7385: 438 case VSC73XX_CHIPID_ID_7388: 439 case VSC73XX_CHIPID_ID_7395: 440 case VSC73XX_CHIPID_ID_7398: 441 break; 442 default: 443 dev_err(vsc->dev, "unsupported chip, id=%04x\n", id); 444 return -ENODEV; 445 } 446 447 vsc->chipid = id; 448 rev = (val >> VSC73XX_CHIPID_REV_SHIFT) & 449 VSC73XX_CHIPID_REV_MASK; 450 dev_info(vsc->dev, "VSC%04X (rev: %d) switch found\n", id, rev); 451 452 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 453 VSC73XX_ICPU_CTRL, &val); 454 if (ret) { 455 dev_err(vsc->dev, "unable to read iCPU control\n"); 456 return ret; 457 } 458 459 /* The iCPU can always be used but can boot in different ways. 460 * If it is initially disabled and has no external memory, 461 * we are in control and can do whatever we like, else we 462 * are probably in trouble (we need some way to communicate 463 * with the running firmware) so we bail out for now. 464 */ 465 icpu_pi_en = !!(val & VSC73XX_ICPU_CTRL_ICPU_PI_EN); 466 icpu_si_boot_en = !!(val & VSC73XX_ICPU_CTRL_BOOT_EN); 467 if (icpu_si_boot_en && icpu_pi_en) { 468 dev_err(vsc->dev, 469 "iCPU enabled boots from SI, has external memory\n"); 470 dev_err(vsc->dev, "no idea how to deal with this\n"); 471 return -ENODEV; 472 } 473 if (icpu_si_boot_en && !icpu_pi_en) { 474 dev_err(vsc->dev, 475 "iCPU enabled boots from PI/SI, no external memory\n"); 476 return -EAGAIN; 477 } 478 if (!icpu_si_boot_en && icpu_pi_en) { 479 dev_err(vsc->dev, 480 "iCPU enabled, boots from PI external memory\n"); 481 dev_err(vsc->dev, "no idea how to deal with this\n"); 482 return -ENODEV; 483 } 484 /* !icpu_si_boot_en && !cpu_pi_en */ 485 dev_info(vsc->dev, "iCPU disabled, no external memory\n"); 486 487 return 0; 488 } 489 490 static int vsc73xx_phy_read(struct dsa_switch *ds, int phy, int regnum) 491 { 492 struct vsc73xx *vsc = ds->priv; 493 u32 cmd; 494 u32 val; 495 int ret; 496 497 /* Setting bit 26 means "read" */ 498 cmd = BIT(26) | (phy << 21) | (regnum << 16); 499 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd); 500 if (ret) 501 return ret; 502 msleep(2); 503 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, 0, 2, &val); 504 if (ret) 505 return ret; 506 if (val & BIT(16)) { 507 dev_err(vsc->dev, "reading reg %02x from phy%d failed\n", 508 regnum, phy); 509 return -EIO; 510 } 511 val &= 0xFFFFU; 512 513 dev_dbg(vsc->dev, "read reg %02x from phy%d = %04x\n", 514 regnum, phy, val); 515 516 return val; 517 } 518 519 static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum, 520 u16 val) 521 { 522 struct vsc73xx *vsc = ds->priv; 523 u32 cmd; 524 int ret; 525 526 /* It was found through tedious experiments that this router 527 * chip really hates to have it's PHYs reset. They 528 * never recover if that happens: autonegotiation stops 529 * working after a reset. Just filter out this command. 530 * (Resetting the whole chip is OK.) 531 */ 532 if (regnum == 0 && (val & BIT(15))) { 533 dev_info(vsc->dev, "reset PHY - disallowed\n"); 534 return 0; 535 } 536 537 cmd = (phy << 21) | (regnum << 16); 538 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd); 539 if (ret) 540 return ret; 541 542 dev_dbg(vsc->dev, "write %04x to reg %02x in phy%d\n", 543 val, regnum, phy); 544 return 0; 545 } 546 547 static enum dsa_tag_protocol vsc73xx_get_tag_protocol(struct dsa_switch *ds, 548 int port, 549 enum dsa_tag_protocol mp) 550 { 551 /* The switch internally uses a 8 byte header with length, 552 * source port, tag, LPA and priority. This is supposedly 553 * only accessible when operating the switch using the internal 554 * CPU or with an external CPU mapping the device in, but not 555 * when operating the switch over SPI and putting frames in/out 556 * on port 6 (the CPU port). So far we must assume that we 557 * cannot access the tag. (See "Internal frame header" section 558 * 3.9.1 in the manual.) 559 */ 560 return DSA_TAG_PROTO_NONE; 561 } 562 563 static int vsc73xx_setup(struct dsa_switch *ds) 564 { 565 struct vsc73xx *vsc = ds->priv; 566 int i; 567 568 dev_info(vsc->dev, "set up the switch\n"); 569 570 /* Issue RESET */ 571 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET, 572 VSC73XX_GLORESET_MASTER_RESET); 573 usleep_range(125, 200); 574 575 /* Initialize memory, initialize RAM bank 0..15 except 6 and 7 576 * This sequence appears in the 577 * VSC7385 SparX-G5 datasheet section 6.6.1 578 * VSC7395 SparX-G5e datasheet section 6.6.1 579 * "initialization sequence". 580 * No explanation is given to the 0x1010400 magic number. 581 */ 582 for (i = 0; i <= 15; i++) { 583 if (i != 6 && i != 7) { 584 vsc73xx_write(vsc, VSC73XX_BLOCK_MEMINIT, 585 2, 586 0, 0x1010400 + i); 587 mdelay(1); 588 } 589 } 590 mdelay(30); 591 592 /* Clear MAC table */ 593 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, 594 VSC73XX_MACACCESS, 595 VSC73XX_MACACCESS_CMD_CLEAR_TABLE); 596 597 /* Clear VLAN table */ 598 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, 599 VSC73XX_VLANACCESS, 600 VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE); 601 602 msleep(40); 603 604 /* Use 20KiB buffers on all ports on VSC7395 605 * The VSC7385 has 16KiB buffers and that is the 606 * default if we don't set this up explicitly. 607 * Port "31" is "all ports". 608 */ 609 if (IS_739X(vsc)) 610 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 0x1f, 611 VSC73XX_Q_MISC_CONF, 612 VSC73XX_Q_MISC_CONF_EXTENT_MEM); 613 614 /* Put all ports into reset until enabled */ 615 for (i = 0; i < 7; i++) { 616 if (i == 5) 617 continue; 618 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 4, 619 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET); 620 } 621 622 /* MII delay, set both GTX and RX delay to 2 ns */ 623 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GMIIDELAY, 624 VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS | 625 VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS); 626 /* Enable reception of frames on all ports */ 627 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_RECVMASK, 628 0x5f); 629 /* IP multicast flood mask (table 144) */ 630 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_IFLODMSK, 631 0xff); 632 633 mdelay(50); 634 635 /* Release reset from the internal PHYs */ 636 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET, 637 VSC73XX_GLORESET_PHY_RESET); 638 639 udelay(4); 640 641 return 0; 642 } 643 644 static void vsc73xx_init_port(struct vsc73xx *vsc, int port) 645 { 646 u32 val; 647 648 /* MAC configure, first reset the port and then write defaults */ 649 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 650 port, 651 VSC73XX_MAC_CFG, 652 VSC73XX_MAC_CFG_RESET); 653 654 /* Take up the port in 1Gbit mode by default, this will be 655 * augmented after auto-negotiation on the PHY-facing 656 * ports. 657 */ 658 if (port == CPU_PORT) 659 val = VSC73XX_MAC_CFG_1000M_F_RGMII; 660 else 661 val = VSC73XX_MAC_CFG_1000M_F_PHY; 662 663 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 664 port, 665 VSC73XX_MAC_CFG, 666 val | 667 VSC73XX_MAC_CFG_TX_EN | 668 VSC73XX_MAC_CFG_RX_EN); 669 670 /* Flow control for the CPU port: 671 * Use a zero delay pause frame when pause condition is left 672 * Obey pause control frames 673 */ 674 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 675 port, 676 VSC73XX_FCCONF, 677 VSC73XX_FCCONF_ZERO_PAUSE_EN | 678 VSC73XX_FCCONF_FLOW_CTRL_OBEY); 679 680 /* Issue pause control frames on PHY facing ports. 681 * Allow early initiation of MAC transmission if the amount 682 * of egress data is below 512 bytes on CPU port. 683 * FIXME: enable 20KiB buffers? 684 */ 685 if (port == CPU_PORT) 686 val = VSC73XX_Q_MISC_CONF_EARLY_TX_512; 687 else 688 val = VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE; 689 val |= VSC73XX_Q_MISC_CONF_EXTENT_MEM; 690 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 691 port, 692 VSC73XX_Q_MISC_CONF, 693 val); 694 695 /* Flow control MAC: a MAC address used in flow control frames */ 696 val = (vsc->addr[5] << 16) | (vsc->addr[4] << 8) | (vsc->addr[3]); 697 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 698 port, 699 VSC73XX_FCMACHI, 700 val); 701 val = (vsc->addr[2] << 16) | (vsc->addr[1] << 8) | (vsc->addr[0]); 702 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 703 port, 704 VSC73XX_FCMACLO, 705 val); 706 707 /* Tell the categorizer to forward pause frames, not control 708 * frame. Do not drop anything. 709 */ 710 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 711 port, 712 VSC73XX_CAT_DROP, 713 VSC73XX_CAT_DROP_FWD_PAUSE_ENA); 714 715 /* Clear all counters */ 716 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 717 port, VSC73XX_C_RX0, 0); 718 } 719 720 static void vsc73xx_reset_port(struct vsc73xx *vsc, int port, u32 initval) 721 { 722 int ret, err; 723 u32 val; 724 725 /* Disable RX on this port */ 726 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 727 VSC73XX_MAC_CFG, 728 VSC73XX_MAC_CFG_RX_EN, 0); 729 730 /* Discard packets */ 731 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 732 VSC73XX_ARBDISC, BIT(port), BIT(port)); 733 734 /* Wait until queue is empty */ 735 ret = read_poll_timeout(vsc73xx_read, err, 736 err < 0 || (val & BIT(port)), 737 VSC73XX_POLL_SLEEP_US, 738 VSC73XX_POLL_TIMEOUT_US, false, 739 vsc, VSC73XX_BLOCK_ARBITER, 0, 740 VSC73XX_ARBEMPTY, &val); 741 if (ret) 742 dev_err(vsc->dev, 743 "timeout waiting for block arbiter\n"); 744 else if (err < 0) 745 dev_err(vsc->dev, "error reading arbiter\n"); 746 747 /* Put this port into reset */ 748 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, 749 VSC73XX_MAC_CFG_RESET | initval); 750 } 751 752 static void vsc73xx_mac_config(struct phylink_config *config, unsigned int mode, 753 const struct phylink_link_state *state) 754 { 755 struct dsa_port *dp = dsa_phylink_to_port(config); 756 struct vsc73xx *vsc = dp->ds->priv; 757 int port = dp->index; 758 759 /* Special handling of the CPU-facing port */ 760 if (port == CPU_PORT) { 761 /* Other ports are already initialized but not this one */ 762 vsc73xx_init_port(vsc, CPU_PORT); 763 /* Select the external port for this interface (EXT_PORT) 764 * Enable the GMII GTX external clock 765 * Use double data rate (DDR mode) 766 */ 767 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 768 CPU_PORT, 769 VSC73XX_ADVPORTM, 770 VSC73XX_ADVPORTM_EXT_PORT | 771 VSC73XX_ADVPORTM_ENA_GTX | 772 VSC73XX_ADVPORTM_DDR_MODE); 773 } 774 } 775 776 static void vsc73xx_mac_link_down(struct phylink_config *config, 777 unsigned int mode, phy_interface_t interface) 778 { 779 struct dsa_port *dp = dsa_phylink_to_port(config); 780 struct vsc73xx *vsc = dp->ds->priv; 781 int port = dp->index; 782 783 /* This routine is described in the datasheet (below ARBDISC register 784 * description) 785 */ 786 vsc73xx_reset_port(vsc, port, 0); 787 788 /* Allow backward dropping of frames from this port */ 789 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 790 VSC73XX_SBACKWDROP, BIT(port), BIT(port)); 791 792 /* Receive mask (disable forwarding) */ 793 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 794 VSC73XX_RECVMASK, BIT(port), 0); 795 } 796 797 static void vsc73xx_mac_link_up(struct phylink_config *config, 798 struct phy_device *phy, unsigned int mode, 799 phy_interface_t interface, int speed, 800 int duplex, bool tx_pause, bool rx_pause) 801 { 802 struct dsa_port *dp = dsa_phylink_to_port(config); 803 struct vsc73xx *vsc = dp->ds->priv; 804 int port = dp->index; 805 u32 val; 806 u8 seed; 807 808 if (speed == SPEED_1000) 809 val = VSC73XX_MAC_CFG_GIGA_MODE | VSC73XX_MAC_CFG_TX_IPG_1000M; 810 else 811 val = VSC73XX_MAC_CFG_TX_IPG_100_10M; 812 813 if (phy_interface_mode_is_rgmii(interface)) 814 val |= VSC73XX_MAC_CFG_CLK_SEL_1000M; 815 else 816 val |= VSC73XX_MAC_CFG_CLK_SEL_EXT; 817 818 if (duplex == DUPLEX_FULL) 819 val |= VSC73XX_MAC_CFG_FDX; 820 821 /* This routine is described in the datasheet (below ARBDISC register 822 * description) 823 */ 824 vsc73xx_reset_port(vsc, port, val); 825 826 /* Seed the port randomness with randomness */ 827 get_random_bytes(&seed, 1); 828 val |= seed << VSC73XX_MAC_CFG_SEED_OFFSET; 829 val |= VSC73XX_MAC_CFG_SEED_LOAD; 830 val |= VSC73XX_MAC_CFG_WEXC_DIS; 831 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val); 832 833 /* Flow control for the PHY facing ports: 834 * Use a zero delay pause frame when pause condition is left 835 * Obey pause control frames 836 * When generating pause frames, use 0xff as pause value 837 */ 838 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_FCCONF, 839 VSC73XX_FCCONF_ZERO_PAUSE_EN | 840 VSC73XX_FCCONF_FLOW_CTRL_OBEY | 841 0xff); 842 843 /* Accept packets again */ 844 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 845 VSC73XX_ARBDISC, BIT(port), 0); 846 847 /* Enable port (forwarding) in the receive mask */ 848 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 849 VSC73XX_RECVMASK, BIT(port), BIT(port)); 850 851 /* Disallow backward dropping of frames from this port */ 852 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 853 VSC73XX_SBACKWDROP, BIT(port), 0); 854 855 /* Enable TX, RX, deassert reset, stop loading seed */ 856 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 857 VSC73XX_MAC_CFG, 858 VSC73XX_MAC_CFG_RESET | VSC73XX_MAC_CFG_SEED_LOAD | 859 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN, 860 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN); 861 } 862 863 static int vsc73xx_port_enable(struct dsa_switch *ds, int port, 864 struct phy_device *phy) 865 { 866 struct vsc73xx *vsc = ds->priv; 867 868 dev_info(vsc->dev, "enable port %d\n", port); 869 vsc73xx_init_port(vsc, port); 870 871 return 0; 872 } 873 874 static void vsc73xx_port_disable(struct dsa_switch *ds, int port) 875 { 876 struct vsc73xx *vsc = ds->priv; 877 878 /* Just put the port into reset */ 879 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, 880 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET); 881 } 882 883 static const struct vsc73xx_counter * 884 vsc73xx_find_counter(struct vsc73xx *vsc, 885 u8 counter, 886 bool tx) 887 { 888 const struct vsc73xx_counter *cnts; 889 int num_cnts; 890 int i; 891 892 if (tx) { 893 cnts = vsc73xx_tx_counters; 894 num_cnts = ARRAY_SIZE(vsc73xx_tx_counters); 895 } else { 896 cnts = vsc73xx_rx_counters; 897 num_cnts = ARRAY_SIZE(vsc73xx_rx_counters); 898 } 899 900 for (i = 0; i < num_cnts; i++) { 901 const struct vsc73xx_counter *cnt; 902 903 cnt = &cnts[i]; 904 if (cnt->counter == counter) 905 return cnt; 906 } 907 908 return NULL; 909 } 910 911 static void vsc73xx_get_strings(struct dsa_switch *ds, int port, u32 stringset, 912 uint8_t *data) 913 { 914 const struct vsc73xx_counter *cnt; 915 struct vsc73xx *vsc = ds->priv; 916 u8 indices[6]; 917 u8 *buf = data; 918 int i; 919 u32 val; 920 int ret; 921 922 if (stringset != ETH_SS_STATS) 923 return; 924 925 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port, 926 VSC73XX_C_CFG, &val); 927 if (ret) 928 return; 929 930 indices[0] = (val & 0x1f); /* RX counter 0 */ 931 indices[1] = ((val >> 5) & 0x1f); /* RX counter 1 */ 932 indices[2] = ((val >> 10) & 0x1f); /* RX counter 2 */ 933 indices[3] = ((val >> 16) & 0x1f); /* TX counter 0 */ 934 indices[4] = ((val >> 21) & 0x1f); /* TX counter 1 */ 935 indices[5] = ((val >> 26) & 0x1f); /* TX counter 2 */ 936 937 /* The first counters is the RX octets */ 938 ethtool_puts(&buf, "RxEtherStatsOctets"); 939 940 /* Each port supports recording 3 RX counters and 3 TX counters, 941 * figure out what counters we use in this set-up and return the 942 * names of them. The hardware default counters will be number of 943 * packets on RX/TX, combined broadcast+multicast packets RX/TX and 944 * total error packets RX/TX. 945 */ 946 for (i = 0; i < 3; i++) { 947 cnt = vsc73xx_find_counter(vsc, indices[i], false); 948 ethtool_puts(&buf, cnt ? cnt->name : ""); 949 } 950 951 /* TX stats begins with the number of TX octets */ 952 ethtool_puts(&buf, "TxEtherStatsOctets"); 953 954 for (i = 3; i < 6; i++) { 955 cnt = vsc73xx_find_counter(vsc, indices[i], true); 956 ethtool_puts(&buf, cnt ? cnt->name : ""); 957 958 } 959 } 960 961 static int vsc73xx_get_sset_count(struct dsa_switch *ds, int port, int sset) 962 { 963 /* We only support SS_STATS */ 964 if (sset != ETH_SS_STATS) 965 return 0; 966 /* RX and TX packets, then 3 RX counters, 3 TX counters */ 967 return 8; 968 } 969 970 static void vsc73xx_get_ethtool_stats(struct dsa_switch *ds, int port, 971 uint64_t *data) 972 { 973 struct vsc73xx *vsc = ds->priv; 974 u8 regs[] = { 975 VSC73XX_RXOCT, 976 VSC73XX_C_RX0, 977 VSC73XX_C_RX1, 978 VSC73XX_C_RX2, 979 VSC73XX_TXOCT, 980 VSC73XX_C_TX0, 981 VSC73XX_C_TX1, 982 VSC73XX_C_TX2, 983 }; 984 u32 val; 985 int ret; 986 int i; 987 988 for (i = 0; i < ARRAY_SIZE(regs); i++) { 989 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port, 990 regs[i], &val); 991 if (ret) { 992 dev_err(vsc->dev, "error reading counter %d\n", i); 993 return; 994 } 995 data[i] = val; 996 } 997 } 998 999 static int vsc73xx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1000 { 1001 struct vsc73xx *vsc = ds->priv; 1002 1003 return vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, 1004 VSC73XX_MAXLEN, new_mtu + ETH_HLEN + ETH_FCS_LEN); 1005 } 1006 1007 /* According to application not "VSC7398 Jumbo Frames" setting 1008 * up the frame size to 9.6 KB does not affect the performance on standard 1009 * frames. It is clear from the application note that 1010 * "9.6 kilobytes" == 9600 bytes. 1011 */ 1012 static int vsc73xx_get_max_mtu(struct dsa_switch *ds, int port) 1013 { 1014 return 9600 - ETH_HLEN - ETH_FCS_LEN; 1015 } 1016 1017 static void vsc73xx_phylink_get_caps(struct dsa_switch *dsa, int port, 1018 struct phylink_config *config) 1019 { 1020 unsigned long *interfaces = config->supported_interfaces; 1021 1022 if (port == 5) 1023 return; 1024 1025 if (port == CPU_PORT) { 1026 __set_bit(PHY_INTERFACE_MODE_MII, interfaces); 1027 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces); 1028 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces); 1029 __set_bit(PHY_INTERFACE_MODE_RGMII, interfaces); 1030 } 1031 1032 if (port <= 4) { 1033 /* Internal PHYs */ 1034 __set_bit(PHY_INTERFACE_MODE_INTERNAL, interfaces); 1035 /* phylib default */ 1036 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces); 1037 } 1038 1039 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000; 1040 } 1041 1042 static const struct phylink_mac_ops vsc73xx_phylink_mac_ops = { 1043 .mac_config = vsc73xx_mac_config, 1044 .mac_link_down = vsc73xx_mac_link_down, 1045 .mac_link_up = vsc73xx_mac_link_up, 1046 }; 1047 1048 static const struct dsa_switch_ops vsc73xx_ds_ops = { 1049 .get_tag_protocol = vsc73xx_get_tag_protocol, 1050 .setup = vsc73xx_setup, 1051 .phy_read = vsc73xx_phy_read, 1052 .phy_write = vsc73xx_phy_write, 1053 .get_strings = vsc73xx_get_strings, 1054 .get_ethtool_stats = vsc73xx_get_ethtool_stats, 1055 .get_sset_count = vsc73xx_get_sset_count, 1056 .port_enable = vsc73xx_port_enable, 1057 .port_disable = vsc73xx_port_disable, 1058 .port_change_mtu = vsc73xx_change_mtu, 1059 .port_max_mtu = vsc73xx_get_max_mtu, 1060 .phylink_get_caps = vsc73xx_phylink_get_caps, 1061 }; 1062 1063 static int vsc73xx_gpio_get(struct gpio_chip *chip, unsigned int offset) 1064 { 1065 struct vsc73xx *vsc = gpiochip_get_data(chip); 1066 u32 val; 1067 int ret; 1068 1069 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1070 VSC73XX_GPIO, &val); 1071 if (ret) 1072 return ret; 1073 1074 return !!(val & BIT(offset)); 1075 } 1076 1077 static void vsc73xx_gpio_set(struct gpio_chip *chip, unsigned int offset, 1078 int val) 1079 { 1080 struct vsc73xx *vsc = gpiochip_get_data(chip); 1081 u32 tmp = val ? BIT(offset) : 0; 1082 1083 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1084 VSC73XX_GPIO, BIT(offset), tmp); 1085 } 1086 1087 static int vsc73xx_gpio_direction_output(struct gpio_chip *chip, 1088 unsigned int offset, int val) 1089 { 1090 struct vsc73xx *vsc = gpiochip_get_data(chip); 1091 u32 tmp = val ? BIT(offset) : 0; 1092 1093 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1094 VSC73XX_GPIO, BIT(offset + 4) | BIT(offset), 1095 BIT(offset + 4) | tmp); 1096 } 1097 1098 static int vsc73xx_gpio_direction_input(struct gpio_chip *chip, 1099 unsigned int offset) 1100 { 1101 struct vsc73xx *vsc = gpiochip_get_data(chip); 1102 1103 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1104 VSC73XX_GPIO, BIT(offset + 4), 1105 0); 1106 } 1107 1108 static int vsc73xx_gpio_get_direction(struct gpio_chip *chip, 1109 unsigned int offset) 1110 { 1111 struct vsc73xx *vsc = gpiochip_get_data(chip); 1112 u32 val; 1113 int ret; 1114 1115 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1116 VSC73XX_GPIO, &val); 1117 if (ret) 1118 return ret; 1119 1120 return !(val & BIT(offset + 4)); 1121 } 1122 1123 static int vsc73xx_gpio_probe(struct vsc73xx *vsc) 1124 { 1125 int ret; 1126 1127 vsc->gc.label = devm_kasprintf(vsc->dev, GFP_KERNEL, "VSC%04x", 1128 vsc->chipid); 1129 if (!vsc->gc.label) 1130 return -ENOMEM; 1131 vsc->gc.ngpio = 4; 1132 vsc->gc.owner = THIS_MODULE; 1133 vsc->gc.parent = vsc->dev; 1134 vsc->gc.base = -1; 1135 vsc->gc.get = vsc73xx_gpio_get; 1136 vsc->gc.set = vsc73xx_gpio_set; 1137 vsc->gc.direction_input = vsc73xx_gpio_direction_input; 1138 vsc->gc.direction_output = vsc73xx_gpio_direction_output; 1139 vsc->gc.get_direction = vsc73xx_gpio_get_direction; 1140 vsc->gc.can_sleep = true; 1141 ret = devm_gpiochip_add_data(vsc->dev, &vsc->gc, vsc); 1142 if (ret) { 1143 dev_err(vsc->dev, "unable to register GPIO chip\n"); 1144 return ret; 1145 } 1146 return 0; 1147 } 1148 1149 int vsc73xx_probe(struct vsc73xx *vsc) 1150 { 1151 struct device *dev = vsc->dev; 1152 int ret; 1153 1154 /* Release reset, if any */ 1155 vsc->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1156 if (IS_ERR(vsc->reset)) { 1157 dev_err(dev, "failed to get RESET GPIO\n"); 1158 return PTR_ERR(vsc->reset); 1159 } 1160 if (vsc->reset) 1161 /* Wait 20ms according to datasheet table 245 */ 1162 msleep(20); 1163 1164 ret = vsc73xx_detect(vsc); 1165 if (ret == -EAGAIN) { 1166 dev_err(vsc->dev, 1167 "Chip seems to be out of control. Assert reset and try again.\n"); 1168 gpiod_set_value_cansleep(vsc->reset, 1); 1169 /* Reset pulse should be 20ns minimum, according to datasheet 1170 * table 245, so 10us should be fine 1171 */ 1172 usleep_range(10, 100); 1173 gpiod_set_value_cansleep(vsc->reset, 0); 1174 /* Wait 20ms according to datasheet table 245 */ 1175 msleep(20); 1176 ret = vsc73xx_detect(vsc); 1177 } 1178 if (ret) { 1179 dev_err(dev, "no chip found (%d)\n", ret); 1180 return -ENODEV; 1181 } 1182 1183 eth_random_addr(vsc->addr); 1184 dev_info(vsc->dev, 1185 "MAC for control frames: %02X:%02X:%02X:%02X:%02X:%02X\n", 1186 vsc->addr[0], vsc->addr[1], vsc->addr[2], 1187 vsc->addr[3], vsc->addr[4], vsc->addr[5]); 1188 1189 vsc->ds = devm_kzalloc(dev, sizeof(*vsc->ds), GFP_KERNEL); 1190 if (!vsc->ds) 1191 return -ENOMEM; 1192 1193 vsc->ds->dev = dev; 1194 vsc->ds->num_ports = VSC73XX_MAX_NUM_PORTS; 1195 vsc->ds->priv = vsc; 1196 1197 vsc->ds->ops = &vsc73xx_ds_ops; 1198 vsc->ds->phylink_mac_ops = &vsc73xx_phylink_mac_ops; 1199 ret = dsa_register_switch(vsc->ds); 1200 if (ret) { 1201 dev_err(dev, "unable to register switch (%d)\n", ret); 1202 return ret; 1203 } 1204 1205 ret = vsc73xx_gpio_probe(vsc); 1206 if (ret) { 1207 dsa_unregister_switch(vsc->ds); 1208 return ret; 1209 } 1210 1211 return 0; 1212 } 1213 EXPORT_SYMBOL(vsc73xx_probe); 1214 1215 void vsc73xx_remove(struct vsc73xx *vsc) 1216 { 1217 dsa_unregister_switch(vsc->ds); 1218 gpiod_set_value(vsc->reset, 1); 1219 } 1220 EXPORT_SYMBOL(vsc73xx_remove); 1221 1222 void vsc73xx_shutdown(struct vsc73xx *vsc) 1223 { 1224 dsa_switch_shutdown(vsc->ds); 1225 } 1226 EXPORT_SYMBOL(vsc73xx_shutdown); 1227 1228 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>"); 1229 MODULE_DESCRIPTION("Vitesse VSC7385/7388/7395/7398 driver"); 1230 MODULE_LICENSE("GPL v2"); 1231