1 // SPDX-License-Identifier: GPL-2.0 2 /* DSA driver for: 3 * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch 4 * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch 5 * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch 6 * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch 7 * 8 * These switches have a built-in 8051 CPU and can download and execute a 9 * firmware in this CPU. They can also be configured to use an external CPU 10 * handling the switch in a memory-mapped manner by connecting to that external 11 * CPU's memory bus. 12 * 13 * Copyright (C) 2018 Linus Wallej <linus.walleij@linaro.org> 14 * Includes portions of code from the firmware uploader by: 15 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> 16 */ 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/device.h> 20 #include <linux/iopoll.h> 21 #include <linux/of.h> 22 #include <linux/of_mdio.h> 23 #include <linux/bitops.h> 24 #include <linux/if_bridge.h> 25 #include <linux/if_vlan.h> 26 #include <linux/etherdevice.h> 27 #include <linux/gpio/consumer.h> 28 #include <linux/gpio/driver.h> 29 #include <linux/dsa/8021q.h> 30 #include <linux/random.h> 31 #include <net/dsa.h> 32 33 #include "vitesse-vsc73xx.h" 34 35 #define VSC73XX_BLOCK_MAC 0x1 /* Subblocks 0-4, 6 (CPU port) */ 36 #define VSC73XX_BLOCK_ANALYZER 0x2 /* Only subblock 0 */ 37 #define VSC73XX_BLOCK_MII 0x3 /* Subblocks 0 and 1 */ 38 #define VSC73XX_BLOCK_MEMINIT 0x3 /* Only subblock 2 */ 39 #define VSC73XX_BLOCK_CAPTURE 0x4 /* Only subblock 2 */ 40 #define VSC73XX_BLOCK_ARBITER 0x5 /* Only subblock 0 */ 41 #define VSC73XX_BLOCK_SYSTEM 0x7 /* Only subblock 0 */ 42 43 #define CPU_PORT 6 /* CPU port */ 44 45 /* MAC Block registers */ 46 #define VSC73XX_MAC_CFG 0x00 47 #define VSC73XX_MACHDXGAP 0x02 48 #define VSC73XX_FCCONF 0x04 49 #define VSC73XX_FCMACHI 0x08 50 #define VSC73XX_FCMACLO 0x0c 51 #define VSC73XX_MAXLEN 0x10 52 #define VSC73XX_ADVPORTM 0x19 53 #define VSC73XX_TXUPDCFG 0x24 54 #define VSC73XX_TXQ_SELECT_CFG 0x28 55 #define VSC73XX_RXOCT 0x50 56 #define VSC73XX_TXOCT 0x51 57 #define VSC73XX_C_RX0 0x52 58 #define VSC73XX_C_RX1 0x53 59 #define VSC73XX_C_RX2 0x54 60 #define VSC73XX_C_TX0 0x55 61 #define VSC73XX_C_TX1 0x56 62 #define VSC73XX_C_TX2 0x57 63 #define VSC73XX_C_CFG 0x58 64 #define VSC73XX_CAT_DROP 0x6e 65 #define VSC73XX_CAT_PR_MISC_L2 0x6f 66 #define VSC73XX_CAT_PR_USR_PRIO 0x75 67 #define VSC73XX_CAT_VLAN_MISC 0x79 68 #define VSC73XX_CAT_PORT_VLAN 0x7a 69 #define VSC73XX_Q_MISC_CONF 0xdf 70 71 /* MAC_CFG register bits */ 72 #define VSC73XX_MAC_CFG_WEXC_DIS BIT(31) 73 #define VSC73XX_MAC_CFG_PORT_RST BIT(29) 74 #define VSC73XX_MAC_CFG_TX_EN BIT(28) 75 #define VSC73XX_MAC_CFG_SEED_LOAD BIT(27) 76 #define VSC73XX_MAC_CFG_SEED_MASK GENMASK(26, 19) 77 #define VSC73XX_MAC_CFG_SEED_OFFSET 19 78 #define VSC73XX_MAC_CFG_FDX BIT(18) 79 #define VSC73XX_MAC_CFG_GIGA_MODE BIT(17) 80 #define VSC73XX_MAC_CFG_RX_EN BIT(16) 81 #define VSC73XX_MAC_CFG_VLAN_DBLAWR BIT(15) 82 #define VSC73XX_MAC_CFG_VLAN_AWR BIT(14) 83 #define VSC73XX_MAC_CFG_100_BASE_T BIT(13) /* Not in manual */ 84 #define VSC73XX_MAC_CFG_TX_IPG_MASK GENMASK(10, 6) 85 #define VSC73XX_MAC_CFG_TX_IPG_OFFSET 6 86 #define VSC73XX_MAC_CFG_TX_IPG_1000M (6 << VSC73XX_MAC_CFG_TX_IPG_OFFSET) 87 #define VSC73XX_MAC_CFG_TX_IPG_100_10M (17 << VSC73XX_MAC_CFG_TX_IPG_OFFSET) 88 #define VSC73XX_MAC_CFG_MAC_RX_RST BIT(5) 89 #define VSC73XX_MAC_CFG_MAC_TX_RST BIT(4) 90 #define VSC73XX_MAC_CFG_CLK_SEL_MASK GENMASK(2, 0) 91 #define VSC73XX_MAC_CFG_CLK_SEL_OFFSET 0 92 #define VSC73XX_MAC_CFG_CLK_SEL_1000M 1 93 #define VSC73XX_MAC_CFG_CLK_SEL_100M 2 94 #define VSC73XX_MAC_CFG_CLK_SEL_10M 3 95 #define VSC73XX_MAC_CFG_CLK_SEL_EXT 4 96 97 #define VSC73XX_MAC_CFG_1000M_F_PHY (VSC73XX_MAC_CFG_FDX | \ 98 VSC73XX_MAC_CFG_GIGA_MODE | \ 99 VSC73XX_MAC_CFG_TX_IPG_1000M | \ 100 VSC73XX_MAC_CFG_CLK_SEL_EXT) 101 #define VSC73XX_MAC_CFG_100_10M_F_PHY (VSC73XX_MAC_CFG_FDX | \ 102 VSC73XX_MAC_CFG_TX_IPG_100_10M | \ 103 VSC73XX_MAC_CFG_CLK_SEL_EXT) 104 #define VSC73XX_MAC_CFG_100_10M_H_PHY (VSC73XX_MAC_CFG_TX_IPG_100_10M | \ 105 VSC73XX_MAC_CFG_CLK_SEL_EXT) 106 #define VSC73XX_MAC_CFG_1000M_F_RGMII (VSC73XX_MAC_CFG_FDX | \ 107 VSC73XX_MAC_CFG_GIGA_MODE | \ 108 VSC73XX_MAC_CFG_TX_IPG_1000M | \ 109 VSC73XX_MAC_CFG_CLK_SEL_1000M) 110 #define VSC73XX_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \ 111 VSC73XX_MAC_CFG_MAC_RX_RST | \ 112 VSC73XX_MAC_CFG_MAC_TX_RST) 113 114 /* Flow control register bits */ 115 #define VSC73XX_FCCONF_ZERO_PAUSE_EN BIT(17) 116 #define VSC73XX_FCCONF_FLOW_CTRL_OBEY BIT(16) 117 #define VSC73XX_FCCONF_PAUSE_VAL_MASK GENMASK(15, 0) 118 119 /* ADVPORTM advanced port setup register bits */ 120 #define VSC73XX_ADVPORTM_IFG_PPM BIT(7) 121 #define VSC73XX_ADVPORTM_EXC_COL_CONT BIT(6) 122 #define VSC73XX_ADVPORTM_EXT_PORT BIT(5) 123 #define VSC73XX_ADVPORTM_INV_GTX BIT(4) 124 #define VSC73XX_ADVPORTM_ENA_GTX BIT(3) 125 #define VSC73XX_ADVPORTM_DDR_MODE BIT(2) 126 #define VSC73XX_ADVPORTM_IO_LOOPBACK BIT(1) 127 #define VSC73XX_ADVPORTM_HOST_LOOPBACK BIT(0) 128 129 /* TXUPDCFG transmit modify setup bits */ 130 #define VSC73XX_TXUPDCFG_DSCP_REWR_MODE GENMASK(20, 19) 131 #define VSC73XX_TXUPDCFG_DSCP_REWR_ENA BIT(18) 132 #define VSC73XX_TXUPDCFG_TX_INT_TO_USRPRIO_ENA BIT(17) 133 #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID GENMASK(15, 4) 134 #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA BIT(3) 135 #define VSC73XX_TXUPDCFG_TX_UPDATE_CRC_CPU_ENA BIT(1) 136 #define VSC73XX_TXUPDCFG_TX_INSERT_TAG BIT(0) 137 138 #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_SHIFT 4 139 140 /* CAT_DROP categorizer frame dropping register bits */ 141 #define VSC73XX_CAT_DROP_DROP_MC_SMAC_ENA BIT(6) 142 #define VSC73XX_CAT_DROP_FWD_CTRL_ENA BIT(4) 143 #define VSC73XX_CAT_DROP_FWD_PAUSE_ENA BIT(3) 144 #define VSC73XX_CAT_DROP_UNTAGGED_ENA BIT(2) 145 #define VSC73XX_CAT_DROP_TAGGED_ENA BIT(1) 146 #define VSC73XX_CAT_DROP_NULL_MAC_ENA BIT(0) 147 148 #define VSC73XX_Q_MISC_CONF_EXTENT_MEM BIT(31) 149 #define VSC73XX_Q_MISC_CONF_EARLY_TX_MASK GENMASK(4, 1) 150 #define VSC73XX_Q_MISC_CONF_EARLY_TX_512 (1 << 1) 151 #define VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE BIT(0) 152 153 /* CAT_VLAN_MISC categorizer VLAN miscellaneous bits */ 154 #define VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA BIT(8) 155 #define VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA BIT(7) 156 157 /* CAT_PORT_VLAN categorizer port VLAN */ 158 #define VSC73XX_CAT_PORT_VLAN_VLAN_CFI BIT(15) 159 #define VSC73XX_CAT_PORT_VLAN_VLAN_USR_PRIO GENMASK(14, 12) 160 #define VSC73XX_CAT_PORT_VLAN_VLAN_VID GENMASK(11, 0) 161 162 /* Frame analyzer block 2 registers */ 163 #define VSC73XX_STORMLIMIT 0x02 164 #define VSC73XX_ADVLEARN 0x03 165 #define VSC73XX_IFLODMSK 0x04 166 #define VSC73XX_VLANMASK 0x05 167 #define VSC73XX_MACHDATA 0x06 168 #define VSC73XX_MACLDATA 0x07 169 #define VSC73XX_ANMOVED 0x08 170 #define VSC73XX_ANAGEFIL 0x09 171 #define VSC73XX_ANEVENTS 0x0a 172 #define VSC73XX_ANCNTMASK 0x0b 173 #define VSC73XX_ANCNTVAL 0x0c 174 #define VSC73XX_LEARNMASK 0x0d 175 #define VSC73XX_UFLODMASK 0x0e 176 #define VSC73XX_MFLODMASK 0x0f 177 #define VSC73XX_RECVMASK 0x10 178 #define VSC73XX_AGGRCTRL 0x20 179 #define VSC73XX_AGGRMSKS 0x30 /* Until 0x3f */ 180 #define VSC73XX_DSTMASKS 0x40 /* Until 0x7f */ 181 #define VSC73XX_SRCMASKS 0x80 /* Until 0x87 */ 182 #define VSC73XX_CAPENAB 0xa0 183 #define VSC73XX_MACACCESS 0xb0 184 #define VSC73XX_IPMCACCESS 0xb1 185 #define VSC73XX_MACTINDX 0xc0 186 #define VSC73XX_VLANACCESS 0xd0 187 #define VSC73XX_VLANTIDX 0xe0 188 #define VSC73XX_AGENCTRL 0xf0 189 #define VSC73XX_CAPRST 0xff 190 191 #define VSC73XX_SRCMASKS_CPU_COPY BIT(27) 192 #define VSC73XX_SRCMASKS_MIRROR BIT(26) 193 #define VSC73XX_SRCMASKS_PORTS_MASK GENMASK(7, 0) 194 195 #define VSC73XX_MACACCESS_CPU_COPY BIT(14) 196 #define VSC73XX_MACACCESS_FWD_KILL BIT(13) 197 #define VSC73XX_MACACCESS_IGNORE_VLAN BIT(12) 198 #define VSC73XX_MACACCESS_AGED_FLAG BIT(11) 199 #define VSC73XX_MACACCESS_VALID BIT(10) 200 #define VSC73XX_MACACCESS_LOCKED BIT(9) 201 #define VSC73XX_MACACCESS_DEST_IDX_MASK GENMASK(8, 3) 202 #define VSC73XX_MACACCESS_CMD_MASK GENMASK(2, 0) 203 #define VSC73XX_MACACCESS_CMD_IDLE 0 204 #define VSC73XX_MACACCESS_CMD_LEARN 1 205 #define VSC73XX_MACACCESS_CMD_FORGET 2 206 #define VSC73XX_MACACCESS_CMD_AGE_TABLE 3 207 #define VSC73XX_MACACCESS_CMD_FLUSH_TABLE 4 208 #define VSC73XX_MACACCESS_CMD_CLEAR_TABLE 5 209 #define VSC73XX_MACACCESS_CMD_READ_ENTRY 6 210 #define VSC73XX_MACACCESS_CMD_WRITE_ENTRY 7 211 212 #define VSC73XX_VLANACCESS_LEARN_DISABLED BIT(30) 213 #define VSC73XX_VLANACCESS_VLAN_MIRROR BIT(29) 214 #define VSC73XX_VLANACCESS_VLAN_SRC_CHECK BIT(28) 215 #define VSC73XX_VLANACCESS_VLAN_PORT_MASK GENMASK(9, 2) 216 #define VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT 2 217 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK GENMASK(1, 0) 218 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE 0 219 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY 1 220 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY 2 221 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE 3 222 223 /* MII block 3 registers */ 224 #define VSC73XX_MII_STAT 0x0 225 #define VSC73XX_MII_CMD 0x1 226 #define VSC73XX_MII_DATA 0x2 227 228 /* Arbiter block 5 registers */ 229 #define VSC73XX_ARBEMPTY 0x0c 230 #define VSC73XX_ARBDISC 0x0e 231 #define VSC73XX_SBACKWDROP 0x12 232 #define VSC73XX_DBACKWDROP 0x13 233 #define VSC73XX_ARBBURSTPROB 0x15 234 235 /* System block 7 registers */ 236 #define VSC73XX_ICPU_SIPAD 0x01 237 #define VSC73XX_GMIIDELAY 0x05 238 #define VSC73XX_ICPU_CTRL 0x10 239 #define VSC73XX_ICPU_ADDR 0x11 240 #define VSC73XX_ICPU_SRAM 0x12 241 #define VSC73XX_HWSEM 0x13 242 #define VSC73XX_GLORESET 0x14 243 #define VSC73XX_ICPU_MBOX_VAL 0x15 244 #define VSC73XX_ICPU_MBOX_SET 0x16 245 #define VSC73XX_ICPU_MBOX_CLR 0x17 246 #define VSC73XX_CHIPID 0x18 247 #define VSC73XX_GPIO 0x34 248 249 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_NONE 0 250 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_4_NS 1 251 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_7_NS 2 252 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS 3 253 254 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_NONE (0 << 4) 255 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_4_NS (1 << 4) 256 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_7_NS (2 << 4) 257 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS (3 << 4) 258 259 #define VSC73XX_ICPU_CTRL_WATCHDOG_RST BIT(31) 260 #define VSC73XX_ICPU_CTRL_CLK_DIV_MASK GENMASK(12, 8) 261 #define VSC73XX_ICPU_CTRL_SRST_HOLD BIT(7) 262 #define VSC73XX_ICPU_CTRL_ICPU_PI_EN BIT(6) 263 #define VSC73XX_ICPU_CTRL_BOOT_EN BIT(3) 264 #define VSC73XX_ICPU_CTRL_EXT_ACC_EN BIT(2) 265 #define VSC73XX_ICPU_CTRL_CLK_EN BIT(1) 266 #define VSC73XX_ICPU_CTRL_SRST BIT(0) 267 268 #define VSC73XX_CHIPID_ID_SHIFT 12 269 #define VSC73XX_CHIPID_ID_MASK 0xffff 270 #define VSC73XX_CHIPID_REV_SHIFT 28 271 #define VSC73XX_CHIPID_REV_MASK 0xf 272 #define VSC73XX_CHIPID_ID_7385 0x7385 273 #define VSC73XX_CHIPID_ID_7388 0x7388 274 #define VSC73XX_CHIPID_ID_7395 0x7395 275 #define VSC73XX_CHIPID_ID_7398 0x7398 276 277 #define VSC73XX_GLORESET_STROBE BIT(4) 278 #define VSC73XX_GLORESET_ICPU_LOCK BIT(3) 279 #define VSC73XX_GLORESET_MEM_LOCK BIT(2) 280 #define VSC73XX_GLORESET_PHY_RESET BIT(1) 281 #define VSC73XX_GLORESET_MASTER_RESET BIT(0) 282 283 #define VSC7385_CLOCK_DELAY ((3 << 4) | 3) 284 #define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3) 285 286 #define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \ 287 VSC73XX_ICPU_CTRL_BOOT_EN | \ 288 VSC73XX_ICPU_CTRL_EXT_ACC_EN) 289 290 #define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \ 291 VSC73XX_ICPU_CTRL_BOOT_EN | \ 292 VSC73XX_ICPU_CTRL_CLK_EN | \ 293 VSC73XX_ICPU_CTRL_SRST) 294 295 #define IS_7385(a) ((a)->chipid == VSC73XX_CHIPID_ID_7385) 296 #define IS_7388(a) ((a)->chipid == VSC73XX_CHIPID_ID_7388) 297 #define IS_7395(a) ((a)->chipid == VSC73XX_CHIPID_ID_7395) 298 #define IS_7398(a) ((a)->chipid == VSC73XX_CHIPID_ID_7398) 299 #define IS_739X(a) (IS_7395(a) || IS_7398(a)) 300 301 #define VSC73XX_POLL_SLEEP_US 1000 302 #define VSC73XX_POLL_TIMEOUT_US 10000 303 304 struct vsc73xx_counter { 305 u8 counter; 306 const char *name; 307 }; 308 309 /* Counters are named according to the MIB standards where applicable. 310 * Some counters are custom, non-standard. The standard counters are 311 * named in accordance with RFC2819, RFC2021 and IEEE Std 802.3-2002 Annex 312 * 30A Counters. 313 */ 314 static const struct vsc73xx_counter vsc73xx_rx_counters[] = { 315 { 0, "RxEtherStatsPkts" }, 316 { 1, "RxBroadcast+MulticastPkts" }, /* non-standard counter */ 317 { 2, "RxTotalErrorPackets" }, /* non-standard counter */ 318 { 3, "RxEtherStatsBroadcastPkts" }, 319 { 4, "RxEtherStatsMulticastPkts" }, 320 { 5, "RxEtherStatsPkts64Octets" }, 321 { 6, "RxEtherStatsPkts65to127Octets" }, 322 { 7, "RxEtherStatsPkts128to255Octets" }, 323 { 8, "RxEtherStatsPkts256to511Octets" }, 324 { 9, "RxEtherStatsPkts512to1023Octets" }, 325 { 10, "RxEtherStatsPkts1024to1518Octets" }, 326 { 11, "RxJumboFrames" }, /* non-standard counter */ 327 { 12, "RxaPauseMACControlFramesTransmitted" }, 328 { 13, "RxFIFODrops" }, /* non-standard counter */ 329 { 14, "RxBackwardDrops" }, /* non-standard counter */ 330 { 15, "RxClassifierDrops" }, /* non-standard counter */ 331 { 16, "RxEtherStatsCRCAlignErrors" }, 332 { 17, "RxEtherStatsUndersizePkts" }, 333 { 18, "RxEtherStatsOversizePkts" }, 334 { 19, "RxEtherStatsFragments" }, 335 { 20, "RxEtherStatsJabbers" }, 336 { 21, "RxaMACControlFramesReceived" }, 337 /* 22-24 are undefined */ 338 { 25, "RxaFramesReceivedOK" }, 339 { 26, "RxQoSClass0" }, /* non-standard counter */ 340 { 27, "RxQoSClass1" }, /* non-standard counter */ 341 { 28, "RxQoSClass2" }, /* non-standard counter */ 342 { 29, "RxQoSClass3" }, /* non-standard counter */ 343 }; 344 345 static const struct vsc73xx_counter vsc73xx_tx_counters[] = { 346 { 0, "TxEtherStatsPkts" }, 347 { 1, "TxBroadcast+MulticastPkts" }, /* non-standard counter */ 348 { 2, "TxTotalErrorPackets" }, /* non-standard counter */ 349 { 3, "TxEtherStatsBroadcastPkts" }, 350 { 4, "TxEtherStatsMulticastPkts" }, 351 { 5, "TxEtherStatsPkts64Octets" }, 352 { 6, "TxEtherStatsPkts65to127Octets" }, 353 { 7, "TxEtherStatsPkts128to255Octets" }, 354 { 8, "TxEtherStatsPkts256to511Octets" }, 355 { 9, "TxEtherStatsPkts512to1023Octets" }, 356 { 10, "TxEtherStatsPkts1024to1518Octets" }, 357 { 11, "TxJumboFrames" }, /* non-standard counter */ 358 { 12, "TxaPauseMACControlFramesTransmitted" }, 359 { 13, "TxFIFODrops" }, /* non-standard counter */ 360 { 14, "TxDrops" }, /* non-standard counter */ 361 { 15, "TxEtherStatsCollisions" }, 362 { 16, "TxEtherStatsCRCAlignErrors" }, 363 { 17, "TxEtherStatsUndersizePkts" }, 364 { 18, "TxEtherStatsOversizePkts" }, 365 { 19, "TxEtherStatsFragments" }, 366 { 20, "TxEtherStatsJabbers" }, 367 /* 21-24 are undefined */ 368 { 25, "TxaFramesReceivedOK" }, 369 { 26, "TxQoSClass0" }, /* non-standard counter */ 370 { 27, "TxQoSClass1" }, /* non-standard counter */ 371 { 28, "TxQoSClass2" }, /* non-standard counter */ 372 { 29, "TxQoSClass3" }, /* non-standard counter */ 373 }; 374 375 struct vsc73xx_vlan_summary { 376 size_t num_tagged; 377 size_t num_untagged; 378 }; 379 380 enum vsc73xx_port_vlan_conf { 381 VSC73XX_VLAN_FILTER, 382 VSC73XX_VLAN_FILTER_UNTAG_ALL, 383 VSC73XX_VLAN_IGNORE, 384 }; 385 386 int vsc73xx_is_addr_valid(u8 block, u8 subblock) 387 { 388 switch (block) { 389 case VSC73XX_BLOCK_MAC: 390 switch (subblock) { 391 case 0 ... 4: 392 case 6: 393 return 1; 394 } 395 break; 396 397 case VSC73XX_BLOCK_ANALYZER: 398 case VSC73XX_BLOCK_SYSTEM: 399 switch (subblock) { 400 case 0: 401 return 1; 402 } 403 break; 404 405 case VSC73XX_BLOCK_MII: 406 case VSC73XX_BLOCK_CAPTURE: 407 case VSC73XX_BLOCK_ARBITER: 408 switch (subblock) { 409 case 0 ... 1: 410 return 1; 411 } 412 break; 413 } 414 415 return 0; 416 } 417 EXPORT_SYMBOL(vsc73xx_is_addr_valid); 418 419 static int vsc73xx_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, 420 u32 *val) 421 { 422 return vsc->ops->read(vsc, block, subblock, reg, val); 423 } 424 425 static int vsc73xx_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, 426 u32 val) 427 { 428 return vsc->ops->write(vsc, block, subblock, reg, val); 429 } 430 431 static int vsc73xx_update_bits(struct vsc73xx *vsc, u8 block, u8 subblock, 432 u8 reg, u32 mask, u32 val) 433 { 434 u32 tmp, orig; 435 int ret; 436 437 /* Same read-modify-write algorithm as e.g. regmap */ 438 ret = vsc73xx_read(vsc, block, subblock, reg, &orig); 439 if (ret) 440 return ret; 441 tmp = orig & ~mask; 442 tmp |= val & mask; 443 return vsc73xx_write(vsc, block, subblock, reg, tmp); 444 } 445 446 static int vsc73xx_detect(struct vsc73xx *vsc) 447 { 448 bool icpu_si_boot_en; 449 bool icpu_pi_en; 450 u32 val; 451 u32 rev; 452 int ret; 453 u32 id; 454 455 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 456 VSC73XX_ICPU_MBOX_VAL, &val); 457 if (ret) { 458 dev_err(vsc->dev, "unable to read mailbox (%d)\n", ret); 459 return ret; 460 } 461 462 if (val == 0xffffffff) { 463 dev_info(vsc->dev, "chip seems dead.\n"); 464 return -EAGAIN; 465 } 466 467 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 468 VSC73XX_CHIPID, &val); 469 if (ret) { 470 dev_err(vsc->dev, "unable to read chip id (%d)\n", ret); 471 return ret; 472 } 473 474 id = (val >> VSC73XX_CHIPID_ID_SHIFT) & 475 VSC73XX_CHIPID_ID_MASK; 476 switch (id) { 477 case VSC73XX_CHIPID_ID_7385: 478 case VSC73XX_CHIPID_ID_7388: 479 case VSC73XX_CHIPID_ID_7395: 480 case VSC73XX_CHIPID_ID_7398: 481 break; 482 default: 483 dev_err(vsc->dev, "unsupported chip, id=%04x\n", id); 484 return -ENODEV; 485 } 486 487 vsc->chipid = id; 488 rev = (val >> VSC73XX_CHIPID_REV_SHIFT) & 489 VSC73XX_CHIPID_REV_MASK; 490 dev_info(vsc->dev, "VSC%04X (rev: %d) switch found\n", id, rev); 491 492 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 493 VSC73XX_ICPU_CTRL, &val); 494 if (ret) { 495 dev_err(vsc->dev, "unable to read iCPU control\n"); 496 return ret; 497 } 498 499 /* The iCPU can always be used but can boot in different ways. 500 * If it is initially disabled and has no external memory, 501 * we are in control and can do whatever we like, else we 502 * are probably in trouble (we need some way to communicate 503 * with the running firmware) so we bail out for now. 504 */ 505 icpu_pi_en = !!(val & VSC73XX_ICPU_CTRL_ICPU_PI_EN); 506 icpu_si_boot_en = !!(val & VSC73XX_ICPU_CTRL_BOOT_EN); 507 if (icpu_si_boot_en && icpu_pi_en) { 508 dev_err(vsc->dev, 509 "iCPU enabled boots from SI, has external memory\n"); 510 dev_err(vsc->dev, "no idea how to deal with this\n"); 511 return -ENODEV; 512 } 513 if (icpu_si_boot_en && !icpu_pi_en) { 514 dev_err(vsc->dev, 515 "iCPU enabled boots from PI/SI, no external memory\n"); 516 return -EAGAIN; 517 } 518 if (!icpu_si_boot_en && icpu_pi_en) { 519 dev_err(vsc->dev, 520 "iCPU enabled, boots from PI external memory\n"); 521 dev_err(vsc->dev, "no idea how to deal with this\n"); 522 return -ENODEV; 523 } 524 /* !icpu_si_boot_en && !cpu_pi_en */ 525 dev_info(vsc->dev, "iCPU disabled, no external memory\n"); 526 527 return 0; 528 } 529 530 static int vsc73xx_phy_read(struct dsa_switch *ds, int phy, int regnum) 531 { 532 struct vsc73xx *vsc = ds->priv; 533 u32 cmd; 534 u32 val; 535 int ret; 536 537 /* Setting bit 26 means "read" */ 538 cmd = BIT(26) | (phy << 21) | (regnum << 16); 539 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd); 540 if (ret) 541 return ret; 542 msleep(2); 543 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, 0, 2, &val); 544 if (ret) 545 return ret; 546 if (val & BIT(16)) { 547 dev_err(vsc->dev, "reading reg %02x from phy%d failed\n", 548 regnum, phy); 549 return -EIO; 550 } 551 val &= 0xFFFFU; 552 553 dev_dbg(vsc->dev, "read reg %02x from phy%d = %04x\n", 554 regnum, phy, val); 555 556 return val; 557 } 558 559 static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum, 560 u16 val) 561 { 562 struct vsc73xx *vsc = ds->priv; 563 u32 cmd; 564 int ret; 565 566 /* It was found through tedious experiments that this router 567 * chip really hates to have it's PHYs reset. They 568 * never recover if that happens: autonegotiation stops 569 * working after a reset. Just filter out this command. 570 * (Resetting the whole chip is OK.) 571 */ 572 if (regnum == 0 && (val & BIT(15))) { 573 dev_info(vsc->dev, "reset PHY - disallowed\n"); 574 return 0; 575 } 576 577 cmd = (phy << 21) | (regnum << 16); 578 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd); 579 if (ret) 580 return ret; 581 582 dev_dbg(vsc->dev, "write %04x to reg %02x in phy%d\n", 583 val, regnum, phy); 584 return 0; 585 } 586 587 static enum dsa_tag_protocol vsc73xx_get_tag_protocol(struct dsa_switch *ds, 588 int port, 589 enum dsa_tag_protocol mp) 590 { 591 /* The switch internally uses a 8 byte header with length, 592 * source port, tag, LPA and priority. This is supposedly 593 * only accessible when operating the switch using the internal 594 * CPU or with an external CPU mapping the device in, but not 595 * when operating the switch over SPI and putting frames in/out 596 * on port 6 (the CPU port). So far we must assume that we 597 * cannot access the tag. (See "Internal frame header" section 598 * 3.9.1 in the manual.) 599 */ 600 return DSA_TAG_PROTO_VSC73XX_8021Q; 601 } 602 603 static int vsc73xx_wait_for_vlan_table_cmd(struct vsc73xx *vsc) 604 { 605 int ret, err; 606 u32 val; 607 608 ret = read_poll_timeout(vsc73xx_read, err, 609 err < 0 || 610 ((val & VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK) == 611 VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE), 612 VSC73XX_POLL_SLEEP_US, VSC73XX_POLL_TIMEOUT_US, 613 false, vsc, VSC73XX_BLOCK_ANALYZER, 614 0, VSC73XX_VLANACCESS, &val); 615 if (ret) 616 return ret; 617 return err; 618 } 619 620 static int 621 vsc73xx_read_vlan_table_entry(struct vsc73xx *vsc, u16 vid, u8 *portmap) 622 { 623 u32 val; 624 int ret; 625 626 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANTIDX, vid); 627 628 ret = vsc73xx_wait_for_vlan_table_cmd(vsc); 629 if (ret) 630 return ret; 631 632 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS, 633 VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK, 634 VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY); 635 636 ret = vsc73xx_wait_for_vlan_table_cmd(vsc); 637 if (ret) 638 return ret; 639 640 vsc73xx_read(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS, &val); 641 *portmap = (val & VSC73XX_VLANACCESS_VLAN_PORT_MASK) >> 642 VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT; 643 644 return 0; 645 } 646 647 static int 648 vsc73xx_write_vlan_table_entry(struct vsc73xx *vsc, u16 vid, u8 portmap) 649 { 650 int ret; 651 652 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANTIDX, vid); 653 654 ret = vsc73xx_wait_for_vlan_table_cmd(vsc); 655 if (ret) 656 return ret; 657 658 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS, 659 VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK | 660 VSC73XX_VLANACCESS_VLAN_SRC_CHECK | 661 VSC73XX_VLANACCESS_VLAN_PORT_MASK, 662 VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY | 663 VSC73XX_VLANACCESS_VLAN_SRC_CHECK | 664 (portmap << VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT)); 665 666 return vsc73xx_wait_for_vlan_table_cmd(vsc); 667 } 668 669 static int 670 vsc73xx_update_vlan_table(struct vsc73xx *vsc, int port, u16 vid, bool set) 671 { 672 u8 portmap; 673 int ret; 674 675 ret = vsc73xx_read_vlan_table_entry(vsc, vid, &portmap); 676 if (ret) 677 return ret; 678 679 if (set) 680 portmap |= BIT(port); 681 else 682 portmap &= ~BIT(port); 683 684 return vsc73xx_write_vlan_table_entry(vsc, vid, portmap); 685 } 686 687 static int vsc73xx_setup(struct dsa_switch *ds) 688 { 689 struct vsc73xx *vsc = ds->priv; 690 int i, ret; 691 692 dev_info(vsc->dev, "set up the switch\n"); 693 694 ds->untag_bridge_pvid = true; 695 ds->max_num_bridges = DSA_TAG_8021Q_MAX_NUM_BRIDGES; 696 697 /* Issue RESET */ 698 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET, 699 VSC73XX_GLORESET_MASTER_RESET); 700 usleep_range(125, 200); 701 702 /* Initialize memory, initialize RAM bank 0..15 except 6 and 7 703 * This sequence appears in the 704 * VSC7385 SparX-G5 datasheet section 6.6.1 705 * VSC7395 SparX-G5e datasheet section 6.6.1 706 * "initialization sequence". 707 * No explanation is given to the 0x1010400 magic number. 708 */ 709 for (i = 0; i <= 15; i++) { 710 if (i != 6 && i != 7) { 711 vsc73xx_write(vsc, VSC73XX_BLOCK_MEMINIT, 712 2, 713 0, 0x1010400 + i); 714 mdelay(1); 715 } 716 } 717 mdelay(30); 718 719 /* Clear MAC table */ 720 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, 721 VSC73XX_MACACCESS, 722 VSC73XX_MACACCESS_CMD_CLEAR_TABLE); 723 724 /* Set VLAN table to default values */ 725 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, 726 VSC73XX_VLANACCESS, 727 VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE); 728 729 msleep(40); 730 731 /* Use 20KiB buffers on all ports on VSC7395 732 * The VSC7385 has 16KiB buffers and that is the 733 * default if we don't set this up explicitly. 734 * Port "31" is "all ports". 735 */ 736 if (IS_739X(vsc)) 737 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 0x1f, 738 VSC73XX_Q_MISC_CONF, 739 VSC73XX_Q_MISC_CONF_EXTENT_MEM); 740 741 /* Put all ports into reset until enabled */ 742 for (i = 0; i < 7; i++) { 743 if (i == 5) 744 continue; 745 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 4, 746 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET); 747 } 748 749 /* MII delay, set both GTX and RX delay to 2 ns */ 750 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GMIIDELAY, 751 VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS | 752 VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS); 753 /* Ingess VLAN reception mask (table 145) */ 754 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANMASK, 755 0xff); 756 /* IP multicast flood mask (table 144) */ 757 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_IFLODMSK, 758 0xff); 759 760 mdelay(50); 761 762 /* Release reset from the internal PHYs */ 763 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET, 764 VSC73XX_GLORESET_PHY_RESET); 765 766 udelay(4); 767 768 /* Clear VLAN table */ 769 for (i = 0; i < VLAN_N_VID; i++) 770 vsc73xx_write_vlan_table_entry(vsc, i, 0); 771 772 INIT_LIST_HEAD(&vsc->vlans); 773 774 rtnl_lock(); 775 ret = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q)); 776 rtnl_unlock(); 777 778 return ret; 779 } 780 781 static void vsc73xx_teardown(struct dsa_switch *ds) 782 { 783 rtnl_lock(); 784 dsa_tag_8021q_unregister(ds); 785 rtnl_unlock(); 786 } 787 788 static void vsc73xx_init_port(struct vsc73xx *vsc, int port) 789 { 790 u32 val; 791 792 /* MAC configure, first reset the port and then write defaults */ 793 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 794 port, 795 VSC73XX_MAC_CFG, 796 VSC73XX_MAC_CFG_RESET); 797 798 /* Take up the port in 1Gbit mode by default, this will be 799 * augmented after auto-negotiation on the PHY-facing 800 * ports. 801 */ 802 if (port == CPU_PORT) 803 val = VSC73XX_MAC_CFG_1000M_F_RGMII; 804 else 805 val = VSC73XX_MAC_CFG_1000M_F_PHY; 806 807 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 808 port, 809 VSC73XX_MAC_CFG, 810 val | 811 VSC73XX_MAC_CFG_TX_EN | 812 VSC73XX_MAC_CFG_RX_EN); 813 814 /* Flow control for the CPU port: 815 * Use a zero delay pause frame when pause condition is left 816 * Obey pause control frames 817 */ 818 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 819 port, 820 VSC73XX_FCCONF, 821 VSC73XX_FCCONF_ZERO_PAUSE_EN | 822 VSC73XX_FCCONF_FLOW_CTRL_OBEY); 823 824 /* Issue pause control frames on PHY facing ports. 825 * Allow early initiation of MAC transmission if the amount 826 * of egress data is below 512 bytes on CPU port. 827 * FIXME: enable 20KiB buffers? 828 */ 829 if (port == CPU_PORT) 830 val = VSC73XX_Q_MISC_CONF_EARLY_TX_512; 831 else 832 val = VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE; 833 val |= VSC73XX_Q_MISC_CONF_EXTENT_MEM; 834 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 835 port, 836 VSC73XX_Q_MISC_CONF, 837 val); 838 839 /* Flow control MAC: a MAC address used in flow control frames */ 840 val = (vsc->addr[5] << 16) | (vsc->addr[4] << 8) | (vsc->addr[3]); 841 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 842 port, 843 VSC73XX_FCMACHI, 844 val); 845 val = (vsc->addr[2] << 16) | (vsc->addr[1] << 8) | (vsc->addr[0]); 846 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 847 port, 848 VSC73XX_FCMACLO, 849 val); 850 851 /* Tell the categorizer to forward pause frames, not control 852 * frame. Do not drop anything. 853 */ 854 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 855 port, 856 VSC73XX_CAT_DROP, 857 VSC73XX_CAT_DROP_FWD_PAUSE_ENA); 858 859 /* Clear all counters */ 860 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 861 port, VSC73XX_C_RX0, 0); 862 } 863 864 static void vsc73xx_reset_port(struct vsc73xx *vsc, int port, u32 initval) 865 { 866 int ret, err; 867 u32 val; 868 869 /* Disable RX on this port */ 870 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 871 VSC73XX_MAC_CFG, 872 VSC73XX_MAC_CFG_RX_EN, 0); 873 874 /* Discard packets */ 875 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 876 VSC73XX_ARBDISC, BIT(port), BIT(port)); 877 878 /* Wait until queue is empty */ 879 ret = read_poll_timeout(vsc73xx_read, err, 880 err < 0 || (val & BIT(port)), 881 VSC73XX_POLL_SLEEP_US, 882 VSC73XX_POLL_TIMEOUT_US, false, 883 vsc, VSC73XX_BLOCK_ARBITER, 0, 884 VSC73XX_ARBEMPTY, &val); 885 if (ret) 886 dev_err(vsc->dev, 887 "timeout waiting for block arbiter\n"); 888 else if (err < 0) 889 dev_err(vsc->dev, "error reading arbiter\n"); 890 891 /* Put this port into reset */ 892 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, 893 VSC73XX_MAC_CFG_RESET | initval); 894 } 895 896 static void vsc73xx_mac_config(struct phylink_config *config, unsigned int mode, 897 const struct phylink_link_state *state) 898 { 899 struct dsa_port *dp = dsa_phylink_to_port(config); 900 struct vsc73xx *vsc = dp->ds->priv; 901 int port = dp->index; 902 903 /* Special handling of the CPU-facing port */ 904 if (port == CPU_PORT) { 905 /* Other ports are already initialized but not this one */ 906 vsc73xx_init_port(vsc, CPU_PORT); 907 /* Select the external port for this interface (EXT_PORT) 908 * Enable the GMII GTX external clock 909 * Use double data rate (DDR mode) 910 */ 911 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 912 CPU_PORT, 913 VSC73XX_ADVPORTM, 914 VSC73XX_ADVPORTM_EXT_PORT | 915 VSC73XX_ADVPORTM_ENA_GTX | 916 VSC73XX_ADVPORTM_DDR_MODE); 917 } 918 } 919 920 static void vsc73xx_mac_link_down(struct phylink_config *config, 921 unsigned int mode, phy_interface_t interface) 922 { 923 struct dsa_port *dp = dsa_phylink_to_port(config); 924 struct vsc73xx *vsc = dp->ds->priv; 925 int port = dp->index; 926 927 /* This routine is described in the datasheet (below ARBDISC register 928 * description) 929 */ 930 vsc73xx_reset_port(vsc, port, 0); 931 932 /* Allow backward dropping of frames from this port */ 933 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 934 VSC73XX_SBACKWDROP, BIT(port), BIT(port)); 935 } 936 937 static void vsc73xx_mac_link_up(struct phylink_config *config, 938 struct phy_device *phy, unsigned int mode, 939 phy_interface_t interface, int speed, 940 int duplex, bool tx_pause, bool rx_pause) 941 { 942 struct dsa_port *dp = dsa_phylink_to_port(config); 943 struct vsc73xx *vsc = dp->ds->priv; 944 int port = dp->index; 945 u32 val; 946 u8 seed; 947 948 if (speed == SPEED_1000) 949 val = VSC73XX_MAC_CFG_GIGA_MODE | VSC73XX_MAC_CFG_TX_IPG_1000M; 950 else 951 val = VSC73XX_MAC_CFG_TX_IPG_100_10M; 952 953 if (phy_interface_mode_is_rgmii(interface)) 954 val |= VSC73XX_MAC_CFG_CLK_SEL_1000M; 955 else 956 val |= VSC73XX_MAC_CFG_CLK_SEL_EXT; 957 958 if (duplex == DUPLEX_FULL) 959 val |= VSC73XX_MAC_CFG_FDX; 960 961 /* This routine is described in the datasheet (below ARBDISC register 962 * description) 963 */ 964 vsc73xx_reset_port(vsc, port, val); 965 966 /* Seed the port randomness with randomness */ 967 get_random_bytes(&seed, 1); 968 val |= seed << VSC73XX_MAC_CFG_SEED_OFFSET; 969 val |= VSC73XX_MAC_CFG_SEED_LOAD; 970 val |= VSC73XX_MAC_CFG_WEXC_DIS; 971 972 /* Those bits are responsible for MTU only. Kernel takes care about MTU, 973 * let's enable +8 bytes frame length unconditionally. 974 */ 975 val |= VSC73XX_MAC_CFG_VLAN_AWR | VSC73XX_MAC_CFG_VLAN_DBLAWR; 976 977 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val); 978 979 /* Flow control for the PHY facing ports: 980 * Use a zero delay pause frame when pause condition is left 981 * Obey pause control frames 982 * When generating pause frames, use 0xff as pause value 983 */ 984 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_FCCONF, 985 VSC73XX_FCCONF_ZERO_PAUSE_EN | 986 VSC73XX_FCCONF_FLOW_CTRL_OBEY | 987 0xff); 988 989 /* Accept packets again */ 990 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 991 VSC73XX_ARBDISC, BIT(port), 0); 992 993 /* Disallow backward dropping of frames from this port */ 994 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 995 VSC73XX_SBACKWDROP, BIT(port), 0); 996 997 /* Enable TX, RX, deassert reset, stop loading seed */ 998 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 999 VSC73XX_MAC_CFG, 1000 VSC73XX_MAC_CFG_RESET | VSC73XX_MAC_CFG_SEED_LOAD | 1001 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN, 1002 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN); 1003 } 1004 1005 static bool vsc73xx_tag_8021q_active(struct dsa_port *dp) 1006 { 1007 return !dsa_port_is_vlan_filtering(dp); 1008 } 1009 1010 static struct vsc73xx_bridge_vlan * 1011 vsc73xx_bridge_vlan_find(struct vsc73xx *vsc, u16 vid) 1012 { 1013 struct vsc73xx_bridge_vlan *vlan; 1014 1015 list_for_each_entry(vlan, &vsc->vlans, list) 1016 if (vlan->vid == vid) 1017 return vlan; 1018 1019 return NULL; 1020 } 1021 1022 static void 1023 vsc73xx_bridge_vlan_remove_port(struct vsc73xx_bridge_vlan *vsc73xx_vlan, 1024 int port) 1025 { 1026 vsc73xx_vlan->portmask &= ~BIT(port); 1027 1028 if (vsc73xx_vlan->portmask) 1029 return; 1030 1031 list_del(&vsc73xx_vlan->list); 1032 kfree(vsc73xx_vlan); 1033 } 1034 1035 static void vsc73xx_bridge_vlan_summary(struct vsc73xx *vsc, int port, 1036 struct vsc73xx_vlan_summary *summary, 1037 u16 ignored_vid) 1038 { 1039 size_t num_tagged = 0, num_untagged = 0; 1040 struct vsc73xx_bridge_vlan *vlan; 1041 1042 list_for_each_entry(vlan, &vsc->vlans, list) { 1043 if (!(vlan->portmask & BIT(port)) || vlan->vid == ignored_vid) 1044 continue; 1045 1046 if (vlan->untagged & BIT(port)) 1047 num_untagged++; 1048 else 1049 num_tagged++; 1050 } 1051 1052 summary->num_untagged = num_untagged; 1053 summary->num_tagged = num_tagged; 1054 } 1055 1056 static u16 vsc73xx_find_first_vlan_untagged(struct vsc73xx *vsc, int port) 1057 { 1058 struct vsc73xx_bridge_vlan *vlan; 1059 1060 list_for_each_entry(vlan, &vsc->vlans, list) 1061 if ((vlan->portmask & BIT(port)) && 1062 (vlan->untagged & BIT(port))) 1063 return vlan->vid; 1064 1065 return VLAN_N_VID; 1066 } 1067 1068 static int vsc73xx_set_vlan_conf(struct vsc73xx *vsc, int port, 1069 enum vsc73xx_port_vlan_conf port_vlan_conf) 1070 { 1071 u32 val = 0; 1072 int ret; 1073 1074 if (port_vlan_conf == VSC73XX_VLAN_IGNORE) 1075 val = VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA | 1076 VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA; 1077 1078 ret = vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1079 VSC73XX_CAT_VLAN_MISC, 1080 VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA | 1081 VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA, val); 1082 if (ret) 1083 return ret; 1084 1085 val = (port_vlan_conf == VSC73XX_VLAN_FILTER) ? 1086 VSC73XX_TXUPDCFG_TX_INSERT_TAG : 0; 1087 1088 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1089 VSC73XX_TXUPDCFG, 1090 VSC73XX_TXUPDCFG_TX_INSERT_TAG, val); 1091 } 1092 1093 /** 1094 * vsc73xx_vlan_commit_conf - Update VLAN configuration of a port 1095 * @vsc: Switch private data structure 1096 * @port: Port index on which to operate 1097 * 1098 * Update the VLAN behavior of a port to make sure that when it is under 1099 * a VLAN filtering bridge, the port is either filtering with tag 1100 * preservation, or filtering with all VLANs egress-untagged. Otherwise, 1101 * the port ignores VLAN tags from packets and applies the port-based 1102 * VID. 1103 * 1104 * Must be called when changes are made to: 1105 * - the bridge VLAN filtering state of the port 1106 * - the number or attributes of VLANs from the bridge VLAN table, 1107 * while the port is currently VLAN-aware 1108 * 1109 * Return: 0 on success, or negative errno on error. 1110 */ 1111 static int vsc73xx_vlan_commit_conf(struct vsc73xx *vsc, int port) 1112 { 1113 enum vsc73xx_port_vlan_conf port_vlan_conf = VSC73XX_VLAN_IGNORE; 1114 struct dsa_port *dp = dsa_to_port(vsc->ds, port); 1115 1116 if (port == CPU_PORT) { 1117 port_vlan_conf = VSC73XX_VLAN_FILTER; 1118 } else if (dsa_port_is_vlan_filtering(dp)) { 1119 struct vsc73xx_vlan_summary summary; 1120 1121 port_vlan_conf = VSC73XX_VLAN_FILTER; 1122 1123 vsc73xx_bridge_vlan_summary(vsc, port, &summary, VLAN_N_VID); 1124 if (summary.num_tagged == 0) 1125 port_vlan_conf = VSC73XX_VLAN_FILTER_UNTAG_ALL; 1126 } 1127 1128 return vsc73xx_set_vlan_conf(vsc, port, port_vlan_conf); 1129 } 1130 1131 static int 1132 vsc73xx_vlan_change_untagged(struct vsc73xx *vsc, int port, u16 vid, bool set) 1133 { 1134 u32 val = 0; 1135 1136 if (set) 1137 val = VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA | 1138 ((vid << VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_SHIFT) & 1139 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID); 1140 1141 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1142 VSC73XX_TXUPDCFG, 1143 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA | 1144 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID, val); 1145 } 1146 1147 /** 1148 * vsc73xx_vlan_commit_untagged - Update native VLAN of a port 1149 * @vsc: Switch private data structure 1150 * @port: Port index on which to operate 1151 * 1152 * Update the native VLAN of a port (the one VLAN which is transmitted 1153 * as egress-tagged on a trunk port) when port is in VLAN filtering mode and 1154 * only one untagged vid is configured. 1155 * In other cases no need to configure it because switch can untag all vlans on 1156 * the port. 1157 * 1158 * Return: 0 on success, or negative errno on error. 1159 */ 1160 static int vsc73xx_vlan_commit_untagged(struct vsc73xx *vsc, int port) 1161 { 1162 struct dsa_port *dp = dsa_to_port(vsc->ds, port); 1163 struct vsc73xx_vlan_summary summary; 1164 u16 vid = 0; 1165 bool valid; 1166 1167 if (!dsa_port_is_vlan_filtering(dp)) 1168 /* Port is configured to untag all vlans in that case. 1169 * No need to commit untagged config change. 1170 */ 1171 return 0; 1172 1173 vsc73xx_bridge_vlan_summary(vsc, port, &summary, VLAN_N_VID); 1174 1175 if (summary.num_untagged > 1) 1176 /* Port must untag all vlans in that case. 1177 * No need to commit untagged config change. 1178 */ 1179 return 0; 1180 1181 valid = (summary.num_untagged == 1); 1182 if (valid) 1183 vid = vsc73xx_find_first_vlan_untagged(vsc, port); 1184 1185 return vsc73xx_vlan_change_untagged(vsc, port, vid, valid); 1186 } 1187 1188 static int 1189 vsc73xx_vlan_change_pvid(struct vsc73xx *vsc, int port, u16 vid, bool set) 1190 { 1191 u32 val = 0; 1192 int ret; 1193 1194 val = set ? 0 : VSC73XX_CAT_DROP_UNTAGGED_ENA; 1195 1196 ret = vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1197 VSC73XX_CAT_DROP, 1198 VSC73XX_CAT_DROP_UNTAGGED_ENA, val); 1199 if (!set || ret) 1200 return ret; 1201 1202 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1203 VSC73XX_CAT_PORT_VLAN, 1204 VSC73XX_CAT_PORT_VLAN_VLAN_VID, 1205 vid & VSC73XX_CAT_PORT_VLAN_VLAN_VID); 1206 } 1207 1208 /** 1209 * vsc73xx_vlan_commit_pvid - Update port-based default VLAN of a port 1210 * @vsc: Switch private data structure 1211 * @port: Port index on which to operate 1212 * 1213 * Update the PVID of a port so that it follows either the bridge PVID 1214 * configuration, when the bridge is currently VLAN-aware, or the PVID 1215 * from tag_8021q, when the port is standalone or under a VLAN-unaware 1216 * bridge. A port with no PVID drops all untagged and VID 0 tagged 1217 * traffic. 1218 * 1219 * Must be called when changes are made to: 1220 * - the bridge VLAN filtering state of the port 1221 * - the number or attributes of VLANs from the bridge VLAN table, 1222 * while the port is currently VLAN-aware 1223 * 1224 * Return: 0 on success, or negative errno on error. 1225 */ 1226 static int vsc73xx_vlan_commit_pvid(struct vsc73xx *vsc, int port) 1227 { 1228 struct vsc73xx_portinfo *portinfo = &vsc->portinfo[port]; 1229 bool valid = portinfo->pvid_tag_8021q_configured; 1230 struct dsa_port *dp = dsa_to_port(vsc->ds, port); 1231 u16 vid = portinfo->pvid_tag_8021q; 1232 1233 if (dsa_port_is_vlan_filtering(dp)) { 1234 vid = portinfo->pvid_vlan_filtering; 1235 valid = portinfo->pvid_vlan_filtering_configured; 1236 } 1237 1238 return vsc73xx_vlan_change_pvid(vsc, port, vid, valid); 1239 } 1240 1241 static int vsc73xx_vlan_commit_settings(struct vsc73xx *vsc, int port) 1242 { 1243 int ret; 1244 1245 ret = vsc73xx_vlan_commit_untagged(vsc, port); 1246 if (ret) 1247 return ret; 1248 1249 ret = vsc73xx_vlan_commit_pvid(vsc, port); 1250 if (ret) 1251 return ret; 1252 1253 return vsc73xx_vlan_commit_conf(vsc, port); 1254 } 1255 1256 static int vsc73xx_port_enable(struct dsa_switch *ds, int port, 1257 struct phy_device *phy) 1258 { 1259 struct vsc73xx *vsc = ds->priv; 1260 1261 dev_info(vsc->dev, "enable port %d\n", port); 1262 vsc73xx_init_port(vsc, port); 1263 1264 return vsc73xx_vlan_commit_settings(vsc, port); 1265 } 1266 1267 static void vsc73xx_port_disable(struct dsa_switch *ds, int port) 1268 { 1269 struct vsc73xx *vsc = ds->priv; 1270 1271 /* Just put the port into reset */ 1272 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, 1273 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET); 1274 } 1275 1276 static const struct vsc73xx_counter * 1277 vsc73xx_find_counter(struct vsc73xx *vsc, 1278 u8 counter, 1279 bool tx) 1280 { 1281 const struct vsc73xx_counter *cnts; 1282 int num_cnts; 1283 int i; 1284 1285 if (tx) { 1286 cnts = vsc73xx_tx_counters; 1287 num_cnts = ARRAY_SIZE(vsc73xx_tx_counters); 1288 } else { 1289 cnts = vsc73xx_rx_counters; 1290 num_cnts = ARRAY_SIZE(vsc73xx_rx_counters); 1291 } 1292 1293 for (i = 0; i < num_cnts; i++) { 1294 const struct vsc73xx_counter *cnt; 1295 1296 cnt = &cnts[i]; 1297 if (cnt->counter == counter) 1298 return cnt; 1299 } 1300 1301 return NULL; 1302 } 1303 1304 static void vsc73xx_get_strings(struct dsa_switch *ds, int port, u32 stringset, 1305 uint8_t *data) 1306 { 1307 const struct vsc73xx_counter *cnt; 1308 struct vsc73xx *vsc = ds->priv; 1309 u8 indices[6]; 1310 u8 *buf = data; 1311 int i; 1312 u32 val; 1313 int ret; 1314 1315 if (stringset != ETH_SS_STATS) 1316 return; 1317 1318 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port, 1319 VSC73XX_C_CFG, &val); 1320 if (ret) 1321 return; 1322 1323 indices[0] = (val & 0x1f); /* RX counter 0 */ 1324 indices[1] = ((val >> 5) & 0x1f); /* RX counter 1 */ 1325 indices[2] = ((val >> 10) & 0x1f); /* RX counter 2 */ 1326 indices[3] = ((val >> 16) & 0x1f); /* TX counter 0 */ 1327 indices[4] = ((val >> 21) & 0x1f); /* TX counter 1 */ 1328 indices[5] = ((val >> 26) & 0x1f); /* TX counter 2 */ 1329 1330 /* The first counters is the RX octets */ 1331 ethtool_puts(&buf, "RxEtherStatsOctets"); 1332 1333 /* Each port supports recording 3 RX counters and 3 TX counters, 1334 * figure out what counters we use in this set-up and return the 1335 * names of them. The hardware default counters will be number of 1336 * packets on RX/TX, combined broadcast+multicast packets RX/TX and 1337 * total error packets RX/TX. 1338 */ 1339 for (i = 0; i < 3; i++) { 1340 cnt = vsc73xx_find_counter(vsc, indices[i], false); 1341 ethtool_puts(&buf, cnt ? cnt->name : ""); 1342 } 1343 1344 /* TX stats begins with the number of TX octets */ 1345 ethtool_puts(&buf, "TxEtherStatsOctets"); 1346 1347 for (i = 3; i < 6; i++) { 1348 cnt = vsc73xx_find_counter(vsc, indices[i], true); 1349 ethtool_puts(&buf, cnt ? cnt->name : ""); 1350 1351 } 1352 } 1353 1354 static int vsc73xx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1355 { 1356 /* We only support SS_STATS */ 1357 if (sset != ETH_SS_STATS) 1358 return 0; 1359 /* RX and TX packets, then 3 RX counters, 3 TX counters */ 1360 return 8; 1361 } 1362 1363 static void vsc73xx_get_ethtool_stats(struct dsa_switch *ds, int port, 1364 uint64_t *data) 1365 { 1366 struct vsc73xx *vsc = ds->priv; 1367 u8 regs[] = { 1368 VSC73XX_RXOCT, 1369 VSC73XX_C_RX0, 1370 VSC73XX_C_RX1, 1371 VSC73XX_C_RX2, 1372 VSC73XX_TXOCT, 1373 VSC73XX_C_TX0, 1374 VSC73XX_C_TX1, 1375 VSC73XX_C_TX2, 1376 }; 1377 u32 val; 1378 int ret; 1379 int i; 1380 1381 for (i = 0; i < ARRAY_SIZE(regs); i++) { 1382 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port, 1383 regs[i], &val); 1384 if (ret) { 1385 dev_err(vsc->dev, "error reading counter %d\n", i); 1386 return; 1387 } 1388 data[i] = val; 1389 } 1390 } 1391 1392 static int vsc73xx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1393 { 1394 struct vsc73xx *vsc = ds->priv; 1395 1396 return vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, 1397 VSC73XX_MAXLEN, new_mtu + ETH_HLEN + ETH_FCS_LEN); 1398 } 1399 1400 /* According to application not "VSC7398 Jumbo Frames" setting 1401 * up the frame size to 9.6 KB does not affect the performance on standard 1402 * frames. It is clear from the application note that 1403 * "9.6 kilobytes" == 9600 bytes. 1404 */ 1405 static int vsc73xx_get_max_mtu(struct dsa_switch *ds, int port) 1406 { 1407 return 9600 - ETH_HLEN - ETH_FCS_LEN; 1408 } 1409 1410 static void vsc73xx_phylink_get_caps(struct dsa_switch *dsa, int port, 1411 struct phylink_config *config) 1412 { 1413 unsigned long *interfaces = config->supported_interfaces; 1414 1415 if (port == 5) 1416 return; 1417 1418 if (port == CPU_PORT) { 1419 __set_bit(PHY_INTERFACE_MODE_MII, interfaces); 1420 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces); 1421 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces); 1422 __set_bit(PHY_INTERFACE_MODE_RGMII, interfaces); 1423 } 1424 1425 if (port <= 4) { 1426 /* Internal PHYs */ 1427 __set_bit(PHY_INTERFACE_MODE_INTERNAL, interfaces); 1428 /* phylib default */ 1429 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces); 1430 } 1431 1432 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000; 1433 } 1434 1435 static int 1436 vsc73xx_port_vlan_filtering(struct dsa_switch *ds, int port, 1437 bool vlan_filtering, struct netlink_ext_ack *extack) 1438 { 1439 struct vsc73xx *vsc = ds->priv; 1440 1441 /* The commit to hardware processed below is required because vsc73xx 1442 * is using tag_8021q. When vlan_filtering is disabled, tag_8021q uses 1443 * pvid/untagged vlans for port recognition. The values configured for 1444 * vlans and pvid/untagged states are stored in portinfo structure. 1445 * When vlan_filtering is enabled, we need to restore pvid/untagged from 1446 * portinfo structure. Analogous routine is processed when 1447 * vlan_filtering is disabled, but values used for tag_8021q are 1448 * restored. 1449 */ 1450 1451 return vsc73xx_vlan_commit_settings(vsc, port); 1452 } 1453 1454 static int vsc73xx_port_vlan_add(struct dsa_switch *ds, int port, 1455 const struct switchdev_obj_port_vlan *vlan, 1456 struct netlink_ext_ack *extack) 1457 { 1458 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1459 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1460 struct dsa_port *dp = dsa_to_port(ds, port); 1461 struct vsc73xx_bridge_vlan *vsc73xx_vlan; 1462 struct vsc73xx_vlan_summary summary; 1463 struct vsc73xx_portinfo *portinfo; 1464 struct vsc73xx *vsc = ds->priv; 1465 bool commit_to_hardware; 1466 int ret = 0; 1467 1468 /* Be sure to deny alterations to the configuration done by tag_8021q. 1469 */ 1470 if (vid_is_dsa_8021q(vlan->vid)) { 1471 NL_SET_ERR_MSG_MOD(extack, 1472 "Range 3072-4095 reserved for dsa_8021q operation"); 1473 return -EBUSY; 1474 } 1475 1476 /* The processed vlan->vid is excluded from the search because the VLAN 1477 * can be re-added with a different set of flags, so it's easiest to 1478 * ignore its old flags from the VLAN database software copy. 1479 */ 1480 vsc73xx_bridge_vlan_summary(vsc, port, &summary, vlan->vid); 1481 1482 /* VSC73XX allows only three untagged states: none, one or all */ 1483 if ((untagged && summary.num_tagged > 0 && summary.num_untagged > 0) || 1484 (!untagged && summary.num_untagged > 1)) { 1485 NL_SET_ERR_MSG_MOD(extack, 1486 "Port can have only none, one or all untagged vlan"); 1487 return -EBUSY; 1488 } 1489 1490 vsc73xx_vlan = vsc73xx_bridge_vlan_find(vsc, vlan->vid); 1491 1492 if (!vsc73xx_vlan) { 1493 vsc73xx_vlan = kzalloc(sizeof(*vsc73xx_vlan), GFP_KERNEL); 1494 if (!vsc73xx_vlan) 1495 return -ENOMEM; 1496 1497 vsc73xx_vlan->vid = vlan->vid; 1498 1499 list_add_tail(&vsc73xx_vlan->list, &vsc->vlans); 1500 } 1501 1502 vsc73xx_vlan->portmask |= BIT(port); 1503 1504 /* CPU port must be always tagged because source port identification is 1505 * based on tag_8021q. 1506 */ 1507 if (port == CPU_PORT) 1508 goto update_vlan_table; 1509 1510 if (untagged) 1511 vsc73xx_vlan->untagged |= BIT(port); 1512 else 1513 vsc73xx_vlan->untagged &= ~BIT(port); 1514 1515 portinfo = &vsc->portinfo[port]; 1516 1517 if (pvid) { 1518 portinfo->pvid_vlan_filtering_configured = true; 1519 portinfo->pvid_vlan_filtering = vlan->vid; 1520 } else if (portinfo->pvid_vlan_filtering_configured && 1521 portinfo->pvid_vlan_filtering == vlan->vid) { 1522 portinfo->pvid_vlan_filtering_configured = false; 1523 } 1524 1525 commit_to_hardware = !vsc73xx_tag_8021q_active(dp); 1526 if (commit_to_hardware) { 1527 ret = vsc73xx_vlan_commit_settings(vsc, port); 1528 if (ret) 1529 goto err; 1530 } 1531 1532 update_vlan_table: 1533 ret = vsc73xx_update_vlan_table(vsc, port, vlan->vid, true); 1534 if (!ret) 1535 return 0; 1536 err: 1537 vsc73xx_bridge_vlan_remove_port(vsc73xx_vlan, port); 1538 return ret; 1539 } 1540 1541 static int vsc73xx_port_vlan_del(struct dsa_switch *ds, int port, 1542 const struct switchdev_obj_port_vlan *vlan) 1543 { 1544 struct vsc73xx_bridge_vlan *vsc73xx_vlan; 1545 struct vsc73xx_portinfo *portinfo; 1546 struct vsc73xx *vsc = ds->priv; 1547 bool commit_to_hardware; 1548 int ret; 1549 1550 ret = vsc73xx_update_vlan_table(vsc, port, vlan->vid, false); 1551 if (ret) 1552 return ret; 1553 1554 portinfo = &vsc->portinfo[port]; 1555 1556 if (portinfo->pvid_vlan_filtering_configured && 1557 portinfo->pvid_vlan_filtering == vlan->vid) 1558 portinfo->pvid_vlan_filtering_configured = false; 1559 1560 vsc73xx_vlan = vsc73xx_bridge_vlan_find(vsc, vlan->vid); 1561 1562 if (vsc73xx_vlan) 1563 vsc73xx_bridge_vlan_remove_port(vsc73xx_vlan, port); 1564 1565 commit_to_hardware = !vsc73xx_tag_8021q_active(dsa_to_port(ds, port)); 1566 1567 if (commit_to_hardware) 1568 return vsc73xx_vlan_commit_settings(vsc, port); 1569 1570 return 0; 1571 } 1572 1573 static int vsc73xx_tag_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid, 1574 u16 flags) 1575 { 1576 bool pvid = flags & BRIDGE_VLAN_INFO_PVID; 1577 struct vsc73xx_portinfo *portinfo; 1578 struct vsc73xx *vsc = ds->priv; 1579 bool commit_to_hardware; 1580 int ret; 1581 1582 portinfo = &vsc->portinfo[port]; 1583 1584 if (pvid) { 1585 portinfo->pvid_tag_8021q_configured = true; 1586 portinfo->pvid_tag_8021q = vid; 1587 } 1588 1589 commit_to_hardware = vsc73xx_tag_8021q_active(dsa_to_port(ds, port)); 1590 if (commit_to_hardware) { 1591 ret = vsc73xx_vlan_commit_settings(vsc, port); 1592 if (ret) 1593 return ret; 1594 } 1595 1596 return vsc73xx_update_vlan_table(vsc, port, vid, true); 1597 } 1598 1599 static int vsc73xx_tag_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid) 1600 { 1601 struct vsc73xx_portinfo *portinfo; 1602 struct vsc73xx *vsc = ds->priv; 1603 1604 portinfo = &vsc->portinfo[port]; 1605 1606 if (portinfo->pvid_tag_8021q_configured && 1607 portinfo->pvid_tag_8021q == vid) { 1608 struct dsa_port *dp = dsa_to_port(ds, port); 1609 bool commit_to_hardware; 1610 int err; 1611 1612 portinfo->pvid_tag_8021q_configured = false; 1613 1614 commit_to_hardware = vsc73xx_tag_8021q_active(dp); 1615 if (commit_to_hardware) { 1616 err = vsc73xx_vlan_commit_settings(vsc, port); 1617 if (err) 1618 return err; 1619 } 1620 } 1621 1622 return vsc73xx_update_vlan_table(vsc, port, vid, false); 1623 } 1624 1625 static int vsc73xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1626 struct switchdev_brport_flags flags, 1627 struct netlink_ext_ack *extack) 1628 { 1629 if (flags.mask & ~BR_LEARNING) 1630 return -EINVAL; 1631 1632 return 0; 1633 } 1634 1635 static int vsc73xx_port_bridge_flags(struct dsa_switch *ds, int port, 1636 struct switchdev_brport_flags flags, 1637 struct netlink_ext_ack *extack) 1638 { 1639 if (flags.mask & BR_LEARNING) { 1640 u32 val = flags.val & BR_LEARNING ? BIT(port) : 0; 1641 struct vsc73xx *vsc = ds->priv; 1642 1643 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1644 VSC73XX_LEARNMASK, BIT(port), val); 1645 } 1646 1647 return 0; 1648 } 1649 1650 static void vsc73xx_refresh_fwd_map(struct dsa_switch *ds, int port, u8 state) 1651 { 1652 struct dsa_port *other_dp, *dp = dsa_to_port(ds, port); 1653 struct vsc73xx *vsc = ds->priv; 1654 u16 mask; 1655 1656 if (state != BR_STATE_FORWARDING) { 1657 /* Ports that aren't in the forwarding state must not 1658 * forward packets anywhere. 1659 */ 1660 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1661 VSC73XX_SRCMASKS + port, 1662 VSC73XX_SRCMASKS_PORTS_MASK, 0); 1663 1664 dsa_switch_for_each_available_port(other_dp, ds) { 1665 if (other_dp == dp) 1666 continue; 1667 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1668 VSC73XX_SRCMASKS + other_dp->index, 1669 BIT(port), 0); 1670 } 1671 1672 return; 1673 } 1674 1675 /* Forwarding ports must forward to the CPU and to other ports 1676 * in the same bridge 1677 */ 1678 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1679 VSC73XX_SRCMASKS + CPU_PORT, BIT(port), BIT(port)); 1680 1681 mask = BIT(CPU_PORT); 1682 1683 dsa_switch_for_each_user_port(other_dp, ds) { 1684 int other_port = other_dp->index; 1685 1686 if (port == other_port || !dsa_port_bridge_same(dp, other_dp) || 1687 other_dp->stp_state != BR_STATE_FORWARDING) 1688 continue; 1689 1690 mask |= BIT(other_port); 1691 1692 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1693 VSC73XX_SRCMASKS + other_port, 1694 BIT(port), BIT(port)); 1695 } 1696 1697 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1698 VSC73XX_SRCMASKS + port, 1699 VSC73XX_SRCMASKS_PORTS_MASK, mask); 1700 } 1701 1702 /* FIXME: STP frames aren't forwarded at this moment. BPDU frames are 1703 * forwarded only from and to PI/SI interface. For more info see chapter 1704 * 2.7.1 (CPU Forwarding) in datasheet. 1705 * This function is required for tag_8021q operations. 1706 */ 1707 static void vsc73xx_port_stp_state_set(struct dsa_switch *ds, int port, 1708 u8 state) 1709 { 1710 struct dsa_port *dp = dsa_to_port(ds, port); 1711 struct vsc73xx *vsc = ds->priv; 1712 u32 val = 0; 1713 1714 if (state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) 1715 val = dp->learning ? BIT(port) : 0; 1716 1717 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1718 VSC73XX_LEARNMASK, BIT(port), val); 1719 1720 val = (state == BR_STATE_BLOCKING || state == BR_STATE_DISABLED) ? 1721 0 : BIT(port); 1722 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1723 VSC73XX_RECVMASK, BIT(port), val); 1724 1725 /* CPU Port should always forward packets when user ports are forwarding 1726 * so let's configure it from other ports only. 1727 */ 1728 if (port != CPU_PORT) 1729 vsc73xx_refresh_fwd_map(ds, port, state); 1730 } 1731 1732 static const struct phylink_mac_ops vsc73xx_phylink_mac_ops = { 1733 .mac_config = vsc73xx_mac_config, 1734 .mac_link_down = vsc73xx_mac_link_down, 1735 .mac_link_up = vsc73xx_mac_link_up, 1736 }; 1737 1738 static const struct dsa_switch_ops vsc73xx_ds_ops = { 1739 .get_tag_protocol = vsc73xx_get_tag_protocol, 1740 .setup = vsc73xx_setup, 1741 .teardown = vsc73xx_teardown, 1742 .phy_read = vsc73xx_phy_read, 1743 .phy_write = vsc73xx_phy_write, 1744 .get_strings = vsc73xx_get_strings, 1745 .get_ethtool_stats = vsc73xx_get_ethtool_stats, 1746 .get_sset_count = vsc73xx_get_sset_count, 1747 .port_enable = vsc73xx_port_enable, 1748 .port_disable = vsc73xx_port_disable, 1749 .port_pre_bridge_flags = vsc73xx_port_pre_bridge_flags, 1750 .port_bridge_flags = vsc73xx_port_bridge_flags, 1751 .port_bridge_join = dsa_tag_8021q_bridge_join, 1752 .port_bridge_leave = dsa_tag_8021q_bridge_leave, 1753 .port_change_mtu = vsc73xx_change_mtu, 1754 .port_max_mtu = vsc73xx_get_max_mtu, 1755 .port_stp_state_set = vsc73xx_port_stp_state_set, 1756 .port_vlan_filtering = vsc73xx_port_vlan_filtering, 1757 .port_vlan_add = vsc73xx_port_vlan_add, 1758 .port_vlan_del = vsc73xx_port_vlan_del, 1759 .phylink_get_caps = vsc73xx_phylink_get_caps, 1760 .tag_8021q_vlan_add = vsc73xx_tag_8021q_vlan_add, 1761 .tag_8021q_vlan_del = vsc73xx_tag_8021q_vlan_del, 1762 }; 1763 1764 static int vsc73xx_gpio_get(struct gpio_chip *chip, unsigned int offset) 1765 { 1766 struct vsc73xx *vsc = gpiochip_get_data(chip); 1767 u32 val; 1768 int ret; 1769 1770 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1771 VSC73XX_GPIO, &val); 1772 if (ret) 1773 return ret; 1774 1775 return !!(val & BIT(offset)); 1776 } 1777 1778 static void vsc73xx_gpio_set(struct gpio_chip *chip, unsigned int offset, 1779 int val) 1780 { 1781 struct vsc73xx *vsc = gpiochip_get_data(chip); 1782 u32 tmp = val ? BIT(offset) : 0; 1783 1784 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1785 VSC73XX_GPIO, BIT(offset), tmp); 1786 } 1787 1788 static int vsc73xx_gpio_direction_output(struct gpio_chip *chip, 1789 unsigned int offset, int val) 1790 { 1791 struct vsc73xx *vsc = gpiochip_get_data(chip); 1792 u32 tmp = val ? BIT(offset) : 0; 1793 1794 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1795 VSC73XX_GPIO, BIT(offset + 4) | BIT(offset), 1796 BIT(offset + 4) | tmp); 1797 } 1798 1799 static int vsc73xx_gpio_direction_input(struct gpio_chip *chip, 1800 unsigned int offset) 1801 { 1802 struct vsc73xx *vsc = gpiochip_get_data(chip); 1803 1804 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1805 VSC73XX_GPIO, BIT(offset + 4), 1806 0); 1807 } 1808 1809 static int vsc73xx_gpio_get_direction(struct gpio_chip *chip, 1810 unsigned int offset) 1811 { 1812 struct vsc73xx *vsc = gpiochip_get_data(chip); 1813 u32 val; 1814 int ret; 1815 1816 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1817 VSC73XX_GPIO, &val); 1818 if (ret) 1819 return ret; 1820 1821 return !(val & BIT(offset + 4)); 1822 } 1823 1824 static int vsc73xx_gpio_probe(struct vsc73xx *vsc) 1825 { 1826 int ret; 1827 1828 vsc->gc.label = devm_kasprintf(vsc->dev, GFP_KERNEL, "VSC%04x", 1829 vsc->chipid); 1830 if (!vsc->gc.label) 1831 return -ENOMEM; 1832 vsc->gc.ngpio = 4; 1833 vsc->gc.owner = THIS_MODULE; 1834 vsc->gc.parent = vsc->dev; 1835 vsc->gc.base = -1; 1836 vsc->gc.get = vsc73xx_gpio_get; 1837 vsc->gc.set = vsc73xx_gpio_set; 1838 vsc->gc.direction_input = vsc73xx_gpio_direction_input; 1839 vsc->gc.direction_output = vsc73xx_gpio_direction_output; 1840 vsc->gc.get_direction = vsc73xx_gpio_get_direction; 1841 vsc->gc.can_sleep = true; 1842 ret = devm_gpiochip_add_data(vsc->dev, &vsc->gc, vsc); 1843 if (ret) { 1844 dev_err(vsc->dev, "unable to register GPIO chip\n"); 1845 return ret; 1846 } 1847 return 0; 1848 } 1849 1850 int vsc73xx_probe(struct vsc73xx *vsc) 1851 { 1852 struct device *dev = vsc->dev; 1853 int ret; 1854 1855 /* Release reset, if any */ 1856 vsc->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1857 if (IS_ERR(vsc->reset)) { 1858 dev_err(dev, "failed to get RESET GPIO\n"); 1859 return PTR_ERR(vsc->reset); 1860 } 1861 if (vsc->reset) 1862 /* Wait 20ms according to datasheet table 245 */ 1863 msleep(20); 1864 1865 ret = vsc73xx_detect(vsc); 1866 if (ret == -EAGAIN) { 1867 dev_err(vsc->dev, 1868 "Chip seems to be out of control. Assert reset and try again.\n"); 1869 gpiod_set_value_cansleep(vsc->reset, 1); 1870 /* Reset pulse should be 20ns minimum, according to datasheet 1871 * table 245, so 10us should be fine 1872 */ 1873 usleep_range(10, 100); 1874 gpiod_set_value_cansleep(vsc->reset, 0); 1875 /* Wait 20ms according to datasheet table 245 */ 1876 msleep(20); 1877 ret = vsc73xx_detect(vsc); 1878 } 1879 if (ret) { 1880 dev_err(dev, "no chip found (%d)\n", ret); 1881 return -ENODEV; 1882 } 1883 1884 eth_random_addr(vsc->addr); 1885 dev_info(vsc->dev, 1886 "MAC for control frames: %02X:%02X:%02X:%02X:%02X:%02X\n", 1887 vsc->addr[0], vsc->addr[1], vsc->addr[2], 1888 vsc->addr[3], vsc->addr[4], vsc->addr[5]); 1889 1890 vsc->ds = devm_kzalloc(dev, sizeof(*vsc->ds), GFP_KERNEL); 1891 if (!vsc->ds) 1892 return -ENOMEM; 1893 1894 vsc->ds->dev = dev; 1895 vsc->ds->num_ports = VSC73XX_MAX_NUM_PORTS; 1896 vsc->ds->priv = vsc; 1897 1898 vsc->ds->ops = &vsc73xx_ds_ops; 1899 vsc->ds->phylink_mac_ops = &vsc73xx_phylink_mac_ops; 1900 ret = dsa_register_switch(vsc->ds); 1901 if (ret) { 1902 dev_err(dev, "unable to register switch (%d)\n", ret); 1903 return ret; 1904 } 1905 1906 ret = vsc73xx_gpio_probe(vsc); 1907 if (ret) { 1908 dsa_unregister_switch(vsc->ds); 1909 return ret; 1910 } 1911 1912 return 0; 1913 } 1914 EXPORT_SYMBOL(vsc73xx_probe); 1915 1916 void vsc73xx_remove(struct vsc73xx *vsc) 1917 { 1918 dsa_unregister_switch(vsc->ds); 1919 gpiod_set_value(vsc->reset, 1); 1920 } 1921 EXPORT_SYMBOL(vsc73xx_remove); 1922 1923 void vsc73xx_shutdown(struct vsc73xx *vsc) 1924 { 1925 dsa_switch_shutdown(vsc->ds); 1926 } 1927 EXPORT_SYMBOL(vsc73xx_shutdown); 1928 1929 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>"); 1930 MODULE_DESCRIPTION("Vitesse VSC7385/7388/7395/7398 driver"); 1931 MODULE_LICENSE("GPL v2"); 1932