1 // SPDX-License-Identifier: GPL-2.0 2 /* DSA driver for: 3 * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch 4 * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch 5 * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch 6 * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch 7 * 8 * These switches have a built-in 8051 CPU and can download and execute a 9 * firmware in this CPU. They can also be configured to use an external CPU 10 * handling the switch in a memory-mapped manner by connecting to that external 11 * CPU's memory bus. 12 * 13 * Copyright (C) 2018 Linus Wallej <linus.walleij@linaro.org> 14 * Includes portions of code from the firmware uploader by: 15 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> 16 */ 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/device.h> 20 #include <linux/iopoll.h> 21 #include <linux/of.h> 22 #include <linux/of_mdio.h> 23 #include <linux/bitops.h> 24 #include <linux/bitfield.h> 25 #include <linux/if_bridge.h> 26 #include <linux/if_vlan.h> 27 #include <linux/etherdevice.h> 28 #include <linux/gpio/consumer.h> 29 #include <linux/gpio/driver.h> 30 #include <linux/dsa/8021q.h> 31 #include <linux/random.h> 32 #include <net/dsa.h> 33 34 #include "vitesse-vsc73xx.h" 35 36 #define VSC73XX_BLOCK_MAC 0x1 /* Subblocks 0-4, 6 (CPU port) */ 37 #define VSC73XX_BLOCK_ANALYZER 0x2 /* Only subblock 0 */ 38 #define VSC73XX_BLOCK_MII 0x3 /* Subblocks 0 and 1 */ 39 #define VSC73XX_BLOCK_MEMINIT 0x3 /* Only subblock 2 */ 40 #define VSC73XX_BLOCK_CAPTURE 0x4 /* Only subblock 2 */ 41 #define VSC73XX_BLOCK_ARBITER 0x5 /* Only subblock 0 */ 42 #define VSC73XX_BLOCK_SYSTEM 0x7 /* Only subblock 0 */ 43 44 /* MII Block subblock */ 45 #define VSC73XX_BLOCK_MII_INTERNAL 0x0 /* Internal MDIO subblock */ 46 #define VSC73XX_BLOCK_MII_EXTERNAL 0x1 /* External MDIO subblock */ 47 48 #define CPU_PORT 6 /* CPU port */ 49 50 /* MAC Block registers */ 51 #define VSC73XX_MAC_CFG 0x00 52 #define VSC73XX_MACHDXGAP 0x02 53 #define VSC73XX_FCCONF 0x04 54 #define VSC73XX_FCMACHI 0x08 55 #define VSC73XX_FCMACLO 0x0c 56 #define VSC73XX_MAXLEN 0x10 57 #define VSC73XX_ADVPORTM 0x19 58 #define VSC73XX_TXUPDCFG 0x24 59 #define VSC73XX_TXQ_SELECT_CFG 0x28 60 #define VSC73XX_RXOCT 0x50 61 #define VSC73XX_TXOCT 0x51 62 #define VSC73XX_C_RX0 0x52 63 #define VSC73XX_C_RX1 0x53 64 #define VSC73XX_C_RX2 0x54 65 #define VSC73XX_C_TX0 0x55 66 #define VSC73XX_C_TX1 0x56 67 #define VSC73XX_C_TX2 0x57 68 #define VSC73XX_C_CFG 0x58 69 #define VSC73XX_CAT_DROP 0x6e 70 #define VSC73XX_CAT_PR_MISC_L2 0x6f 71 #define VSC73XX_CAT_PR_USR_PRIO 0x75 72 #define VSC73XX_CAT_VLAN_MISC 0x79 73 #define VSC73XX_CAT_PORT_VLAN 0x7a 74 #define VSC73XX_Q_MISC_CONF 0xdf 75 76 /* MAC_CFG register bits */ 77 #define VSC73XX_MAC_CFG_WEXC_DIS BIT(31) 78 #define VSC73XX_MAC_CFG_PORT_RST BIT(29) 79 #define VSC73XX_MAC_CFG_TX_EN BIT(28) 80 #define VSC73XX_MAC_CFG_SEED_LOAD BIT(27) 81 #define VSC73XX_MAC_CFG_SEED_MASK GENMASK(26, 19) 82 #define VSC73XX_MAC_CFG_SEED_OFFSET 19 83 #define VSC73XX_MAC_CFG_FDX BIT(18) 84 #define VSC73XX_MAC_CFG_GIGA_MODE BIT(17) 85 #define VSC73XX_MAC_CFG_RX_EN BIT(16) 86 #define VSC73XX_MAC_CFG_VLAN_DBLAWR BIT(15) 87 #define VSC73XX_MAC_CFG_VLAN_AWR BIT(14) 88 #define VSC73XX_MAC_CFG_100_BASE_T BIT(13) /* Not in manual */ 89 #define VSC73XX_MAC_CFG_TX_IPG_MASK GENMASK(10, 6) 90 #define VSC73XX_MAC_CFG_TX_IPG_OFFSET 6 91 #define VSC73XX_MAC_CFG_TX_IPG_1000M (6 << VSC73XX_MAC_CFG_TX_IPG_OFFSET) 92 #define VSC73XX_MAC_CFG_TX_IPG_100_10M (17 << VSC73XX_MAC_CFG_TX_IPG_OFFSET) 93 #define VSC73XX_MAC_CFG_MAC_RX_RST BIT(5) 94 #define VSC73XX_MAC_CFG_MAC_TX_RST BIT(4) 95 #define VSC73XX_MAC_CFG_CLK_SEL_MASK GENMASK(2, 0) 96 #define VSC73XX_MAC_CFG_CLK_SEL_OFFSET 0 97 #define VSC73XX_MAC_CFG_CLK_SEL_1000M 1 98 #define VSC73XX_MAC_CFG_CLK_SEL_100M 2 99 #define VSC73XX_MAC_CFG_CLK_SEL_10M 3 100 #define VSC73XX_MAC_CFG_CLK_SEL_EXT 4 101 102 #define VSC73XX_MAC_CFG_1000M_F_PHY (VSC73XX_MAC_CFG_FDX | \ 103 VSC73XX_MAC_CFG_GIGA_MODE | \ 104 VSC73XX_MAC_CFG_TX_IPG_1000M | \ 105 VSC73XX_MAC_CFG_CLK_SEL_EXT) 106 #define VSC73XX_MAC_CFG_100_10M_F_PHY (VSC73XX_MAC_CFG_FDX | \ 107 VSC73XX_MAC_CFG_TX_IPG_100_10M | \ 108 VSC73XX_MAC_CFG_CLK_SEL_EXT) 109 #define VSC73XX_MAC_CFG_100_10M_H_PHY (VSC73XX_MAC_CFG_TX_IPG_100_10M | \ 110 VSC73XX_MAC_CFG_CLK_SEL_EXT) 111 #define VSC73XX_MAC_CFG_1000M_F_RGMII (VSC73XX_MAC_CFG_FDX | \ 112 VSC73XX_MAC_CFG_GIGA_MODE | \ 113 VSC73XX_MAC_CFG_TX_IPG_1000M | \ 114 VSC73XX_MAC_CFG_CLK_SEL_1000M) 115 #define VSC73XX_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \ 116 VSC73XX_MAC_CFG_MAC_RX_RST | \ 117 VSC73XX_MAC_CFG_MAC_TX_RST) 118 119 /* Flow control register bits */ 120 #define VSC73XX_FCCONF_ZERO_PAUSE_EN BIT(17) 121 #define VSC73XX_FCCONF_FLOW_CTRL_OBEY BIT(16) 122 #define VSC73XX_FCCONF_PAUSE_VAL_MASK GENMASK(15, 0) 123 124 /* ADVPORTM advanced port setup register bits */ 125 #define VSC73XX_ADVPORTM_IFG_PPM BIT(7) 126 #define VSC73XX_ADVPORTM_EXC_COL_CONT BIT(6) 127 #define VSC73XX_ADVPORTM_EXT_PORT BIT(5) 128 #define VSC73XX_ADVPORTM_INV_GTX BIT(4) 129 #define VSC73XX_ADVPORTM_ENA_GTX BIT(3) 130 #define VSC73XX_ADVPORTM_DDR_MODE BIT(2) 131 #define VSC73XX_ADVPORTM_IO_LOOPBACK BIT(1) 132 #define VSC73XX_ADVPORTM_HOST_LOOPBACK BIT(0) 133 134 /* TXUPDCFG transmit modify setup bits */ 135 #define VSC73XX_TXUPDCFG_DSCP_REWR_MODE GENMASK(20, 19) 136 #define VSC73XX_TXUPDCFG_DSCP_REWR_ENA BIT(18) 137 #define VSC73XX_TXUPDCFG_TX_INT_TO_USRPRIO_ENA BIT(17) 138 #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID GENMASK(15, 4) 139 #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA BIT(3) 140 #define VSC73XX_TXUPDCFG_TX_UPDATE_CRC_CPU_ENA BIT(1) 141 #define VSC73XX_TXUPDCFG_TX_INSERT_TAG BIT(0) 142 143 #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_SHIFT 4 144 145 /* CAT_DROP categorizer frame dropping register bits */ 146 #define VSC73XX_CAT_DROP_DROP_MC_SMAC_ENA BIT(6) 147 #define VSC73XX_CAT_DROP_FWD_CTRL_ENA BIT(4) 148 #define VSC73XX_CAT_DROP_FWD_PAUSE_ENA BIT(3) 149 #define VSC73XX_CAT_DROP_UNTAGGED_ENA BIT(2) 150 #define VSC73XX_CAT_DROP_TAGGED_ENA BIT(1) 151 #define VSC73XX_CAT_DROP_NULL_MAC_ENA BIT(0) 152 153 #define VSC73XX_Q_MISC_CONF_EXTENT_MEM BIT(31) 154 #define VSC73XX_Q_MISC_CONF_EARLY_TX_MASK GENMASK(4, 1) 155 #define VSC73XX_Q_MISC_CONF_EARLY_TX_512 (1 << 1) 156 #define VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE BIT(0) 157 158 /* CAT_VLAN_MISC categorizer VLAN miscellaneous bits */ 159 #define VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA BIT(8) 160 #define VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA BIT(7) 161 162 /* CAT_PORT_VLAN categorizer port VLAN */ 163 #define VSC73XX_CAT_PORT_VLAN_VLAN_CFI BIT(15) 164 #define VSC73XX_CAT_PORT_VLAN_VLAN_USR_PRIO GENMASK(14, 12) 165 #define VSC73XX_CAT_PORT_VLAN_VLAN_VID GENMASK(11, 0) 166 167 /* Frame analyzer block 2 registers */ 168 #define VSC73XX_STORMLIMIT 0x02 169 #define VSC73XX_ADVLEARN 0x03 170 #define VSC73XX_IFLODMSK 0x04 171 #define VSC73XX_VLANMASK 0x05 172 #define VSC73XX_MACHDATA 0x06 173 #define VSC73XX_MACLDATA 0x07 174 #define VSC73XX_ANMOVED 0x08 175 #define VSC73XX_ANAGEFIL 0x09 176 #define VSC73XX_ANEVENTS 0x0a 177 #define VSC73XX_ANCNTMASK 0x0b 178 #define VSC73XX_ANCNTVAL 0x0c 179 #define VSC73XX_LEARNMASK 0x0d 180 #define VSC73XX_UFLODMASK 0x0e 181 #define VSC73XX_MFLODMASK 0x0f 182 #define VSC73XX_RECVMASK 0x10 183 #define VSC73XX_AGGRCTRL 0x20 184 #define VSC73XX_AGGRMSKS 0x30 /* Until 0x3f */ 185 #define VSC73XX_DSTMASKS 0x40 /* Until 0x7f */ 186 #define VSC73XX_SRCMASKS 0x80 /* Until 0x87 */ 187 #define VSC73XX_CAPENAB 0xa0 188 #define VSC73XX_MACACCESS 0xb0 189 #define VSC73XX_IPMCACCESS 0xb1 190 #define VSC73XX_MACTINDX 0xc0 191 #define VSC73XX_VLANACCESS 0xd0 192 #define VSC73XX_VLANTIDX 0xe0 193 #define VSC73XX_AGENCTRL 0xf0 194 #define VSC73XX_CAPRST 0xff 195 196 #define VSC73XX_SRCMASKS_CPU_COPY BIT(27) 197 #define VSC73XX_SRCMASKS_MIRROR BIT(26) 198 #define VSC73XX_SRCMASKS_PORTS_MASK GENMASK(7, 0) 199 200 #define VSC73XX_MACACCESS_CPU_COPY BIT(14) 201 #define VSC73XX_MACACCESS_FWD_KILL BIT(13) 202 #define VSC73XX_MACACCESS_IGNORE_VLAN BIT(12) 203 #define VSC73XX_MACACCESS_AGED_FLAG BIT(11) 204 #define VSC73XX_MACACCESS_VALID BIT(10) 205 #define VSC73XX_MACACCESS_LOCKED BIT(9) 206 #define VSC73XX_MACACCESS_DEST_IDX_MASK GENMASK(8, 3) 207 #define VSC73XX_MACACCESS_CMD_MASK GENMASK(2, 0) 208 #define VSC73XX_MACACCESS_CMD_IDLE 0 209 #define VSC73XX_MACACCESS_CMD_LEARN 1 210 #define VSC73XX_MACACCESS_CMD_FORGET 2 211 #define VSC73XX_MACACCESS_CMD_AGE_TABLE 3 212 #define VSC73XX_MACACCESS_CMD_FLUSH_TABLE 4 213 #define VSC73XX_MACACCESS_CMD_CLEAR_TABLE 5 214 #define VSC73XX_MACACCESS_CMD_READ_ENTRY 6 215 #define VSC73XX_MACACCESS_CMD_WRITE_ENTRY 7 216 217 #define VSC73XX_VLANACCESS_LEARN_DISABLED BIT(30) 218 #define VSC73XX_VLANACCESS_VLAN_MIRROR BIT(29) 219 #define VSC73XX_VLANACCESS_VLAN_SRC_CHECK BIT(28) 220 #define VSC73XX_VLANACCESS_VLAN_PORT_MASK GENMASK(9, 2) 221 #define VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT 2 222 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK GENMASK(1, 0) 223 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE 0 224 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY 1 225 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY 2 226 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE 3 227 228 /* MII block 3 registers */ 229 #define VSC73XX_MII_STAT 0x0 230 #define VSC73XX_MII_CMD 0x1 231 #define VSC73XX_MII_DATA 0x2 232 #define VSC73XX_MII_MPRES 0x3 233 234 #define VSC73XX_MII_STAT_BUSY BIT(3) 235 #define VSC73XX_MII_STAT_READ BIT(2) 236 #define VSC73XX_MII_STAT_WRITE BIT(1) 237 238 #define VSC73XX_MII_CMD_SCAN BIT(27) 239 #define VSC73XX_MII_CMD_OPERATION BIT(26) 240 #define VSC73XX_MII_CMD_PHY_ADDR GENMASK(25, 21) 241 #define VSC73XX_MII_CMD_PHY_REG GENMASK(20, 16) 242 #define VSC73XX_MII_CMD_WRITE_DATA GENMASK(15, 0) 243 244 #define VSC73XX_MII_DATA_FAILURE BIT(16) 245 #define VSC73XX_MII_DATA_READ_DATA GENMASK(15, 0) 246 247 #define VSC73XX_MII_MPRES_NOPREAMBLE BIT(6) 248 #define VSC73XX_MII_MPRES_PRESCALEVAL GENMASK(5, 0) 249 #define VSC73XX_MII_PRESCALEVAL_MIN 3 /* min allowed mdio clock prescaler */ 250 251 /* Arbiter block 5 registers */ 252 #define VSC73XX_ARBEMPTY 0x0c 253 #define VSC73XX_ARBDISC 0x0e 254 #define VSC73XX_SBACKWDROP 0x12 255 #define VSC73XX_DBACKWDROP 0x13 256 #define VSC73XX_ARBBURSTPROB 0x15 257 258 /* System block 7 registers */ 259 #define VSC73XX_ICPU_SIPAD 0x01 260 #define VSC73XX_GMIIDELAY 0x05 261 #define VSC73XX_ICPU_CTRL 0x10 262 #define VSC73XX_ICPU_ADDR 0x11 263 #define VSC73XX_ICPU_SRAM 0x12 264 #define VSC73XX_HWSEM 0x13 265 #define VSC73XX_GLORESET 0x14 266 #define VSC73XX_ICPU_MBOX_VAL 0x15 267 #define VSC73XX_ICPU_MBOX_SET 0x16 268 #define VSC73XX_ICPU_MBOX_CLR 0x17 269 #define VSC73XX_CHIPID 0x18 270 #define VSC73XX_GPIO 0x34 271 272 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_NONE 0 273 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_4_NS 1 274 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_7_NS 2 275 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS 3 276 277 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_NONE (0 << 4) 278 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_4_NS (1 << 4) 279 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_7_NS (2 << 4) 280 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS (3 << 4) 281 282 #define VSC73XX_ICPU_CTRL_WATCHDOG_RST BIT(31) 283 #define VSC73XX_ICPU_CTRL_CLK_DIV_MASK GENMASK(12, 8) 284 #define VSC73XX_ICPU_CTRL_SRST_HOLD BIT(7) 285 #define VSC73XX_ICPU_CTRL_ICPU_PI_EN BIT(6) 286 #define VSC73XX_ICPU_CTRL_BOOT_EN BIT(3) 287 #define VSC73XX_ICPU_CTRL_EXT_ACC_EN BIT(2) 288 #define VSC73XX_ICPU_CTRL_CLK_EN BIT(1) 289 #define VSC73XX_ICPU_CTRL_SRST BIT(0) 290 291 #define VSC73XX_CHIPID_ID_SHIFT 12 292 #define VSC73XX_CHIPID_ID_MASK 0xffff 293 #define VSC73XX_CHIPID_REV_SHIFT 28 294 #define VSC73XX_CHIPID_REV_MASK 0xf 295 #define VSC73XX_CHIPID_ID_7385 0x7385 296 #define VSC73XX_CHIPID_ID_7388 0x7388 297 #define VSC73XX_CHIPID_ID_7395 0x7395 298 #define VSC73XX_CHIPID_ID_7398 0x7398 299 300 #define VSC73XX_GLORESET_STROBE BIT(4) 301 #define VSC73XX_GLORESET_ICPU_LOCK BIT(3) 302 #define VSC73XX_GLORESET_MEM_LOCK BIT(2) 303 #define VSC73XX_GLORESET_PHY_RESET BIT(1) 304 #define VSC73XX_GLORESET_MASTER_RESET BIT(0) 305 306 #define VSC7385_CLOCK_DELAY ((3 << 4) | 3) 307 #define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3) 308 309 #define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \ 310 VSC73XX_ICPU_CTRL_BOOT_EN | \ 311 VSC73XX_ICPU_CTRL_EXT_ACC_EN) 312 313 #define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \ 314 VSC73XX_ICPU_CTRL_BOOT_EN | \ 315 VSC73XX_ICPU_CTRL_CLK_EN | \ 316 VSC73XX_ICPU_CTRL_SRST) 317 318 #define IS_7385(a) ((a)->chipid == VSC73XX_CHIPID_ID_7385) 319 #define IS_7388(a) ((a)->chipid == VSC73XX_CHIPID_ID_7388) 320 #define IS_7395(a) ((a)->chipid == VSC73XX_CHIPID_ID_7395) 321 #define IS_7398(a) ((a)->chipid == VSC73XX_CHIPID_ID_7398) 322 #define IS_739X(a) (IS_7395(a) || IS_7398(a)) 323 324 #define VSC73XX_POLL_SLEEP_US 1000 325 #define VSC73XX_POLL_TIMEOUT_US 10000 326 327 struct vsc73xx_counter { 328 u8 counter; 329 const char *name; 330 }; 331 332 /* Counters are named according to the MIB standards where applicable. 333 * Some counters are custom, non-standard. The standard counters are 334 * named in accordance with RFC2819, RFC2021 and IEEE Std 802.3-2002 Annex 335 * 30A Counters. 336 */ 337 static const struct vsc73xx_counter vsc73xx_rx_counters[] = { 338 { 0, "RxEtherStatsPkts" }, 339 { 1, "RxBroadcast+MulticastPkts" }, /* non-standard counter */ 340 { 2, "RxTotalErrorPackets" }, /* non-standard counter */ 341 { 3, "RxEtherStatsBroadcastPkts" }, 342 { 4, "RxEtherStatsMulticastPkts" }, 343 { 5, "RxEtherStatsPkts64Octets" }, 344 { 6, "RxEtherStatsPkts65to127Octets" }, 345 { 7, "RxEtherStatsPkts128to255Octets" }, 346 { 8, "RxEtherStatsPkts256to511Octets" }, 347 { 9, "RxEtherStatsPkts512to1023Octets" }, 348 { 10, "RxEtherStatsPkts1024to1518Octets" }, 349 { 11, "RxJumboFrames" }, /* non-standard counter */ 350 { 12, "RxaPauseMACControlFramesTransmitted" }, 351 { 13, "RxFIFODrops" }, /* non-standard counter */ 352 { 14, "RxBackwardDrops" }, /* non-standard counter */ 353 { 15, "RxClassifierDrops" }, /* non-standard counter */ 354 { 16, "RxEtherStatsCRCAlignErrors" }, 355 { 17, "RxEtherStatsUndersizePkts" }, 356 { 18, "RxEtherStatsOversizePkts" }, 357 { 19, "RxEtherStatsFragments" }, 358 { 20, "RxEtherStatsJabbers" }, 359 { 21, "RxaMACControlFramesReceived" }, 360 /* 22-24 are undefined */ 361 { 25, "RxaFramesReceivedOK" }, 362 { 26, "RxQoSClass0" }, /* non-standard counter */ 363 { 27, "RxQoSClass1" }, /* non-standard counter */ 364 { 28, "RxQoSClass2" }, /* non-standard counter */ 365 { 29, "RxQoSClass3" }, /* non-standard counter */ 366 }; 367 368 static const struct vsc73xx_counter vsc73xx_tx_counters[] = { 369 { 0, "TxEtherStatsPkts" }, 370 { 1, "TxBroadcast+MulticastPkts" }, /* non-standard counter */ 371 { 2, "TxTotalErrorPackets" }, /* non-standard counter */ 372 { 3, "TxEtherStatsBroadcastPkts" }, 373 { 4, "TxEtherStatsMulticastPkts" }, 374 { 5, "TxEtherStatsPkts64Octets" }, 375 { 6, "TxEtherStatsPkts65to127Octets" }, 376 { 7, "TxEtherStatsPkts128to255Octets" }, 377 { 8, "TxEtherStatsPkts256to511Octets" }, 378 { 9, "TxEtherStatsPkts512to1023Octets" }, 379 { 10, "TxEtherStatsPkts1024to1518Octets" }, 380 { 11, "TxJumboFrames" }, /* non-standard counter */ 381 { 12, "TxaPauseMACControlFramesTransmitted" }, 382 { 13, "TxFIFODrops" }, /* non-standard counter */ 383 { 14, "TxDrops" }, /* non-standard counter */ 384 { 15, "TxEtherStatsCollisions" }, 385 { 16, "TxEtherStatsCRCAlignErrors" }, 386 { 17, "TxEtherStatsUndersizePkts" }, 387 { 18, "TxEtherStatsOversizePkts" }, 388 { 19, "TxEtherStatsFragments" }, 389 { 20, "TxEtherStatsJabbers" }, 390 /* 21-24 are undefined */ 391 { 25, "TxaFramesReceivedOK" }, 392 { 26, "TxQoSClass0" }, /* non-standard counter */ 393 { 27, "TxQoSClass1" }, /* non-standard counter */ 394 { 28, "TxQoSClass2" }, /* non-standard counter */ 395 { 29, "TxQoSClass3" }, /* non-standard counter */ 396 }; 397 398 struct vsc73xx_vlan_summary { 399 size_t num_tagged; 400 size_t num_untagged; 401 }; 402 403 enum vsc73xx_port_vlan_conf { 404 VSC73XX_VLAN_FILTER, 405 VSC73XX_VLAN_FILTER_UNTAG_ALL, 406 VSC73XX_VLAN_IGNORE, 407 }; 408 409 int vsc73xx_is_addr_valid(u8 block, u8 subblock) 410 { 411 switch (block) { 412 case VSC73XX_BLOCK_MAC: 413 switch (subblock) { 414 case 0 ... 4: 415 case 6: 416 return 1; 417 } 418 break; 419 420 case VSC73XX_BLOCK_ANALYZER: 421 case VSC73XX_BLOCK_SYSTEM: 422 switch (subblock) { 423 case 0: 424 return 1; 425 } 426 break; 427 428 case VSC73XX_BLOCK_MII: 429 case VSC73XX_BLOCK_CAPTURE: 430 case VSC73XX_BLOCK_ARBITER: 431 switch (subblock) { 432 case 0 ... 1: 433 return 1; 434 } 435 break; 436 } 437 438 return 0; 439 } 440 EXPORT_SYMBOL(vsc73xx_is_addr_valid); 441 442 static int vsc73xx_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, 443 u32 *val) 444 { 445 return vsc->ops->read(vsc, block, subblock, reg, val); 446 } 447 448 static int vsc73xx_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, 449 u32 val) 450 { 451 return vsc->ops->write(vsc, block, subblock, reg, val); 452 } 453 454 static int vsc73xx_update_bits(struct vsc73xx *vsc, u8 block, u8 subblock, 455 u8 reg, u32 mask, u32 val) 456 { 457 u32 tmp, orig; 458 int ret; 459 460 /* Same read-modify-write algorithm as e.g. regmap */ 461 ret = vsc73xx_read(vsc, block, subblock, reg, &orig); 462 if (ret) 463 return ret; 464 tmp = orig & ~mask; 465 tmp |= val & mask; 466 return vsc73xx_write(vsc, block, subblock, reg, tmp); 467 } 468 469 static int vsc73xx_detect(struct vsc73xx *vsc) 470 { 471 bool icpu_si_boot_en; 472 bool icpu_pi_en; 473 u32 val; 474 u32 rev; 475 int ret; 476 u32 id; 477 478 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 479 VSC73XX_ICPU_MBOX_VAL, &val); 480 if (ret) { 481 dev_err(vsc->dev, "unable to read mailbox (%d)\n", ret); 482 return ret; 483 } 484 485 if (val == 0xffffffff) { 486 dev_info(vsc->dev, "chip seems dead.\n"); 487 return -EAGAIN; 488 } 489 490 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 491 VSC73XX_CHIPID, &val); 492 if (ret) { 493 dev_err(vsc->dev, "unable to read chip id (%d)\n", ret); 494 return ret; 495 } 496 497 id = (val >> VSC73XX_CHIPID_ID_SHIFT) & 498 VSC73XX_CHIPID_ID_MASK; 499 switch (id) { 500 case VSC73XX_CHIPID_ID_7385: 501 case VSC73XX_CHIPID_ID_7388: 502 case VSC73XX_CHIPID_ID_7395: 503 case VSC73XX_CHIPID_ID_7398: 504 break; 505 default: 506 dev_err(vsc->dev, "unsupported chip, id=%04x\n", id); 507 return -ENODEV; 508 } 509 510 vsc->chipid = id; 511 rev = (val >> VSC73XX_CHIPID_REV_SHIFT) & 512 VSC73XX_CHIPID_REV_MASK; 513 dev_info(vsc->dev, "VSC%04X (rev: %d) switch found\n", id, rev); 514 515 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 516 VSC73XX_ICPU_CTRL, &val); 517 if (ret) { 518 dev_err(vsc->dev, "unable to read iCPU control\n"); 519 return ret; 520 } 521 522 /* The iCPU can always be used but can boot in different ways. 523 * If it is initially disabled and has no external memory, 524 * we are in control and can do whatever we like, else we 525 * are probably in trouble (we need some way to communicate 526 * with the running firmware) so we bail out for now. 527 */ 528 icpu_pi_en = !!(val & VSC73XX_ICPU_CTRL_ICPU_PI_EN); 529 icpu_si_boot_en = !!(val & VSC73XX_ICPU_CTRL_BOOT_EN); 530 if (icpu_si_boot_en && icpu_pi_en) { 531 dev_err(vsc->dev, 532 "iCPU enabled boots from SI, has external memory\n"); 533 dev_err(vsc->dev, "no idea how to deal with this\n"); 534 return -ENODEV; 535 } 536 if (icpu_si_boot_en && !icpu_pi_en) { 537 dev_err(vsc->dev, 538 "iCPU enabled boots from PI/SI, no external memory\n"); 539 return -EAGAIN; 540 } 541 if (!icpu_si_boot_en && icpu_pi_en) { 542 dev_err(vsc->dev, 543 "iCPU enabled, boots from PI external memory\n"); 544 dev_err(vsc->dev, "no idea how to deal with this\n"); 545 return -ENODEV; 546 } 547 /* !icpu_si_boot_en && !cpu_pi_en */ 548 dev_info(vsc->dev, "iCPU disabled, no external memory\n"); 549 550 return 0; 551 } 552 553 static int vsc73xx_phy_read(struct dsa_switch *ds, int phy, int regnum) 554 { 555 struct vsc73xx *vsc = ds->priv; 556 u32 cmd; 557 u32 val; 558 int ret; 559 560 /* Setting bit 26 means "read" */ 561 cmd = VSC73XX_MII_CMD_OPERATION | 562 FIELD_PREP(VSC73XX_MII_CMD_PHY_ADDR, phy) | 563 FIELD_PREP(VSC73XX_MII_CMD_PHY_REG, regnum); 564 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL, 565 VSC73XX_MII_CMD, cmd); 566 if (ret) 567 return ret; 568 msleep(2); 569 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL, 570 VSC73XX_MII_DATA, &val); 571 if (ret) 572 return ret; 573 if (val & VSC73XX_MII_DATA_FAILURE) { 574 dev_err(vsc->dev, "reading reg %02x from phy%d failed\n", 575 regnum, phy); 576 return -EIO; 577 } 578 val &= VSC73XX_MII_DATA_READ_DATA; 579 580 dev_dbg(vsc->dev, "read reg %02x from phy%d = %04x\n", 581 regnum, phy, val); 582 583 return val; 584 } 585 586 static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum, 587 u16 val) 588 { 589 struct vsc73xx *vsc = ds->priv; 590 u32 cmd; 591 int ret; 592 593 /* It was found through tedious experiments that this router 594 * chip really hates to have it's PHYs reset. They 595 * never recover if that happens: autonegotiation stops 596 * working after a reset. Just filter out this command. 597 * (Resetting the whole chip is OK.) 598 */ 599 if (regnum == 0 && (val & BIT(15))) { 600 dev_info(vsc->dev, "reset PHY - disallowed\n"); 601 return 0; 602 } 603 604 cmd = FIELD_PREP(VSC73XX_MII_CMD_PHY_ADDR, phy) | 605 FIELD_PREP(VSC73XX_MII_CMD_PHY_REG, regnum); 606 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL, 607 VSC73XX_MII_CMD, cmd); 608 if (ret) 609 return ret; 610 611 dev_dbg(vsc->dev, "write %04x to reg %02x in phy%d\n", 612 val, regnum, phy); 613 return 0; 614 } 615 616 static enum dsa_tag_protocol vsc73xx_get_tag_protocol(struct dsa_switch *ds, 617 int port, 618 enum dsa_tag_protocol mp) 619 { 620 /* The switch internally uses a 8 byte header with length, 621 * source port, tag, LPA and priority. This is supposedly 622 * only accessible when operating the switch using the internal 623 * CPU or with an external CPU mapping the device in, but not 624 * when operating the switch over SPI and putting frames in/out 625 * on port 6 (the CPU port). So far we must assume that we 626 * cannot access the tag. (See "Internal frame header" section 627 * 3.9.1 in the manual.) 628 */ 629 return DSA_TAG_PROTO_VSC73XX_8021Q; 630 } 631 632 static int vsc73xx_wait_for_vlan_table_cmd(struct vsc73xx *vsc) 633 { 634 int ret, err; 635 u32 val; 636 637 ret = read_poll_timeout(vsc73xx_read, err, 638 err < 0 || 639 ((val & VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK) == 640 VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE), 641 VSC73XX_POLL_SLEEP_US, VSC73XX_POLL_TIMEOUT_US, 642 false, vsc, VSC73XX_BLOCK_ANALYZER, 643 0, VSC73XX_VLANACCESS, &val); 644 if (ret) 645 return ret; 646 return err; 647 } 648 649 static int 650 vsc73xx_read_vlan_table_entry(struct vsc73xx *vsc, u16 vid, u8 *portmap) 651 { 652 u32 val; 653 int ret; 654 655 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANTIDX, vid); 656 657 ret = vsc73xx_wait_for_vlan_table_cmd(vsc); 658 if (ret) 659 return ret; 660 661 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS, 662 VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK, 663 VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY); 664 665 ret = vsc73xx_wait_for_vlan_table_cmd(vsc); 666 if (ret) 667 return ret; 668 669 vsc73xx_read(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS, &val); 670 *portmap = (val & VSC73XX_VLANACCESS_VLAN_PORT_MASK) >> 671 VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT; 672 673 return 0; 674 } 675 676 static int 677 vsc73xx_write_vlan_table_entry(struct vsc73xx *vsc, u16 vid, u8 portmap) 678 { 679 int ret; 680 681 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANTIDX, vid); 682 683 ret = vsc73xx_wait_for_vlan_table_cmd(vsc); 684 if (ret) 685 return ret; 686 687 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS, 688 VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK | 689 VSC73XX_VLANACCESS_VLAN_SRC_CHECK | 690 VSC73XX_VLANACCESS_VLAN_PORT_MASK, 691 VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY | 692 VSC73XX_VLANACCESS_VLAN_SRC_CHECK | 693 (portmap << VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT)); 694 695 return vsc73xx_wait_for_vlan_table_cmd(vsc); 696 } 697 698 static int 699 vsc73xx_update_vlan_table(struct vsc73xx *vsc, int port, u16 vid, bool set) 700 { 701 u8 portmap; 702 int ret; 703 704 ret = vsc73xx_read_vlan_table_entry(vsc, vid, &portmap); 705 if (ret) 706 return ret; 707 708 if (set) 709 portmap |= BIT(port); 710 else 711 portmap &= ~BIT(port); 712 713 return vsc73xx_write_vlan_table_entry(vsc, vid, portmap); 714 } 715 716 static int vsc73xx_configure_rgmii_port_delay(struct dsa_switch *ds) 717 { 718 /* Keep 2.0 ns delay for backward complatibility */ 719 u32 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS; 720 u32 rx_delay = VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS; 721 struct dsa_port *dp = dsa_to_port(ds, CPU_PORT); 722 struct device_node *port_dn = dp->dn; 723 struct vsc73xx *vsc = ds->priv; 724 u32 delay; 725 726 if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay)) { 727 switch (delay) { 728 case 0: 729 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_NONE; 730 break; 731 case 1400: 732 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_4_NS; 733 break; 734 case 1700: 735 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_7_NS; 736 break; 737 case 2000: 738 break; 739 default: 740 dev_err(vsc->dev, 741 "Unsupported RGMII Transmit Clock Delay\n"); 742 return -EINVAL; 743 } 744 } else { 745 dev_dbg(vsc->dev, 746 "RGMII Transmit Clock Delay isn't configured, set to 2.0 ns\n"); 747 } 748 749 if (!of_property_read_u32(port_dn, "rx-internal-delay-ps", &delay)) { 750 switch (delay) { 751 case 0: 752 rx_delay = VSC73XX_GMIIDELAY_GMII0_RXDELAY_NONE; 753 break; 754 case 1400: 755 rx_delay = VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_4_NS; 756 break; 757 case 1700: 758 rx_delay = VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_7_NS; 759 break; 760 case 2000: 761 break; 762 default: 763 dev_err(vsc->dev, 764 "Unsupported RGMII Receive Clock Delay value\n"); 765 return -EINVAL; 766 } 767 } else { 768 dev_dbg(vsc->dev, 769 "RGMII Receive Clock Delay isn't configured, set to 2.0 ns\n"); 770 } 771 772 /* MII delay, set both GTX and RX delay */ 773 return vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GMIIDELAY, 774 tx_delay | rx_delay); 775 } 776 777 static int vsc73xx_setup(struct dsa_switch *ds) 778 { 779 struct vsc73xx *vsc = ds->priv; 780 int i, ret, val; 781 782 dev_info(vsc->dev, "set up the switch\n"); 783 784 ds->untag_bridge_pvid = true; 785 ds->max_num_bridges = DSA_TAG_8021Q_MAX_NUM_BRIDGES; 786 787 /* Issue RESET */ 788 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET, 789 VSC73XX_GLORESET_MASTER_RESET); 790 usleep_range(125, 200); 791 792 /* Initialize memory, initialize RAM bank 0..15 except 6 and 7 793 * This sequence appears in the 794 * VSC7385 SparX-G5 datasheet section 6.6.1 795 * VSC7395 SparX-G5e datasheet section 6.6.1 796 * "initialization sequence". 797 * No explanation is given to the 0x1010400 magic number. 798 */ 799 for (i = 0; i <= 15; i++) { 800 if (i != 6 && i != 7) { 801 vsc73xx_write(vsc, VSC73XX_BLOCK_MEMINIT, 802 2, 803 0, 0x1010400 + i); 804 mdelay(1); 805 } 806 } 807 mdelay(30); 808 809 /* Clear MAC table */ 810 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, 811 VSC73XX_MACACCESS, 812 VSC73XX_MACACCESS_CMD_CLEAR_TABLE); 813 814 /* Set VLAN table to default values */ 815 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, 816 VSC73XX_VLANACCESS, 817 VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE); 818 819 msleep(40); 820 821 /* Use 20KiB buffers on all ports on VSC7395 822 * The VSC7385 has 16KiB buffers and that is the 823 * default if we don't set this up explicitly. 824 * Port "31" is "all ports". 825 */ 826 if (IS_739X(vsc)) 827 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 0x1f, 828 VSC73XX_Q_MISC_CONF, 829 VSC73XX_Q_MISC_CONF_EXTENT_MEM); 830 831 /* Put all ports into reset until enabled */ 832 for (i = 0; i < 7; i++) { 833 if (i == 5) 834 continue; 835 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 4, 836 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET); 837 } 838 839 /* Configure RGMII delay */ 840 ret = vsc73xx_configure_rgmii_port_delay(ds); 841 if (ret) 842 return ret; 843 844 /* Ingess VLAN reception mask (table 145) */ 845 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANMASK, 846 0xff); 847 /* IP multicast flood mask (table 144) */ 848 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_IFLODMSK, 849 0xff); 850 851 mdelay(50); 852 853 /* Disable preamble and use maximum allowed clock for the internal 854 * mdio bus, used for communication with internal PHYs only. 855 */ 856 val = VSC73XX_MII_MPRES_NOPREAMBLE | 857 FIELD_PREP(VSC73XX_MII_MPRES_PRESCALEVAL, 858 VSC73XX_MII_PRESCALEVAL_MIN); 859 vsc73xx_write(vsc, VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL, 860 VSC73XX_MII_MPRES, val); 861 862 /* Release reset from the internal PHYs */ 863 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET, 864 VSC73XX_GLORESET_PHY_RESET); 865 866 udelay(4); 867 868 /* Clear VLAN table */ 869 for (i = 0; i < VLAN_N_VID; i++) 870 vsc73xx_write_vlan_table_entry(vsc, i, 0); 871 872 INIT_LIST_HEAD(&vsc->vlans); 873 874 rtnl_lock(); 875 ret = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q)); 876 rtnl_unlock(); 877 878 return ret; 879 } 880 881 static void vsc73xx_teardown(struct dsa_switch *ds) 882 { 883 rtnl_lock(); 884 dsa_tag_8021q_unregister(ds); 885 rtnl_unlock(); 886 } 887 888 static void vsc73xx_init_port(struct vsc73xx *vsc, int port) 889 { 890 u32 val; 891 892 /* MAC configure, first reset the port and then write defaults */ 893 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 894 port, 895 VSC73XX_MAC_CFG, 896 VSC73XX_MAC_CFG_RESET); 897 898 /* Take up the port in 1Gbit mode by default, this will be 899 * augmented after auto-negotiation on the PHY-facing 900 * ports. 901 */ 902 if (port == CPU_PORT) 903 val = VSC73XX_MAC_CFG_1000M_F_RGMII; 904 else 905 val = VSC73XX_MAC_CFG_1000M_F_PHY; 906 907 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 908 port, 909 VSC73XX_MAC_CFG, 910 val | 911 VSC73XX_MAC_CFG_TX_EN | 912 VSC73XX_MAC_CFG_RX_EN); 913 914 /* Flow control for the CPU port: 915 * Use a zero delay pause frame when pause condition is left 916 * Obey pause control frames 917 */ 918 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 919 port, 920 VSC73XX_FCCONF, 921 VSC73XX_FCCONF_ZERO_PAUSE_EN | 922 VSC73XX_FCCONF_FLOW_CTRL_OBEY); 923 924 /* Issue pause control frames on PHY facing ports. 925 * Allow early initiation of MAC transmission if the amount 926 * of egress data is below 512 bytes on CPU port. 927 * FIXME: enable 20KiB buffers? 928 */ 929 if (port == CPU_PORT) 930 val = VSC73XX_Q_MISC_CONF_EARLY_TX_512; 931 else 932 val = VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE; 933 val |= VSC73XX_Q_MISC_CONF_EXTENT_MEM; 934 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 935 port, 936 VSC73XX_Q_MISC_CONF, 937 val); 938 939 /* Flow control MAC: a MAC address used in flow control frames */ 940 val = (vsc->addr[5] << 16) | (vsc->addr[4] << 8) | (vsc->addr[3]); 941 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 942 port, 943 VSC73XX_FCMACHI, 944 val); 945 val = (vsc->addr[2] << 16) | (vsc->addr[1] << 8) | (vsc->addr[0]); 946 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 947 port, 948 VSC73XX_FCMACLO, 949 val); 950 951 /* Tell the categorizer to forward pause frames, not control 952 * frame. Do not drop anything. 953 */ 954 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 955 port, 956 VSC73XX_CAT_DROP, 957 VSC73XX_CAT_DROP_FWD_PAUSE_ENA); 958 959 /* Clear all counters */ 960 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 961 port, VSC73XX_C_RX0, 0); 962 } 963 964 static void vsc73xx_reset_port(struct vsc73xx *vsc, int port, u32 initval) 965 { 966 int ret, err; 967 u32 val; 968 969 /* Disable RX on this port */ 970 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 971 VSC73XX_MAC_CFG, 972 VSC73XX_MAC_CFG_RX_EN, 0); 973 974 /* Discard packets */ 975 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 976 VSC73XX_ARBDISC, BIT(port), BIT(port)); 977 978 /* Wait until queue is empty */ 979 ret = read_poll_timeout(vsc73xx_read, err, 980 err < 0 || (val & BIT(port)), 981 VSC73XX_POLL_SLEEP_US, 982 VSC73XX_POLL_TIMEOUT_US, false, 983 vsc, VSC73XX_BLOCK_ARBITER, 0, 984 VSC73XX_ARBEMPTY, &val); 985 if (ret) 986 dev_err(vsc->dev, 987 "timeout waiting for block arbiter\n"); 988 else if (err < 0) 989 dev_err(vsc->dev, "error reading arbiter\n"); 990 991 /* Put this port into reset */ 992 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, 993 VSC73XX_MAC_CFG_RESET | initval); 994 } 995 996 static void vsc73xx_mac_config(struct phylink_config *config, unsigned int mode, 997 const struct phylink_link_state *state) 998 { 999 struct dsa_port *dp = dsa_phylink_to_port(config); 1000 struct vsc73xx *vsc = dp->ds->priv; 1001 int port = dp->index; 1002 1003 /* Special handling of the CPU-facing port */ 1004 if (port == CPU_PORT) { 1005 /* Other ports are already initialized but not this one */ 1006 vsc73xx_init_port(vsc, CPU_PORT); 1007 /* Select the external port for this interface (EXT_PORT) 1008 * Enable the GMII GTX external clock 1009 * Use double data rate (DDR mode) 1010 */ 1011 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 1012 CPU_PORT, 1013 VSC73XX_ADVPORTM, 1014 VSC73XX_ADVPORTM_EXT_PORT | 1015 VSC73XX_ADVPORTM_ENA_GTX | 1016 VSC73XX_ADVPORTM_DDR_MODE); 1017 } 1018 } 1019 1020 static void vsc73xx_mac_link_down(struct phylink_config *config, 1021 unsigned int mode, phy_interface_t interface) 1022 { 1023 struct dsa_port *dp = dsa_phylink_to_port(config); 1024 struct vsc73xx *vsc = dp->ds->priv; 1025 int port = dp->index; 1026 1027 /* This routine is described in the datasheet (below ARBDISC register 1028 * description) 1029 */ 1030 vsc73xx_reset_port(vsc, port, 0); 1031 1032 /* Allow backward dropping of frames from this port */ 1033 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 1034 VSC73XX_SBACKWDROP, BIT(port), BIT(port)); 1035 } 1036 1037 static void vsc73xx_mac_link_up(struct phylink_config *config, 1038 struct phy_device *phy, unsigned int mode, 1039 phy_interface_t interface, int speed, 1040 int duplex, bool tx_pause, bool rx_pause) 1041 { 1042 struct dsa_port *dp = dsa_phylink_to_port(config); 1043 struct vsc73xx *vsc = dp->ds->priv; 1044 int port = dp->index; 1045 u32 val; 1046 u8 seed; 1047 1048 if (speed == SPEED_1000) 1049 val = VSC73XX_MAC_CFG_GIGA_MODE | VSC73XX_MAC_CFG_TX_IPG_1000M; 1050 else 1051 val = VSC73XX_MAC_CFG_TX_IPG_100_10M; 1052 1053 if (phy_interface_mode_is_rgmii(interface)) 1054 val |= VSC73XX_MAC_CFG_CLK_SEL_1000M; 1055 else 1056 val |= VSC73XX_MAC_CFG_CLK_SEL_EXT; 1057 1058 if (duplex == DUPLEX_FULL) 1059 val |= VSC73XX_MAC_CFG_FDX; 1060 1061 /* This routine is described in the datasheet (below ARBDISC register 1062 * description) 1063 */ 1064 vsc73xx_reset_port(vsc, port, val); 1065 1066 /* Seed the port randomness with randomness */ 1067 get_random_bytes(&seed, 1); 1068 val |= seed << VSC73XX_MAC_CFG_SEED_OFFSET; 1069 val |= VSC73XX_MAC_CFG_SEED_LOAD; 1070 val |= VSC73XX_MAC_CFG_WEXC_DIS; 1071 1072 /* Those bits are responsible for MTU only. Kernel takes care about MTU, 1073 * let's enable +8 bytes frame length unconditionally. 1074 */ 1075 val |= VSC73XX_MAC_CFG_VLAN_AWR | VSC73XX_MAC_CFG_VLAN_DBLAWR; 1076 1077 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val); 1078 1079 /* Flow control for the PHY facing ports: 1080 * Use a zero delay pause frame when pause condition is left 1081 * Obey pause control frames 1082 * When generating pause frames, use 0xff as pause value 1083 */ 1084 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_FCCONF, 1085 VSC73XX_FCCONF_ZERO_PAUSE_EN | 1086 VSC73XX_FCCONF_FLOW_CTRL_OBEY | 1087 0xff); 1088 1089 /* Accept packets again */ 1090 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 1091 VSC73XX_ARBDISC, BIT(port), 0); 1092 1093 /* Disallow backward dropping of frames from this port */ 1094 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 1095 VSC73XX_SBACKWDROP, BIT(port), 0); 1096 1097 /* Enable TX, RX, deassert reset, stop loading seed */ 1098 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1099 VSC73XX_MAC_CFG, 1100 VSC73XX_MAC_CFG_RESET | VSC73XX_MAC_CFG_SEED_LOAD | 1101 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN, 1102 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN); 1103 } 1104 1105 static bool vsc73xx_tag_8021q_active(struct dsa_port *dp) 1106 { 1107 return !dsa_port_is_vlan_filtering(dp); 1108 } 1109 1110 static struct vsc73xx_bridge_vlan * 1111 vsc73xx_bridge_vlan_find(struct vsc73xx *vsc, u16 vid) 1112 { 1113 struct vsc73xx_bridge_vlan *vlan; 1114 1115 list_for_each_entry(vlan, &vsc->vlans, list) 1116 if (vlan->vid == vid) 1117 return vlan; 1118 1119 return NULL; 1120 } 1121 1122 static void 1123 vsc73xx_bridge_vlan_remove_port(struct vsc73xx_bridge_vlan *vsc73xx_vlan, 1124 int port) 1125 { 1126 vsc73xx_vlan->portmask &= ~BIT(port); 1127 1128 if (vsc73xx_vlan->portmask) 1129 return; 1130 1131 list_del(&vsc73xx_vlan->list); 1132 kfree(vsc73xx_vlan); 1133 } 1134 1135 static void vsc73xx_bridge_vlan_summary(struct vsc73xx *vsc, int port, 1136 struct vsc73xx_vlan_summary *summary, 1137 u16 ignored_vid) 1138 { 1139 size_t num_tagged = 0, num_untagged = 0; 1140 struct vsc73xx_bridge_vlan *vlan; 1141 1142 list_for_each_entry(vlan, &vsc->vlans, list) { 1143 if (!(vlan->portmask & BIT(port)) || vlan->vid == ignored_vid) 1144 continue; 1145 1146 if (vlan->untagged & BIT(port)) 1147 num_untagged++; 1148 else 1149 num_tagged++; 1150 } 1151 1152 summary->num_untagged = num_untagged; 1153 summary->num_tagged = num_tagged; 1154 } 1155 1156 static u16 vsc73xx_find_first_vlan_untagged(struct vsc73xx *vsc, int port) 1157 { 1158 struct vsc73xx_bridge_vlan *vlan; 1159 1160 list_for_each_entry(vlan, &vsc->vlans, list) 1161 if ((vlan->portmask & BIT(port)) && 1162 (vlan->untagged & BIT(port))) 1163 return vlan->vid; 1164 1165 return VLAN_N_VID; 1166 } 1167 1168 static int vsc73xx_set_vlan_conf(struct vsc73xx *vsc, int port, 1169 enum vsc73xx_port_vlan_conf port_vlan_conf) 1170 { 1171 u32 val = 0; 1172 int ret; 1173 1174 if (port_vlan_conf == VSC73XX_VLAN_IGNORE) 1175 val = VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA | 1176 VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA; 1177 1178 ret = vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1179 VSC73XX_CAT_VLAN_MISC, 1180 VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA | 1181 VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA, val); 1182 if (ret) 1183 return ret; 1184 1185 val = (port_vlan_conf == VSC73XX_VLAN_FILTER) ? 1186 VSC73XX_TXUPDCFG_TX_INSERT_TAG : 0; 1187 1188 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1189 VSC73XX_TXUPDCFG, 1190 VSC73XX_TXUPDCFG_TX_INSERT_TAG, val); 1191 } 1192 1193 /** 1194 * vsc73xx_vlan_commit_conf - Update VLAN configuration of a port 1195 * @vsc: Switch private data structure 1196 * @port: Port index on which to operate 1197 * 1198 * Update the VLAN behavior of a port to make sure that when it is under 1199 * a VLAN filtering bridge, the port is either filtering with tag 1200 * preservation, or filtering with all VLANs egress-untagged. Otherwise, 1201 * the port ignores VLAN tags from packets and applies the port-based 1202 * VID. 1203 * 1204 * Must be called when changes are made to: 1205 * - the bridge VLAN filtering state of the port 1206 * - the number or attributes of VLANs from the bridge VLAN table, 1207 * while the port is currently VLAN-aware 1208 * 1209 * Return: 0 on success, or negative errno on error. 1210 */ 1211 static int vsc73xx_vlan_commit_conf(struct vsc73xx *vsc, int port) 1212 { 1213 enum vsc73xx_port_vlan_conf port_vlan_conf = VSC73XX_VLAN_IGNORE; 1214 struct dsa_port *dp = dsa_to_port(vsc->ds, port); 1215 1216 if (port == CPU_PORT) { 1217 port_vlan_conf = VSC73XX_VLAN_FILTER; 1218 } else if (dsa_port_is_vlan_filtering(dp)) { 1219 struct vsc73xx_vlan_summary summary; 1220 1221 port_vlan_conf = VSC73XX_VLAN_FILTER; 1222 1223 vsc73xx_bridge_vlan_summary(vsc, port, &summary, VLAN_N_VID); 1224 if (summary.num_tagged == 0) 1225 port_vlan_conf = VSC73XX_VLAN_FILTER_UNTAG_ALL; 1226 } 1227 1228 return vsc73xx_set_vlan_conf(vsc, port, port_vlan_conf); 1229 } 1230 1231 static int 1232 vsc73xx_vlan_change_untagged(struct vsc73xx *vsc, int port, u16 vid, bool set) 1233 { 1234 u32 val = 0; 1235 1236 if (set) 1237 val = VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA | 1238 ((vid << VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_SHIFT) & 1239 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID); 1240 1241 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1242 VSC73XX_TXUPDCFG, 1243 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA | 1244 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID, val); 1245 } 1246 1247 /** 1248 * vsc73xx_vlan_commit_untagged - Update native VLAN of a port 1249 * @vsc: Switch private data structure 1250 * @port: Port index on which to operate 1251 * 1252 * Update the native VLAN of a port (the one VLAN which is transmitted 1253 * as egress-tagged on a trunk port) when port is in VLAN filtering mode and 1254 * only one untagged vid is configured. 1255 * In other cases no need to configure it because switch can untag all vlans on 1256 * the port. 1257 * 1258 * Return: 0 on success, or negative errno on error. 1259 */ 1260 static int vsc73xx_vlan_commit_untagged(struct vsc73xx *vsc, int port) 1261 { 1262 struct dsa_port *dp = dsa_to_port(vsc->ds, port); 1263 struct vsc73xx_vlan_summary summary; 1264 u16 vid = 0; 1265 bool valid; 1266 1267 if (!dsa_port_is_vlan_filtering(dp)) 1268 /* Port is configured to untag all vlans in that case. 1269 * No need to commit untagged config change. 1270 */ 1271 return 0; 1272 1273 vsc73xx_bridge_vlan_summary(vsc, port, &summary, VLAN_N_VID); 1274 1275 if (summary.num_untagged > 1) 1276 /* Port must untag all vlans in that case. 1277 * No need to commit untagged config change. 1278 */ 1279 return 0; 1280 1281 valid = (summary.num_untagged == 1); 1282 if (valid) 1283 vid = vsc73xx_find_first_vlan_untagged(vsc, port); 1284 1285 return vsc73xx_vlan_change_untagged(vsc, port, vid, valid); 1286 } 1287 1288 static int 1289 vsc73xx_vlan_change_pvid(struct vsc73xx *vsc, int port, u16 vid, bool set) 1290 { 1291 u32 val = 0; 1292 int ret; 1293 1294 val = set ? 0 : VSC73XX_CAT_DROP_UNTAGGED_ENA; 1295 1296 ret = vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1297 VSC73XX_CAT_DROP, 1298 VSC73XX_CAT_DROP_UNTAGGED_ENA, val); 1299 if (!set || ret) 1300 return ret; 1301 1302 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1303 VSC73XX_CAT_PORT_VLAN, 1304 VSC73XX_CAT_PORT_VLAN_VLAN_VID, 1305 vid & VSC73XX_CAT_PORT_VLAN_VLAN_VID); 1306 } 1307 1308 /** 1309 * vsc73xx_vlan_commit_pvid - Update port-based default VLAN of a port 1310 * @vsc: Switch private data structure 1311 * @port: Port index on which to operate 1312 * 1313 * Update the PVID of a port so that it follows either the bridge PVID 1314 * configuration, when the bridge is currently VLAN-aware, or the PVID 1315 * from tag_8021q, when the port is standalone or under a VLAN-unaware 1316 * bridge. A port with no PVID drops all untagged and VID 0 tagged 1317 * traffic. 1318 * 1319 * Must be called when changes are made to: 1320 * - the bridge VLAN filtering state of the port 1321 * - the number or attributes of VLANs from the bridge VLAN table, 1322 * while the port is currently VLAN-aware 1323 * 1324 * Return: 0 on success, or negative errno on error. 1325 */ 1326 static int vsc73xx_vlan_commit_pvid(struct vsc73xx *vsc, int port) 1327 { 1328 struct vsc73xx_portinfo *portinfo = &vsc->portinfo[port]; 1329 bool valid = portinfo->pvid_tag_8021q_configured; 1330 struct dsa_port *dp = dsa_to_port(vsc->ds, port); 1331 u16 vid = portinfo->pvid_tag_8021q; 1332 1333 if (dsa_port_is_vlan_filtering(dp)) { 1334 vid = portinfo->pvid_vlan_filtering; 1335 valid = portinfo->pvid_vlan_filtering_configured; 1336 } 1337 1338 return vsc73xx_vlan_change_pvid(vsc, port, vid, valid); 1339 } 1340 1341 static int vsc73xx_vlan_commit_settings(struct vsc73xx *vsc, int port) 1342 { 1343 int ret; 1344 1345 ret = vsc73xx_vlan_commit_untagged(vsc, port); 1346 if (ret) 1347 return ret; 1348 1349 ret = vsc73xx_vlan_commit_pvid(vsc, port); 1350 if (ret) 1351 return ret; 1352 1353 return vsc73xx_vlan_commit_conf(vsc, port); 1354 } 1355 1356 static int vsc73xx_port_enable(struct dsa_switch *ds, int port, 1357 struct phy_device *phy) 1358 { 1359 struct vsc73xx *vsc = ds->priv; 1360 1361 dev_info(vsc->dev, "enable port %d\n", port); 1362 vsc73xx_init_port(vsc, port); 1363 1364 return vsc73xx_vlan_commit_settings(vsc, port); 1365 } 1366 1367 static void vsc73xx_port_disable(struct dsa_switch *ds, int port) 1368 { 1369 struct vsc73xx *vsc = ds->priv; 1370 1371 /* Just put the port into reset */ 1372 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, 1373 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET); 1374 } 1375 1376 static const struct vsc73xx_counter * 1377 vsc73xx_find_counter(struct vsc73xx *vsc, 1378 u8 counter, 1379 bool tx) 1380 { 1381 const struct vsc73xx_counter *cnts; 1382 int num_cnts; 1383 int i; 1384 1385 if (tx) { 1386 cnts = vsc73xx_tx_counters; 1387 num_cnts = ARRAY_SIZE(vsc73xx_tx_counters); 1388 } else { 1389 cnts = vsc73xx_rx_counters; 1390 num_cnts = ARRAY_SIZE(vsc73xx_rx_counters); 1391 } 1392 1393 for (i = 0; i < num_cnts; i++) { 1394 const struct vsc73xx_counter *cnt; 1395 1396 cnt = &cnts[i]; 1397 if (cnt->counter == counter) 1398 return cnt; 1399 } 1400 1401 return NULL; 1402 } 1403 1404 static void vsc73xx_get_strings(struct dsa_switch *ds, int port, u32 stringset, 1405 uint8_t *data) 1406 { 1407 const struct vsc73xx_counter *cnt; 1408 struct vsc73xx *vsc = ds->priv; 1409 u8 indices[6]; 1410 u8 *buf = data; 1411 int i; 1412 u32 val; 1413 int ret; 1414 1415 if (stringset != ETH_SS_STATS) 1416 return; 1417 1418 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port, 1419 VSC73XX_C_CFG, &val); 1420 if (ret) 1421 return; 1422 1423 indices[0] = (val & 0x1f); /* RX counter 0 */ 1424 indices[1] = ((val >> 5) & 0x1f); /* RX counter 1 */ 1425 indices[2] = ((val >> 10) & 0x1f); /* RX counter 2 */ 1426 indices[3] = ((val >> 16) & 0x1f); /* TX counter 0 */ 1427 indices[4] = ((val >> 21) & 0x1f); /* TX counter 1 */ 1428 indices[5] = ((val >> 26) & 0x1f); /* TX counter 2 */ 1429 1430 /* The first counters is the RX octets */ 1431 ethtool_puts(&buf, "RxEtherStatsOctets"); 1432 1433 /* Each port supports recording 3 RX counters and 3 TX counters, 1434 * figure out what counters we use in this set-up and return the 1435 * names of them. The hardware default counters will be number of 1436 * packets on RX/TX, combined broadcast+multicast packets RX/TX and 1437 * total error packets RX/TX. 1438 */ 1439 for (i = 0; i < 3; i++) { 1440 cnt = vsc73xx_find_counter(vsc, indices[i], false); 1441 ethtool_puts(&buf, cnt ? cnt->name : ""); 1442 } 1443 1444 /* TX stats begins with the number of TX octets */ 1445 ethtool_puts(&buf, "TxEtherStatsOctets"); 1446 1447 for (i = 3; i < 6; i++) { 1448 cnt = vsc73xx_find_counter(vsc, indices[i], true); 1449 ethtool_puts(&buf, cnt ? cnt->name : ""); 1450 1451 } 1452 } 1453 1454 static int vsc73xx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1455 { 1456 /* We only support SS_STATS */ 1457 if (sset != ETH_SS_STATS) 1458 return 0; 1459 /* RX and TX packets, then 3 RX counters, 3 TX counters */ 1460 return 8; 1461 } 1462 1463 static void vsc73xx_get_ethtool_stats(struct dsa_switch *ds, int port, 1464 uint64_t *data) 1465 { 1466 struct vsc73xx *vsc = ds->priv; 1467 u8 regs[] = { 1468 VSC73XX_RXOCT, 1469 VSC73XX_C_RX0, 1470 VSC73XX_C_RX1, 1471 VSC73XX_C_RX2, 1472 VSC73XX_TXOCT, 1473 VSC73XX_C_TX0, 1474 VSC73XX_C_TX1, 1475 VSC73XX_C_TX2, 1476 }; 1477 u32 val; 1478 int ret; 1479 int i; 1480 1481 for (i = 0; i < ARRAY_SIZE(regs); i++) { 1482 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port, 1483 regs[i], &val); 1484 if (ret) { 1485 dev_err(vsc->dev, "error reading counter %d\n", i); 1486 return; 1487 } 1488 data[i] = val; 1489 } 1490 } 1491 1492 static int vsc73xx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1493 { 1494 struct vsc73xx *vsc = ds->priv; 1495 1496 return vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, 1497 VSC73XX_MAXLEN, new_mtu + ETH_HLEN + ETH_FCS_LEN); 1498 } 1499 1500 /* According to application not "VSC7398 Jumbo Frames" setting 1501 * up the frame size to 9.6 KB does not affect the performance on standard 1502 * frames. It is clear from the application note that 1503 * "9.6 kilobytes" == 9600 bytes. 1504 */ 1505 static int vsc73xx_get_max_mtu(struct dsa_switch *ds, int port) 1506 { 1507 return 9600 - ETH_HLEN - ETH_FCS_LEN; 1508 } 1509 1510 static void vsc73xx_phylink_get_caps(struct dsa_switch *dsa, int port, 1511 struct phylink_config *config) 1512 { 1513 unsigned long *interfaces = config->supported_interfaces; 1514 1515 if (port == 5) 1516 return; 1517 1518 if (port == CPU_PORT) { 1519 __set_bit(PHY_INTERFACE_MODE_MII, interfaces); 1520 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces); 1521 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces); 1522 __set_bit(PHY_INTERFACE_MODE_RGMII, interfaces); 1523 } 1524 1525 if (port <= 4) { 1526 /* Internal PHYs */ 1527 __set_bit(PHY_INTERFACE_MODE_INTERNAL, interfaces); 1528 /* phylib default */ 1529 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces); 1530 } 1531 1532 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000; 1533 } 1534 1535 static int 1536 vsc73xx_port_vlan_filtering(struct dsa_switch *ds, int port, 1537 bool vlan_filtering, struct netlink_ext_ack *extack) 1538 { 1539 struct vsc73xx *vsc = ds->priv; 1540 1541 /* The commit to hardware processed below is required because vsc73xx 1542 * is using tag_8021q. When vlan_filtering is disabled, tag_8021q uses 1543 * pvid/untagged vlans for port recognition. The values configured for 1544 * vlans and pvid/untagged states are stored in portinfo structure. 1545 * When vlan_filtering is enabled, we need to restore pvid/untagged from 1546 * portinfo structure. Analogous routine is processed when 1547 * vlan_filtering is disabled, but values used for tag_8021q are 1548 * restored. 1549 */ 1550 1551 return vsc73xx_vlan_commit_settings(vsc, port); 1552 } 1553 1554 static int vsc73xx_port_vlan_add(struct dsa_switch *ds, int port, 1555 const struct switchdev_obj_port_vlan *vlan, 1556 struct netlink_ext_ack *extack) 1557 { 1558 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1559 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1560 struct dsa_port *dp = dsa_to_port(ds, port); 1561 struct vsc73xx_bridge_vlan *vsc73xx_vlan; 1562 struct vsc73xx_vlan_summary summary; 1563 struct vsc73xx_portinfo *portinfo; 1564 struct vsc73xx *vsc = ds->priv; 1565 bool commit_to_hardware; 1566 int ret = 0; 1567 1568 /* Be sure to deny alterations to the configuration done by tag_8021q. 1569 */ 1570 if (vid_is_dsa_8021q(vlan->vid)) { 1571 NL_SET_ERR_MSG_MOD(extack, 1572 "Range 3072-4095 reserved for dsa_8021q operation"); 1573 return -EBUSY; 1574 } 1575 1576 /* The processed vlan->vid is excluded from the search because the VLAN 1577 * can be re-added with a different set of flags, so it's easiest to 1578 * ignore its old flags from the VLAN database software copy. 1579 */ 1580 vsc73xx_bridge_vlan_summary(vsc, port, &summary, vlan->vid); 1581 1582 /* VSC73XX allows only three untagged states: none, one or all */ 1583 if ((untagged && summary.num_tagged > 0 && summary.num_untagged > 0) || 1584 (!untagged && summary.num_untagged > 1)) { 1585 NL_SET_ERR_MSG_MOD(extack, 1586 "Port can have only none, one or all untagged vlan"); 1587 return -EBUSY; 1588 } 1589 1590 vsc73xx_vlan = vsc73xx_bridge_vlan_find(vsc, vlan->vid); 1591 1592 if (!vsc73xx_vlan) { 1593 vsc73xx_vlan = kzalloc(sizeof(*vsc73xx_vlan), GFP_KERNEL); 1594 if (!vsc73xx_vlan) 1595 return -ENOMEM; 1596 1597 vsc73xx_vlan->vid = vlan->vid; 1598 1599 list_add_tail(&vsc73xx_vlan->list, &vsc->vlans); 1600 } 1601 1602 vsc73xx_vlan->portmask |= BIT(port); 1603 1604 /* CPU port must be always tagged because source port identification is 1605 * based on tag_8021q. 1606 */ 1607 if (port == CPU_PORT) 1608 goto update_vlan_table; 1609 1610 if (untagged) 1611 vsc73xx_vlan->untagged |= BIT(port); 1612 else 1613 vsc73xx_vlan->untagged &= ~BIT(port); 1614 1615 portinfo = &vsc->portinfo[port]; 1616 1617 if (pvid) { 1618 portinfo->pvid_vlan_filtering_configured = true; 1619 portinfo->pvid_vlan_filtering = vlan->vid; 1620 } else if (portinfo->pvid_vlan_filtering_configured && 1621 portinfo->pvid_vlan_filtering == vlan->vid) { 1622 portinfo->pvid_vlan_filtering_configured = false; 1623 } 1624 1625 commit_to_hardware = !vsc73xx_tag_8021q_active(dp); 1626 if (commit_to_hardware) { 1627 ret = vsc73xx_vlan_commit_settings(vsc, port); 1628 if (ret) 1629 goto err; 1630 } 1631 1632 update_vlan_table: 1633 ret = vsc73xx_update_vlan_table(vsc, port, vlan->vid, true); 1634 if (!ret) 1635 return 0; 1636 err: 1637 vsc73xx_bridge_vlan_remove_port(vsc73xx_vlan, port); 1638 return ret; 1639 } 1640 1641 static int vsc73xx_port_vlan_del(struct dsa_switch *ds, int port, 1642 const struct switchdev_obj_port_vlan *vlan) 1643 { 1644 struct vsc73xx_bridge_vlan *vsc73xx_vlan; 1645 struct vsc73xx_portinfo *portinfo; 1646 struct vsc73xx *vsc = ds->priv; 1647 bool commit_to_hardware; 1648 int ret; 1649 1650 ret = vsc73xx_update_vlan_table(vsc, port, vlan->vid, false); 1651 if (ret) 1652 return ret; 1653 1654 portinfo = &vsc->portinfo[port]; 1655 1656 if (portinfo->pvid_vlan_filtering_configured && 1657 portinfo->pvid_vlan_filtering == vlan->vid) 1658 portinfo->pvid_vlan_filtering_configured = false; 1659 1660 vsc73xx_vlan = vsc73xx_bridge_vlan_find(vsc, vlan->vid); 1661 1662 if (vsc73xx_vlan) 1663 vsc73xx_bridge_vlan_remove_port(vsc73xx_vlan, port); 1664 1665 commit_to_hardware = !vsc73xx_tag_8021q_active(dsa_to_port(ds, port)); 1666 1667 if (commit_to_hardware) 1668 return vsc73xx_vlan_commit_settings(vsc, port); 1669 1670 return 0; 1671 } 1672 1673 static int vsc73xx_tag_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid, 1674 u16 flags) 1675 { 1676 bool pvid = flags & BRIDGE_VLAN_INFO_PVID; 1677 struct vsc73xx_portinfo *portinfo; 1678 struct vsc73xx *vsc = ds->priv; 1679 bool commit_to_hardware; 1680 int ret; 1681 1682 portinfo = &vsc->portinfo[port]; 1683 1684 if (pvid) { 1685 portinfo->pvid_tag_8021q_configured = true; 1686 portinfo->pvid_tag_8021q = vid; 1687 } 1688 1689 commit_to_hardware = vsc73xx_tag_8021q_active(dsa_to_port(ds, port)); 1690 if (commit_to_hardware) { 1691 ret = vsc73xx_vlan_commit_settings(vsc, port); 1692 if (ret) 1693 return ret; 1694 } 1695 1696 return vsc73xx_update_vlan_table(vsc, port, vid, true); 1697 } 1698 1699 static int vsc73xx_tag_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid) 1700 { 1701 struct vsc73xx_portinfo *portinfo; 1702 struct vsc73xx *vsc = ds->priv; 1703 1704 portinfo = &vsc->portinfo[port]; 1705 1706 if (portinfo->pvid_tag_8021q_configured && 1707 portinfo->pvid_tag_8021q == vid) { 1708 struct dsa_port *dp = dsa_to_port(ds, port); 1709 bool commit_to_hardware; 1710 int err; 1711 1712 portinfo->pvid_tag_8021q_configured = false; 1713 1714 commit_to_hardware = vsc73xx_tag_8021q_active(dp); 1715 if (commit_to_hardware) { 1716 err = vsc73xx_vlan_commit_settings(vsc, port); 1717 if (err) 1718 return err; 1719 } 1720 } 1721 1722 return vsc73xx_update_vlan_table(vsc, port, vid, false); 1723 } 1724 1725 static int vsc73xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1726 struct switchdev_brport_flags flags, 1727 struct netlink_ext_ack *extack) 1728 { 1729 if (flags.mask & ~BR_LEARNING) 1730 return -EINVAL; 1731 1732 return 0; 1733 } 1734 1735 static int vsc73xx_port_bridge_flags(struct dsa_switch *ds, int port, 1736 struct switchdev_brport_flags flags, 1737 struct netlink_ext_ack *extack) 1738 { 1739 if (flags.mask & BR_LEARNING) { 1740 u32 val = flags.val & BR_LEARNING ? BIT(port) : 0; 1741 struct vsc73xx *vsc = ds->priv; 1742 1743 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1744 VSC73XX_LEARNMASK, BIT(port), val); 1745 } 1746 1747 return 0; 1748 } 1749 1750 static void vsc73xx_refresh_fwd_map(struct dsa_switch *ds, int port, u8 state) 1751 { 1752 struct dsa_port *other_dp, *dp = dsa_to_port(ds, port); 1753 struct vsc73xx *vsc = ds->priv; 1754 u16 mask; 1755 1756 if (state != BR_STATE_FORWARDING) { 1757 /* Ports that aren't in the forwarding state must not 1758 * forward packets anywhere. 1759 */ 1760 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1761 VSC73XX_SRCMASKS + port, 1762 VSC73XX_SRCMASKS_PORTS_MASK, 0); 1763 1764 dsa_switch_for_each_available_port(other_dp, ds) { 1765 if (other_dp == dp) 1766 continue; 1767 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1768 VSC73XX_SRCMASKS + other_dp->index, 1769 BIT(port), 0); 1770 } 1771 1772 return; 1773 } 1774 1775 /* Forwarding ports must forward to the CPU and to other ports 1776 * in the same bridge 1777 */ 1778 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1779 VSC73XX_SRCMASKS + CPU_PORT, BIT(port), BIT(port)); 1780 1781 mask = BIT(CPU_PORT); 1782 1783 dsa_switch_for_each_user_port(other_dp, ds) { 1784 int other_port = other_dp->index; 1785 1786 if (port == other_port || !dsa_port_bridge_same(dp, other_dp) || 1787 other_dp->stp_state != BR_STATE_FORWARDING) 1788 continue; 1789 1790 mask |= BIT(other_port); 1791 1792 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1793 VSC73XX_SRCMASKS + other_port, 1794 BIT(port), BIT(port)); 1795 } 1796 1797 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1798 VSC73XX_SRCMASKS + port, 1799 VSC73XX_SRCMASKS_PORTS_MASK, mask); 1800 } 1801 1802 /* FIXME: STP frames aren't forwarded at this moment. BPDU frames are 1803 * forwarded only from and to PI/SI interface. For more info see chapter 1804 * 2.7.1 (CPU Forwarding) in datasheet. 1805 * This function is required for tag_8021q operations. 1806 */ 1807 static void vsc73xx_port_stp_state_set(struct dsa_switch *ds, int port, 1808 u8 state) 1809 { 1810 struct dsa_port *dp = dsa_to_port(ds, port); 1811 struct vsc73xx *vsc = ds->priv; 1812 u32 val = 0; 1813 1814 if (state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) 1815 val = dp->learning ? BIT(port) : 0; 1816 1817 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1818 VSC73XX_LEARNMASK, BIT(port), val); 1819 1820 val = (state == BR_STATE_BLOCKING || state == BR_STATE_DISABLED) ? 1821 0 : BIT(port); 1822 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1823 VSC73XX_RECVMASK, BIT(port), val); 1824 1825 /* CPU Port should always forward packets when user ports are forwarding 1826 * so let's configure it from other ports only. 1827 */ 1828 if (port != CPU_PORT) 1829 vsc73xx_refresh_fwd_map(ds, port, state); 1830 } 1831 1832 static const struct phylink_mac_ops vsc73xx_phylink_mac_ops = { 1833 .mac_config = vsc73xx_mac_config, 1834 .mac_link_down = vsc73xx_mac_link_down, 1835 .mac_link_up = vsc73xx_mac_link_up, 1836 }; 1837 1838 static const struct dsa_switch_ops vsc73xx_ds_ops = { 1839 .get_tag_protocol = vsc73xx_get_tag_protocol, 1840 .setup = vsc73xx_setup, 1841 .teardown = vsc73xx_teardown, 1842 .phy_read = vsc73xx_phy_read, 1843 .phy_write = vsc73xx_phy_write, 1844 .get_strings = vsc73xx_get_strings, 1845 .get_ethtool_stats = vsc73xx_get_ethtool_stats, 1846 .get_sset_count = vsc73xx_get_sset_count, 1847 .port_enable = vsc73xx_port_enable, 1848 .port_disable = vsc73xx_port_disable, 1849 .port_pre_bridge_flags = vsc73xx_port_pre_bridge_flags, 1850 .port_bridge_flags = vsc73xx_port_bridge_flags, 1851 .port_bridge_join = dsa_tag_8021q_bridge_join, 1852 .port_bridge_leave = dsa_tag_8021q_bridge_leave, 1853 .port_change_mtu = vsc73xx_change_mtu, 1854 .port_max_mtu = vsc73xx_get_max_mtu, 1855 .port_stp_state_set = vsc73xx_port_stp_state_set, 1856 .port_vlan_filtering = vsc73xx_port_vlan_filtering, 1857 .port_vlan_add = vsc73xx_port_vlan_add, 1858 .port_vlan_del = vsc73xx_port_vlan_del, 1859 .phylink_get_caps = vsc73xx_phylink_get_caps, 1860 .tag_8021q_vlan_add = vsc73xx_tag_8021q_vlan_add, 1861 .tag_8021q_vlan_del = vsc73xx_tag_8021q_vlan_del, 1862 }; 1863 1864 static int vsc73xx_gpio_get(struct gpio_chip *chip, unsigned int offset) 1865 { 1866 struct vsc73xx *vsc = gpiochip_get_data(chip); 1867 u32 val; 1868 int ret; 1869 1870 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1871 VSC73XX_GPIO, &val); 1872 if (ret) 1873 return ret; 1874 1875 return !!(val & BIT(offset)); 1876 } 1877 1878 static void vsc73xx_gpio_set(struct gpio_chip *chip, unsigned int offset, 1879 int val) 1880 { 1881 struct vsc73xx *vsc = gpiochip_get_data(chip); 1882 u32 tmp = val ? BIT(offset) : 0; 1883 1884 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1885 VSC73XX_GPIO, BIT(offset), tmp); 1886 } 1887 1888 static int vsc73xx_gpio_direction_output(struct gpio_chip *chip, 1889 unsigned int offset, int val) 1890 { 1891 struct vsc73xx *vsc = gpiochip_get_data(chip); 1892 u32 tmp = val ? BIT(offset) : 0; 1893 1894 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1895 VSC73XX_GPIO, BIT(offset + 4) | BIT(offset), 1896 BIT(offset + 4) | tmp); 1897 } 1898 1899 static int vsc73xx_gpio_direction_input(struct gpio_chip *chip, 1900 unsigned int offset) 1901 { 1902 struct vsc73xx *vsc = gpiochip_get_data(chip); 1903 1904 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1905 VSC73XX_GPIO, BIT(offset + 4), 1906 0); 1907 } 1908 1909 static int vsc73xx_gpio_get_direction(struct gpio_chip *chip, 1910 unsigned int offset) 1911 { 1912 struct vsc73xx *vsc = gpiochip_get_data(chip); 1913 u32 val; 1914 int ret; 1915 1916 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1917 VSC73XX_GPIO, &val); 1918 if (ret) 1919 return ret; 1920 1921 return !(val & BIT(offset + 4)); 1922 } 1923 1924 static int vsc73xx_gpio_probe(struct vsc73xx *vsc) 1925 { 1926 int ret; 1927 1928 vsc->gc.label = devm_kasprintf(vsc->dev, GFP_KERNEL, "VSC%04x", 1929 vsc->chipid); 1930 if (!vsc->gc.label) 1931 return -ENOMEM; 1932 vsc->gc.ngpio = 4; 1933 vsc->gc.owner = THIS_MODULE; 1934 vsc->gc.parent = vsc->dev; 1935 vsc->gc.base = -1; 1936 vsc->gc.get = vsc73xx_gpio_get; 1937 vsc->gc.set = vsc73xx_gpio_set; 1938 vsc->gc.direction_input = vsc73xx_gpio_direction_input; 1939 vsc->gc.direction_output = vsc73xx_gpio_direction_output; 1940 vsc->gc.get_direction = vsc73xx_gpio_get_direction; 1941 vsc->gc.can_sleep = true; 1942 ret = devm_gpiochip_add_data(vsc->dev, &vsc->gc, vsc); 1943 if (ret) { 1944 dev_err(vsc->dev, "unable to register GPIO chip\n"); 1945 return ret; 1946 } 1947 return 0; 1948 } 1949 1950 int vsc73xx_probe(struct vsc73xx *vsc) 1951 { 1952 struct device *dev = vsc->dev; 1953 int ret; 1954 1955 /* Release reset, if any */ 1956 vsc->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1957 if (IS_ERR(vsc->reset)) { 1958 dev_err(dev, "failed to get RESET GPIO\n"); 1959 return PTR_ERR(vsc->reset); 1960 } 1961 if (vsc->reset) 1962 /* Wait 20ms according to datasheet table 245 */ 1963 msleep(20); 1964 1965 ret = vsc73xx_detect(vsc); 1966 if (ret == -EAGAIN) { 1967 dev_err(vsc->dev, 1968 "Chip seems to be out of control. Assert reset and try again.\n"); 1969 gpiod_set_value_cansleep(vsc->reset, 1); 1970 /* Reset pulse should be 20ns minimum, according to datasheet 1971 * table 245, so 10us should be fine 1972 */ 1973 usleep_range(10, 100); 1974 gpiod_set_value_cansleep(vsc->reset, 0); 1975 /* Wait 20ms according to datasheet table 245 */ 1976 msleep(20); 1977 ret = vsc73xx_detect(vsc); 1978 } 1979 if (ret) { 1980 dev_err(dev, "no chip found (%d)\n", ret); 1981 return -ENODEV; 1982 } 1983 1984 eth_random_addr(vsc->addr); 1985 dev_info(vsc->dev, 1986 "MAC for control frames: %02X:%02X:%02X:%02X:%02X:%02X\n", 1987 vsc->addr[0], vsc->addr[1], vsc->addr[2], 1988 vsc->addr[3], vsc->addr[4], vsc->addr[5]); 1989 1990 vsc->ds = devm_kzalloc(dev, sizeof(*vsc->ds), GFP_KERNEL); 1991 if (!vsc->ds) 1992 return -ENOMEM; 1993 1994 vsc->ds->dev = dev; 1995 vsc->ds->num_ports = VSC73XX_MAX_NUM_PORTS; 1996 vsc->ds->priv = vsc; 1997 1998 vsc->ds->ops = &vsc73xx_ds_ops; 1999 vsc->ds->phylink_mac_ops = &vsc73xx_phylink_mac_ops; 2000 ret = dsa_register_switch(vsc->ds); 2001 if (ret) { 2002 dev_err(dev, "unable to register switch (%d)\n", ret); 2003 return ret; 2004 } 2005 2006 ret = vsc73xx_gpio_probe(vsc); 2007 if (ret) { 2008 dsa_unregister_switch(vsc->ds); 2009 return ret; 2010 } 2011 2012 return 0; 2013 } 2014 EXPORT_SYMBOL(vsc73xx_probe); 2015 2016 void vsc73xx_remove(struct vsc73xx *vsc) 2017 { 2018 dsa_unregister_switch(vsc->ds); 2019 gpiod_set_value(vsc->reset, 1); 2020 } 2021 EXPORT_SYMBOL(vsc73xx_remove); 2022 2023 void vsc73xx_shutdown(struct vsc73xx *vsc) 2024 { 2025 dsa_switch_shutdown(vsc->ds); 2026 } 2027 EXPORT_SYMBOL(vsc73xx_shutdown); 2028 2029 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>"); 2030 MODULE_DESCRIPTION("Vitesse VSC7385/7388/7395/7398 driver"); 2031 MODULE_LICENSE("GPL v2"); 2032