1 // SPDX-License-Identifier: GPL-2.0 2 /* DSA driver for: 3 * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch 4 * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch 5 * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch 6 * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch 7 * 8 * These switches have a built-in 8051 CPU and can download and execute a 9 * firmware in this CPU. They can also be configured to use an external CPU 10 * handling the switch in a memory-mapped manner by connecting to that external 11 * CPU's memory bus. 12 * 13 * Copyright (C) 2018 Linus Wallej <linus.walleij@linaro.org> 14 * Includes portions of code from the firmware uploader by: 15 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> 16 */ 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/device.h> 20 #include <linux/iopoll.h> 21 #include <linux/of.h> 22 #include <linux/of_mdio.h> 23 #include <linux/bitops.h> 24 #include <linux/if_bridge.h> 25 #include <linux/if_vlan.h> 26 #include <linux/etherdevice.h> 27 #include <linux/gpio/consumer.h> 28 #include <linux/gpio/driver.h> 29 #include <linux/dsa/8021q.h> 30 #include <linux/random.h> 31 #include <net/dsa.h> 32 33 #include "vitesse-vsc73xx.h" 34 35 #define VSC73XX_BLOCK_MAC 0x1 /* Subblocks 0-4, 6 (CPU port) */ 36 #define VSC73XX_BLOCK_ANALYZER 0x2 /* Only subblock 0 */ 37 #define VSC73XX_BLOCK_MII 0x3 /* Subblocks 0 and 1 */ 38 #define VSC73XX_BLOCK_MEMINIT 0x3 /* Only subblock 2 */ 39 #define VSC73XX_BLOCK_CAPTURE 0x4 /* Only subblock 2 */ 40 #define VSC73XX_BLOCK_ARBITER 0x5 /* Only subblock 0 */ 41 #define VSC73XX_BLOCK_SYSTEM 0x7 /* Only subblock 0 */ 42 43 /* MII Block subblock */ 44 #define VSC73XX_BLOCK_MII_INTERNAL 0x0 /* Internal MDIO subblock */ 45 #define VSC73XX_BLOCK_MII_EXTERNAL 0x1 /* External MDIO subblock */ 46 47 #define CPU_PORT 6 /* CPU port */ 48 49 /* MAC Block registers */ 50 #define VSC73XX_MAC_CFG 0x00 51 #define VSC73XX_MACHDXGAP 0x02 52 #define VSC73XX_FCCONF 0x04 53 #define VSC73XX_FCMACHI 0x08 54 #define VSC73XX_FCMACLO 0x0c 55 #define VSC73XX_MAXLEN 0x10 56 #define VSC73XX_ADVPORTM 0x19 57 #define VSC73XX_TXUPDCFG 0x24 58 #define VSC73XX_TXQ_SELECT_CFG 0x28 59 #define VSC73XX_RXOCT 0x50 60 #define VSC73XX_TXOCT 0x51 61 #define VSC73XX_C_RX0 0x52 62 #define VSC73XX_C_RX1 0x53 63 #define VSC73XX_C_RX2 0x54 64 #define VSC73XX_C_TX0 0x55 65 #define VSC73XX_C_TX1 0x56 66 #define VSC73XX_C_TX2 0x57 67 #define VSC73XX_C_CFG 0x58 68 #define VSC73XX_CAT_DROP 0x6e 69 #define VSC73XX_CAT_PR_MISC_L2 0x6f 70 #define VSC73XX_CAT_PR_USR_PRIO 0x75 71 #define VSC73XX_CAT_VLAN_MISC 0x79 72 #define VSC73XX_CAT_PORT_VLAN 0x7a 73 #define VSC73XX_Q_MISC_CONF 0xdf 74 75 /* MAC_CFG register bits */ 76 #define VSC73XX_MAC_CFG_WEXC_DIS BIT(31) 77 #define VSC73XX_MAC_CFG_PORT_RST BIT(29) 78 #define VSC73XX_MAC_CFG_TX_EN BIT(28) 79 #define VSC73XX_MAC_CFG_SEED_LOAD BIT(27) 80 #define VSC73XX_MAC_CFG_SEED_MASK GENMASK(26, 19) 81 #define VSC73XX_MAC_CFG_SEED_OFFSET 19 82 #define VSC73XX_MAC_CFG_FDX BIT(18) 83 #define VSC73XX_MAC_CFG_GIGA_MODE BIT(17) 84 #define VSC73XX_MAC_CFG_RX_EN BIT(16) 85 #define VSC73XX_MAC_CFG_VLAN_DBLAWR BIT(15) 86 #define VSC73XX_MAC_CFG_VLAN_AWR BIT(14) 87 #define VSC73XX_MAC_CFG_100_BASE_T BIT(13) /* Not in manual */ 88 #define VSC73XX_MAC_CFG_TX_IPG_MASK GENMASK(10, 6) 89 #define VSC73XX_MAC_CFG_TX_IPG_OFFSET 6 90 #define VSC73XX_MAC_CFG_TX_IPG_1000M (6 << VSC73XX_MAC_CFG_TX_IPG_OFFSET) 91 #define VSC73XX_MAC_CFG_TX_IPG_100_10M (17 << VSC73XX_MAC_CFG_TX_IPG_OFFSET) 92 #define VSC73XX_MAC_CFG_MAC_RX_RST BIT(5) 93 #define VSC73XX_MAC_CFG_MAC_TX_RST BIT(4) 94 #define VSC73XX_MAC_CFG_CLK_SEL_MASK GENMASK(2, 0) 95 #define VSC73XX_MAC_CFG_CLK_SEL_OFFSET 0 96 #define VSC73XX_MAC_CFG_CLK_SEL_1000M 1 97 #define VSC73XX_MAC_CFG_CLK_SEL_100M 2 98 #define VSC73XX_MAC_CFG_CLK_SEL_10M 3 99 #define VSC73XX_MAC_CFG_CLK_SEL_EXT 4 100 101 #define VSC73XX_MAC_CFG_1000M_F_PHY (VSC73XX_MAC_CFG_FDX | \ 102 VSC73XX_MAC_CFG_GIGA_MODE | \ 103 VSC73XX_MAC_CFG_TX_IPG_1000M | \ 104 VSC73XX_MAC_CFG_CLK_SEL_EXT) 105 #define VSC73XX_MAC_CFG_100_10M_F_PHY (VSC73XX_MAC_CFG_FDX | \ 106 VSC73XX_MAC_CFG_TX_IPG_100_10M | \ 107 VSC73XX_MAC_CFG_CLK_SEL_EXT) 108 #define VSC73XX_MAC_CFG_100_10M_H_PHY (VSC73XX_MAC_CFG_TX_IPG_100_10M | \ 109 VSC73XX_MAC_CFG_CLK_SEL_EXT) 110 #define VSC73XX_MAC_CFG_1000M_F_RGMII (VSC73XX_MAC_CFG_FDX | \ 111 VSC73XX_MAC_CFG_GIGA_MODE | \ 112 VSC73XX_MAC_CFG_TX_IPG_1000M | \ 113 VSC73XX_MAC_CFG_CLK_SEL_1000M) 114 #define VSC73XX_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \ 115 VSC73XX_MAC_CFG_MAC_RX_RST | \ 116 VSC73XX_MAC_CFG_MAC_TX_RST) 117 118 /* Flow control register bits */ 119 #define VSC73XX_FCCONF_ZERO_PAUSE_EN BIT(17) 120 #define VSC73XX_FCCONF_FLOW_CTRL_OBEY BIT(16) 121 #define VSC73XX_FCCONF_PAUSE_VAL_MASK GENMASK(15, 0) 122 123 /* ADVPORTM advanced port setup register bits */ 124 #define VSC73XX_ADVPORTM_IFG_PPM BIT(7) 125 #define VSC73XX_ADVPORTM_EXC_COL_CONT BIT(6) 126 #define VSC73XX_ADVPORTM_EXT_PORT BIT(5) 127 #define VSC73XX_ADVPORTM_INV_GTX BIT(4) 128 #define VSC73XX_ADVPORTM_ENA_GTX BIT(3) 129 #define VSC73XX_ADVPORTM_DDR_MODE BIT(2) 130 #define VSC73XX_ADVPORTM_IO_LOOPBACK BIT(1) 131 #define VSC73XX_ADVPORTM_HOST_LOOPBACK BIT(0) 132 133 /* TXUPDCFG transmit modify setup bits */ 134 #define VSC73XX_TXUPDCFG_DSCP_REWR_MODE GENMASK(20, 19) 135 #define VSC73XX_TXUPDCFG_DSCP_REWR_ENA BIT(18) 136 #define VSC73XX_TXUPDCFG_TX_INT_TO_USRPRIO_ENA BIT(17) 137 #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID GENMASK(15, 4) 138 #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA BIT(3) 139 #define VSC73XX_TXUPDCFG_TX_UPDATE_CRC_CPU_ENA BIT(1) 140 #define VSC73XX_TXUPDCFG_TX_INSERT_TAG BIT(0) 141 142 #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_SHIFT 4 143 144 /* CAT_DROP categorizer frame dropping register bits */ 145 #define VSC73XX_CAT_DROP_DROP_MC_SMAC_ENA BIT(6) 146 #define VSC73XX_CAT_DROP_FWD_CTRL_ENA BIT(4) 147 #define VSC73XX_CAT_DROP_FWD_PAUSE_ENA BIT(3) 148 #define VSC73XX_CAT_DROP_UNTAGGED_ENA BIT(2) 149 #define VSC73XX_CAT_DROP_TAGGED_ENA BIT(1) 150 #define VSC73XX_CAT_DROP_NULL_MAC_ENA BIT(0) 151 152 #define VSC73XX_Q_MISC_CONF_EXTENT_MEM BIT(31) 153 #define VSC73XX_Q_MISC_CONF_EARLY_TX_MASK GENMASK(4, 1) 154 #define VSC73XX_Q_MISC_CONF_EARLY_TX_512 (1 << 1) 155 #define VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE BIT(0) 156 157 /* CAT_VLAN_MISC categorizer VLAN miscellaneous bits */ 158 #define VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA BIT(8) 159 #define VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA BIT(7) 160 161 /* CAT_PORT_VLAN categorizer port VLAN */ 162 #define VSC73XX_CAT_PORT_VLAN_VLAN_CFI BIT(15) 163 #define VSC73XX_CAT_PORT_VLAN_VLAN_USR_PRIO GENMASK(14, 12) 164 #define VSC73XX_CAT_PORT_VLAN_VLAN_VID GENMASK(11, 0) 165 166 /* Frame analyzer block 2 registers */ 167 #define VSC73XX_STORMLIMIT 0x02 168 #define VSC73XX_ADVLEARN 0x03 169 #define VSC73XX_IFLODMSK 0x04 170 #define VSC73XX_VLANMASK 0x05 171 #define VSC73XX_MACHDATA 0x06 172 #define VSC73XX_MACLDATA 0x07 173 #define VSC73XX_ANMOVED 0x08 174 #define VSC73XX_ANAGEFIL 0x09 175 #define VSC73XX_ANEVENTS 0x0a 176 #define VSC73XX_ANCNTMASK 0x0b 177 #define VSC73XX_ANCNTVAL 0x0c 178 #define VSC73XX_LEARNMASK 0x0d 179 #define VSC73XX_UFLODMASK 0x0e 180 #define VSC73XX_MFLODMASK 0x0f 181 #define VSC73XX_RECVMASK 0x10 182 #define VSC73XX_AGGRCTRL 0x20 183 #define VSC73XX_AGGRMSKS 0x30 /* Until 0x3f */ 184 #define VSC73XX_DSTMASKS 0x40 /* Until 0x7f */ 185 #define VSC73XX_SRCMASKS 0x80 /* Until 0x87 */ 186 #define VSC73XX_CAPENAB 0xa0 187 #define VSC73XX_MACACCESS 0xb0 188 #define VSC73XX_IPMCACCESS 0xb1 189 #define VSC73XX_MACTINDX 0xc0 190 #define VSC73XX_VLANACCESS 0xd0 191 #define VSC73XX_VLANTIDX 0xe0 192 #define VSC73XX_AGENCTRL 0xf0 193 #define VSC73XX_CAPRST 0xff 194 195 #define VSC73XX_SRCMASKS_CPU_COPY BIT(27) 196 #define VSC73XX_SRCMASKS_MIRROR BIT(26) 197 #define VSC73XX_SRCMASKS_PORTS_MASK GENMASK(7, 0) 198 199 #define VSC73XX_MACACCESS_CPU_COPY BIT(14) 200 #define VSC73XX_MACACCESS_FWD_KILL BIT(13) 201 #define VSC73XX_MACACCESS_IGNORE_VLAN BIT(12) 202 #define VSC73XX_MACACCESS_AGED_FLAG BIT(11) 203 #define VSC73XX_MACACCESS_VALID BIT(10) 204 #define VSC73XX_MACACCESS_LOCKED BIT(9) 205 #define VSC73XX_MACACCESS_DEST_IDX_MASK GENMASK(8, 3) 206 #define VSC73XX_MACACCESS_CMD_MASK GENMASK(2, 0) 207 #define VSC73XX_MACACCESS_CMD_IDLE 0 208 #define VSC73XX_MACACCESS_CMD_LEARN 1 209 #define VSC73XX_MACACCESS_CMD_FORGET 2 210 #define VSC73XX_MACACCESS_CMD_AGE_TABLE 3 211 #define VSC73XX_MACACCESS_CMD_FLUSH_TABLE 4 212 #define VSC73XX_MACACCESS_CMD_CLEAR_TABLE 5 213 #define VSC73XX_MACACCESS_CMD_READ_ENTRY 6 214 #define VSC73XX_MACACCESS_CMD_WRITE_ENTRY 7 215 216 #define VSC73XX_VLANACCESS_LEARN_DISABLED BIT(30) 217 #define VSC73XX_VLANACCESS_VLAN_MIRROR BIT(29) 218 #define VSC73XX_VLANACCESS_VLAN_SRC_CHECK BIT(28) 219 #define VSC73XX_VLANACCESS_VLAN_PORT_MASK GENMASK(9, 2) 220 #define VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT 2 221 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK GENMASK(1, 0) 222 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE 0 223 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY 1 224 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY 2 225 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE 3 226 227 /* MII block 3 registers */ 228 #define VSC73XX_MII_STAT 0x0 229 #define VSC73XX_MII_CMD 0x1 230 #define VSC73XX_MII_DATA 0x2 231 232 #define VSC73XX_MII_STAT_BUSY BIT(3) 233 234 /* Arbiter block 5 registers */ 235 #define VSC73XX_ARBEMPTY 0x0c 236 #define VSC73XX_ARBDISC 0x0e 237 #define VSC73XX_SBACKWDROP 0x12 238 #define VSC73XX_DBACKWDROP 0x13 239 #define VSC73XX_ARBBURSTPROB 0x15 240 241 /* System block 7 registers */ 242 #define VSC73XX_ICPU_SIPAD 0x01 243 #define VSC73XX_GMIIDELAY 0x05 244 #define VSC73XX_ICPU_CTRL 0x10 245 #define VSC73XX_ICPU_ADDR 0x11 246 #define VSC73XX_ICPU_SRAM 0x12 247 #define VSC73XX_HWSEM 0x13 248 #define VSC73XX_GLORESET 0x14 249 #define VSC73XX_ICPU_MBOX_VAL 0x15 250 #define VSC73XX_ICPU_MBOX_SET 0x16 251 #define VSC73XX_ICPU_MBOX_CLR 0x17 252 #define VSC73XX_CHIPID 0x18 253 #define VSC73XX_GPIO 0x34 254 255 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_NONE 0 256 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_4_NS 1 257 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_7_NS 2 258 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS 3 259 260 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_NONE (0 << 4) 261 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_4_NS (1 << 4) 262 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_7_NS (2 << 4) 263 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS (3 << 4) 264 265 #define VSC73XX_ICPU_CTRL_WATCHDOG_RST BIT(31) 266 #define VSC73XX_ICPU_CTRL_CLK_DIV_MASK GENMASK(12, 8) 267 #define VSC73XX_ICPU_CTRL_SRST_HOLD BIT(7) 268 #define VSC73XX_ICPU_CTRL_ICPU_PI_EN BIT(6) 269 #define VSC73XX_ICPU_CTRL_BOOT_EN BIT(3) 270 #define VSC73XX_ICPU_CTRL_EXT_ACC_EN BIT(2) 271 #define VSC73XX_ICPU_CTRL_CLK_EN BIT(1) 272 #define VSC73XX_ICPU_CTRL_SRST BIT(0) 273 274 #define VSC73XX_CHIPID_ID_SHIFT 12 275 #define VSC73XX_CHIPID_ID_MASK 0xffff 276 #define VSC73XX_CHIPID_REV_SHIFT 28 277 #define VSC73XX_CHIPID_REV_MASK 0xf 278 #define VSC73XX_CHIPID_ID_7385 0x7385 279 #define VSC73XX_CHIPID_ID_7388 0x7388 280 #define VSC73XX_CHIPID_ID_7395 0x7395 281 #define VSC73XX_CHIPID_ID_7398 0x7398 282 283 #define VSC73XX_GLORESET_STROBE BIT(4) 284 #define VSC73XX_GLORESET_ICPU_LOCK BIT(3) 285 #define VSC73XX_GLORESET_MEM_LOCK BIT(2) 286 #define VSC73XX_GLORESET_PHY_RESET BIT(1) 287 #define VSC73XX_GLORESET_MASTER_RESET BIT(0) 288 289 #define VSC7385_CLOCK_DELAY ((3 << 4) | 3) 290 #define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3) 291 292 #define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \ 293 VSC73XX_ICPU_CTRL_BOOT_EN | \ 294 VSC73XX_ICPU_CTRL_EXT_ACC_EN) 295 296 #define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \ 297 VSC73XX_ICPU_CTRL_BOOT_EN | \ 298 VSC73XX_ICPU_CTRL_CLK_EN | \ 299 VSC73XX_ICPU_CTRL_SRST) 300 301 #define IS_7385(a) ((a)->chipid == VSC73XX_CHIPID_ID_7385) 302 #define IS_7388(a) ((a)->chipid == VSC73XX_CHIPID_ID_7388) 303 #define IS_7395(a) ((a)->chipid == VSC73XX_CHIPID_ID_7395) 304 #define IS_7398(a) ((a)->chipid == VSC73XX_CHIPID_ID_7398) 305 #define IS_739X(a) (IS_7395(a) || IS_7398(a)) 306 307 #define VSC73XX_POLL_SLEEP_US 1000 308 #define VSC73XX_MDIO_POLL_SLEEP_US 5 309 #define VSC73XX_POLL_TIMEOUT_US 10000 310 311 struct vsc73xx_counter { 312 u8 counter; 313 const char *name; 314 }; 315 316 /* Counters are named according to the MIB standards where applicable. 317 * Some counters are custom, non-standard. The standard counters are 318 * named in accordance with RFC2819, RFC2021 and IEEE Std 802.3-2002 Annex 319 * 30A Counters. 320 */ 321 static const struct vsc73xx_counter vsc73xx_rx_counters[] = { 322 { 0, "RxEtherStatsPkts" }, 323 { 1, "RxBroadcast+MulticastPkts" }, /* non-standard counter */ 324 { 2, "RxTotalErrorPackets" }, /* non-standard counter */ 325 { 3, "RxEtherStatsBroadcastPkts" }, 326 { 4, "RxEtherStatsMulticastPkts" }, 327 { 5, "RxEtherStatsPkts64Octets" }, 328 { 6, "RxEtherStatsPkts65to127Octets" }, 329 { 7, "RxEtherStatsPkts128to255Octets" }, 330 { 8, "RxEtherStatsPkts256to511Octets" }, 331 { 9, "RxEtherStatsPkts512to1023Octets" }, 332 { 10, "RxEtherStatsPkts1024to1518Octets" }, 333 { 11, "RxJumboFrames" }, /* non-standard counter */ 334 { 12, "RxaPauseMACControlFramesTransmitted" }, 335 { 13, "RxFIFODrops" }, /* non-standard counter */ 336 { 14, "RxBackwardDrops" }, /* non-standard counter */ 337 { 15, "RxClassifierDrops" }, /* non-standard counter */ 338 { 16, "RxEtherStatsCRCAlignErrors" }, 339 { 17, "RxEtherStatsUndersizePkts" }, 340 { 18, "RxEtherStatsOversizePkts" }, 341 { 19, "RxEtherStatsFragments" }, 342 { 20, "RxEtherStatsJabbers" }, 343 { 21, "RxaMACControlFramesReceived" }, 344 /* 22-24 are undefined */ 345 { 25, "RxaFramesReceivedOK" }, 346 { 26, "RxQoSClass0" }, /* non-standard counter */ 347 { 27, "RxQoSClass1" }, /* non-standard counter */ 348 { 28, "RxQoSClass2" }, /* non-standard counter */ 349 { 29, "RxQoSClass3" }, /* non-standard counter */ 350 }; 351 352 static const struct vsc73xx_counter vsc73xx_tx_counters[] = { 353 { 0, "TxEtherStatsPkts" }, 354 { 1, "TxBroadcast+MulticastPkts" }, /* non-standard counter */ 355 { 2, "TxTotalErrorPackets" }, /* non-standard counter */ 356 { 3, "TxEtherStatsBroadcastPkts" }, 357 { 4, "TxEtherStatsMulticastPkts" }, 358 { 5, "TxEtherStatsPkts64Octets" }, 359 { 6, "TxEtherStatsPkts65to127Octets" }, 360 { 7, "TxEtherStatsPkts128to255Octets" }, 361 { 8, "TxEtherStatsPkts256to511Octets" }, 362 { 9, "TxEtherStatsPkts512to1023Octets" }, 363 { 10, "TxEtherStatsPkts1024to1518Octets" }, 364 { 11, "TxJumboFrames" }, /* non-standard counter */ 365 { 12, "TxaPauseMACControlFramesTransmitted" }, 366 { 13, "TxFIFODrops" }, /* non-standard counter */ 367 { 14, "TxDrops" }, /* non-standard counter */ 368 { 15, "TxEtherStatsCollisions" }, 369 { 16, "TxEtherStatsCRCAlignErrors" }, 370 { 17, "TxEtherStatsUndersizePkts" }, 371 { 18, "TxEtherStatsOversizePkts" }, 372 { 19, "TxEtherStatsFragments" }, 373 { 20, "TxEtherStatsJabbers" }, 374 /* 21-24 are undefined */ 375 { 25, "TxaFramesReceivedOK" }, 376 { 26, "TxQoSClass0" }, /* non-standard counter */ 377 { 27, "TxQoSClass1" }, /* non-standard counter */ 378 { 28, "TxQoSClass2" }, /* non-standard counter */ 379 { 29, "TxQoSClass3" }, /* non-standard counter */ 380 }; 381 382 struct vsc73xx_vlan_summary { 383 size_t num_tagged; 384 size_t num_untagged; 385 }; 386 387 enum vsc73xx_port_vlan_conf { 388 VSC73XX_VLAN_FILTER, 389 VSC73XX_VLAN_FILTER_UNTAG_ALL, 390 VSC73XX_VLAN_IGNORE, 391 }; 392 393 int vsc73xx_is_addr_valid(u8 block, u8 subblock) 394 { 395 switch (block) { 396 case VSC73XX_BLOCK_MAC: 397 switch (subblock) { 398 case 0 ... 4: 399 case 6: 400 return 1; 401 } 402 break; 403 404 case VSC73XX_BLOCK_ANALYZER: 405 case VSC73XX_BLOCK_SYSTEM: 406 switch (subblock) { 407 case 0: 408 return 1; 409 } 410 break; 411 412 case VSC73XX_BLOCK_MII: 413 case VSC73XX_BLOCK_CAPTURE: 414 case VSC73XX_BLOCK_ARBITER: 415 switch (subblock) { 416 case 0 ... 1: 417 return 1; 418 } 419 break; 420 } 421 422 return 0; 423 } 424 EXPORT_SYMBOL(vsc73xx_is_addr_valid); 425 426 static int vsc73xx_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, 427 u32 *val) 428 { 429 return vsc->ops->read(vsc, block, subblock, reg, val); 430 } 431 432 static int vsc73xx_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, 433 u32 val) 434 { 435 return vsc->ops->write(vsc, block, subblock, reg, val); 436 } 437 438 static int vsc73xx_update_bits(struct vsc73xx *vsc, u8 block, u8 subblock, 439 u8 reg, u32 mask, u32 val) 440 { 441 u32 tmp, orig; 442 int ret; 443 444 /* Same read-modify-write algorithm as e.g. regmap */ 445 ret = vsc73xx_read(vsc, block, subblock, reg, &orig); 446 if (ret) 447 return ret; 448 tmp = orig & ~mask; 449 tmp |= val & mask; 450 return vsc73xx_write(vsc, block, subblock, reg, tmp); 451 } 452 453 static int vsc73xx_detect(struct vsc73xx *vsc) 454 { 455 bool icpu_si_boot_en; 456 bool icpu_pi_en; 457 u32 val; 458 u32 rev; 459 int ret; 460 u32 id; 461 462 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 463 VSC73XX_ICPU_MBOX_VAL, &val); 464 if (ret) { 465 dev_err(vsc->dev, "unable to read mailbox (%d)\n", ret); 466 return ret; 467 } 468 469 if (val == 0xffffffff) { 470 dev_info(vsc->dev, "chip seems dead.\n"); 471 return -EAGAIN; 472 } 473 474 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 475 VSC73XX_CHIPID, &val); 476 if (ret) { 477 dev_err(vsc->dev, "unable to read chip id (%d)\n", ret); 478 return ret; 479 } 480 481 id = (val >> VSC73XX_CHIPID_ID_SHIFT) & 482 VSC73XX_CHIPID_ID_MASK; 483 switch (id) { 484 case VSC73XX_CHIPID_ID_7385: 485 case VSC73XX_CHIPID_ID_7388: 486 case VSC73XX_CHIPID_ID_7395: 487 case VSC73XX_CHIPID_ID_7398: 488 break; 489 default: 490 dev_err(vsc->dev, "unsupported chip, id=%04x\n", id); 491 return -ENODEV; 492 } 493 494 vsc->chipid = id; 495 rev = (val >> VSC73XX_CHIPID_REV_SHIFT) & 496 VSC73XX_CHIPID_REV_MASK; 497 dev_info(vsc->dev, "VSC%04X (rev: %d) switch found\n", id, rev); 498 499 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 500 VSC73XX_ICPU_CTRL, &val); 501 if (ret) { 502 dev_err(vsc->dev, "unable to read iCPU control\n"); 503 return ret; 504 } 505 506 /* The iCPU can always be used but can boot in different ways. 507 * If it is initially disabled and has no external memory, 508 * we are in control and can do whatever we like, else we 509 * are probably in trouble (we need some way to communicate 510 * with the running firmware) so we bail out for now. 511 */ 512 icpu_pi_en = !!(val & VSC73XX_ICPU_CTRL_ICPU_PI_EN); 513 icpu_si_boot_en = !!(val & VSC73XX_ICPU_CTRL_BOOT_EN); 514 if (icpu_si_boot_en && icpu_pi_en) { 515 dev_err(vsc->dev, 516 "iCPU enabled boots from SI, has external memory\n"); 517 dev_err(vsc->dev, "no idea how to deal with this\n"); 518 return -ENODEV; 519 } 520 if (icpu_si_boot_en && !icpu_pi_en) { 521 dev_err(vsc->dev, 522 "iCPU enabled boots from PI/SI, no external memory\n"); 523 return -EAGAIN; 524 } 525 if (!icpu_si_boot_en && icpu_pi_en) { 526 dev_err(vsc->dev, 527 "iCPU enabled, boots from PI external memory\n"); 528 dev_err(vsc->dev, "no idea how to deal with this\n"); 529 return -ENODEV; 530 } 531 /* !icpu_si_boot_en && !cpu_pi_en */ 532 dev_info(vsc->dev, "iCPU disabled, no external memory\n"); 533 534 return 0; 535 } 536 537 static int vsc73xx_mdio_busy_check(struct vsc73xx *vsc) 538 { 539 int ret, err; 540 u32 val; 541 542 ret = read_poll_timeout(vsc73xx_read, err, 543 err < 0 || !(val & VSC73XX_MII_STAT_BUSY), 544 VSC73XX_MDIO_POLL_SLEEP_US, 545 VSC73XX_POLL_TIMEOUT_US, false, vsc, 546 VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL, 547 VSC73XX_MII_STAT, &val); 548 if (ret) 549 return ret; 550 return err; 551 } 552 553 static int vsc73xx_phy_read(struct dsa_switch *ds, int phy, int regnum) 554 { 555 struct vsc73xx *vsc = ds->priv; 556 u32 cmd; 557 u32 val; 558 int ret; 559 560 ret = vsc73xx_mdio_busy_check(vsc); 561 if (ret) 562 return ret; 563 564 /* Setting bit 26 means "read" */ 565 cmd = BIT(26) | (phy << 21) | (regnum << 16); 566 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd); 567 if (ret) 568 return ret; 569 570 ret = vsc73xx_mdio_busy_check(vsc); 571 if (ret) 572 return ret; 573 574 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, 0, 2, &val); 575 if (ret) 576 return ret; 577 if (val & BIT(16)) { 578 dev_err(vsc->dev, "reading reg %02x from phy%d failed\n", 579 regnum, phy); 580 return -EIO; 581 } 582 val &= 0xFFFFU; 583 584 dev_dbg(vsc->dev, "read reg %02x from phy%d = %04x\n", 585 regnum, phy, val); 586 587 return val; 588 } 589 590 static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum, 591 u16 val) 592 { 593 struct vsc73xx *vsc = ds->priv; 594 u32 cmd; 595 int ret; 596 597 ret = vsc73xx_mdio_busy_check(vsc); 598 if (ret) 599 return ret; 600 601 cmd = (phy << 21) | (regnum << 16) | val; 602 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd); 603 if (ret) 604 return ret; 605 606 dev_dbg(vsc->dev, "write %04x to reg %02x in phy%d\n", 607 val, regnum, phy); 608 return 0; 609 } 610 611 static enum dsa_tag_protocol vsc73xx_get_tag_protocol(struct dsa_switch *ds, 612 int port, 613 enum dsa_tag_protocol mp) 614 { 615 /* The switch internally uses a 8 byte header with length, 616 * source port, tag, LPA and priority. This is supposedly 617 * only accessible when operating the switch using the internal 618 * CPU or with an external CPU mapping the device in, but not 619 * when operating the switch over SPI and putting frames in/out 620 * on port 6 (the CPU port). So far we must assume that we 621 * cannot access the tag. (See "Internal frame header" section 622 * 3.9.1 in the manual.) 623 */ 624 return DSA_TAG_PROTO_VSC73XX_8021Q; 625 } 626 627 static int vsc73xx_wait_for_vlan_table_cmd(struct vsc73xx *vsc) 628 { 629 int ret, err; 630 u32 val; 631 632 ret = read_poll_timeout(vsc73xx_read, err, 633 err < 0 || 634 ((val & VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK) == 635 VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE), 636 VSC73XX_POLL_SLEEP_US, VSC73XX_POLL_TIMEOUT_US, 637 false, vsc, VSC73XX_BLOCK_ANALYZER, 638 0, VSC73XX_VLANACCESS, &val); 639 if (ret) 640 return ret; 641 return err; 642 } 643 644 static int 645 vsc73xx_read_vlan_table_entry(struct vsc73xx *vsc, u16 vid, u8 *portmap) 646 { 647 u32 val; 648 int ret; 649 650 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANTIDX, vid); 651 652 ret = vsc73xx_wait_for_vlan_table_cmd(vsc); 653 if (ret) 654 return ret; 655 656 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS, 657 VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK, 658 VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY); 659 660 ret = vsc73xx_wait_for_vlan_table_cmd(vsc); 661 if (ret) 662 return ret; 663 664 vsc73xx_read(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS, &val); 665 *portmap = (val & VSC73XX_VLANACCESS_VLAN_PORT_MASK) >> 666 VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT; 667 668 return 0; 669 } 670 671 static int 672 vsc73xx_write_vlan_table_entry(struct vsc73xx *vsc, u16 vid, u8 portmap) 673 { 674 int ret; 675 676 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANTIDX, vid); 677 678 ret = vsc73xx_wait_for_vlan_table_cmd(vsc); 679 if (ret) 680 return ret; 681 682 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS, 683 VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK | 684 VSC73XX_VLANACCESS_VLAN_SRC_CHECK | 685 VSC73XX_VLANACCESS_VLAN_PORT_MASK, 686 VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY | 687 VSC73XX_VLANACCESS_VLAN_SRC_CHECK | 688 (portmap << VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT)); 689 690 return vsc73xx_wait_for_vlan_table_cmd(vsc); 691 } 692 693 static int 694 vsc73xx_update_vlan_table(struct vsc73xx *vsc, int port, u16 vid, bool set) 695 { 696 u8 portmap; 697 int ret; 698 699 ret = vsc73xx_read_vlan_table_entry(vsc, vid, &portmap); 700 if (ret) 701 return ret; 702 703 if (set) 704 portmap |= BIT(port); 705 else 706 portmap &= ~BIT(port); 707 708 return vsc73xx_write_vlan_table_entry(vsc, vid, portmap); 709 } 710 711 static int vsc73xx_setup(struct dsa_switch *ds) 712 { 713 struct vsc73xx *vsc = ds->priv; 714 int i, ret; 715 716 dev_info(vsc->dev, "set up the switch\n"); 717 718 ds->untag_bridge_pvid = true; 719 ds->max_num_bridges = DSA_TAG_8021Q_MAX_NUM_BRIDGES; 720 721 /* Issue RESET */ 722 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET, 723 VSC73XX_GLORESET_MASTER_RESET); 724 usleep_range(125, 200); 725 726 /* Initialize memory, initialize RAM bank 0..15 except 6 and 7 727 * This sequence appears in the 728 * VSC7385 SparX-G5 datasheet section 6.6.1 729 * VSC7395 SparX-G5e datasheet section 6.6.1 730 * "initialization sequence". 731 * No explanation is given to the 0x1010400 magic number. 732 */ 733 for (i = 0; i <= 15; i++) { 734 if (i != 6 && i != 7) { 735 vsc73xx_write(vsc, VSC73XX_BLOCK_MEMINIT, 736 2, 737 0, 0x1010400 + i); 738 mdelay(1); 739 } 740 } 741 mdelay(30); 742 743 /* Clear MAC table */ 744 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, 745 VSC73XX_MACACCESS, 746 VSC73XX_MACACCESS_CMD_CLEAR_TABLE); 747 748 /* Set VLAN table to default values */ 749 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, 750 VSC73XX_VLANACCESS, 751 VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE); 752 753 msleep(40); 754 755 /* Use 20KiB buffers on all ports on VSC7395 756 * The VSC7385 has 16KiB buffers and that is the 757 * default if we don't set this up explicitly. 758 * Port "31" is "all ports". 759 */ 760 if (IS_739X(vsc)) 761 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 0x1f, 762 VSC73XX_Q_MISC_CONF, 763 VSC73XX_Q_MISC_CONF_EXTENT_MEM); 764 765 /* Put all ports into reset until enabled */ 766 for (i = 0; i < 7; i++) { 767 if (i == 5) 768 continue; 769 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 4, 770 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET); 771 } 772 773 /* MII delay, set both GTX and RX delay to 2 ns */ 774 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GMIIDELAY, 775 VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS | 776 VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS); 777 /* Ingess VLAN reception mask (table 145) */ 778 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANMASK, 779 0xff); 780 /* IP multicast flood mask (table 144) */ 781 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_IFLODMSK, 782 0xff); 783 784 mdelay(50); 785 786 /* Release reset from the internal PHYs */ 787 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET, 788 VSC73XX_GLORESET_PHY_RESET); 789 790 udelay(4); 791 792 /* Clear VLAN table */ 793 for (i = 0; i < VLAN_N_VID; i++) 794 vsc73xx_write_vlan_table_entry(vsc, i, 0); 795 796 INIT_LIST_HEAD(&vsc->vlans); 797 798 rtnl_lock(); 799 ret = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q)); 800 rtnl_unlock(); 801 802 return ret; 803 } 804 805 static void vsc73xx_teardown(struct dsa_switch *ds) 806 { 807 rtnl_lock(); 808 dsa_tag_8021q_unregister(ds); 809 rtnl_unlock(); 810 } 811 812 static void vsc73xx_init_port(struct vsc73xx *vsc, int port) 813 { 814 u32 val; 815 816 /* MAC configure, first reset the port and then write defaults */ 817 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 818 port, 819 VSC73XX_MAC_CFG, 820 VSC73XX_MAC_CFG_RESET); 821 822 /* Take up the port in 1Gbit mode by default, this will be 823 * augmented after auto-negotiation on the PHY-facing 824 * ports. 825 */ 826 if (port == CPU_PORT) 827 val = VSC73XX_MAC_CFG_1000M_F_RGMII; 828 else 829 val = VSC73XX_MAC_CFG_1000M_F_PHY; 830 831 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 832 port, 833 VSC73XX_MAC_CFG, 834 val | 835 VSC73XX_MAC_CFG_TX_EN | 836 VSC73XX_MAC_CFG_RX_EN); 837 838 /* Flow control for the CPU port: 839 * Use a zero delay pause frame when pause condition is left 840 * Obey pause control frames 841 */ 842 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 843 port, 844 VSC73XX_FCCONF, 845 VSC73XX_FCCONF_ZERO_PAUSE_EN | 846 VSC73XX_FCCONF_FLOW_CTRL_OBEY); 847 848 /* Issue pause control frames on PHY facing ports. 849 * Allow early initiation of MAC transmission if the amount 850 * of egress data is below 512 bytes on CPU port. 851 * FIXME: enable 20KiB buffers? 852 */ 853 if (port == CPU_PORT) 854 val = VSC73XX_Q_MISC_CONF_EARLY_TX_512; 855 else 856 val = VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE; 857 val |= VSC73XX_Q_MISC_CONF_EXTENT_MEM; 858 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 859 port, 860 VSC73XX_Q_MISC_CONF, 861 val); 862 863 /* Flow control MAC: a MAC address used in flow control frames */ 864 val = (vsc->addr[5] << 16) | (vsc->addr[4] << 8) | (vsc->addr[3]); 865 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 866 port, 867 VSC73XX_FCMACHI, 868 val); 869 val = (vsc->addr[2] << 16) | (vsc->addr[1] << 8) | (vsc->addr[0]); 870 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 871 port, 872 VSC73XX_FCMACLO, 873 val); 874 875 /* Tell the categorizer to forward pause frames, not control 876 * frame. Do not drop anything. 877 */ 878 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 879 port, 880 VSC73XX_CAT_DROP, 881 VSC73XX_CAT_DROP_FWD_PAUSE_ENA); 882 883 /* Clear all counters */ 884 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 885 port, VSC73XX_C_RX0, 0); 886 } 887 888 static void vsc73xx_reset_port(struct vsc73xx *vsc, int port, u32 initval) 889 { 890 int ret, err; 891 u32 val; 892 893 /* Disable RX on this port */ 894 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 895 VSC73XX_MAC_CFG, 896 VSC73XX_MAC_CFG_RX_EN, 0); 897 898 /* Discard packets */ 899 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 900 VSC73XX_ARBDISC, BIT(port), BIT(port)); 901 902 /* Wait until queue is empty */ 903 ret = read_poll_timeout(vsc73xx_read, err, 904 err < 0 || (val & BIT(port)), 905 VSC73XX_POLL_SLEEP_US, 906 VSC73XX_POLL_TIMEOUT_US, false, 907 vsc, VSC73XX_BLOCK_ARBITER, 0, 908 VSC73XX_ARBEMPTY, &val); 909 if (ret) 910 dev_err(vsc->dev, 911 "timeout waiting for block arbiter\n"); 912 else if (err < 0) 913 dev_err(vsc->dev, "error reading arbiter\n"); 914 915 /* Put this port into reset */ 916 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, 917 VSC73XX_MAC_CFG_RESET | initval); 918 } 919 920 static void vsc73xx_mac_config(struct phylink_config *config, unsigned int mode, 921 const struct phylink_link_state *state) 922 { 923 struct dsa_port *dp = dsa_phylink_to_port(config); 924 struct vsc73xx *vsc = dp->ds->priv; 925 int port = dp->index; 926 927 /* Special handling of the CPU-facing port */ 928 if (port == CPU_PORT) { 929 /* Other ports are already initialized but not this one */ 930 vsc73xx_init_port(vsc, CPU_PORT); 931 /* Select the external port for this interface (EXT_PORT) 932 * Enable the GMII GTX external clock 933 * Use double data rate (DDR mode) 934 */ 935 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 936 CPU_PORT, 937 VSC73XX_ADVPORTM, 938 VSC73XX_ADVPORTM_EXT_PORT | 939 VSC73XX_ADVPORTM_ENA_GTX | 940 VSC73XX_ADVPORTM_DDR_MODE); 941 } 942 } 943 944 static void vsc73xx_mac_link_down(struct phylink_config *config, 945 unsigned int mode, phy_interface_t interface) 946 { 947 struct dsa_port *dp = dsa_phylink_to_port(config); 948 struct vsc73xx *vsc = dp->ds->priv; 949 int port = dp->index; 950 951 /* This routine is described in the datasheet (below ARBDISC register 952 * description) 953 */ 954 vsc73xx_reset_port(vsc, port, 0); 955 956 /* Allow backward dropping of frames from this port */ 957 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 958 VSC73XX_SBACKWDROP, BIT(port), BIT(port)); 959 } 960 961 static void vsc73xx_mac_link_up(struct phylink_config *config, 962 struct phy_device *phy, unsigned int mode, 963 phy_interface_t interface, int speed, 964 int duplex, bool tx_pause, bool rx_pause) 965 { 966 struct dsa_port *dp = dsa_phylink_to_port(config); 967 struct vsc73xx *vsc = dp->ds->priv; 968 int port = dp->index; 969 u32 val; 970 u8 seed; 971 972 if (speed == SPEED_1000) 973 val = VSC73XX_MAC_CFG_GIGA_MODE | VSC73XX_MAC_CFG_TX_IPG_1000M; 974 else 975 val = VSC73XX_MAC_CFG_TX_IPG_100_10M; 976 977 if (phy_interface_mode_is_rgmii(interface)) 978 val |= VSC73XX_MAC_CFG_CLK_SEL_1000M; 979 else 980 val |= VSC73XX_MAC_CFG_CLK_SEL_EXT; 981 982 if (duplex == DUPLEX_FULL) 983 val |= VSC73XX_MAC_CFG_FDX; 984 else 985 /* In datasheet description ("Port Mode Procedure" in 5.6.2) 986 * this bit is configured only for half duplex. 987 */ 988 val |= VSC73XX_MAC_CFG_WEXC_DIS; 989 990 /* This routine is described in the datasheet (below ARBDISC register 991 * description) 992 */ 993 vsc73xx_reset_port(vsc, port, val); 994 995 /* Seed the port randomness with randomness */ 996 get_random_bytes(&seed, 1); 997 val |= seed << VSC73XX_MAC_CFG_SEED_OFFSET; 998 val |= VSC73XX_MAC_CFG_SEED_LOAD; 999 1000 /* Those bits are responsible for MTU only. Kernel takes care about MTU, 1001 * let's enable +8 bytes frame length unconditionally. 1002 */ 1003 val |= VSC73XX_MAC_CFG_VLAN_AWR | VSC73XX_MAC_CFG_VLAN_DBLAWR; 1004 1005 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val); 1006 1007 /* Flow control for the PHY facing ports: 1008 * Use a zero delay pause frame when pause condition is left 1009 * Obey pause control frames 1010 * When generating pause frames, use 0xff as pause value 1011 */ 1012 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_FCCONF, 1013 VSC73XX_FCCONF_ZERO_PAUSE_EN | 1014 VSC73XX_FCCONF_FLOW_CTRL_OBEY | 1015 0xff); 1016 1017 /* Accept packets again */ 1018 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 1019 VSC73XX_ARBDISC, BIT(port), 0); 1020 1021 /* Disallow backward dropping of frames from this port */ 1022 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 1023 VSC73XX_SBACKWDROP, BIT(port), 0); 1024 1025 /* Enable TX, RX, deassert reset, stop loading seed */ 1026 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1027 VSC73XX_MAC_CFG, 1028 VSC73XX_MAC_CFG_RESET | VSC73XX_MAC_CFG_SEED_LOAD | 1029 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN, 1030 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN); 1031 } 1032 1033 static bool vsc73xx_tag_8021q_active(struct dsa_port *dp) 1034 { 1035 return !dsa_port_is_vlan_filtering(dp); 1036 } 1037 1038 static struct vsc73xx_bridge_vlan * 1039 vsc73xx_bridge_vlan_find(struct vsc73xx *vsc, u16 vid) 1040 { 1041 struct vsc73xx_bridge_vlan *vlan; 1042 1043 list_for_each_entry(vlan, &vsc->vlans, list) 1044 if (vlan->vid == vid) 1045 return vlan; 1046 1047 return NULL; 1048 } 1049 1050 static void 1051 vsc73xx_bridge_vlan_remove_port(struct vsc73xx_bridge_vlan *vsc73xx_vlan, 1052 int port) 1053 { 1054 vsc73xx_vlan->portmask &= ~BIT(port); 1055 1056 if (vsc73xx_vlan->portmask) 1057 return; 1058 1059 list_del(&vsc73xx_vlan->list); 1060 kfree(vsc73xx_vlan); 1061 } 1062 1063 static void vsc73xx_bridge_vlan_summary(struct vsc73xx *vsc, int port, 1064 struct vsc73xx_vlan_summary *summary, 1065 u16 ignored_vid) 1066 { 1067 size_t num_tagged = 0, num_untagged = 0; 1068 struct vsc73xx_bridge_vlan *vlan; 1069 1070 list_for_each_entry(vlan, &vsc->vlans, list) { 1071 if (!(vlan->portmask & BIT(port)) || vlan->vid == ignored_vid) 1072 continue; 1073 1074 if (vlan->untagged & BIT(port)) 1075 num_untagged++; 1076 else 1077 num_tagged++; 1078 } 1079 1080 summary->num_untagged = num_untagged; 1081 summary->num_tagged = num_tagged; 1082 } 1083 1084 static u16 vsc73xx_find_first_vlan_untagged(struct vsc73xx *vsc, int port) 1085 { 1086 struct vsc73xx_bridge_vlan *vlan; 1087 1088 list_for_each_entry(vlan, &vsc->vlans, list) 1089 if ((vlan->portmask & BIT(port)) && 1090 (vlan->untagged & BIT(port))) 1091 return vlan->vid; 1092 1093 return VLAN_N_VID; 1094 } 1095 1096 static int vsc73xx_set_vlan_conf(struct vsc73xx *vsc, int port, 1097 enum vsc73xx_port_vlan_conf port_vlan_conf) 1098 { 1099 u32 val = 0; 1100 int ret; 1101 1102 if (port_vlan_conf == VSC73XX_VLAN_IGNORE) 1103 val = VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA | 1104 VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA; 1105 1106 ret = vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1107 VSC73XX_CAT_VLAN_MISC, 1108 VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA | 1109 VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA, val); 1110 if (ret) 1111 return ret; 1112 1113 val = (port_vlan_conf == VSC73XX_VLAN_FILTER) ? 1114 VSC73XX_TXUPDCFG_TX_INSERT_TAG : 0; 1115 1116 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1117 VSC73XX_TXUPDCFG, 1118 VSC73XX_TXUPDCFG_TX_INSERT_TAG, val); 1119 } 1120 1121 /** 1122 * vsc73xx_vlan_commit_conf - Update VLAN configuration of a port 1123 * @vsc: Switch private data structure 1124 * @port: Port index on which to operate 1125 * 1126 * Update the VLAN behavior of a port to make sure that when it is under 1127 * a VLAN filtering bridge, the port is either filtering with tag 1128 * preservation, or filtering with all VLANs egress-untagged. Otherwise, 1129 * the port ignores VLAN tags from packets and applies the port-based 1130 * VID. 1131 * 1132 * Must be called when changes are made to: 1133 * - the bridge VLAN filtering state of the port 1134 * - the number or attributes of VLANs from the bridge VLAN table, 1135 * while the port is currently VLAN-aware 1136 * 1137 * Return: 0 on success, or negative errno on error. 1138 */ 1139 static int vsc73xx_vlan_commit_conf(struct vsc73xx *vsc, int port) 1140 { 1141 enum vsc73xx_port_vlan_conf port_vlan_conf = VSC73XX_VLAN_IGNORE; 1142 struct dsa_port *dp = dsa_to_port(vsc->ds, port); 1143 1144 if (port == CPU_PORT) { 1145 port_vlan_conf = VSC73XX_VLAN_FILTER; 1146 } else if (dsa_port_is_vlan_filtering(dp)) { 1147 struct vsc73xx_vlan_summary summary; 1148 1149 port_vlan_conf = VSC73XX_VLAN_FILTER; 1150 1151 vsc73xx_bridge_vlan_summary(vsc, port, &summary, VLAN_N_VID); 1152 if (summary.num_tagged == 0) 1153 port_vlan_conf = VSC73XX_VLAN_FILTER_UNTAG_ALL; 1154 } 1155 1156 return vsc73xx_set_vlan_conf(vsc, port, port_vlan_conf); 1157 } 1158 1159 static int 1160 vsc73xx_vlan_change_untagged(struct vsc73xx *vsc, int port, u16 vid, bool set) 1161 { 1162 u32 val = 0; 1163 1164 if (set) 1165 val = VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA | 1166 ((vid << VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_SHIFT) & 1167 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID); 1168 1169 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1170 VSC73XX_TXUPDCFG, 1171 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA | 1172 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID, val); 1173 } 1174 1175 /** 1176 * vsc73xx_vlan_commit_untagged - Update native VLAN of a port 1177 * @vsc: Switch private data structure 1178 * @port: Port index on which to operate 1179 * 1180 * Update the native VLAN of a port (the one VLAN which is transmitted 1181 * as egress-tagged on a trunk port) when port is in VLAN filtering mode and 1182 * only one untagged vid is configured. 1183 * In other cases no need to configure it because switch can untag all vlans on 1184 * the port. 1185 * 1186 * Return: 0 on success, or negative errno on error. 1187 */ 1188 static int vsc73xx_vlan_commit_untagged(struct vsc73xx *vsc, int port) 1189 { 1190 struct dsa_port *dp = dsa_to_port(vsc->ds, port); 1191 struct vsc73xx_vlan_summary summary; 1192 u16 vid = 0; 1193 bool valid; 1194 1195 if (!dsa_port_is_vlan_filtering(dp)) 1196 /* Port is configured to untag all vlans in that case. 1197 * No need to commit untagged config change. 1198 */ 1199 return 0; 1200 1201 vsc73xx_bridge_vlan_summary(vsc, port, &summary, VLAN_N_VID); 1202 1203 if (summary.num_untagged > 1) 1204 /* Port must untag all vlans in that case. 1205 * No need to commit untagged config change. 1206 */ 1207 return 0; 1208 1209 valid = (summary.num_untagged == 1); 1210 if (valid) 1211 vid = vsc73xx_find_first_vlan_untagged(vsc, port); 1212 1213 return vsc73xx_vlan_change_untagged(vsc, port, vid, valid); 1214 } 1215 1216 static int 1217 vsc73xx_vlan_change_pvid(struct vsc73xx *vsc, int port, u16 vid, bool set) 1218 { 1219 u32 val = 0; 1220 int ret; 1221 1222 val = set ? 0 : VSC73XX_CAT_DROP_UNTAGGED_ENA; 1223 1224 ret = vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1225 VSC73XX_CAT_DROP, 1226 VSC73XX_CAT_DROP_UNTAGGED_ENA, val); 1227 if (!set || ret) 1228 return ret; 1229 1230 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1231 VSC73XX_CAT_PORT_VLAN, 1232 VSC73XX_CAT_PORT_VLAN_VLAN_VID, 1233 vid & VSC73XX_CAT_PORT_VLAN_VLAN_VID); 1234 } 1235 1236 /** 1237 * vsc73xx_vlan_commit_pvid - Update port-based default VLAN of a port 1238 * @vsc: Switch private data structure 1239 * @port: Port index on which to operate 1240 * 1241 * Update the PVID of a port so that it follows either the bridge PVID 1242 * configuration, when the bridge is currently VLAN-aware, or the PVID 1243 * from tag_8021q, when the port is standalone or under a VLAN-unaware 1244 * bridge. A port with no PVID drops all untagged and VID 0 tagged 1245 * traffic. 1246 * 1247 * Must be called when changes are made to: 1248 * - the bridge VLAN filtering state of the port 1249 * - the number or attributes of VLANs from the bridge VLAN table, 1250 * while the port is currently VLAN-aware 1251 * 1252 * Return: 0 on success, or negative errno on error. 1253 */ 1254 static int vsc73xx_vlan_commit_pvid(struct vsc73xx *vsc, int port) 1255 { 1256 struct vsc73xx_portinfo *portinfo = &vsc->portinfo[port]; 1257 bool valid = portinfo->pvid_tag_8021q_configured; 1258 struct dsa_port *dp = dsa_to_port(vsc->ds, port); 1259 u16 vid = portinfo->pvid_tag_8021q; 1260 1261 if (dsa_port_is_vlan_filtering(dp)) { 1262 vid = portinfo->pvid_vlan_filtering; 1263 valid = portinfo->pvid_vlan_filtering_configured; 1264 } 1265 1266 return vsc73xx_vlan_change_pvid(vsc, port, vid, valid); 1267 } 1268 1269 static int vsc73xx_vlan_commit_settings(struct vsc73xx *vsc, int port) 1270 { 1271 int ret; 1272 1273 ret = vsc73xx_vlan_commit_untagged(vsc, port); 1274 if (ret) 1275 return ret; 1276 1277 ret = vsc73xx_vlan_commit_pvid(vsc, port); 1278 if (ret) 1279 return ret; 1280 1281 return vsc73xx_vlan_commit_conf(vsc, port); 1282 } 1283 1284 static int vsc73xx_port_enable(struct dsa_switch *ds, int port, 1285 struct phy_device *phy) 1286 { 1287 struct vsc73xx *vsc = ds->priv; 1288 1289 dev_info(vsc->dev, "enable port %d\n", port); 1290 vsc73xx_init_port(vsc, port); 1291 1292 return vsc73xx_vlan_commit_settings(vsc, port); 1293 } 1294 1295 static void vsc73xx_port_disable(struct dsa_switch *ds, int port) 1296 { 1297 struct vsc73xx *vsc = ds->priv; 1298 1299 /* Just put the port into reset */ 1300 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, 1301 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET); 1302 } 1303 1304 static const struct vsc73xx_counter * 1305 vsc73xx_find_counter(struct vsc73xx *vsc, 1306 u8 counter, 1307 bool tx) 1308 { 1309 const struct vsc73xx_counter *cnts; 1310 int num_cnts; 1311 int i; 1312 1313 if (tx) { 1314 cnts = vsc73xx_tx_counters; 1315 num_cnts = ARRAY_SIZE(vsc73xx_tx_counters); 1316 } else { 1317 cnts = vsc73xx_rx_counters; 1318 num_cnts = ARRAY_SIZE(vsc73xx_rx_counters); 1319 } 1320 1321 for (i = 0; i < num_cnts; i++) { 1322 const struct vsc73xx_counter *cnt; 1323 1324 cnt = &cnts[i]; 1325 if (cnt->counter == counter) 1326 return cnt; 1327 } 1328 1329 return NULL; 1330 } 1331 1332 static void vsc73xx_get_strings(struct dsa_switch *ds, int port, u32 stringset, 1333 uint8_t *data) 1334 { 1335 const struct vsc73xx_counter *cnt; 1336 struct vsc73xx *vsc = ds->priv; 1337 u8 indices[6]; 1338 u8 *buf = data; 1339 int i; 1340 u32 val; 1341 int ret; 1342 1343 if (stringset != ETH_SS_STATS) 1344 return; 1345 1346 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port, 1347 VSC73XX_C_CFG, &val); 1348 if (ret) 1349 return; 1350 1351 indices[0] = (val & 0x1f); /* RX counter 0 */ 1352 indices[1] = ((val >> 5) & 0x1f); /* RX counter 1 */ 1353 indices[2] = ((val >> 10) & 0x1f); /* RX counter 2 */ 1354 indices[3] = ((val >> 16) & 0x1f); /* TX counter 0 */ 1355 indices[4] = ((val >> 21) & 0x1f); /* TX counter 1 */ 1356 indices[5] = ((val >> 26) & 0x1f); /* TX counter 2 */ 1357 1358 /* The first counters is the RX octets */ 1359 ethtool_puts(&buf, "RxEtherStatsOctets"); 1360 1361 /* Each port supports recording 3 RX counters and 3 TX counters, 1362 * figure out what counters we use in this set-up and return the 1363 * names of them. The hardware default counters will be number of 1364 * packets on RX/TX, combined broadcast+multicast packets RX/TX and 1365 * total error packets RX/TX. 1366 */ 1367 for (i = 0; i < 3; i++) { 1368 cnt = vsc73xx_find_counter(vsc, indices[i], false); 1369 ethtool_puts(&buf, cnt ? cnt->name : ""); 1370 } 1371 1372 /* TX stats begins with the number of TX octets */ 1373 ethtool_puts(&buf, "TxEtherStatsOctets"); 1374 1375 for (i = 3; i < 6; i++) { 1376 cnt = vsc73xx_find_counter(vsc, indices[i], true); 1377 ethtool_puts(&buf, cnt ? cnt->name : ""); 1378 1379 } 1380 } 1381 1382 static int vsc73xx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1383 { 1384 /* We only support SS_STATS */ 1385 if (sset != ETH_SS_STATS) 1386 return 0; 1387 /* RX and TX packets, then 3 RX counters, 3 TX counters */ 1388 return 8; 1389 } 1390 1391 static void vsc73xx_get_ethtool_stats(struct dsa_switch *ds, int port, 1392 uint64_t *data) 1393 { 1394 struct vsc73xx *vsc = ds->priv; 1395 u8 regs[] = { 1396 VSC73XX_RXOCT, 1397 VSC73XX_C_RX0, 1398 VSC73XX_C_RX1, 1399 VSC73XX_C_RX2, 1400 VSC73XX_TXOCT, 1401 VSC73XX_C_TX0, 1402 VSC73XX_C_TX1, 1403 VSC73XX_C_TX2, 1404 }; 1405 u32 val; 1406 int ret; 1407 int i; 1408 1409 for (i = 0; i < ARRAY_SIZE(regs); i++) { 1410 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port, 1411 regs[i], &val); 1412 if (ret) { 1413 dev_err(vsc->dev, "error reading counter %d\n", i); 1414 return; 1415 } 1416 data[i] = val; 1417 } 1418 } 1419 1420 static int vsc73xx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1421 { 1422 struct vsc73xx *vsc = ds->priv; 1423 1424 return vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, 1425 VSC73XX_MAXLEN, new_mtu + ETH_HLEN + ETH_FCS_LEN); 1426 } 1427 1428 /* According to application not "VSC7398 Jumbo Frames" setting 1429 * up the frame size to 9.6 KB does not affect the performance on standard 1430 * frames. It is clear from the application note that 1431 * "9.6 kilobytes" == 9600 bytes. 1432 */ 1433 static int vsc73xx_get_max_mtu(struct dsa_switch *ds, int port) 1434 { 1435 return 9600 - ETH_HLEN - ETH_FCS_LEN; 1436 } 1437 1438 static void vsc73xx_phylink_get_caps(struct dsa_switch *dsa, int port, 1439 struct phylink_config *config) 1440 { 1441 unsigned long *interfaces = config->supported_interfaces; 1442 1443 if (port == 5) 1444 return; 1445 1446 if (port == CPU_PORT) { 1447 __set_bit(PHY_INTERFACE_MODE_MII, interfaces); 1448 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces); 1449 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces); 1450 __set_bit(PHY_INTERFACE_MODE_RGMII, interfaces); 1451 } 1452 1453 if (port <= 4) { 1454 /* Internal PHYs */ 1455 __set_bit(PHY_INTERFACE_MODE_INTERNAL, interfaces); 1456 /* phylib default */ 1457 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces); 1458 } 1459 1460 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000; 1461 } 1462 1463 static int 1464 vsc73xx_port_vlan_filtering(struct dsa_switch *ds, int port, 1465 bool vlan_filtering, struct netlink_ext_ack *extack) 1466 { 1467 struct vsc73xx *vsc = ds->priv; 1468 1469 /* The commit to hardware processed below is required because vsc73xx 1470 * is using tag_8021q. When vlan_filtering is disabled, tag_8021q uses 1471 * pvid/untagged vlans for port recognition. The values configured for 1472 * vlans and pvid/untagged states are stored in portinfo structure. 1473 * When vlan_filtering is enabled, we need to restore pvid/untagged from 1474 * portinfo structure. Analogous routine is processed when 1475 * vlan_filtering is disabled, but values used for tag_8021q are 1476 * restored. 1477 */ 1478 1479 return vsc73xx_vlan_commit_settings(vsc, port); 1480 } 1481 1482 static int vsc73xx_port_vlan_add(struct dsa_switch *ds, int port, 1483 const struct switchdev_obj_port_vlan *vlan, 1484 struct netlink_ext_ack *extack) 1485 { 1486 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1487 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1488 struct dsa_port *dp = dsa_to_port(ds, port); 1489 struct vsc73xx_bridge_vlan *vsc73xx_vlan; 1490 struct vsc73xx_vlan_summary summary; 1491 struct vsc73xx_portinfo *portinfo; 1492 struct vsc73xx *vsc = ds->priv; 1493 bool commit_to_hardware; 1494 int ret = 0; 1495 1496 /* Be sure to deny alterations to the configuration done by tag_8021q. 1497 */ 1498 if (vid_is_dsa_8021q(vlan->vid)) { 1499 NL_SET_ERR_MSG_MOD(extack, 1500 "Range 3072-4095 reserved for dsa_8021q operation"); 1501 return -EBUSY; 1502 } 1503 1504 /* The processed vlan->vid is excluded from the search because the VLAN 1505 * can be re-added with a different set of flags, so it's easiest to 1506 * ignore its old flags from the VLAN database software copy. 1507 */ 1508 vsc73xx_bridge_vlan_summary(vsc, port, &summary, vlan->vid); 1509 1510 /* VSC73XX allows only three untagged states: none, one or all */ 1511 if ((untagged && summary.num_tagged > 0 && summary.num_untagged > 0) || 1512 (!untagged && summary.num_untagged > 1)) { 1513 NL_SET_ERR_MSG_MOD(extack, 1514 "Port can have only none, one or all untagged vlan"); 1515 return -EBUSY; 1516 } 1517 1518 vsc73xx_vlan = vsc73xx_bridge_vlan_find(vsc, vlan->vid); 1519 1520 if (!vsc73xx_vlan) { 1521 vsc73xx_vlan = kzalloc(sizeof(*vsc73xx_vlan), GFP_KERNEL); 1522 if (!vsc73xx_vlan) 1523 return -ENOMEM; 1524 1525 vsc73xx_vlan->vid = vlan->vid; 1526 1527 list_add_tail(&vsc73xx_vlan->list, &vsc->vlans); 1528 } 1529 1530 vsc73xx_vlan->portmask |= BIT(port); 1531 1532 /* CPU port must be always tagged because source port identification is 1533 * based on tag_8021q. 1534 */ 1535 if (port == CPU_PORT) 1536 goto update_vlan_table; 1537 1538 if (untagged) 1539 vsc73xx_vlan->untagged |= BIT(port); 1540 else 1541 vsc73xx_vlan->untagged &= ~BIT(port); 1542 1543 portinfo = &vsc->portinfo[port]; 1544 1545 if (pvid) { 1546 portinfo->pvid_vlan_filtering_configured = true; 1547 portinfo->pvid_vlan_filtering = vlan->vid; 1548 } else if (portinfo->pvid_vlan_filtering_configured && 1549 portinfo->pvid_vlan_filtering == vlan->vid) { 1550 portinfo->pvid_vlan_filtering_configured = false; 1551 } 1552 1553 commit_to_hardware = !vsc73xx_tag_8021q_active(dp); 1554 if (commit_to_hardware) { 1555 ret = vsc73xx_vlan_commit_settings(vsc, port); 1556 if (ret) 1557 goto err; 1558 } 1559 1560 update_vlan_table: 1561 ret = vsc73xx_update_vlan_table(vsc, port, vlan->vid, true); 1562 if (!ret) 1563 return 0; 1564 err: 1565 vsc73xx_bridge_vlan_remove_port(vsc73xx_vlan, port); 1566 return ret; 1567 } 1568 1569 static int vsc73xx_port_vlan_del(struct dsa_switch *ds, int port, 1570 const struct switchdev_obj_port_vlan *vlan) 1571 { 1572 struct vsc73xx_bridge_vlan *vsc73xx_vlan; 1573 struct vsc73xx_portinfo *portinfo; 1574 struct vsc73xx *vsc = ds->priv; 1575 bool commit_to_hardware; 1576 int ret; 1577 1578 ret = vsc73xx_update_vlan_table(vsc, port, vlan->vid, false); 1579 if (ret) 1580 return ret; 1581 1582 portinfo = &vsc->portinfo[port]; 1583 1584 if (portinfo->pvid_vlan_filtering_configured && 1585 portinfo->pvid_vlan_filtering == vlan->vid) 1586 portinfo->pvid_vlan_filtering_configured = false; 1587 1588 vsc73xx_vlan = vsc73xx_bridge_vlan_find(vsc, vlan->vid); 1589 1590 if (vsc73xx_vlan) 1591 vsc73xx_bridge_vlan_remove_port(vsc73xx_vlan, port); 1592 1593 commit_to_hardware = !vsc73xx_tag_8021q_active(dsa_to_port(ds, port)); 1594 1595 if (commit_to_hardware) 1596 return vsc73xx_vlan_commit_settings(vsc, port); 1597 1598 return 0; 1599 } 1600 1601 static int vsc73xx_tag_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid, 1602 u16 flags) 1603 { 1604 bool pvid = flags & BRIDGE_VLAN_INFO_PVID; 1605 struct vsc73xx_portinfo *portinfo; 1606 struct vsc73xx *vsc = ds->priv; 1607 bool commit_to_hardware; 1608 int ret; 1609 1610 portinfo = &vsc->portinfo[port]; 1611 1612 if (pvid) { 1613 portinfo->pvid_tag_8021q_configured = true; 1614 portinfo->pvid_tag_8021q = vid; 1615 } 1616 1617 commit_to_hardware = vsc73xx_tag_8021q_active(dsa_to_port(ds, port)); 1618 if (commit_to_hardware) { 1619 ret = vsc73xx_vlan_commit_settings(vsc, port); 1620 if (ret) 1621 return ret; 1622 } 1623 1624 return vsc73xx_update_vlan_table(vsc, port, vid, true); 1625 } 1626 1627 static int vsc73xx_tag_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid) 1628 { 1629 struct vsc73xx_portinfo *portinfo; 1630 struct vsc73xx *vsc = ds->priv; 1631 1632 portinfo = &vsc->portinfo[port]; 1633 1634 if (portinfo->pvid_tag_8021q_configured && 1635 portinfo->pvid_tag_8021q == vid) { 1636 struct dsa_port *dp = dsa_to_port(ds, port); 1637 bool commit_to_hardware; 1638 int err; 1639 1640 portinfo->pvid_tag_8021q_configured = false; 1641 1642 commit_to_hardware = vsc73xx_tag_8021q_active(dp); 1643 if (commit_to_hardware) { 1644 err = vsc73xx_vlan_commit_settings(vsc, port); 1645 if (err) 1646 return err; 1647 } 1648 } 1649 1650 return vsc73xx_update_vlan_table(vsc, port, vid, false); 1651 } 1652 1653 static int vsc73xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1654 struct switchdev_brport_flags flags, 1655 struct netlink_ext_ack *extack) 1656 { 1657 if (flags.mask & ~BR_LEARNING) 1658 return -EINVAL; 1659 1660 return 0; 1661 } 1662 1663 static int vsc73xx_port_bridge_flags(struct dsa_switch *ds, int port, 1664 struct switchdev_brport_flags flags, 1665 struct netlink_ext_ack *extack) 1666 { 1667 if (flags.mask & BR_LEARNING) { 1668 u32 val = flags.val & BR_LEARNING ? BIT(port) : 0; 1669 struct vsc73xx *vsc = ds->priv; 1670 1671 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1672 VSC73XX_LEARNMASK, BIT(port), val); 1673 } 1674 1675 return 0; 1676 } 1677 1678 static void vsc73xx_refresh_fwd_map(struct dsa_switch *ds, int port, u8 state) 1679 { 1680 struct dsa_port *other_dp, *dp = dsa_to_port(ds, port); 1681 struct vsc73xx *vsc = ds->priv; 1682 u16 mask; 1683 1684 if (state != BR_STATE_FORWARDING) { 1685 /* Ports that aren't in the forwarding state must not 1686 * forward packets anywhere. 1687 */ 1688 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1689 VSC73XX_SRCMASKS + port, 1690 VSC73XX_SRCMASKS_PORTS_MASK, 0); 1691 1692 dsa_switch_for_each_available_port(other_dp, ds) { 1693 if (other_dp == dp) 1694 continue; 1695 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1696 VSC73XX_SRCMASKS + other_dp->index, 1697 BIT(port), 0); 1698 } 1699 1700 return; 1701 } 1702 1703 /* Forwarding ports must forward to the CPU and to other ports 1704 * in the same bridge 1705 */ 1706 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1707 VSC73XX_SRCMASKS + CPU_PORT, BIT(port), BIT(port)); 1708 1709 mask = BIT(CPU_PORT); 1710 1711 dsa_switch_for_each_user_port(other_dp, ds) { 1712 int other_port = other_dp->index; 1713 1714 if (port == other_port || !dsa_port_bridge_same(dp, other_dp) || 1715 other_dp->stp_state != BR_STATE_FORWARDING) 1716 continue; 1717 1718 mask |= BIT(other_port); 1719 1720 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1721 VSC73XX_SRCMASKS + other_port, 1722 BIT(port), BIT(port)); 1723 } 1724 1725 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1726 VSC73XX_SRCMASKS + port, 1727 VSC73XX_SRCMASKS_PORTS_MASK, mask); 1728 } 1729 1730 /* FIXME: STP frames aren't forwarded at this moment. BPDU frames are 1731 * forwarded only from and to PI/SI interface. For more info see chapter 1732 * 2.7.1 (CPU Forwarding) in datasheet. 1733 * This function is required for tag_8021q operations. 1734 */ 1735 static void vsc73xx_port_stp_state_set(struct dsa_switch *ds, int port, 1736 u8 state) 1737 { 1738 struct dsa_port *dp = dsa_to_port(ds, port); 1739 struct vsc73xx *vsc = ds->priv; 1740 u32 val = 0; 1741 1742 if (state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) 1743 val = dp->learning ? BIT(port) : 0; 1744 1745 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1746 VSC73XX_LEARNMASK, BIT(port), val); 1747 1748 val = (state == BR_STATE_BLOCKING || state == BR_STATE_DISABLED) ? 1749 0 : BIT(port); 1750 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1751 VSC73XX_RECVMASK, BIT(port), val); 1752 1753 /* CPU Port should always forward packets when user ports are forwarding 1754 * so let's configure it from other ports only. 1755 */ 1756 if (port != CPU_PORT) 1757 vsc73xx_refresh_fwd_map(ds, port, state); 1758 } 1759 1760 static const struct phylink_mac_ops vsc73xx_phylink_mac_ops = { 1761 .mac_config = vsc73xx_mac_config, 1762 .mac_link_down = vsc73xx_mac_link_down, 1763 .mac_link_up = vsc73xx_mac_link_up, 1764 }; 1765 1766 static const struct dsa_switch_ops vsc73xx_ds_ops = { 1767 .get_tag_protocol = vsc73xx_get_tag_protocol, 1768 .setup = vsc73xx_setup, 1769 .teardown = vsc73xx_teardown, 1770 .phy_read = vsc73xx_phy_read, 1771 .phy_write = vsc73xx_phy_write, 1772 .get_strings = vsc73xx_get_strings, 1773 .get_ethtool_stats = vsc73xx_get_ethtool_stats, 1774 .get_sset_count = vsc73xx_get_sset_count, 1775 .port_enable = vsc73xx_port_enable, 1776 .port_disable = vsc73xx_port_disable, 1777 .port_pre_bridge_flags = vsc73xx_port_pre_bridge_flags, 1778 .port_bridge_flags = vsc73xx_port_bridge_flags, 1779 .port_bridge_join = dsa_tag_8021q_bridge_join, 1780 .port_bridge_leave = dsa_tag_8021q_bridge_leave, 1781 .port_change_mtu = vsc73xx_change_mtu, 1782 .port_max_mtu = vsc73xx_get_max_mtu, 1783 .port_stp_state_set = vsc73xx_port_stp_state_set, 1784 .port_vlan_filtering = vsc73xx_port_vlan_filtering, 1785 .port_vlan_add = vsc73xx_port_vlan_add, 1786 .port_vlan_del = vsc73xx_port_vlan_del, 1787 .phylink_get_caps = vsc73xx_phylink_get_caps, 1788 .tag_8021q_vlan_add = vsc73xx_tag_8021q_vlan_add, 1789 .tag_8021q_vlan_del = vsc73xx_tag_8021q_vlan_del, 1790 }; 1791 1792 static int vsc73xx_gpio_get(struct gpio_chip *chip, unsigned int offset) 1793 { 1794 struct vsc73xx *vsc = gpiochip_get_data(chip); 1795 u32 val; 1796 int ret; 1797 1798 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1799 VSC73XX_GPIO, &val); 1800 if (ret) 1801 return ret; 1802 1803 return !!(val & BIT(offset)); 1804 } 1805 1806 static void vsc73xx_gpio_set(struct gpio_chip *chip, unsigned int offset, 1807 int val) 1808 { 1809 struct vsc73xx *vsc = gpiochip_get_data(chip); 1810 u32 tmp = val ? BIT(offset) : 0; 1811 1812 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1813 VSC73XX_GPIO, BIT(offset), tmp); 1814 } 1815 1816 static int vsc73xx_gpio_direction_output(struct gpio_chip *chip, 1817 unsigned int offset, int val) 1818 { 1819 struct vsc73xx *vsc = gpiochip_get_data(chip); 1820 u32 tmp = val ? BIT(offset) : 0; 1821 1822 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1823 VSC73XX_GPIO, BIT(offset + 4) | BIT(offset), 1824 BIT(offset + 4) | tmp); 1825 } 1826 1827 static int vsc73xx_gpio_direction_input(struct gpio_chip *chip, 1828 unsigned int offset) 1829 { 1830 struct vsc73xx *vsc = gpiochip_get_data(chip); 1831 1832 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1833 VSC73XX_GPIO, BIT(offset + 4), 1834 0); 1835 } 1836 1837 static int vsc73xx_gpio_get_direction(struct gpio_chip *chip, 1838 unsigned int offset) 1839 { 1840 struct vsc73xx *vsc = gpiochip_get_data(chip); 1841 u32 val; 1842 int ret; 1843 1844 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1845 VSC73XX_GPIO, &val); 1846 if (ret) 1847 return ret; 1848 1849 return !(val & BIT(offset + 4)); 1850 } 1851 1852 static int vsc73xx_gpio_probe(struct vsc73xx *vsc) 1853 { 1854 int ret; 1855 1856 vsc->gc.label = devm_kasprintf(vsc->dev, GFP_KERNEL, "VSC%04x", 1857 vsc->chipid); 1858 if (!vsc->gc.label) 1859 return -ENOMEM; 1860 vsc->gc.ngpio = 4; 1861 vsc->gc.owner = THIS_MODULE; 1862 vsc->gc.parent = vsc->dev; 1863 vsc->gc.base = -1; 1864 vsc->gc.get = vsc73xx_gpio_get; 1865 vsc->gc.set = vsc73xx_gpio_set; 1866 vsc->gc.direction_input = vsc73xx_gpio_direction_input; 1867 vsc->gc.direction_output = vsc73xx_gpio_direction_output; 1868 vsc->gc.get_direction = vsc73xx_gpio_get_direction; 1869 vsc->gc.can_sleep = true; 1870 ret = devm_gpiochip_add_data(vsc->dev, &vsc->gc, vsc); 1871 if (ret) { 1872 dev_err(vsc->dev, "unable to register GPIO chip\n"); 1873 return ret; 1874 } 1875 return 0; 1876 } 1877 1878 int vsc73xx_probe(struct vsc73xx *vsc) 1879 { 1880 struct device *dev = vsc->dev; 1881 int ret; 1882 1883 /* Release reset, if any */ 1884 vsc->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1885 if (IS_ERR(vsc->reset)) { 1886 dev_err(dev, "failed to get RESET GPIO\n"); 1887 return PTR_ERR(vsc->reset); 1888 } 1889 if (vsc->reset) 1890 /* Wait 20ms according to datasheet table 245 */ 1891 msleep(20); 1892 1893 ret = vsc73xx_detect(vsc); 1894 if (ret == -EAGAIN) { 1895 dev_err(vsc->dev, 1896 "Chip seems to be out of control. Assert reset and try again.\n"); 1897 gpiod_set_value_cansleep(vsc->reset, 1); 1898 /* Reset pulse should be 20ns minimum, according to datasheet 1899 * table 245, so 10us should be fine 1900 */ 1901 usleep_range(10, 100); 1902 gpiod_set_value_cansleep(vsc->reset, 0); 1903 /* Wait 20ms according to datasheet table 245 */ 1904 msleep(20); 1905 ret = vsc73xx_detect(vsc); 1906 } 1907 if (ret) { 1908 dev_err(dev, "no chip found (%d)\n", ret); 1909 return -ENODEV; 1910 } 1911 1912 eth_random_addr(vsc->addr); 1913 dev_info(vsc->dev, 1914 "MAC for control frames: %02X:%02X:%02X:%02X:%02X:%02X\n", 1915 vsc->addr[0], vsc->addr[1], vsc->addr[2], 1916 vsc->addr[3], vsc->addr[4], vsc->addr[5]); 1917 1918 vsc->ds = devm_kzalloc(dev, sizeof(*vsc->ds), GFP_KERNEL); 1919 if (!vsc->ds) 1920 return -ENOMEM; 1921 1922 vsc->ds->dev = dev; 1923 vsc->ds->num_ports = VSC73XX_MAX_NUM_PORTS; 1924 vsc->ds->priv = vsc; 1925 1926 vsc->ds->ops = &vsc73xx_ds_ops; 1927 vsc->ds->phylink_mac_ops = &vsc73xx_phylink_mac_ops; 1928 ret = dsa_register_switch(vsc->ds); 1929 if (ret) { 1930 dev_err(dev, "unable to register switch (%d)\n", ret); 1931 return ret; 1932 } 1933 1934 ret = vsc73xx_gpio_probe(vsc); 1935 if (ret) { 1936 dsa_unregister_switch(vsc->ds); 1937 return ret; 1938 } 1939 1940 return 0; 1941 } 1942 EXPORT_SYMBOL(vsc73xx_probe); 1943 1944 void vsc73xx_remove(struct vsc73xx *vsc) 1945 { 1946 dsa_unregister_switch(vsc->ds); 1947 gpiod_set_value(vsc->reset, 1); 1948 } 1949 EXPORT_SYMBOL(vsc73xx_remove); 1950 1951 void vsc73xx_shutdown(struct vsc73xx *vsc) 1952 { 1953 dsa_switch_shutdown(vsc->ds); 1954 } 1955 EXPORT_SYMBOL(vsc73xx_shutdown); 1956 1957 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>"); 1958 MODULE_DESCRIPTION("Vitesse VSC7385/7388/7395/7398 driver"); 1959 MODULE_LICENSE("GPL v2"); 1960