1 // SPDX-License-Identifier: GPL-2.0 2 /* DSA driver for: 3 * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch 4 * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch 5 * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch 6 * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch 7 * 8 * These switches have a built-in 8051 CPU and can download and execute a 9 * firmware in this CPU. They can also be configured to use an external CPU 10 * handling the switch in a memory-mapped manner by connecting to that external 11 * CPU's memory bus. 12 * 13 * Copyright (C) 2018 Linus Wallej <linus.walleij@linaro.org> 14 * Includes portions of code from the firmware uploader by: 15 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> 16 */ 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/device.h> 20 #include <linux/iopoll.h> 21 #include <linux/of.h> 22 #include <linux/of_mdio.h> 23 #include <linux/bitops.h> 24 #include <linux/if_bridge.h> 25 #include <linux/if_vlan.h> 26 #include <linux/etherdevice.h> 27 #include <linux/gpio/consumer.h> 28 #include <linux/gpio/driver.h> 29 #include <linux/dsa/8021q.h> 30 #include <linux/random.h> 31 #include <net/dsa.h> 32 33 #include "vitesse-vsc73xx.h" 34 35 #define VSC73XX_BLOCK_MAC 0x1 /* Subblocks 0-4, 6 (CPU port) */ 36 #define VSC73XX_BLOCK_ANALYZER 0x2 /* Only subblock 0 */ 37 #define VSC73XX_BLOCK_MII 0x3 /* Subblocks 0 and 1 */ 38 #define VSC73XX_BLOCK_MEMINIT 0x3 /* Only subblock 2 */ 39 #define VSC73XX_BLOCK_CAPTURE 0x4 /* Only subblock 2 */ 40 #define VSC73XX_BLOCK_ARBITER 0x5 /* Only subblock 0 */ 41 #define VSC73XX_BLOCK_SYSTEM 0x7 /* Only subblock 0 */ 42 43 #define CPU_PORT 6 /* CPU port */ 44 45 /* MAC Block registers */ 46 #define VSC73XX_MAC_CFG 0x00 47 #define VSC73XX_MACHDXGAP 0x02 48 #define VSC73XX_FCCONF 0x04 49 #define VSC73XX_FCMACHI 0x08 50 #define VSC73XX_FCMACLO 0x0c 51 #define VSC73XX_MAXLEN 0x10 52 #define VSC73XX_ADVPORTM 0x19 53 #define VSC73XX_TXUPDCFG 0x24 54 #define VSC73XX_TXQ_SELECT_CFG 0x28 55 #define VSC73XX_RXOCT 0x50 56 #define VSC73XX_TXOCT 0x51 57 #define VSC73XX_C_RX0 0x52 58 #define VSC73XX_C_RX1 0x53 59 #define VSC73XX_C_RX2 0x54 60 #define VSC73XX_C_TX0 0x55 61 #define VSC73XX_C_TX1 0x56 62 #define VSC73XX_C_TX2 0x57 63 #define VSC73XX_C_CFG 0x58 64 #define VSC73XX_CAT_DROP 0x6e 65 #define VSC73XX_CAT_PR_MISC_L2 0x6f 66 #define VSC73XX_CAT_PR_USR_PRIO 0x75 67 #define VSC73XX_CAT_VLAN_MISC 0x79 68 #define VSC73XX_CAT_PORT_VLAN 0x7a 69 #define VSC73XX_Q_MISC_CONF 0xdf 70 71 /* MAC_CFG register bits */ 72 #define VSC73XX_MAC_CFG_WEXC_DIS BIT(31) 73 #define VSC73XX_MAC_CFG_PORT_RST BIT(29) 74 #define VSC73XX_MAC_CFG_TX_EN BIT(28) 75 #define VSC73XX_MAC_CFG_SEED_LOAD BIT(27) 76 #define VSC73XX_MAC_CFG_SEED_MASK GENMASK(26, 19) 77 #define VSC73XX_MAC_CFG_SEED_OFFSET 19 78 #define VSC73XX_MAC_CFG_FDX BIT(18) 79 #define VSC73XX_MAC_CFG_GIGA_MODE BIT(17) 80 #define VSC73XX_MAC_CFG_RX_EN BIT(16) 81 #define VSC73XX_MAC_CFG_VLAN_DBLAWR BIT(15) 82 #define VSC73XX_MAC_CFG_VLAN_AWR BIT(14) 83 #define VSC73XX_MAC_CFG_100_BASE_T BIT(13) /* Not in manual */ 84 #define VSC73XX_MAC_CFG_TX_IPG_MASK GENMASK(10, 6) 85 #define VSC73XX_MAC_CFG_TX_IPG_OFFSET 6 86 #define VSC73XX_MAC_CFG_TX_IPG_1000M (6 << VSC73XX_MAC_CFG_TX_IPG_OFFSET) 87 #define VSC73XX_MAC_CFG_TX_IPG_100_10M (17 << VSC73XX_MAC_CFG_TX_IPG_OFFSET) 88 #define VSC73XX_MAC_CFG_MAC_RX_RST BIT(5) 89 #define VSC73XX_MAC_CFG_MAC_TX_RST BIT(4) 90 #define VSC73XX_MAC_CFG_CLK_SEL_MASK GENMASK(2, 0) 91 #define VSC73XX_MAC_CFG_CLK_SEL_OFFSET 0 92 #define VSC73XX_MAC_CFG_CLK_SEL_1000M 1 93 #define VSC73XX_MAC_CFG_CLK_SEL_100M 2 94 #define VSC73XX_MAC_CFG_CLK_SEL_10M 3 95 #define VSC73XX_MAC_CFG_CLK_SEL_EXT 4 96 97 #define VSC73XX_MAC_CFG_1000M_F_PHY (VSC73XX_MAC_CFG_FDX | \ 98 VSC73XX_MAC_CFG_GIGA_MODE | \ 99 VSC73XX_MAC_CFG_TX_IPG_1000M | \ 100 VSC73XX_MAC_CFG_CLK_SEL_EXT) 101 #define VSC73XX_MAC_CFG_100_10M_F_PHY (VSC73XX_MAC_CFG_FDX | \ 102 VSC73XX_MAC_CFG_TX_IPG_100_10M | \ 103 VSC73XX_MAC_CFG_CLK_SEL_EXT) 104 #define VSC73XX_MAC_CFG_100_10M_H_PHY (VSC73XX_MAC_CFG_TX_IPG_100_10M | \ 105 VSC73XX_MAC_CFG_CLK_SEL_EXT) 106 #define VSC73XX_MAC_CFG_1000M_F_RGMII (VSC73XX_MAC_CFG_FDX | \ 107 VSC73XX_MAC_CFG_GIGA_MODE | \ 108 VSC73XX_MAC_CFG_TX_IPG_1000M | \ 109 VSC73XX_MAC_CFG_CLK_SEL_1000M) 110 #define VSC73XX_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \ 111 VSC73XX_MAC_CFG_MAC_RX_RST | \ 112 VSC73XX_MAC_CFG_MAC_TX_RST) 113 114 /* Flow control register bits */ 115 #define VSC73XX_FCCONF_ZERO_PAUSE_EN BIT(17) 116 #define VSC73XX_FCCONF_FLOW_CTRL_OBEY BIT(16) 117 #define VSC73XX_FCCONF_PAUSE_VAL_MASK GENMASK(15, 0) 118 119 /* ADVPORTM advanced port setup register bits */ 120 #define VSC73XX_ADVPORTM_IFG_PPM BIT(7) 121 #define VSC73XX_ADVPORTM_EXC_COL_CONT BIT(6) 122 #define VSC73XX_ADVPORTM_EXT_PORT BIT(5) 123 #define VSC73XX_ADVPORTM_INV_GTX BIT(4) 124 #define VSC73XX_ADVPORTM_ENA_GTX BIT(3) 125 #define VSC73XX_ADVPORTM_DDR_MODE BIT(2) 126 #define VSC73XX_ADVPORTM_IO_LOOPBACK BIT(1) 127 #define VSC73XX_ADVPORTM_HOST_LOOPBACK BIT(0) 128 129 /* TXUPDCFG transmit modify setup bits */ 130 #define VSC73XX_TXUPDCFG_DSCP_REWR_MODE GENMASK(20, 19) 131 #define VSC73XX_TXUPDCFG_DSCP_REWR_ENA BIT(18) 132 #define VSC73XX_TXUPDCFG_TX_INT_TO_USRPRIO_ENA BIT(17) 133 #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID GENMASK(15, 4) 134 #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA BIT(3) 135 #define VSC73XX_TXUPDCFG_TX_UPDATE_CRC_CPU_ENA BIT(1) 136 #define VSC73XX_TXUPDCFG_TX_INSERT_TAG BIT(0) 137 138 #define VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_SHIFT 4 139 140 /* CAT_DROP categorizer frame dropping register bits */ 141 #define VSC73XX_CAT_DROP_DROP_MC_SMAC_ENA BIT(6) 142 #define VSC73XX_CAT_DROP_FWD_CTRL_ENA BIT(4) 143 #define VSC73XX_CAT_DROP_FWD_PAUSE_ENA BIT(3) 144 #define VSC73XX_CAT_DROP_UNTAGGED_ENA BIT(2) 145 #define VSC73XX_CAT_DROP_TAGGED_ENA BIT(1) 146 #define VSC73XX_CAT_DROP_NULL_MAC_ENA BIT(0) 147 148 #define VSC73XX_Q_MISC_CONF_EXTENT_MEM BIT(31) 149 #define VSC73XX_Q_MISC_CONF_EARLY_TX_MASK GENMASK(4, 1) 150 #define VSC73XX_Q_MISC_CONF_EARLY_TX_512 (1 << 1) 151 #define VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE BIT(0) 152 153 /* CAT_VLAN_MISC categorizer VLAN miscellaneous bits */ 154 #define VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA BIT(8) 155 #define VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA BIT(7) 156 157 /* CAT_PORT_VLAN categorizer port VLAN */ 158 #define VSC73XX_CAT_PORT_VLAN_VLAN_CFI BIT(15) 159 #define VSC73XX_CAT_PORT_VLAN_VLAN_USR_PRIO GENMASK(14, 12) 160 #define VSC73XX_CAT_PORT_VLAN_VLAN_VID GENMASK(11, 0) 161 162 /* Frame analyzer block 2 registers */ 163 #define VSC73XX_STORMLIMIT 0x02 164 #define VSC73XX_ADVLEARN 0x03 165 #define VSC73XX_IFLODMSK 0x04 166 #define VSC73XX_VLANMASK 0x05 167 #define VSC73XX_MACHDATA 0x06 168 #define VSC73XX_MACLDATA 0x07 169 #define VSC73XX_ANMOVED 0x08 170 #define VSC73XX_ANAGEFIL 0x09 171 #define VSC73XX_ANEVENTS 0x0a 172 #define VSC73XX_ANCNTMASK 0x0b 173 #define VSC73XX_ANCNTVAL 0x0c 174 #define VSC73XX_LEARNMASK 0x0d 175 #define VSC73XX_UFLODMASK 0x0e 176 #define VSC73XX_MFLODMASK 0x0f 177 #define VSC73XX_RECVMASK 0x10 178 #define VSC73XX_AGGRCTRL 0x20 179 #define VSC73XX_AGGRMSKS 0x30 /* Until 0x3f */ 180 #define VSC73XX_DSTMASKS 0x40 /* Until 0x7f */ 181 #define VSC73XX_SRCMASKS 0x80 /* Until 0x87 */ 182 #define VSC73XX_CAPENAB 0xa0 183 #define VSC73XX_MACACCESS 0xb0 184 #define VSC73XX_IPMCACCESS 0xb1 185 #define VSC73XX_MACTINDX 0xc0 186 #define VSC73XX_VLANACCESS 0xd0 187 #define VSC73XX_VLANTIDX 0xe0 188 #define VSC73XX_AGENCTRL 0xf0 189 #define VSC73XX_CAPRST 0xff 190 191 #define VSC73XX_SRCMASKS_CPU_COPY BIT(27) 192 #define VSC73XX_SRCMASKS_MIRROR BIT(26) 193 #define VSC73XX_SRCMASKS_PORTS_MASK GENMASK(7, 0) 194 195 #define VSC73XX_MACACCESS_CPU_COPY BIT(14) 196 #define VSC73XX_MACACCESS_FWD_KILL BIT(13) 197 #define VSC73XX_MACACCESS_IGNORE_VLAN BIT(12) 198 #define VSC73XX_MACACCESS_AGED_FLAG BIT(11) 199 #define VSC73XX_MACACCESS_VALID BIT(10) 200 #define VSC73XX_MACACCESS_LOCKED BIT(9) 201 #define VSC73XX_MACACCESS_DEST_IDX_MASK GENMASK(8, 3) 202 #define VSC73XX_MACACCESS_CMD_MASK GENMASK(2, 0) 203 #define VSC73XX_MACACCESS_CMD_IDLE 0 204 #define VSC73XX_MACACCESS_CMD_LEARN 1 205 #define VSC73XX_MACACCESS_CMD_FORGET 2 206 #define VSC73XX_MACACCESS_CMD_AGE_TABLE 3 207 #define VSC73XX_MACACCESS_CMD_FLUSH_TABLE 4 208 #define VSC73XX_MACACCESS_CMD_CLEAR_TABLE 5 209 #define VSC73XX_MACACCESS_CMD_READ_ENTRY 6 210 #define VSC73XX_MACACCESS_CMD_WRITE_ENTRY 7 211 212 #define VSC73XX_VLANACCESS_LEARN_DISABLED BIT(30) 213 #define VSC73XX_VLANACCESS_VLAN_MIRROR BIT(29) 214 #define VSC73XX_VLANACCESS_VLAN_SRC_CHECK BIT(28) 215 #define VSC73XX_VLANACCESS_VLAN_PORT_MASK GENMASK(9, 2) 216 #define VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT 2 217 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK GENMASK(1, 0) 218 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE 0 219 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY 1 220 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY 2 221 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE 3 222 223 /* MII block 3 registers */ 224 #define VSC73XX_MII_STAT 0x0 225 #define VSC73XX_MII_CMD 0x1 226 #define VSC73XX_MII_DATA 0x2 227 228 /* Arbiter block 5 registers */ 229 #define VSC73XX_ARBEMPTY 0x0c 230 #define VSC73XX_ARBDISC 0x0e 231 #define VSC73XX_SBACKWDROP 0x12 232 #define VSC73XX_DBACKWDROP 0x13 233 #define VSC73XX_ARBBURSTPROB 0x15 234 235 /* System block 7 registers */ 236 #define VSC73XX_ICPU_SIPAD 0x01 237 #define VSC73XX_GMIIDELAY 0x05 238 #define VSC73XX_ICPU_CTRL 0x10 239 #define VSC73XX_ICPU_ADDR 0x11 240 #define VSC73XX_ICPU_SRAM 0x12 241 #define VSC73XX_HWSEM 0x13 242 #define VSC73XX_GLORESET 0x14 243 #define VSC73XX_ICPU_MBOX_VAL 0x15 244 #define VSC73XX_ICPU_MBOX_SET 0x16 245 #define VSC73XX_ICPU_MBOX_CLR 0x17 246 #define VSC73XX_CHIPID 0x18 247 #define VSC73XX_GPIO 0x34 248 249 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_NONE 0 250 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_4_NS 1 251 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_7_NS 2 252 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS 3 253 254 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_NONE (0 << 4) 255 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_4_NS (1 << 4) 256 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_7_NS (2 << 4) 257 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS (3 << 4) 258 259 #define VSC73XX_ICPU_CTRL_WATCHDOG_RST BIT(31) 260 #define VSC73XX_ICPU_CTRL_CLK_DIV_MASK GENMASK(12, 8) 261 #define VSC73XX_ICPU_CTRL_SRST_HOLD BIT(7) 262 #define VSC73XX_ICPU_CTRL_ICPU_PI_EN BIT(6) 263 #define VSC73XX_ICPU_CTRL_BOOT_EN BIT(3) 264 #define VSC73XX_ICPU_CTRL_EXT_ACC_EN BIT(2) 265 #define VSC73XX_ICPU_CTRL_CLK_EN BIT(1) 266 #define VSC73XX_ICPU_CTRL_SRST BIT(0) 267 268 #define VSC73XX_CHIPID_ID_SHIFT 12 269 #define VSC73XX_CHIPID_ID_MASK 0xffff 270 #define VSC73XX_CHIPID_REV_SHIFT 28 271 #define VSC73XX_CHIPID_REV_MASK 0xf 272 #define VSC73XX_CHIPID_ID_7385 0x7385 273 #define VSC73XX_CHIPID_ID_7388 0x7388 274 #define VSC73XX_CHIPID_ID_7395 0x7395 275 #define VSC73XX_CHIPID_ID_7398 0x7398 276 277 #define VSC73XX_GLORESET_STROBE BIT(4) 278 #define VSC73XX_GLORESET_ICPU_LOCK BIT(3) 279 #define VSC73XX_GLORESET_MEM_LOCK BIT(2) 280 #define VSC73XX_GLORESET_PHY_RESET BIT(1) 281 #define VSC73XX_GLORESET_MASTER_RESET BIT(0) 282 283 #define VSC7385_CLOCK_DELAY ((3 << 4) | 3) 284 #define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3) 285 286 #define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \ 287 VSC73XX_ICPU_CTRL_BOOT_EN | \ 288 VSC73XX_ICPU_CTRL_EXT_ACC_EN) 289 290 #define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \ 291 VSC73XX_ICPU_CTRL_BOOT_EN | \ 292 VSC73XX_ICPU_CTRL_CLK_EN | \ 293 VSC73XX_ICPU_CTRL_SRST) 294 295 #define IS_7385(a) ((a)->chipid == VSC73XX_CHIPID_ID_7385) 296 #define IS_7388(a) ((a)->chipid == VSC73XX_CHIPID_ID_7388) 297 #define IS_7395(a) ((a)->chipid == VSC73XX_CHIPID_ID_7395) 298 #define IS_7398(a) ((a)->chipid == VSC73XX_CHIPID_ID_7398) 299 #define IS_739X(a) (IS_7395(a) || IS_7398(a)) 300 301 #define VSC73XX_POLL_SLEEP_US 1000 302 #define VSC73XX_POLL_TIMEOUT_US 10000 303 304 struct vsc73xx_counter { 305 u8 counter; 306 const char *name; 307 }; 308 309 /* Counters are named according to the MIB standards where applicable. 310 * Some counters are custom, non-standard. The standard counters are 311 * named in accordance with RFC2819, RFC2021 and IEEE Std 802.3-2002 Annex 312 * 30A Counters. 313 */ 314 static const struct vsc73xx_counter vsc73xx_rx_counters[] = { 315 { 0, "RxEtherStatsPkts" }, 316 { 1, "RxBroadcast+MulticastPkts" }, /* non-standard counter */ 317 { 2, "RxTotalErrorPackets" }, /* non-standard counter */ 318 { 3, "RxEtherStatsBroadcastPkts" }, 319 { 4, "RxEtherStatsMulticastPkts" }, 320 { 5, "RxEtherStatsPkts64Octets" }, 321 { 6, "RxEtherStatsPkts65to127Octets" }, 322 { 7, "RxEtherStatsPkts128to255Octets" }, 323 { 8, "RxEtherStatsPkts256to511Octets" }, 324 { 9, "RxEtherStatsPkts512to1023Octets" }, 325 { 10, "RxEtherStatsPkts1024to1518Octets" }, 326 { 11, "RxJumboFrames" }, /* non-standard counter */ 327 { 12, "RxaPauseMACControlFramesTransmitted" }, 328 { 13, "RxFIFODrops" }, /* non-standard counter */ 329 { 14, "RxBackwardDrops" }, /* non-standard counter */ 330 { 15, "RxClassifierDrops" }, /* non-standard counter */ 331 { 16, "RxEtherStatsCRCAlignErrors" }, 332 { 17, "RxEtherStatsUndersizePkts" }, 333 { 18, "RxEtherStatsOversizePkts" }, 334 { 19, "RxEtherStatsFragments" }, 335 { 20, "RxEtherStatsJabbers" }, 336 { 21, "RxaMACControlFramesReceived" }, 337 /* 22-24 are undefined */ 338 { 25, "RxaFramesReceivedOK" }, 339 { 26, "RxQoSClass0" }, /* non-standard counter */ 340 { 27, "RxQoSClass1" }, /* non-standard counter */ 341 { 28, "RxQoSClass2" }, /* non-standard counter */ 342 { 29, "RxQoSClass3" }, /* non-standard counter */ 343 }; 344 345 static const struct vsc73xx_counter vsc73xx_tx_counters[] = { 346 { 0, "TxEtherStatsPkts" }, 347 { 1, "TxBroadcast+MulticastPkts" }, /* non-standard counter */ 348 { 2, "TxTotalErrorPackets" }, /* non-standard counter */ 349 { 3, "TxEtherStatsBroadcastPkts" }, 350 { 4, "TxEtherStatsMulticastPkts" }, 351 { 5, "TxEtherStatsPkts64Octets" }, 352 { 6, "TxEtherStatsPkts65to127Octets" }, 353 { 7, "TxEtherStatsPkts128to255Octets" }, 354 { 8, "TxEtherStatsPkts256to511Octets" }, 355 { 9, "TxEtherStatsPkts512to1023Octets" }, 356 { 10, "TxEtherStatsPkts1024to1518Octets" }, 357 { 11, "TxJumboFrames" }, /* non-standard counter */ 358 { 12, "TxaPauseMACControlFramesTransmitted" }, 359 { 13, "TxFIFODrops" }, /* non-standard counter */ 360 { 14, "TxDrops" }, /* non-standard counter */ 361 { 15, "TxEtherStatsCollisions" }, 362 { 16, "TxEtherStatsCRCAlignErrors" }, 363 { 17, "TxEtherStatsUndersizePkts" }, 364 { 18, "TxEtherStatsOversizePkts" }, 365 { 19, "TxEtherStatsFragments" }, 366 { 20, "TxEtherStatsJabbers" }, 367 /* 21-24 are undefined */ 368 { 25, "TxaFramesReceivedOK" }, 369 { 26, "TxQoSClass0" }, /* non-standard counter */ 370 { 27, "TxQoSClass1" }, /* non-standard counter */ 371 { 28, "TxQoSClass2" }, /* non-standard counter */ 372 { 29, "TxQoSClass3" }, /* non-standard counter */ 373 }; 374 375 struct vsc73xx_vlan_summary { 376 size_t num_tagged; 377 size_t num_untagged; 378 }; 379 380 enum vsc73xx_port_vlan_conf { 381 VSC73XX_VLAN_FILTER, 382 VSC73XX_VLAN_FILTER_UNTAG_ALL, 383 VSC73XX_VLAN_IGNORE, 384 }; 385 386 int vsc73xx_is_addr_valid(u8 block, u8 subblock) 387 { 388 switch (block) { 389 case VSC73XX_BLOCK_MAC: 390 switch (subblock) { 391 case 0 ... 4: 392 case 6: 393 return 1; 394 } 395 break; 396 397 case VSC73XX_BLOCK_ANALYZER: 398 case VSC73XX_BLOCK_SYSTEM: 399 switch (subblock) { 400 case 0: 401 return 1; 402 } 403 break; 404 405 case VSC73XX_BLOCK_MII: 406 case VSC73XX_BLOCK_CAPTURE: 407 case VSC73XX_BLOCK_ARBITER: 408 switch (subblock) { 409 case 0 ... 1: 410 return 1; 411 } 412 break; 413 } 414 415 return 0; 416 } 417 EXPORT_SYMBOL(vsc73xx_is_addr_valid); 418 419 static int vsc73xx_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, 420 u32 *val) 421 { 422 return vsc->ops->read(vsc, block, subblock, reg, val); 423 } 424 425 static int vsc73xx_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, 426 u32 val) 427 { 428 return vsc->ops->write(vsc, block, subblock, reg, val); 429 } 430 431 static int vsc73xx_update_bits(struct vsc73xx *vsc, u8 block, u8 subblock, 432 u8 reg, u32 mask, u32 val) 433 { 434 u32 tmp, orig; 435 int ret; 436 437 /* Same read-modify-write algorithm as e.g. regmap */ 438 ret = vsc73xx_read(vsc, block, subblock, reg, &orig); 439 if (ret) 440 return ret; 441 tmp = orig & ~mask; 442 tmp |= val & mask; 443 return vsc73xx_write(vsc, block, subblock, reg, tmp); 444 } 445 446 static int vsc73xx_detect(struct vsc73xx *vsc) 447 { 448 bool icpu_si_boot_en; 449 bool icpu_pi_en; 450 u32 val; 451 u32 rev; 452 int ret; 453 u32 id; 454 455 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 456 VSC73XX_ICPU_MBOX_VAL, &val); 457 if (ret) { 458 dev_err(vsc->dev, "unable to read mailbox (%d)\n", ret); 459 return ret; 460 } 461 462 if (val == 0xffffffff) { 463 dev_info(vsc->dev, "chip seems dead.\n"); 464 return -EAGAIN; 465 } 466 467 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 468 VSC73XX_CHIPID, &val); 469 if (ret) { 470 dev_err(vsc->dev, "unable to read chip id (%d)\n", ret); 471 return ret; 472 } 473 474 id = (val >> VSC73XX_CHIPID_ID_SHIFT) & 475 VSC73XX_CHIPID_ID_MASK; 476 switch (id) { 477 case VSC73XX_CHIPID_ID_7385: 478 case VSC73XX_CHIPID_ID_7388: 479 case VSC73XX_CHIPID_ID_7395: 480 case VSC73XX_CHIPID_ID_7398: 481 break; 482 default: 483 dev_err(vsc->dev, "unsupported chip, id=%04x\n", id); 484 return -ENODEV; 485 } 486 487 vsc->chipid = id; 488 rev = (val >> VSC73XX_CHIPID_REV_SHIFT) & 489 VSC73XX_CHIPID_REV_MASK; 490 dev_info(vsc->dev, "VSC%04X (rev: %d) switch found\n", id, rev); 491 492 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 493 VSC73XX_ICPU_CTRL, &val); 494 if (ret) { 495 dev_err(vsc->dev, "unable to read iCPU control\n"); 496 return ret; 497 } 498 499 /* The iCPU can always be used but can boot in different ways. 500 * If it is initially disabled and has no external memory, 501 * we are in control and can do whatever we like, else we 502 * are probably in trouble (we need some way to communicate 503 * with the running firmware) so we bail out for now. 504 */ 505 icpu_pi_en = !!(val & VSC73XX_ICPU_CTRL_ICPU_PI_EN); 506 icpu_si_boot_en = !!(val & VSC73XX_ICPU_CTRL_BOOT_EN); 507 if (icpu_si_boot_en && icpu_pi_en) { 508 dev_err(vsc->dev, 509 "iCPU enabled boots from SI, has external memory\n"); 510 dev_err(vsc->dev, "no idea how to deal with this\n"); 511 return -ENODEV; 512 } 513 if (icpu_si_boot_en && !icpu_pi_en) { 514 dev_err(vsc->dev, 515 "iCPU enabled boots from PI/SI, no external memory\n"); 516 return -EAGAIN; 517 } 518 if (!icpu_si_boot_en && icpu_pi_en) { 519 dev_err(vsc->dev, 520 "iCPU enabled, boots from PI external memory\n"); 521 dev_err(vsc->dev, "no idea how to deal with this\n"); 522 return -ENODEV; 523 } 524 /* !icpu_si_boot_en && !cpu_pi_en */ 525 dev_info(vsc->dev, "iCPU disabled, no external memory\n"); 526 527 return 0; 528 } 529 530 static int vsc73xx_phy_read(struct dsa_switch *ds, int phy, int regnum) 531 { 532 struct vsc73xx *vsc = ds->priv; 533 u32 cmd; 534 u32 val; 535 int ret; 536 537 /* Setting bit 26 means "read" */ 538 cmd = BIT(26) | (phy << 21) | (regnum << 16); 539 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd); 540 if (ret) 541 return ret; 542 msleep(2); 543 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, 0, 2, &val); 544 if (ret) 545 return ret; 546 if (val & BIT(16)) { 547 dev_err(vsc->dev, "reading reg %02x from phy%d failed\n", 548 regnum, phy); 549 return -EIO; 550 } 551 val &= 0xFFFFU; 552 553 dev_dbg(vsc->dev, "read reg %02x from phy%d = %04x\n", 554 regnum, phy, val); 555 556 return val; 557 } 558 559 static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum, 560 u16 val) 561 { 562 struct vsc73xx *vsc = ds->priv; 563 u32 cmd; 564 int ret; 565 566 /* It was found through tedious experiments that this router 567 * chip really hates to have it's PHYs reset. They 568 * never recover if that happens: autonegotiation stops 569 * working after a reset. Just filter out this command. 570 * (Resetting the whole chip is OK.) 571 */ 572 if (regnum == 0 && (val & BIT(15))) { 573 dev_info(vsc->dev, "reset PHY - disallowed\n"); 574 return 0; 575 } 576 577 cmd = (phy << 21) | (regnum << 16); 578 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd); 579 if (ret) 580 return ret; 581 582 dev_dbg(vsc->dev, "write %04x to reg %02x in phy%d\n", 583 val, regnum, phy); 584 return 0; 585 } 586 587 static enum dsa_tag_protocol vsc73xx_get_tag_protocol(struct dsa_switch *ds, 588 int port, 589 enum dsa_tag_protocol mp) 590 { 591 /* The switch internally uses a 8 byte header with length, 592 * source port, tag, LPA and priority. This is supposedly 593 * only accessible when operating the switch using the internal 594 * CPU or with an external CPU mapping the device in, but not 595 * when operating the switch over SPI and putting frames in/out 596 * on port 6 (the CPU port). So far we must assume that we 597 * cannot access the tag. (See "Internal frame header" section 598 * 3.9.1 in the manual.) 599 */ 600 return DSA_TAG_PROTO_VSC73XX_8021Q; 601 } 602 603 static int vsc73xx_wait_for_vlan_table_cmd(struct vsc73xx *vsc) 604 { 605 int ret, err; 606 u32 val; 607 608 ret = read_poll_timeout(vsc73xx_read, err, 609 err < 0 || 610 ((val & VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK) == 611 VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE), 612 VSC73XX_POLL_SLEEP_US, VSC73XX_POLL_TIMEOUT_US, 613 false, vsc, VSC73XX_BLOCK_ANALYZER, 614 0, VSC73XX_VLANACCESS, &val); 615 if (ret) 616 return ret; 617 return err; 618 } 619 620 static int 621 vsc73xx_read_vlan_table_entry(struct vsc73xx *vsc, u16 vid, u8 *portmap) 622 { 623 u32 val; 624 int ret; 625 626 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANTIDX, vid); 627 628 ret = vsc73xx_wait_for_vlan_table_cmd(vsc); 629 if (ret) 630 return ret; 631 632 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS, 633 VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK, 634 VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY); 635 636 ret = vsc73xx_wait_for_vlan_table_cmd(vsc); 637 if (ret) 638 return ret; 639 640 vsc73xx_read(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS, &val); 641 *portmap = (val & VSC73XX_VLANACCESS_VLAN_PORT_MASK) >> 642 VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT; 643 644 return 0; 645 } 646 647 static int 648 vsc73xx_write_vlan_table_entry(struct vsc73xx *vsc, u16 vid, u8 portmap) 649 { 650 int ret; 651 652 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANTIDX, vid); 653 654 ret = vsc73xx_wait_for_vlan_table_cmd(vsc); 655 if (ret) 656 return ret; 657 658 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANACCESS, 659 VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK | 660 VSC73XX_VLANACCESS_VLAN_SRC_CHECK | 661 VSC73XX_VLANACCESS_VLAN_PORT_MASK, 662 VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY | 663 VSC73XX_VLANACCESS_VLAN_SRC_CHECK | 664 (portmap << VSC73XX_VLANACCESS_VLAN_PORT_MASK_SHIFT)); 665 666 return vsc73xx_wait_for_vlan_table_cmd(vsc); 667 } 668 669 static int 670 vsc73xx_update_vlan_table(struct vsc73xx *vsc, int port, u16 vid, bool set) 671 { 672 u8 portmap; 673 int ret; 674 675 ret = vsc73xx_read_vlan_table_entry(vsc, vid, &portmap); 676 if (ret) 677 return ret; 678 679 if (set) 680 portmap |= BIT(port); 681 else 682 portmap &= ~BIT(port); 683 684 return vsc73xx_write_vlan_table_entry(vsc, vid, portmap); 685 } 686 687 static int vsc73xx_configure_rgmii_port_delay(struct dsa_switch *ds) 688 { 689 /* Keep 2.0 ns delay for backward complatibility */ 690 u32 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS; 691 u32 rx_delay = VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS; 692 struct dsa_port *dp = dsa_to_port(ds, CPU_PORT); 693 struct device_node *port_dn = dp->dn; 694 struct vsc73xx *vsc = ds->priv; 695 u32 delay; 696 697 if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay)) { 698 switch (delay) { 699 case 0: 700 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_NONE; 701 break; 702 case 1400: 703 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_4_NS; 704 break; 705 case 1700: 706 tx_delay = VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_7_NS; 707 break; 708 case 2000: 709 break; 710 default: 711 dev_err(vsc->dev, 712 "Unsupported RGMII Transmit Clock Delay\n"); 713 return -EINVAL; 714 } 715 } else { 716 dev_dbg(vsc->dev, 717 "RGMII Transmit Clock Delay isn't configured, set to 2.0 ns\n"); 718 } 719 720 if (!of_property_read_u32(port_dn, "rx-internal-delay-ps", &delay)) { 721 switch (delay) { 722 case 0: 723 rx_delay = VSC73XX_GMIIDELAY_GMII0_RXDELAY_NONE; 724 break; 725 case 1400: 726 rx_delay = VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_4_NS; 727 break; 728 case 1700: 729 rx_delay = VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_7_NS; 730 break; 731 case 2000: 732 break; 733 default: 734 dev_err(vsc->dev, 735 "Unsupported RGMII Receive Clock Delay value\n"); 736 return -EINVAL; 737 } 738 } else { 739 dev_dbg(vsc->dev, 740 "RGMII Receive Clock Delay isn't configured, set to 2.0 ns\n"); 741 } 742 743 /* MII delay, set both GTX and RX delay */ 744 return vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GMIIDELAY, 745 tx_delay | rx_delay); 746 } 747 748 static int vsc73xx_setup(struct dsa_switch *ds) 749 { 750 struct vsc73xx *vsc = ds->priv; 751 int i, ret; 752 753 dev_info(vsc->dev, "set up the switch\n"); 754 755 ds->untag_bridge_pvid = true; 756 ds->max_num_bridges = DSA_TAG_8021Q_MAX_NUM_BRIDGES; 757 758 /* Issue RESET */ 759 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET, 760 VSC73XX_GLORESET_MASTER_RESET); 761 usleep_range(125, 200); 762 763 /* Initialize memory, initialize RAM bank 0..15 except 6 and 7 764 * This sequence appears in the 765 * VSC7385 SparX-G5 datasheet section 6.6.1 766 * VSC7395 SparX-G5e datasheet section 6.6.1 767 * "initialization sequence". 768 * No explanation is given to the 0x1010400 magic number. 769 */ 770 for (i = 0; i <= 15; i++) { 771 if (i != 6 && i != 7) { 772 vsc73xx_write(vsc, VSC73XX_BLOCK_MEMINIT, 773 2, 774 0, 0x1010400 + i); 775 mdelay(1); 776 } 777 } 778 mdelay(30); 779 780 /* Clear MAC table */ 781 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, 782 VSC73XX_MACACCESS, 783 VSC73XX_MACACCESS_CMD_CLEAR_TABLE); 784 785 /* Set VLAN table to default values */ 786 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, 787 VSC73XX_VLANACCESS, 788 VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE); 789 790 msleep(40); 791 792 /* Use 20KiB buffers on all ports on VSC7395 793 * The VSC7385 has 16KiB buffers and that is the 794 * default if we don't set this up explicitly. 795 * Port "31" is "all ports". 796 */ 797 if (IS_739X(vsc)) 798 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 0x1f, 799 VSC73XX_Q_MISC_CONF, 800 VSC73XX_Q_MISC_CONF_EXTENT_MEM); 801 802 /* Put all ports into reset until enabled */ 803 for (i = 0; i < 7; i++) { 804 if (i == 5) 805 continue; 806 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 4, 807 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET); 808 } 809 810 /* Configure RGMII delay */ 811 ret = vsc73xx_configure_rgmii_port_delay(ds); 812 if (ret) 813 return ret; 814 815 /* Ingess VLAN reception mask (table 145) */ 816 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_VLANMASK, 817 0xff); 818 /* IP multicast flood mask (table 144) */ 819 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_IFLODMSK, 820 0xff); 821 822 mdelay(50); 823 824 /* Release reset from the internal PHYs */ 825 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET, 826 VSC73XX_GLORESET_PHY_RESET); 827 828 udelay(4); 829 830 /* Clear VLAN table */ 831 for (i = 0; i < VLAN_N_VID; i++) 832 vsc73xx_write_vlan_table_entry(vsc, i, 0); 833 834 INIT_LIST_HEAD(&vsc->vlans); 835 836 rtnl_lock(); 837 ret = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q)); 838 rtnl_unlock(); 839 840 return ret; 841 } 842 843 static void vsc73xx_teardown(struct dsa_switch *ds) 844 { 845 rtnl_lock(); 846 dsa_tag_8021q_unregister(ds); 847 rtnl_unlock(); 848 } 849 850 static void vsc73xx_init_port(struct vsc73xx *vsc, int port) 851 { 852 u32 val; 853 854 /* MAC configure, first reset the port and then write defaults */ 855 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 856 port, 857 VSC73XX_MAC_CFG, 858 VSC73XX_MAC_CFG_RESET); 859 860 /* Take up the port in 1Gbit mode by default, this will be 861 * augmented after auto-negotiation on the PHY-facing 862 * ports. 863 */ 864 if (port == CPU_PORT) 865 val = VSC73XX_MAC_CFG_1000M_F_RGMII; 866 else 867 val = VSC73XX_MAC_CFG_1000M_F_PHY; 868 869 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 870 port, 871 VSC73XX_MAC_CFG, 872 val | 873 VSC73XX_MAC_CFG_TX_EN | 874 VSC73XX_MAC_CFG_RX_EN); 875 876 /* Flow control for the CPU port: 877 * Use a zero delay pause frame when pause condition is left 878 * Obey pause control frames 879 */ 880 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 881 port, 882 VSC73XX_FCCONF, 883 VSC73XX_FCCONF_ZERO_PAUSE_EN | 884 VSC73XX_FCCONF_FLOW_CTRL_OBEY); 885 886 /* Issue pause control frames on PHY facing ports. 887 * Allow early initiation of MAC transmission if the amount 888 * of egress data is below 512 bytes on CPU port. 889 * FIXME: enable 20KiB buffers? 890 */ 891 if (port == CPU_PORT) 892 val = VSC73XX_Q_MISC_CONF_EARLY_TX_512; 893 else 894 val = VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE; 895 val |= VSC73XX_Q_MISC_CONF_EXTENT_MEM; 896 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 897 port, 898 VSC73XX_Q_MISC_CONF, 899 val); 900 901 /* Flow control MAC: a MAC address used in flow control frames */ 902 val = (vsc->addr[5] << 16) | (vsc->addr[4] << 8) | (vsc->addr[3]); 903 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 904 port, 905 VSC73XX_FCMACHI, 906 val); 907 val = (vsc->addr[2] << 16) | (vsc->addr[1] << 8) | (vsc->addr[0]); 908 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 909 port, 910 VSC73XX_FCMACLO, 911 val); 912 913 /* Tell the categorizer to forward pause frames, not control 914 * frame. Do not drop anything. 915 */ 916 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 917 port, 918 VSC73XX_CAT_DROP, 919 VSC73XX_CAT_DROP_FWD_PAUSE_ENA); 920 921 /* Clear all counters */ 922 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 923 port, VSC73XX_C_RX0, 0); 924 } 925 926 static void vsc73xx_reset_port(struct vsc73xx *vsc, int port, u32 initval) 927 { 928 int ret, err; 929 u32 val; 930 931 /* Disable RX on this port */ 932 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 933 VSC73XX_MAC_CFG, 934 VSC73XX_MAC_CFG_RX_EN, 0); 935 936 /* Discard packets */ 937 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 938 VSC73XX_ARBDISC, BIT(port), BIT(port)); 939 940 /* Wait until queue is empty */ 941 ret = read_poll_timeout(vsc73xx_read, err, 942 err < 0 || (val & BIT(port)), 943 VSC73XX_POLL_SLEEP_US, 944 VSC73XX_POLL_TIMEOUT_US, false, 945 vsc, VSC73XX_BLOCK_ARBITER, 0, 946 VSC73XX_ARBEMPTY, &val); 947 if (ret) 948 dev_err(vsc->dev, 949 "timeout waiting for block arbiter\n"); 950 else if (err < 0) 951 dev_err(vsc->dev, "error reading arbiter\n"); 952 953 /* Put this port into reset */ 954 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, 955 VSC73XX_MAC_CFG_RESET | initval); 956 } 957 958 static void vsc73xx_mac_config(struct phylink_config *config, unsigned int mode, 959 const struct phylink_link_state *state) 960 { 961 struct dsa_port *dp = dsa_phylink_to_port(config); 962 struct vsc73xx *vsc = dp->ds->priv; 963 int port = dp->index; 964 965 /* Special handling of the CPU-facing port */ 966 if (port == CPU_PORT) { 967 /* Other ports are already initialized but not this one */ 968 vsc73xx_init_port(vsc, CPU_PORT); 969 /* Select the external port for this interface (EXT_PORT) 970 * Enable the GMII GTX external clock 971 * Use double data rate (DDR mode) 972 */ 973 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 974 CPU_PORT, 975 VSC73XX_ADVPORTM, 976 VSC73XX_ADVPORTM_EXT_PORT | 977 VSC73XX_ADVPORTM_ENA_GTX | 978 VSC73XX_ADVPORTM_DDR_MODE); 979 } 980 } 981 982 static void vsc73xx_mac_link_down(struct phylink_config *config, 983 unsigned int mode, phy_interface_t interface) 984 { 985 struct dsa_port *dp = dsa_phylink_to_port(config); 986 struct vsc73xx *vsc = dp->ds->priv; 987 int port = dp->index; 988 989 /* This routine is described in the datasheet (below ARBDISC register 990 * description) 991 */ 992 vsc73xx_reset_port(vsc, port, 0); 993 994 /* Allow backward dropping of frames from this port */ 995 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 996 VSC73XX_SBACKWDROP, BIT(port), BIT(port)); 997 } 998 999 static void vsc73xx_mac_link_up(struct phylink_config *config, 1000 struct phy_device *phy, unsigned int mode, 1001 phy_interface_t interface, int speed, 1002 int duplex, bool tx_pause, bool rx_pause) 1003 { 1004 struct dsa_port *dp = dsa_phylink_to_port(config); 1005 struct vsc73xx *vsc = dp->ds->priv; 1006 int port = dp->index; 1007 u32 val; 1008 u8 seed; 1009 1010 if (speed == SPEED_1000) 1011 val = VSC73XX_MAC_CFG_GIGA_MODE | VSC73XX_MAC_CFG_TX_IPG_1000M; 1012 else 1013 val = VSC73XX_MAC_CFG_TX_IPG_100_10M; 1014 1015 if (phy_interface_mode_is_rgmii(interface)) 1016 val |= VSC73XX_MAC_CFG_CLK_SEL_1000M; 1017 else 1018 val |= VSC73XX_MAC_CFG_CLK_SEL_EXT; 1019 1020 if (duplex == DUPLEX_FULL) 1021 val |= VSC73XX_MAC_CFG_FDX; 1022 1023 /* This routine is described in the datasheet (below ARBDISC register 1024 * description) 1025 */ 1026 vsc73xx_reset_port(vsc, port, val); 1027 1028 /* Seed the port randomness with randomness */ 1029 get_random_bytes(&seed, 1); 1030 val |= seed << VSC73XX_MAC_CFG_SEED_OFFSET; 1031 val |= VSC73XX_MAC_CFG_SEED_LOAD; 1032 val |= VSC73XX_MAC_CFG_WEXC_DIS; 1033 1034 /* Those bits are responsible for MTU only. Kernel takes care about MTU, 1035 * let's enable +8 bytes frame length unconditionally. 1036 */ 1037 val |= VSC73XX_MAC_CFG_VLAN_AWR | VSC73XX_MAC_CFG_VLAN_DBLAWR; 1038 1039 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val); 1040 1041 /* Flow control for the PHY facing ports: 1042 * Use a zero delay pause frame when pause condition is left 1043 * Obey pause control frames 1044 * When generating pause frames, use 0xff as pause value 1045 */ 1046 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_FCCONF, 1047 VSC73XX_FCCONF_ZERO_PAUSE_EN | 1048 VSC73XX_FCCONF_FLOW_CTRL_OBEY | 1049 0xff); 1050 1051 /* Accept packets again */ 1052 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 1053 VSC73XX_ARBDISC, BIT(port), 0); 1054 1055 /* Disallow backward dropping of frames from this port */ 1056 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 1057 VSC73XX_SBACKWDROP, BIT(port), 0); 1058 1059 /* Enable TX, RX, deassert reset, stop loading seed */ 1060 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1061 VSC73XX_MAC_CFG, 1062 VSC73XX_MAC_CFG_RESET | VSC73XX_MAC_CFG_SEED_LOAD | 1063 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN, 1064 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN); 1065 } 1066 1067 static bool vsc73xx_tag_8021q_active(struct dsa_port *dp) 1068 { 1069 return !dsa_port_is_vlan_filtering(dp); 1070 } 1071 1072 static struct vsc73xx_bridge_vlan * 1073 vsc73xx_bridge_vlan_find(struct vsc73xx *vsc, u16 vid) 1074 { 1075 struct vsc73xx_bridge_vlan *vlan; 1076 1077 list_for_each_entry(vlan, &vsc->vlans, list) 1078 if (vlan->vid == vid) 1079 return vlan; 1080 1081 return NULL; 1082 } 1083 1084 static void 1085 vsc73xx_bridge_vlan_remove_port(struct vsc73xx_bridge_vlan *vsc73xx_vlan, 1086 int port) 1087 { 1088 vsc73xx_vlan->portmask &= ~BIT(port); 1089 1090 if (vsc73xx_vlan->portmask) 1091 return; 1092 1093 list_del(&vsc73xx_vlan->list); 1094 kfree(vsc73xx_vlan); 1095 } 1096 1097 static void vsc73xx_bridge_vlan_summary(struct vsc73xx *vsc, int port, 1098 struct vsc73xx_vlan_summary *summary, 1099 u16 ignored_vid) 1100 { 1101 size_t num_tagged = 0, num_untagged = 0; 1102 struct vsc73xx_bridge_vlan *vlan; 1103 1104 list_for_each_entry(vlan, &vsc->vlans, list) { 1105 if (!(vlan->portmask & BIT(port)) || vlan->vid == ignored_vid) 1106 continue; 1107 1108 if (vlan->untagged & BIT(port)) 1109 num_untagged++; 1110 else 1111 num_tagged++; 1112 } 1113 1114 summary->num_untagged = num_untagged; 1115 summary->num_tagged = num_tagged; 1116 } 1117 1118 static u16 vsc73xx_find_first_vlan_untagged(struct vsc73xx *vsc, int port) 1119 { 1120 struct vsc73xx_bridge_vlan *vlan; 1121 1122 list_for_each_entry(vlan, &vsc->vlans, list) 1123 if ((vlan->portmask & BIT(port)) && 1124 (vlan->untagged & BIT(port))) 1125 return vlan->vid; 1126 1127 return VLAN_N_VID; 1128 } 1129 1130 static int vsc73xx_set_vlan_conf(struct vsc73xx *vsc, int port, 1131 enum vsc73xx_port_vlan_conf port_vlan_conf) 1132 { 1133 u32 val = 0; 1134 int ret; 1135 1136 if (port_vlan_conf == VSC73XX_VLAN_IGNORE) 1137 val = VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA | 1138 VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA; 1139 1140 ret = vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1141 VSC73XX_CAT_VLAN_MISC, 1142 VSC73XX_CAT_VLAN_MISC_VLAN_TCI_IGNORE_ENA | 1143 VSC73XX_CAT_VLAN_MISC_VLAN_KEEP_TAG_ENA, val); 1144 if (ret) 1145 return ret; 1146 1147 val = (port_vlan_conf == VSC73XX_VLAN_FILTER) ? 1148 VSC73XX_TXUPDCFG_TX_INSERT_TAG : 0; 1149 1150 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1151 VSC73XX_TXUPDCFG, 1152 VSC73XX_TXUPDCFG_TX_INSERT_TAG, val); 1153 } 1154 1155 /** 1156 * vsc73xx_vlan_commit_conf - Update VLAN configuration of a port 1157 * @vsc: Switch private data structure 1158 * @port: Port index on which to operate 1159 * 1160 * Update the VLAN behavior of a port to make sure that when it is under 1161 * a VLAN filtering bridge, the port is either filtering with tag 1162 * preservation, or filtering with all VLANs egress-untagged. Otherwise, 1163 * the port ignores VLAN tags from packets and applies the port-based 1164 * VID. 1165 * 1166 * Must be called when changes are made to: 1167 * - the bridge VLAN filtering state of the port 1168 * - the number or attributes of VLANs from the bridge VLAN table, 1169 * while the port is currently VLAN-aware 1170 * 1171 * Return: 0 on success, or negative errno on error. 1172 */ 1173 static int vsc73xx_vlan_commit_conf(struct vsc73xx *vsc, int port) 1174 { 1175 enum vsc73xx_port_vlan_conf port_vlan_conf = VSC73XX_VLAN_IGNORE; 1176 struct dsa_port *dp = dsa_to_port(vsc->ds, port); 1177 1178 if (port == CPU_PORT) { 1179 port_vlan_conf = VSC73XX_VLAN_FILTER; 1180 } else if (dsa_port_is_vlan_filtering(dp)) { 1181 struct vsc73xx_vlan_summary summary; 1182 1183 port_vlan_conf = VSC73XX_VLAN_FILTER; 1184 1185 vsc73xx_bridge_vlan_summary(vsc, port, &summary, VLAN_N_VID); 1186 if (summary.num_tagged == 0) 1187 port_vlan_conf = VSC73XX_VLAN_FILTER_UNTAG_ALL; 1188 } 1189 1190 return vsc73xx_set_vlan_conf(vsc, port, port_vlan_conf); 1191 } 1192 1193 static int 1194 vsc73xx_vlan_change_untagged(struct vsc73xx *vsc, int port, u16 vid, bool set) 1195 { 1196 u32 val = 0; 1197 1198 if (set) 1199 val = VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA | 1200 ((vid << VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_SHIFT) & 1201 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID); 1202 1203 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1204 VSC73XX_TXUPDCFG, 1205 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID_ENA | 1206 VSC73XX_TXUPDCFG_TX_UNTAGGED_VID, val); 1207 } 1208 1209 /** 1210 * vsc73xx_vlan_commit_untagged - Update native VLAN of a port 1211 * @vsc: Switch private data structure 1212 * @port: Port index on which to operate 1213 * 1214 * Update the native VLAN of a port (the one VLAN which is transmitted 1215 * as egress-tagged on a trunk port) when port is in VLAN filtering mode and 1216 * only one untagged vid is configured. 1217 * In other cases no need to configure it because switch can untag all vlans on 1218 * the port. 1219 * 1220 * Return: 0 on success, or negative errno on error. 1221 */ 1222 static int vsc73xx_vlan_commit_untagged(struct vsc73xx *vsc, int port) 1223 { 1224 struct dsa_port *dp = dsa_to_port(vsc->ds, port); 1225 struct vsc73xx_vlan_summary summary; 1226 u16 vid = 0; 1227 bool valid; 1228 1229 if (!dsa_port_is_vlan_filtering(dp)) 1230 /* Port is configured to untag all vlans in that case. 1231 * No need to commit untagged config change. 1232 */ 1233 return 0; 1234 1235 vsc73xx_bridge_vlan_summary(vsc, port, &summary, VLAN_N_VID); 1236 1237 if (summary.num_untagged > 1) 1238 /* Port must untag all vlans in that case. 1239 * No need to commit untagged config change. 1240 */ 1241 return 0; 1242 1243 valid = (summary.num_untagged == 1); 1244 if (valid) 1245 vid = vsc73xx_find_first_vlan_untagged(vsc, port); 1246 1247 return vsc73xx_vlan_change_untagged(vsc, port, vid, valid); 1248 } 1249 1250 static int 1251 vsc73xx_vlan_change_pvid(struct vsc73xx *vsc, int port, u16 vid, bool set) 1252 { 1253 u32 val = 0; 1254 int ret; 1255 1256 val = set ? 0 : VSC73XX_CAT_DROP_UNTAGGED_ENA; 1257 1258 ret = vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1259 VSC73XX_CAT_DROP, 1260 VSC73XX_CAT_DROP_UNTAGGED_ENA, val); 1261 if (!set || ret) 1262 return ret; 1263 1264 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 1265 VSC73XX_CAT_PORT_VLAN, 1266 VSC73XX_CAT_PORT_VLAN_VLAN_VID, 1267 vid & VSC73XX_CAT_PORT_VLAN_VLAN_VID); 1268 } 1269 1270 /** 1271 * vsc73xx_vlan_commit_pvid - Update port-based default VLAN of a port 1272 * @vsc: Switch private data structure 1273 * @port: Port index on which to operate 1274 * 1275 * Update the PVID of a port so that it follows either the bridge PVID 1276 * configuration, when the bridge is currently VLAN-aware, or the PVID 1277 * from tag_8021q, when the port is standalone or under a VLAN-unaware 1278 * bridge. A port with no PVID drops all untagged and VID 0 tagged 1279 * traffic. 1280 * 1281 * Must be called when changes are made to: 1282 * - the bridge VLAN filtering state of the port 1283 * - the number or attributes of VLANs from the bridge VLAN table, 1284 * while the port is currently VLAN-aware 1285 * 1286 * Return: 0 on success, or negative errno on error. 1287 */ 1288 static int vsc73xx_vlan_commit_pvid(struct vsc73xx *vsc, int port) 1289 { 1290 struct vsc73xx_portinfo *portinfo = &vsc->portinfo[port]; 1291 bool valid = portinfo->pvid_tag_8021q_configured; 1292 struct dsa_port *dp = dsa_to_port(vsc->ds, port); 1293 u16 vid = portinfo->pvid_tag_8021q; 1294 1295 if (dsa_port_is_vlan_filtering(dp)) { 1296 vid = portinfo->pvid_vlan_filtering; 1297 valid = portinfo->pvid_vlan_filtering_configured; 1298 } 1299 1300 return vsc73xx_vlan_change_pvid(vsc, port, vid, valid); 1301 } 1302 1303 static int vsc73xx_vlan_commit_settings(struct vsc73xx *vsc, int port) 1304 { 1305 int ret; 1306 1307 ret = vsc73xx_vlan_commit_untagged(vsc, port); 1308 if (ret) 1309 return ret; 1310 1311 ret = vsc73xx_vlan_commit_pvid(vsc, port); 1312 if (ret) 1313 return ret; 1314 1315 return vsc73xx_vlan_commit_conf(vsc, port); 1316 } 1317 1318 static int vsc73xx_port_enable(struct dsa_switch *ds, int port, 1319 struct phy_device *phy) 1320 { 1321 struct vsc73xx *vsc = ds->priv; 1322 1323 dev_info(vsc->dev, "enable port %d\n", port); 1324 vsc73xx_init_port(vsc, port); 1325 1326 return vsc73xx_vlan_commit_settings(vsc, port); 1327 } 1328 1329 static void vsc73xx_port_disable(struct dsa_switch *ds, int port) 1330 { 1331 struct vsc73xx *vsc = ds->priv; 1332 1333 /* Just put the port into reset */ 1334 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, 1335 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET); 1336 } 1337 1338 static const struct vsc73xx_counter * 1339 vsc73xx_find_counter(struct vsc73xx *vsc, 1340 u8 counter, 1341 bool tx) 1342 { 1343 const struct vsc73xx_counter *cnts; 1344 int num_cnts; 1345 int i; 1346 1347 if (tx) { 1348 cnts = vsc73xx_tx_counters; 1349 num_cnts = ARRAY_SIZE(vsc73xx_tx_counters); 1350 } else { 1351 cnts = vsc73xx_rx_counters; 1352 num_cnts = ARRAY_SIZE(vsc73xx_rx_counters); 1353 } 1354 1355 for (i = 0; i < num_cnts; i++) { 1356 const struct vsc73xx_counter *cnt; 1357 1358 cnt = &cnts[i]; 1359 if (cnt->counter == counter) 1360 return cnt; 1361 } 1362 1363 return NULL; 1364 } 1365 1366 static void vsc73xx_get_strings(struct dsa_switch *ds, int port, u32 stringset, 1367 uint8_t *data) 1368 { 1369 const struct vsc73xx_counter *cnt; 1370 struct vsc73xx *vsc = ds->priv; 1371 u8 indices[6]; 1372 u8 *buf = data; 1373 int i; 1374 u32 val; 1375 int ret; 1376 1377 if (stringset != ETH_SS_STATS) 1378 return; 1379 1380 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port, 1381 VSC73XX_C_CFG, &val); 1382 if (ret) 1383 return; 1384 1385 indices[0] = (val & 0x1f); /* RX counter 0 */ 1386 indices[1] = ((val >> 5) & 0x1f); /* RX counter 1 */ 1387 indices[2] = ((val >> 10) & 0x1f); /* RX counter 2 */ 1388 indices[3] = ((val >> 16) & 0x1f); /* TX counter 0 */ 1389 indices[4] = ((val >> 21) & 0x1f); /* TX counter 1 */ 1390 indices[5] = ((val >> 26) & 0x1f); /* TX counter 2 */ 1391 1392 /* The first counters is the RX octets */ 1393 ethtool_puts(&buf, "RxEtherStatsOctets"); 1394 1395 /* Each port supports recording 3 RX counters and 3 TX counters, 1396 * figure out what counters we use in this set-up and return the 1397 * names of them. The hardware default counters will be number of 1398 * packets on RX/TX, combined broadcast+multicast packets RX/TX and 1399 * total error packets RX/TX. 1400 */ 1401 for (i = 0; i < 3; i++) { 1402 cnt = vsc73xx_find_counter(vsc, indices[i], false); 1403 ethtool_puts(&buf, cnt ? cnt->name : ""); 1404 } 1405 1406 /* TX stats begins with the number of TX octets */ 1407 ethtool_puts(&buf, "TxEtherStatsOctets"); 1408 1409 for (i = 3; i < 6; i++) { 1410 cnt = vsc73xx_find_counter(vsc, indices[i], true); 1411 ethtool_puts(&buf, cnt ? cnt->name : ""); 1412 1413 } 1414 } 1415 1416 static int vsc73xx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1417 { 1418 /* We only support SS_STATS */ 1419 if (sset != ETH_SS_STATS) 1420 return 0; 1421 /* RX and TX packets, then 3 RX counters, 3 TX counters */ 1422 return 8; 1423 } 1424 1425 static void vsc73xx_get_ethtool_stats(struct dsa_switch *ds, int port, 1426 uint64_t *data) 1427 { 1428 struct vsc73xx *vsc = ds->priv; 1429 u8 regs[] = { 1430 VSC73XX_RXOCT, 1431 VSC73XX_C_RX0, 1432 VSC73XX_C_RX1, 1433 VSC73XX_C_RX2, 1434 VSC73XX_TXOCT, 1435 VSC73XX_C_TX0, 1436 VSC73XX_C_TX1, 1437 VSC73XX_C_TX2, 1438 }; 1439 u32 val; 1440 int ret; 1441 int i; 1442 1443 for (i = 0; i < ARRAY_SIZE(regs); i++) { 1444 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port, 1445 regs[i], &val); 1446 if (ret) { 1447 dev_err(vsc->dev, "error reading counter %d\n", i); 1448 return; 1449 } 1450 data[i] = val; 1451 } 1452 } 1453 1454 static int vsc73xx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1455 { 1456 struct vsc73xx *vsc = ds->priv; 1457 1458 return vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, 1459 VSC73XX_MAXLEN, new_mtu + ETH_HLEN + ETH_FCS_LEN); 1460 } 1461 1462 /* According to application not "VSC7398 Jumbo Frames" setting 1463 * up the frame size to 9.6 KB does not affect the performance on standard 1464 * frames. It is clear from the application note that 1465 * "9.6 kilobytes" == 9600 bytes. 1466 */ 1467 static int vsc73xx_get_max_mtu(struct dsa_switch *ds, int port) 1468 { 1469 return 9600 - ETH_HLEN - ETH_FCS_LEN; 1470 } 1471 1472 static void vsc73xx_phylink_get_caps(struct dsa_switch *dsa, int port, 1473 struct phylink_config *config) 1474 { 1475 unsigned long *interfaces = config->supported_interfaces; 1476 1477 if (port == 5) 1478 return; 1479 1480 if (port == CPU_PORT) { 1481 __set_bit(PHY_INTERFACE_MODE_MII, interfaces); 1482 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces); 1483 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces); 1484 __set_bit(PHY_INTERFACE_MODE_RGMII, interfaces); 1485 } 1486 1487 if (port <= 4) { 1488 /* Internal PHYs */ 1489 __set_bit(PHY_INTERFACE_MODE_INTERNAL, interfaces); 1490 /* phylib default */ 1491 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces); 1492 } 1493 1494 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000; 1495 } 1496 1497 static int 1498 vsc73xx_port_vlan_filtering(struct dsa_switch *ds, int port, 1499 bool vlan_filtering, struct netlink_ext_ack *extack) 1500 { 1501 struct vsc73xx *vsc = ds->priv; 1502 1503 /* The commit to hardware processed below is required because vsc73xx 1504 * is using tag_8021q. When vlan_filtering is disabled, tag_8021q uses 1505 * pvid/untagged vlans for port recognition. The values configured for 1506 * vlans and pvid/untagged states are stored in portinfo structure. 1507 * When vlan_filtering is enabled, we need to restore pvid/untagged from 1508 * portinfo structure. Analogous routine is processed when 1509 * vlan_filtering is disabled, but values used for tag_8021q are 1510 * restored. 1511 */ 1512 1513 return vsc73xx_vlan_commit_settings(vsc, port); 1514 } 1515 1516 static int vsc73xx_port_vlan_add(struct dsa_switch *ds, int port, 1517 const struct switchdev_obj_port_vlan *vlan, 1518 struct netlink_ext_ack *extack) 1519 { 1520 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1521 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1522 struct dsa_port *dp = dsa_to_port(ds, port); 1523 struct vsc73xx_bridge_vlan *vsc73xx_vlan; 1524 struct vsc73xx_vlan_summary summary; 1525 struct vsc73xx_portinfo *portinfo; 1526 struct vsc73xx *vsc = ds->priv; 1527 bool commit_to_hardware; 1528 int ret = 0; 1529 1530 /* Be sure to deny alterations to the configuration done by tag_8021q. 1531 */ 1532 if (vid_is_dsa_8021q(vlan->vid)) { 1533 NL_SET_ERR_MSG_MOD(extack, 1534 "Range 3072-4095 reserved for dsa_8021q operation"); 1535 return -EBUSY; 1536 } 1537 1538 /* The processed vlan->vid is excluded from the search because the VLAN 1539 * can be re-added with a different set of flags, so it's easiest to 1540 * ignore its old flags from the VLAN database software copy. 1541 */ 1542 vsc73xx_bridge_vlan_summary(vsc, port, &summary, vlan->vid); 1543 1544 /* VSC73XX allows only three untagged states: none, one or all */ 1545 if ((untagged && summary.num_tagged > 0 && summary.num_untagged > 0) || 1546 (!untagged && summary.num_untagged > 1)) { 1547 NL_SET_ERR_MSG_MOD(extack, 1548 "Port can have only none, one or all untagged vlan"); 1549 return -EBUSY; 1550 } 1551 1552 vsc73xx_vlan = vsc73xx_bridge_vlan_find(vsc, vlan->vid); 1553 1554 if (!vsc73xx_vlan) { 1555 vsc73xx_vlan = kzalloc(sizeof(*vsc73xx_vlan), GFP_KERNEL); 1556 if (!vsc73xx_vlan) 1557 return -ENOMEM; 1558 1559 vsc73xx_vlan->vid = vlan->vid; 1560 1561 list_add_tail(&vsc73xx_vlan->list, &vsc->vlans); 1562 } 1563 1564 vsc73xx_vlan->portmask |= BIT(port); 1565 1566 /* CPU port must be always tagged because source port identification is 1567 * based on tag_8021q. 1568 */ 1569 if (port == CPU_PORT) 1570 goto update_vlan_table; 1571 1572 if (untagged) 1573 vsc73xx_vlan->untagged |= BIT(port); 1574 else 1575 vsc73xx_vlan->untagged &= ~BIT(port); 1576 1577 portinfo = &vsc->portinfo[port]; 1578 1579 if (pvid) { 1580 portinfo->pvid_vlan_filtering_configured = true; 1581 portinfo->pvid_vlan_filtering = vlan->vid; 1582 } else if (portinfo->pvid_vlan_filtering_configured && 1583 portinfo->pvid_vlan_filtering == vlan->vid) { 1584 portinfo->pvid_vlan_filtering_configured = false; 1585 } 1586 1587 commit_to_hardware = !vsc73xx_tag_8021q_active(dp); 1588 if (commit_to_hardware) { 1589 ret = vsc73xx_vlan_commit_settings(vsc, port); 1590 if (ret) 1591 goto err; 1592 } 1593 1594 update_vlan_table: 1595 ret = vsc73xx_update_vlan_table(vsc, port, vlan->vid, true); 1596 if (!ret) 1597 return 0; 1598 err: 1599 vsc73xx_bridge_vlan_remove_port(vsc73xx_vlan, port); 1600 return ret; 1601 } 1602 1603 static int vsc73xx_port_vlan_del(struct dsa_switch *ds, int port, 1604 const struct switchdev_obj_port_vlan *vlan) 1605 { 1606 struct vsc73xx_bridge_vlan *vsc73xx_vlan; 1607 struct vsc73xx_portinfo *portinfo; 1608 struct vsc73xx *vsc = ds->priv; 1609 bool commit_to_hardware; 1610 int ret; 1611 1612 ret = vsc73xx_update_vlan_table(vsc, port, vlan->vid, false); 1613 if (ret) 1614 return ret; 1615 1616 portinfo = &vsc->portinfo[port]; 1617 1618 if (portinfo->pvid_vlan_filtering_configured && 1619 portinfo->pvid_vlan_filtering == vlan->vid) 1620 portinfo->pvid_vlan_filtering_configured = false; 1621 1622 vsc73xx_vlan = vsc73xx_bridge_vlan_find(vsc, vlan->vid); 1623 1624 if (vsc73xx_vlan) 1625 vsc73xx_bridge_vlan_remove_port(vsc73xx_vlan, port); 1626 1627 commit_to_hardware = !vsc73xx_tag_8021q_active(dsa_to_port(ds, port)); 1628 1629 if (commit_to_hardware) 1630 return vsc73xx_vlan_commit_settings(vsc, port); 1631 1632 return 0; 1633 } 1634 1635 static int vsc73xx_tag_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid, 1636 u16 flags) 1637 { 1638 bool pvid = flags & BRIDGE_VLAN_INFO_PVID; 1639 struct vsc73xx_portinfo *portinfo; 1640 struct vsc73xx *vsc = ds->priv; 1641 bool commit_to_hardware; 1642 int ret; 1643 1644 portinfo = &vsc->portinfo[port]; 1645 1646 if (pvid) { 1647 portinfo->pvid_tag_8021q_configured = true; 1648 portinfo->pvid_tag_8021q = vid; 1649 } 1650 1651 commit_to_hardware = vsc73xx_tag_8021q_active(dsa_to_port(ds, port)); 1652 if (commit_to_hardware) { 1653 ret = vsc73xx_vlan_commit_settings(vsc, port); 1654 if (ret) 1655 return ret; 1656 } 1657 1658 return vsc73xx_update_vlan_table(vsc, port, vid, true); 1659 } 1660 1661 static int vsc73xx_tag_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid) 1662 { 1663 struct vsc73xx_portinfo *portinfo; 1664 struct vsc73xx *vsc = ds->priv; 1665 1666 portinfo = &vsc->portinfo[port]; 1667 1668 if (portinfo->pvid_tag_8021q_configured && 1669 portinfo->pvid_tag_8021q == vid) { 1670 struct dsa_port *dp = dsa_to_port(ds, port); 1671 bool commit_to_hardware; 1672 int err; 1673 1674 portinfo->pvid_tag_8021q_configured = false; 1675 1676 commit_to_hardware = vsc73xx_tag_8021q_active(dp); 1677 if (commit_to_hardware) { 1678 err = vsc73xx_vlan_commit_settings(vsc, port); 1679 if (err) 1680 return err; 1681 } 1682 } 1683 1684 return vsc73xx_update_vlan_table(vsc, port, vid, false); 1685 } 1686 1687 static int vsc73xx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1688 struct switchdev_brport_flags flags, 1689 struct netlink_ext_ack *extack) 1690 { 1691 if (flags.mask & ~BR_LEARNING) 1692 return -EINVAL; 1693 1694 return 0; 1695 } 1696 1697 static int vsc73xx_port_bridge_flags(struct dsa_switch *ds, int port, 1698 struct switchdev_brport_flags flags, 1699 struct netlink_ext_ack *extack) 1700 { 1701 if (flags.mask & BR_LEARNING) { 1702 u32 val = flags.val & BR_LEARNING ? BIT(port) : 0; 1703 struct vsc73xx *vsc = ds->priv; 1704 1705 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1706 VSC73XX_LEARNMASK, BIT(port), val); 1707 } 1708 1709 return 0; 1710 } 1711 1712 static void vsc73xx_refresh_fwd_map(struct dsa_switch *ds, int port, u8 state) 1713 { 1714 struct dsa_port *other_dp, *dp = dsa_to_port(ds, port); 1715 struct vsc73xx *vsc = ds->priv; 1716 u16 mask; 1717 1718 if (state != BR_STATE_FORWARDING) { 1719 /* Ports that aren't in the forwarding state must not 1720 * forward packets anywhere. 1721 */ 1722 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1723 VSC73XX_SRCMASKS + port, 1724 VSC73XX_SRCMASKS_PORTS_MASK, 0); 1725 1726 dsa_switch_for_each_available_port(other_dp, ds) { 1727 if (other_dp == dp) 1728 continue; 1729 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1730 VSC73XX_SRCMASKS + other_dp->index, 1731 BIT(port), 0); 1732 } 1733 1734 return; 1735 } 1736 1737 /* Forwarding ports must forward to the CPU and to other ports 1738 * in the same bridge 1739 */ 1740 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1741 VSC73XX_SRCMASKS + CPU_PORT, BIT(port), BIT(port)); 1742 1743 mask = BIT(CPU_PORT); 1744 1745 dsa_switch_for_each_user_port(other_dp, ds) { 1746 int other_port = other_dp->index; 1747 1748 if (port == other_port || !dsa_port_bridge_same(dp, other_dp) || 1749 other_dp->stp_state != BR_STATE_FORWARDING) 1750 continue; 1751 1752 mask |= BIT(other_port); 1753 1754 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1755 VSC73XX_SRCMASKS + other_port, 1756 BIT(port), BIT(port)); 1757 } 1758 1759 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1760 VSC73XX_SRCMASKS + port, 1761 VSC73XX_SRCMASKS_PORTS_MASK, mask); 1762 } 1763 1764 /* FIXME: STP frames aren't forwarded at this moment. BPDU frames are 1765 * forwarded only from and to PI/SI interface. For more info see chapter 1766 * 2.7.1 (CPU Forwarding) in datasheet. 1767 * This function is required for tag_8021q operations. 1768 */ 1769 static void vsc73xx_port_stp_state_set(struct dsa_switch *ds, int port, 1770 u8 state) 1771 { 1772 struct dsa_port *dp = dsa_to_port(ds, port); 1773 struct vsc73xx *vsc = ds->priv; 1774 u32 val = 0; 1775 1776 if (state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) 1777 val = dp->learning ? BIT(port) : 0; 1778 1779 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1780 VSC73XX_LEARNMASK, BIT(port), val); 1781 1782 val = (state == BR_STATE_BLOCKING || state == BR_STATE_DISABLED) ? 1783 0 : BIT(port); 1784 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 1785 VSC73XX_RECVMASK, BIT(port), val); 1786 1787 /* CPU Port should always forward packets when user ports are forwarding 1788 * so let's configure it from other ports only. 1789 */ 1790 if (port != CPU_PORT) 1791 vsc73xx_refresh_fwd_map(ds, port, state); 1792 } 1793 1794 static const struct phylink_mac_ops vsc73xx_phylink_mac_ops = { 1795 .mac_config = vsc73xx_mac_config, 1796 .mac_link_down = vsc73xx_mac_link_down, 1797 .mac_link_up = vsc73xx_mac_link_up, 1798 }; 1799 1800 static const struct dsa_switch_ops vsc73xx_ds_ops = { 1801 .get_tag_protocol = vsc73xx_get_tag_protocol, 1802 .setup = vsc73xx_setup, 1803 .teardown = vsc73xx_teardown, 1804 .phy_read = vsc73xx_phy_read, 1805 .phy_write = vsc73xx_phy_write, 1806 .get_strings = vsc73xx_get_strings, 1807 .get_ethtool_stats = vsc73xx_get_ethtool_stats, 1808 .get_sset_count = vsc73xx_get_sset_count, 1809 .port_enable = vsc73xx_port_enable, 1810 .port_disable = vsc73xx_port_disable, 1811 .port_pre_bridge_flags = vsc73xx_port_pre_bridge_flags, 1812 .port_bridge_flags = vsc73xx_port_bridge_flags, 1813 .port_bridge_join = dsa_tag_8021q_bridge_join, 1814 .port_bridge_leave = dsa_tag_8021q_bridge_leave, 1815 .port_change_mtu = vsc73xx_change_mtu, 1816 .port_max_mtu = vsc73xx_get_max_mtu, 1817 .port_stp_state_set = vsc73xx_port_stp_state_set, 1818 .port_vlan_filtering = vsc73xx_port_vlan_filtering, 1819 .port_vlan_add = vsc73xx_port_vlan_add, 1820 .port_vlan_del = vsc73xx_port_vlan_del, 1821 .phylink_get_caps = vsc73xx_phylink_get_caps, 1822 .tag_8021q_vlan_add = vsc73xx_tag_8021q_vlan_add, 1823 .tag_8021q_vlan_del = vsc73xx_tag_8021q_vlan_del, 1824 }; 1825 1826 static int vsc73xx_gpio_get(struct gpio_chip *chip, unsigned int offset) 1827 { 1828 struct vsc73xx *vsc = gpiochip_get_data(chip); 1829 u32 val; 1830 int ret; 1831 1832 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1833 VSC73XX_GPIO, &val); 1834 if (ret) 1835 return ret; 1836 1837 return !!(val & BIT(offset)); 1838 } 1839 1840 static void vsc73xx_gpio_set(struct gpio_chip *chip, unsigned int offset, 1841 int val) 1842 { 1843 struct vsc73xx *vsc = gpiochip_get_data(chip); 1844 u32 tmp = val ? BIT(offset) : 0; 1845 1846 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1847 VSC73XX_GPIO, BIT(offset), tmp); 1848 } 1849 1850 static int vsc73xx_gpio_direction_output(struct gpio_chip *chip, 1851 unsigned int offset, int val) 1852 { 1853 struct vsc73xx *vsc = gpiochip_get_data(chip); 1854 u32 tmp = val ? BIT(offset) : 0; 1855 1856 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1857 VSC73XX_GPIO, BIT(offset + 4) | BIT(offset), 1858 BIT(offset + 4) | tmp); 1859 } 1860 1861 static int vsc73xx_gpio_direction_input(struct gpio_chip *chip, 1862 unsigned int offset) 1863 { 1864 struct vsc73xx *vsc = gpiochip_get_data(chip); 1865 1866 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1867 VSC73XX_GPIO, BIT(offset + 4), 1868 0); 1869 } 1870 1871 static int vsc73xx_gpio_get_direction(struct gpio_chip *chip, 1872 unsigned int offset) 1873 { 1874 struct vsc73xx *vsc = gpiochip_get_data(chip); 1875 u32 val; 1876 int ret; 1877 1878 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1879 VSC73XX_GPIO, &val); 1880 if (ret) 1881 return ret; 1882 1883 return !(val & BIT(offset + 4)); 1884 } 1885 1886 static int vsc73xx_gpio_probe(struct vsc73xx *vsc) 1887 { 1888 int ret; 1889 1890 vsc->gc.label = devm_kasprintf(vsc->dev, GFP_KERNEL, "VSC%04x", 1891 vsc->chipid); 1892 if (!vsc->gc.label) 1893 return -ENOMEM; 1894 vsc->gc.ngpio = 4; 1895 vsc->gc.owner = THIS_MODULE; 1896 vsc->gc.parent = vsc->dev; 1897 vsc->gc.base = -1; 1898 vsc->gc.get = vsc73xx_gpio_get; 1899 vsc->gc.set = vsc73xx_gpio_set; 1900 vsc->gc.direction_input = vsc73xx_gpio_direction_input; 1901 vsc->gc.direction_output = vsc73xx_gpio_direction_output; 1902 vsc->gc.get_direction = vsc73xx_gpio_get_direction; 1903 vsc->gc.can_sleep = true; 1904 ret = devm_gpiochip_add_data(vsc->dev, &vsc->gc, vsc); 1905 if (ret) { 1906 dev_err(vsc->dev, "unable to register GPIO chip\n"); 1907 return ret; 1908 } 1909 return 0; 1910 } 1911 1912 int vsc73xx_probe(struct vsc73xx *vsc) 1913 { 1914 struct device *dev = vsc->dev; 1915 int ret; 1916 1917 /* Release reset, if any */ 1918 vsc->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1919 if (IS_ERR(vsc->reset)) { 1920 dev_err(dev, "failed to get RESET GPIO\n"); 1921 return PTR_ERR(vsc->reset); 1922 } 1923 if (vsc->reset) 1924 /* Wait 20ms according to datasheet table 245 */ 1925 msleep(20); 1926 1927 ret = vsc73xx_detect(vsc); 1928 if (ret == -EAGAIN) { 1929 dev_err(vsc->dev, 1930 "Chip seems to be out of control. Assert reset and try again.\n"); 1931 gpiod_set_value_cansleep(vsc->reset, 1); 1932 /* Reset pulse should be 20ns minimum, according to datasheet 1933 * table 245, so 10us should be fine 1934 */ 1935 usleep_range(10, 100); 1936 gpiod_set_value_cansleep(vsc->reset, 0); 1937 /* Wait 20ms according to datasheet table 245 */ 1938 msleep(20); 1939 ret = vsc73xx_detect(vsc); 1940 } 1941 if (ret) { 1942 dev_err(dev, "no chip found (%d)\n", ret); 1943 return -ENODEV; 1944 } 1945 1946 eth_random_addr(vsc->addr); 1947 dev_info(vsc->dev, 1948 "MAC for control frames: %02X:%02X:%02X:%02X:%02X:%02X\n", 1949 vsc->addr[0], vsc->addr[1], vsc->addr[2], 1950 vsc->addr[3], vsc->addr[4], vsc->addr[5]); 1951 1952 vsc->ds = devm_kzalloc(dev, sizeof(*vsc->ds), GFP_KERNEL); 1953 if (!vsc->ds) 1954 return -ENOMEM; 1955 1956 vsc->ds->dev = dev; 1957 vsc->ds->num_ports = VSC73XX_MAX_NUM_PORTS; 1958 vsc->ds->priv = vsc; 1959 1960 vsc->ds->ops = &vsc73xx_ds_ops; 1961 vsc->ds->phylink_mac_ops = &vsc73xx_phylink_mac_ops; 1962 ret = dsa_register_switch(vsc->ds); 1963 if (ret) { 1964 dev_err(dev, "unable to register switch (%d)\n", ret); 1965 return ret; 1966 } 1967 1968 ret = vsc73xx_gpio_probe(vsc); 1969 if (ret) { 1970 dsa_unregister_switch(vsc->ds); 1971 return ret; 1972 } 1973 1974 return 0; 1975 } 1976 EXPORT_SYMBOL(vsc73xx_probe); 1977 1978 void vsc73xx_remove(struct vsc73xx *vsc) 1979 { 1980 dsa_unregister_switch(vsc->ds); 1981 gpiod_set_value(vsc->reset, 1); 1982 } 1983 EXPORT_SYMBOL(vsc73xx_remove); 1984 1985 void vsc73xx_shutdown(struct vsc73xx *vsc) 1986 { 1987 dsa_switch_shutdown(vsc->ds); 1988 } 1989 EXPORT_SYMBOL(vsc73xx_shutdown); 1990 1991 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>"); 1992 MODULE_DESCRIPTION("Vitesse VSC7385/7388/7395/7398 driver"); 1993 MODULE_LICENSE("GPL v2"); 1994