1 // SPDX-License-Identifier: BSD-3-Clause 2 /* Copyright (c) 2016-2018, NXP Semiconductors 3 * Copyright (c) 2018, Sensor-Technik Wiedemann GmbH 4 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com> 5 */ 6 #include <linux/spi/spi.h> 7 #include <linux/packing.h> 8 #include "sja1105.h" 9 10 #define SJA1105_SIZE_RESET_CMD 4 11 #define SJA1105_SIZE_SPI_MSG_HEADER 4 12 #define SJA1105_SIZE_SPI_MSG_MAXLEN (64 * 4) 13 14 struct sja1105_chunk { 15 u8 *buf; 16 size_t len; 17 u64 reg_addr; 18 }; 19 20 static void 21 sja1105_spi_message_pack(void *buf, const struct sja1105_spi_message *msg) 22 { 23 const int size = SJA1105_SIZE_SPI_MSG_HEADER; 24 25 memset(buf, 0, size); 26 27 sja1105_pack(buf, &msg->access, 31, 31, size); 28 sja1105_pack(buf, &msg->read_count, 30, 25, size); 29 sja1105_pack(buf, &msg->address, 24, 4, size); 30 } 31 32 #define sja1105_hdr_xfer(xfers, chunk) \ 33 ((xfers) + 2 * (chunk)) 34 #define sja1105_chunk_xfer(xfers, chunk) \ 35 ((xfers) + 2 * (chunk) + 1) 36 #define sja1105_hdr_buf(hdr_bufs, chunk) \ 37 ((hdr_bufs) + (chunk) * SJA1105_SIZE_SPI_MSG_HEADER) 38 39 /* If @rw is: 40 * - SPI_WRITE: creates and sends an SPI write message at absolute 41 * address reg_addr, taking @len bytes from *buf 42 * - SPI_READ: creates and sends an SPI read message from absolute 43 * address reg_addr, writing @len bytes into *buf 44 */ 45 int sja1105_xfer_buf(const struct sja1105_private *priv, 46 sja1105_spi_rw_mode_t rw, u64 reg_addr, 47 u8 *buf, size_t len) 48 { 49 struct sja1105_chunk chunk = { 50 .len = min_t(size_t, len, SJA1105_SIZE_SPI_MSG_MAXLEN), 51 .reg_addr = reg_addr, 52 .buf = buf, 53 }; 54 struct spi_device *spi = priv->spidev; 55 struct spi_transfer *xfers; 56 int num_chunks; 57 int rc, i = 0; 58 u8 *hdr_bufs; 59 60 num_chunks = DIV_ROUND_UP(len, SJA1105_SIZE_SPI_MSG_MAXLEN); 61 62 /* One transfer for each message header, one for each message 63 * payload (chunk). 64 */ 65 xfers = kcalloc(2 * num_chunks, sizeof(struct spi_transfer), 66 GFP_KERNEL); 67 if (!xfers) 68 return -ENOMEM; 69 70 /* Packed buffers for the num_chunks SPI message headers, 71 * stored as a contiguous array 72 */ 73 hdr_bufs = kcalloc(num_chunks, SJA1105_SIZE_SPI_MSG_HEADER, 74 GFP_KERNEL); 75 if (!hdr_bufs) { 76 kfree(xfers); 77 return -ENOMEM; 78 } 79 80 for (i = 0; i < num_chunks; i++) { 81 struct spi_transfer *chunk_xfer = sja1105_chunk_xfer(xfers, i); 82 struct spi_transfer *hdr_xfer = sja1105_hdr_xfer(xfers, i); 83 u8 *hdr_buf = sja1105_hdr_buf(hdr_bufs, i); 84 struct sja1105_spi_message msg; 85 86 /* Populate the transfer's header buffer */ 87 msg.address = chunk.reg_addr; 88 msg.access = rw; 89 if (rw == SPI_READ) 90 msg.read_count = chunk.len / 4; 91 else 92 /* Ignored */ 93 msg.read_count = 0; 94 sja1105_spi_message_pack(hdr_buf, &msg); 95 hdr_xfer->tx_buf = hdr_buf; 96 hdr_xfer->len = SJA1105_SIZE_SPI_MSG_HEADER; 97 98 /* Populate the transfer's data buffer */ 99 if (rw == SPI_READ) 100 chunk_xfer->rx_buf = chunk.buf; 101 else 102 chunk_xfer->tx_buf = chunk.buf; 103 chunk_xfer->len = chunk.len; 104 105 /* Calculate next chunk */ 106 chunk.buf += chunk.len; 107 chunk.reg_addr += chunk.len / 4; 108 chunk.len = min_t(size_t, (ptrdiff_t)(buf + len - chunk.buf), 109 SJA1105_SIZE_SPI_MSG_MAXLEN); 110 111 /* De-assert the chip select after each chunk. */ 112 if (chunk.len) 113 chunk_xfer->cs_change = 1; 114 } 115 116 rc = spi_sync_transfer(spi, xfers, 2 * num_chunks); 117 if (rc < 0) 118 dev_err(&spi->dev, "SPI transfer failed: %d\n", rc); 119 120 kfree(hdr_bufs); 121 kfree(xfers); 122 123 return rc; 124 } 125 126 /* If @rw is: 127 * - SPI_WRITE: creates and sends an SPI write message at absolute 128 * address reg_addr 129 * - SPI_READ: creates and sends an SPI read message from absolute 130 * address reg_addr 131 * 132 * The u64 *value is unpacked, meaning that it's stored in the native 133 * CPU endianness and directly usable by software running on the core. 134 */ 135 int sja1105_xfer_u64(const struct sja1105_private *priv, 136 sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value) 137 { 138 u8 packed_buf[8]; 139 int rc; 140 141 if (rw == SPI_WRITE) 142 sja1105_pack(packed_buf, value, 63, 0, 8); 143 144 rc = sja1105_xfer_buf(priv, rw, reg_addr, packed_buf, 8); 145 146 if (rw == SPI_READ) 147 sja1105_unpack(packed_buf, value, 63, 0, 8); 148 149 return rc; 150 } 151 152 /* Same as above, but transfers only a 4 byte word */ 153 int sja1105_xfer_u32(const struct sja1105_private *priv, 154 sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value) 155 { 156 u8 packed_buf[4]; 157 u64 tmp; 158 int rc; 159 160 if (rw == SPI_WRITE) { 161 /* The packing API only supports u64 as CPU word size, 162 * so we need to convert. 163 */ 164 tmp = *value; 165 sja1105_pack(packed_buf, &tmp, 31, 0, 4); 166 } 167 168 rc = sja1105_xfer_buf(priv, rw, reg_addr, packed_buf, 4); 169 170 if (rw == SPI_READ) { 171 sja1105_unpack(packed_buf, &tmp, 31, 0, 4); 172 *value = tmp; 173 } 174 175 return rc; 176 } 177 178 /* Back-ported structure from UM11040 Table 112. 179 * Reset control register (addr. 100440h) 180 * In the SJA1105 E/T, only warm_rst and cold_rst are 181 * supported (exposed in UM10944 as rst_ctrl), but the bit 182 * offsets of warm_rst and cold_rst are actually reversed. 183 */ 184 struct sja1105_reset_cmd { 185 u64 switch_rst; 186 u64 cfg_rst; 187 u64 car_rst; 188 u64 otp_rst; 189 u64 warm_rst; 190 u64 cold_rst; 191 u64 por_rst; 192 }; 193 194 static void 195 sja1105et_reset_cmd_pack(void *buf, const struct sja1105_reset_cmd *reset) 196 { 197 const int size = SJA1105_SIZE_RESET_CMD; 198 199 memset(buf, 0, size); 200 201 sja1105_pack(buf, &reset->cold_rst, 3, 3, size); 202 sja1105_pack(buf, &reset->warm_rst, 2, 2, size); 203 } 204 205 static void 206 sja1105pqrs_reset_cmd_pack(void *buf, const struct sja1105_reset_cmd *reset) 207 { 208 const int size = SJA1105_SIZE_RESET_CMD; 209 210 memset(buf, 0, size); 211 212 sja1105_pack(buf, &reset->switch_rst, 8, 8, size); 213 sja1105_pack(buf, &reset->cfg_rst, 7, 7, size); 214 sja1105_pack(buf, &reset->car_rst, 5, 5, size); 215 sja1105_pack(buf, &reset->otp_rst, 4, 4, size); 216 sja1105_pack(buf, &reset->warm_rst, 3, 3, size); 217 sja1105_pack(buf, &reset->cold_rst, 2, 2, size); 218 sja1105_pack(buf, &reset->por_rst, 1, 1, size); 219 } 220 221 static int sja1105et_reset_cmd(const void *ctx, const void *data) 222 { 223 const struct sja1105_private *priv = ctx; 224 const struct sja1105_reset_cmd *reset = data; 225 const struct sja1105_regs *regs = priv->info->regs; 226 struct device *dev = priv->ds->dev; 227 u8 packed_buf[SJA1105_SIZE_RESET_CMD]; 228 229 if (reset->switch_rst || 230 reset->cfg_rst || 231 reset->car_rst || 232 reset->otp_rst || 233 reset->por_rst) { 234 dev_err(dev, "Only warm and cold reset is supported " 235 "for SJA1105 E/T!\n"); 236 return -EINVAL; 237 } 238 239 if (reset->warm_rst) 240 dev_dbg(dev, "Warm reset requested\n"); 241 if (reset->cold_rst) 242 dev_dbg(dev, "Cold reset requested\n"); 243 244 sja1105et_reset_cmd_pack(packed_buf, reset); 245 246 return sja1105_xfer_buf(priv, SPI_WRITE, regs->rgu, packed_buf, 247 SJA1105_SIZE_RESET_CMD); 248 } 249 250 static int sja1105pqrs_reset_cmd(const void *ctx, const void *data) 251 { 252 const struct sja1105_private *priv = ctx; 253 const struct sja1105_reset_cmd *reset = data; 254 const struct sja1105_regs *regs = priv->info->regs; 255 struct device *dev = priv->ds->dev; 256 u8 packed_buf[SJA1105_SIZE_RESET_CMD]; 257 258 if (reset->switch_rst) 259 dev_dbg(dev, "Main reset for all functional modules requested\n"); 260 if (reset->cfg_rst) 261 dev_dbg(dev, "Chip configuration reset requested\n"); 262 if (reset->car_rst) 263 dev_dbg(dev, "Clock and reset control logic reset requested\n"); 264 if (reset->otp_rst) 265 dev_dbg(dev, "OTP read cycle for reading product " 266 "config settings requested\n"); 267 if (reset->warm_rst) 268 dev_dbg(dev, "Warm reset requested\n"); 269 if (reset->cold_rst) 270 dev_dbg(dev, "Cold reset requested\n"); 271 if (reset->por_rst) 272 dev_dbg(dev, "Power-on reset requested\n"); 273 274 sja1105pqrs_reset_cmd_pack(packed_buf, reset); 275 276 return sja1105_xfer_buf(priv, SPI_WRITE, regs->rgu, packed_buf, 277 SJA1105_SIZE_RESET_CMD); 278 } 279 280 static int sja1105_cold_reset(const struct sja1105_private *priv) 281 { 282 struct sja1105_reset_cmd reset = {0}; 283 284 reset.cold_rst = 1; 285 return priv->info->reset_cmd(priv, &reset); 286 } 287 288 int sja1105_inhibit_tx(const struct sja1105_private *priv, 289 unsigned long port_bitmap, bool tx_inhibited) 290 { 291 const struct sja1105_regs *regs = priv->info->regs; 292 u32 inhibit_cmd; 293 int rc; 294 295 rc = sja1105_xfer_u32(priv, SPI_READ, regs->port_control, 296 &inhibit_cmd); 297 if (rc < 0) 298 return rc; 299 300 if (tx_inhibited) 301 inhibit_cmd |= port_bitmap; 302 else 303 inhibit_cmd &= ~port_bitmap; 304 305 return sja1105_xfer_u32(priv, SPI_WRITE, regs->port_control, 306 &inhibit_cmd); 307 } 308 309 struct sja1105_status { 310 u64 configs; 311 u64 crcchkl; 312 u64 ids; 313 u64 crcchkg; 314 }; 315 316 /* This is not reading the entire General Status area, which is also 317 * divergent between E/T and P/Q/R/S, but only the relevant bits for 318 * ensuring that the static config upload procedure was successful. 319 */ 320 static void sja1105_status_unpack(void *buf, struct sja1105_status *status) 321 { 322 /* So that addition translates to 4 bytes */ 323 u32 *p = buf; 324 325 /* device_id is missing from the buffer, but we don't 326 * want to diverge from the manual definition of the 327 * register addresses, so we'll back off one step with 328 * the register pointer, and never access p[0]. 329 */ 330 p--; 331 sja1105_unpack(p + 0x1, &status->configs, 31, 31, 4); 332 sja1105_unpack(p + 0x1, &status->crcchkl, 30, 30, 4); 333 sja1105_unpack(p + 0x1, &status->ids, 29, 29, 4); 334 sja1105_unpack(p + 0x1, &status->crcchkg, 28, 28, 4); 335 } 336 337 static int sja1105_status_get(struct sja1105_private *priv, 338 struct sja1105_status *status) 339 { 340 const struct sja1105_regs *regs = priv->info->regs; 341 u8 packed_buf[4]; 342 int rc; 343 344 rc = sja1105_xfer_buf(priv, SPI_READ, regs->status, packed_buf, 4); 345 if (rc < 0) 346 return rc; 347 348 sja1105_status_unpack(packed_buf, status); 349 350 return 0; 351 } 352 353 /* Not const because unpacking priv->static_config into buffers and preparing 354 * for upload requires the recalculation of table CRCs and updating the 355 * structures with these. 356 */ 357 static int 358 static_config_buf_prepare_for_upload(struct sja1105_private *priv, 359 void *config_buf, int buf_len) 360 { 361 struct sja1105_static_config *config = &priv->static_config; 362 struct sja1105_table_header final_header; 363 sja1105_config_valid_t valid; 364 char *final_header_ptr; 365 int crc_len; 366 367 valid = sja1105_static_config_check_valid(config); 368 if (valid != SJA1105_CONFIG_OK) { 369 dev_err(&priv->spidev->dev, 370 sja1105_static_config_error_msg[valid]); 371 return -EINVAL; 372 } 373 374 /* Write Device ID and config tables to config_buf */ 375 sja1105_static_config_pack(config_buf, config); 376 /* Recalculate CRC of the last header (right now 0xDEADBEEF). 377 * Don't include the CRC field itself. 378 */ 379 crc_len = buf_len - 4; 380 /* Read the whole table header */ 381 final_header_ptr = config_buf + buf_len - SJA1105_SIZE_TABLE_HEADER; 382 sja1105_table_header_packing(final_header_ptr, &final_header, UNPACK); 383 /* Modify */ 384 final_header.crc = sja1105_crc32(config_buf, crc_len); 385 /* Rewrite */ 386 sja1105_table_header_packing(final_header_ptr, &final_header, PACK); 387 388 return 0; 389 } 390 391 #define RETRIES 10 392 393 int sja1105_static_config_upload(struct sja1105_private *priv) 394 { 395 unsigned long port_bitmap = GENMASK_ULL(SJA1105_NUM_PORTS - 1, 0); 396 struct sja1105_static_config *config = &priv->static_config; 397 const struct sja1105_regs *regs = priv->info->regs; 398 struct device *dev = &priv->spidev->dev; 399 struct sja1105_status status; 400 int rc, retries = RETRIES; 401 u8 *config_buf; 402 int buf_len; 403 404 buf_len = sja1105_static_config_get_length(config); 405 config_buf = kcalloc(buf_len, sizeof(char), GFP_KERNEL); 406 if (!config_buf) 407 return -ENOMEM; 408 409 rc = static_config_buf_prepare_for_upload(priv, config_buf, buf_len); 410 if (rc < 0) { 411 dev_err(dev, "Invalid config, cannot upload\n"); 412 rc = -EINVAL; 413 goto out; 414 } 415 /* Prevent PHY jabbering during switch reset by inhibiting 416 * Tx on all ports and waiting for current packet to drain. 417 * Otherwise, the PHY will see an unterminated Ethernet packet. 418 */ 419 rc = sja1105_inhibit_tx(priv, port_bitmap, true); 420 if (rc < 0) { 421 dev_err(dev, "Failed to inhibit Tx on ports\n"); 422 rc = -ENXIO; 423 goto out; 424 } 425 /* Wait for an eventual egress packet to finish transmission 426 * (reach IFG). It is guaranteed that a second one will not 427 * follow, and that switch cold reset is thus safe 428 */ 429 usleep_range(500, 1000); 430 do { 431 /* Put the SJA1105 in programming mode */ 432 rc = sja1105_cold_reset(priv); 433 if (rc < 0) { 434 dev_err(dev, "Failed to reset switch, retrying...\n"); 435 continue; 436 } 437 /* Wait for the switch to come out of reset */ 438 usleep_range(1000, 5000); 439 /* Upload the static config to the device */ 440 rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->config, 441 config_buf, buf_len); 442 if (rc < 0) { 443 dev_err(dev, "Failed to upload config, retrying...\n"); 444 continue; 445 } 446 /* Check that SJA1105 responded well to the config upload */ 447 rc = sja1105_status_get(priv, &status); 448 if (rc < 0) 449 continue; 450 451 if (status.ids == 1) { 452 dev_err(dev, "Mismatch between hardware and static config " 453 "device id. Wrote 0x%llx, wants 0x%llx\n", 454 config->device_id, priv->info->device_id); 455 continue; 456 } 457 if (status.crcchkl == 1) { 458 dev_err(dev, "Switch reported invalid local CRC on " 459 "the uploaded config, retrying...\n"); 460 continue; 461 } 462 if (status.crcchkg == 1) { 463 dev_err(dev, "Switch reported invalid global CRC on " 464 "the uploaded config, retrying...\n"); 465 continue; 466 } 467 if (status.configs == 0) { 468 dev_err(dev, "Switch reported that configuration is " 469 "invalid, retrying...\n"); 470 continue; 471 } 472 /* Success! */ 473 break; 474 } while (--retries); 475 476 if (!retries) { 477 rc = -EIO; 478 dev_err(dev, "Failed to upload config to device, giving up\n"); 479 goto out; 480 } else if (retries != RETRIES) { 481 dev_info(dev, "Succeeded after %d tried\n", RETRIES - retries); 482 } 483 484 rc = sja1105_ptp_reset(priv->ds); 485 if (rc < 0) 486 dev_err(dev, "Failed to reset PTP clock: %d\n", rc); 487 488 dev_info(dev, "Reset switch and programmed static config\n"); 489 490 out: 491 kfree(config_buf); 492 return rc; 493 } 494 495 static struct sja1105_regs sja1105et_regs = { 496 .device_id = 0x0, 497 .prod_id = 0x100BC3, 498 .status = 0x1, 499 .port_control = 0x11, 500 .config = 0x020000, 501 .rgu = 0x100440, 502 /* UM10944.pdf, Table 86, ACU Register overview */ 503 .pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808}, 504 .rmii_pll1 = 0x10000A, 505 .cgu_idiv = {0x10000B, 0x10000C, 0x10000D, 0x10000E, 0x10000F}, 506 .mac = {0x200, 0x202, 0x204, 0x206, 0x208}, 507 .mac_hl1 = {0x400, 0x410, 0x420, 0x430, 0x440}, 508 .mac_hl2 = {0x600, 0x610, 0x620, 0x630, 0x640}, 509 /* UM10944.pdf, Table 78, CGU Register overview */ 510 .mii_tx_clk = {0x100013, 0x10001A, 0x100021, 0x100028, 0x10002F}, 511 .mii_rx_clk = {0x100014, 0x10001B, 0x100022, 0x100029, 0x100030}, 512 .mii_ext_tx_clk = {0x100018, 0x10001F, 0x100026, 0x10002D, 0x100034}, 513 .mii_ext_rx_clk = {0x100019, 0x100020, 0x100027, 0x10002E, 0x100035}, 514 .rgmii_tx_clk = {0x100016, 0x10001D, 0x100024, 0x10002B, 0x100032}, 515 .rmii_ref_clk = {0x100015, 0x10001C, 0x100023, 0x10002A, 0x100031}, 516 .rmii_ext_tx_clk = {0x100018, 0x10001F, 0x100026, 0x10002D, 0x100034}, 517 .ptpegr_ts = {0xC0, 0xC2, 0xC4, 0xC6, 0xC8}, 518 .ptp_control = 0x17, 519 .ptpclkval = 0x18, /* Spans 0x18 to 0x19 */ 520 .ptpclkrate = 0x1A, 521 }; 522 523 static struct sja1105_regs sja1105pqrs_regs = { 524 .device_id = 0x0, 525 .prod_id = 0x100BC3, 526 .status = 0x1, 527 .port_control = 0x12, 528 .config = 0x020000, 529 .rgu = 0x100440, 530 /* UM10944.pdf, Table 86, ACU Register overview */ 531 .pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808}, 532 .pad_mii_id = {0x100810, 0x100811, 0x100812, 0x100813, 0x100814}, 533 .rmii_pll1 = 0x10000A, 534 .cgu_idiv = {0x10000B, 0x10000C, 0x10000D, 0x10000E, 0x10000F}, 535 .mac = {0x200, 0x202, 0x204, 0x206, 0x208}, 536 .mac_hl1 = {0x400, 0x410, 0x420, 0x430, 0x440}, 537 .mac_hl2 = {0x600, 0x610, 0x620, 0x630, 0x640}, 538 /* UM11040.pdf, Table 114 */ 539 .mii_tx_clk = {0x100013, 0x100019, 0x10001F, 0x100025, 0x10002B}, 540 .mii_rx_clk = {0x100014, 0x10001A, 0x100020, 0x100026, 0x10002C}, 541 .mii_ext_tx_clk = {0x100017, 0x10001D, 0x100023, 0x100029, 0x10002F}, 542 .mii_ext_rx_clk = {0x100018, 0x10001E, 0x100024, 0x10002A, 0x100030}, 543 .rgmii_tx_clk = {0x100016, 0x10001C, 0x100022, 0x100028, 0x10002E}, 544 .rmii_ref_clk = {0x100015, 0x10001B, 0x100021, 0x100027, 0x10002D}, 545 .rmii_ext_tx_clk = {0x100017, 0x10001D, 0x100023, 0x100029, 0x10002F}, 546 .qlevel = {0x604, 0x614, 0x624, 0x634, 0x644}, 547 .ptpegr_ts = {0xC0, 0xC4, 0xC8, 0xCC, 0xD0}, 548 .ptp_control = 0x18, 549 .ptpclkval = 0x19, 550 .ptpclkrate = 0x1B, 551 }; 552 553 struct sja1105_info sja1105e_info = { 554 .device_id = SJA1105E_DEVICE_ID, 555 .part_no = SJA1105ET_PART_NO, 556 .static_ops = sja1105e_table_ops, 557 .dyn_ops = sja1105et_dyn_ops, 558 .ptp_ts_bits = 24, 559 .ptpegr_ts_bytes = 4, 560 .reset_cmd = sja1105et_reset_cmd, 561 .fdb_add_cmd = sja1105et_fdb_add, 562 .fdb_del_cmd = sja1105et_fdb_del, 563 .ptp_cmd = sja1105et_ptp_cmd, 564 .regs = &sja1105et_regs, 565 .name = "SJA1105E", 566 }; 567 struct sja1105_info sja1105t_info = { 568 .device_id = SJA1105T_DEVICE_ID, 569 .part_no = SJA1105ET_PART_NO, 570 .static_ops = sja1105t_table_ops, 571 .dyn_ops = sja1105et_dyn_ops, 572 .ptp_ts_bits = 24, 573 .ptpegr_ts_bytes = 4, 574 .reset_cmd = sja1105et_reset_cmd, 575 .fdb_add_cmd = sja1105et_fdb_add, 576 .fdb_del_cmd = sja1105et_fdb_del, 577 .ptp_cmd = sja1105et_ptp_cmd, 578 .regs = &sja1105et_regs, 579 .name = "SJA1105T", 580 }; 581 struct sja1105_info sja1105p_info = { 582 .device_id = SJA1105PR_DEVICE_ID, 583 .part_no = SJA1105P_PART_NO, 584 .static_ops = sja1105p_table_ops, 585 .dyn_ops = sja1105pqrs_dyn_ops, 586 .ptp_ts_bits = 32, 587 .ptpegr_ts_bytes = 8, 588 .setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay, 589 .reset_cmd = sja1105pqrs_reset_cmd, 590 .fdb_add_cmd = sja1105pqrs_fdb_add, 591 .fdb_del_cmd = sja1105pqrs_fdb_del, 592 .ptp_cmd = sja1105pqrs_ptp_cmd, 593 .regs = &sja1105pqrs_regs, 594 .name = "SJA1105P", 595 }; 596 struct sja1105_info sja1105q_info = { 597 .device_id = SJA1105QS_DEVICE_ID, 598 .part_no = SJA1105Q_PART_NO, 599 .static_ops = sja1105q_table_ops, 600 .dyn_ops = sja1105pqrs_dyn_ops, 601 .ptp_ts_bits = 32, 602 .ptpegr_ts_bytes = 8, 603 .setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay, 604 .reset_cmd = sja1105pqrs_reset_cmd, 605 .fdb_add_cmd = sja1105pqrs_fdb_add, 606 .fdb_del_cmd = sja1105pqrs_fdb_del, 607 .ptp_cmd = sja1105pqrs_ptp_cmd, 608 .regs = &sja1105pqrs_regs, 609 .name = "SJA1105Q", 610 }; 611 struct sja1105_info sja1105r_info = { 612 .device_id = SJA1105PR_DEVICE_ID, 613 .part_no = SJA1105R_PART_NO, 614 .static_ops = sja1105r_table_ops, 615 .dyn_ops = sja1105pqrs_dyn_ops, 616 .ptp_ts_bits = 32, 617 .ptpegr_ts_bytes = 8, 618 .setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay, 619 .reset_cmd = sja1105pqrs_reset_cmd, 620 .fdb_add_cmd = sja1105pqrs_fdb_add, 621 .fdb_del_cmd = sja1105pqrs_fdb_del, 622 .ptp_cmd = sja1105pqrs_ptp_cmd, 623 .regs = &sja1105pqrs_regs, 624 .name = "SJA1105R", 625 }; 626 struct sja1105_info sja1105s_info = { 627 .device_id = SJA1105QS_DEVICE_ID, 628 .part_no = SJA1105S_PART_NO, 629 .static_ops = sja1105s_table_ops, 630 .dyn_ops = sja1105pqrs_dyn_ops, 631 .regs = &sja1105pqrs_regs, 632 .ptp_ts_bits = 32, 633 .ptpegr_ts_bytes = 8, 634 .setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay, 635 .reset_cmd = sja1105pqrs_reset_cmd, 636 .fdb_add_cmd = sja1105pqrs_fdb_add, 637 .fdb_del_cmd = sja1105pqrs_fdb_del, 638 .ptp_cmd = sja1105pqrs_ptp_cmd, 639 .name = "SJA1105S", 640 }; 641