1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH 3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com> 4 */ 5 6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 7 8 #include <linux/delay.h> 9 #include <linux/module.h> 10 #include <linux/printk.h> 11 #include <linux/spi/spi.h> 12 #include <linux/errno.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/phylink.h> 15 #include <linux/of.h> 16 #include <linux/of_net.h> 17 #include <linux/of_mdio.h> 18 #include <linux/pcs/pcs-xpcs.h> 19 #include <linux/netdev_features.h> 20 #include <linux/netdevice.h> 21 #include <linux/if_bridge.h> 22 #include <linux/if_ether.h> 23 #include <linux/dsa/8021q.h> 24 #include <linux/units.h> 25 26 #include "sja1105.h" 27 #include "sja1105_tas.h" 28 29 #define SJA1105_UNKNOWN_MULTICAST 0x010000000000ull 30 31 /* Configure the optional reset pin and bring up switch */ 32 static int sja1105_hw_reset(struct device *dev, unsigned int pulse_len, 33 unsigned int startup_delay) 34 { 35 struct gpio_desc *gpio; 36 37 gpio = gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 38 if (IS_ERR(gpio)) 39 return PTR_ERR(gpio); 40 41 if (!gpio) 42 return 0; 43 44 gpiod_set_value_cansleep(gpio, 1); 45 /* Wait for minimum reset pulse length */ 46 msleep(pulse_len); 47 gpiod_set_value_cansleep(gpio, 0); 48 /* Wait until chip is ready after reset */ 49 msleep(startup_delay); 50 51 gpiod_put(gpio); 52 53 return 0; 54 } 55 56 static void 57 sja1105_port_allow_traffic(struct sja1105_l2_forwarding_entry *l2_fwd, 58 int from, int to, bool allow) 59 { 60 if (allow) 61 l2_fwd[from].reach_port |= BIT(to); 62 else 63 l2_fwd[from].reach_port &= ~BIT(to); 64 } 65 66 static bool sja1105_can_forward(struct sja1105_l2_forwarding_entry *l2_fwd, 67 int from, int to) 68 { 69 return !!(l2_fwd[from].reach_port & BIT(to)); 70 } 71 72 static int sja1105_is_vlan_configured(struct sja1105_private *priv, u16 vid) 73 { 74 struct sja1105_vlan_lookup_entry *vlan; 75 int count, i; 76 77 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries; 78 count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count; 79 80 for (i = 0; i < count; i++) 81 if (vlan[i].vlanid == vid) 82 return i; 83 84 /* Return an invalid entry index if not found */ 85 return -1; 86 } 87 88 static int sja1105_drop_untagged(struct dsa_switch *ds, int port, bool drop) 89 { 90 struct sja1105_private *priv = ds->priv; 91 struct sja1105_mac_config_entry *mac; 92 93 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; 94 95 if (mac[port].drpuntag == drop) 96 return 0; 97 98 mac[port].drpuntag = drop; 99 100 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port, 101 &mac[port], true); 102 } 103 104 static int sja1105_pvid_apply(struct sja1105_private *priv, int port, u16 pvid) 105 { 106 struct sja1105_mac_config_entry *mac; 107 108 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; 109 110 if (mac[port].vlanid == pvid) 111 return 0; 112 113 mac[port].vlanid = pvid; 114 115 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port, 116 &mac[port], true); 117 } 118 119 static int sja1105_commit_pvid(struct dsa_switch *ds, int port) 120 { 121 struct dsa_port *dp = dsa_to_port(ds, port); 122 struct net_device *br = dsa_port_bridge_dev_get(dp); 123 struct sja1105_private *priv = ds->priv; 124 struct sja1105_vlan_lookup_entry *vlan; 125 bool drop_untagged = false; 126 int match, rc; 127 u16 pvid; 128 129 if (br && br_vlan_enabled(br)) 130 pvid = priv->bridge_pvid[port]; 131 else 132 pvid = priv->tag_8021q_pvid[port]; 133 134 rc = sja1105_pvid_apply(priv, port, pvid); 135 if (rc) 136 return rc; 137 138 /* Only force dropping of untagged packets when the port is under a 139 * VLAN-aware bridge. When the tag_8021q pvid is used, we are 140 * deliberately removing the RX VLAN from the port's VMEMB_PORT list, 141 * to prevent DSA tag spoofing from the link partner. Untagged packets 142 * are the only ones that should be received with tag_8021q, so 143 * definitely don't drop them. 144 */ 145 if (pvid == priv->bridge_pvid[port]) { 146 vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries; 147 148 match = sja1105_is_vlan_configured(priv, pvid); 149 150 if (match < 0 || !(vlan[match].vmemb_port & BIT(port))) 151 drop_untagged = true; 152 } 153 154 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 155 drop_untagged = true; 156 157 return sja1105_drop_untagged(ds, port, drop_untagged); 158 } 159 160 static int sja1105_init_mac_settings(struct sja1105_private *priv) 161 { 162 struct sja1105_mac_config_entry default_mac = { 163 /* Enable all 8 priority queues on egress. 164 * Every queue i holds top[i] - base[i] frames. 165 * Sum of top[i] - base[i] is 511 (max hardware limit). 166 */ 167 .top = {0x3F, 0x7F, 0xBF, 0xFF, 0x13F, 0x17F, 0x1BF, 0x1FF}, 168 .base = {0x0, 0x40, 0x80, 0xC0, 0x100, 0x140, 0x180, 0x1C0}, 169 .enabled = {true, true, true, true, true, true, true, true}, 170 /* Keep standard IFG of 12 bytes on egress. */ 171 .ifg = 0, 172 /* Always put the MAC speed in automatic mode, where it can be 173 * adjusted at runtime by PHYLINK. 174 */ 175 .speed = priv->info->port_speed[SJA1105_SPEED_AUTO], 176 /* No static correction for 1-step 1588 events */ 177 .tp_delin = 0, 178 .tp_delout = 0, 179 /* Disable aging for critical TTEthernet traffic */ 180 .maxage = 0xFF, 181 /* Internal VLAN (pvid) to apply to untagged ingress */ 182 .vlanprio = 0, 183 .vlanid = 1, 184 .ing_mirr = false, 185 .egr_mirr = false, 186 /* Don't drop traffic with other EtherType than ETH_P_IP */ 187 .drpnona664 = false, 188 /* Don't drop double-tagged traffic */ 189 .drpdtag = false, 190 /* Don't drop untagged traffic */ 191 .drpuntag = false, 192 /* Don't retag 802.1p (VID 0) traffic with the pvid */ 193 .retag = false, 194 /* Disable learning and I/O on user ports by default - 195 * STP will enable it. 196 */ 197 .dyn_learn = false, 198 .egress = false, 199 .ingress = false, 200 }; 201 struct sja1105_mac_config_entry *mac; 202 struct dsa_switch *ds = priv->ds; 203 struct sja1105_table *table; 204 struct dsa_port *dp; 205 206 table = &priv->static_config.tables[BLK_IDX_MAC_CONFIG]; 207 208 /* Discard previous MAC Configuration Table */ 209 if (table->entry_count) { 210 kfree(table->entries); 211 table->entry_count = 0; 212 } 213 214 table->entries = kcalloc(table->ops->max_entry_count, 215 table->ops->unpacked_entry_size, GFP_KERNEL); 216 if (!table->entries) 217 return -ENOMEM; 218 219 table->entry_count = table->ops->max_entry_count; 220 221 mac = table->entries; 222 223 list_for_each_entry(dp, &ds->dst->ports, list) { 224 if (dp->ds != ds) 225 continue; 226 227 mac[dp->index] = default_mac; 228 229 /* Let sja1105_bridge_stp_state_set() keep address learning 230 * enabled for the DSA ports. CPU ports use software-assisted 231 * learning to ensure that only FDB entries belonging to the 232 * bridge are learned, and that they are learned towards all 233 * CPU ports in a cross-chip topology if multiple CPU ports 234 * exist. 235 */ 236 if (dsa_port_is_dsa(dp)) 237 dp->learning = true; 238 239 /* Disallow untagged packets from being received on the 240 * CPU and DSA ports. 241 */ 242 if (dsa_port_is_cpu(dp) || dsa_port_is_dsa(dp)) 243 mac[dp->index].drpuntag = true; 244 } 245 246 return 0; 247 } 248 249 static int sja1105_init_mii_settings(struct sja1105_private *priv) 250 { 251 struct device *dev = &priv->spidev->dev; 252 struct sja1105_xmii_params_entry *mii; 253 struct dsa_switch *ds = priv->ds; 254 struct sja1105_table *table; 255 int i; 256 257 table = &priv->static_config.tables[BLK_IDX_XMII_PARAMS]; 258 259 /* Discard previous xMII Mode Parameters Table */ 260 if (table->entry_count) { 261 kfree(table->entries); 262 table->entry_count = 0; 263 } 264 265 table->entries = kcalloc(table->ops->max_entry_count, 266 table->ops->unpacked_entry_size, GFP_KERNEL); 267 if (!table->entries) 268 return -ENOMEM; 269 270 /* Override table based on PHYLINK DT bindings */ 271 table->entry_count = table->ops->max_entry_count; 272 273 mii = table->entries; 274 275 for (i = 0; i < ds->num_ports; i++) { 276 sja1105_mii_role_t role = XMII_MAC; 277 278 if (dsa_is_unused_port(priv->ds, i)) 279 continue; 280 281 switch (priv->phy_mode[i]) { 282 case PHY_INTERFACE_MODE_INTERNAL: 283 if (priv->info->internal_phy[i] == SJA1105_NO_PHY) 284 goto unsupported; 285 286 mii->xmii_mode[i] = XMII_MODE_MII; 287 if (priv->info->internal_phy[i] == SJA1105_PHY_BASE_TX) 288 mii->special[i] = true; 289 290 break; 291 case PHY_INTERFACE_MODE_REVMII: 292 role = XMII_PHY; 293 fallthrough; 294 case PHY_INTERFACE_MODE_MII: 295 if (!priv->info->supports_mii[i]) 296 goto unsupported; 297 298 mii->xmii_mode[i] = XMII_MODE_MII; 299 break; 300 case PHY_INTERFACE_MODE_REVRMII: 301 role = XMII_PHY; 302 fallthrough; 303 case PHY_INTERFACE_MODE_RMII: 304 if (!priv->info->supports_rmii[i]) 305 goto unsupported; 306 307 mii->xmii_mode[i] = XMII_MODE_RMII; 308 break; 309 case PHY_INTERFACE_MODE_RGMII: 310 case PHY_INTERFACE_MODE_RGMII_ID: 311 case PHY_INTERFACE_MODE_RGMII_RXID: 312 case PHY_INTERFACE_MODE_RGMII_TXID: 313 if (!priv->info->supports_rgmii[i]) 314 goto unsupported; 315 316 mii->xmii_mode[i] = XMII_MODE_RGMII; 317 break; 318 case PHY_INTERFACE_MODE_SGMII: 319 if (!priv->info->supports_sgmii[i]) 320 goto unsupported; 321 322 mii->xmii_mode[i] = XMII_MODE_SGMII; 323 mii->special[i] = true; 324 break; 325 case PHY_INTERFACE_MODE_2500BASEX: 326 if (!priv->info->supports_2500basex[i]) 327 goto unsupported; 328 329 mii->xmii_mode[i] = XMII_MODE_SGMII; 330 mii->special[i] = true; 331 break; 332 unsupported: 333 default: 334 dev_err(dev, "Unsupported PHY mode %s on port %d!\n", 335 phy_modes(priv->phy_mode[i]), i); 336 return -EINVAL; 337 } 338 339 mii->phy_mac[i] = role; 340 } 341 return 0; 342 } 343 344 static int sja1105_init_static_fdb(struct sja1105_private *priv) 345 { 346 struct sja1105_l2_lookup_entry *l2_lookup; 347 struct sja1105_table *table; 348 int port; 349 350 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP]; 351 352 /* We only populate the FDB table through dynamic L2 Address Lookup 353 * entries, except for a special entry at the end which is a catch-all 354 * for unknown multicast and will be used to control flooding domain. 355 */ 356 if (table->entry_count) { 357 kfree(table->entries); 358 table->entry_count = 0; 359 } 360 361 if (!priv->info->can_limit_mcast_flood) 362 return 0; 363 364 table->entries = kcalloc(1, table->ops->unpacked_entry_size, 365 GFP_KERNEL); 366 if (!table->entries) 367 return -ENOMEM; 368 369 table->entry_count = 1; 370 l2_lookup = table->entries; 371 372 /* All L2 multicast addresses have an odd first octet */ 373 l2_lookup[0].macaddr = SJA1105_UNKNOWN_MULTICAST; 374 l2_lookup[0].mask_macaddr = SJA1105_UNKNOWN_MULTICAST; 375 l2_lookup[0].lockeds = true; 376 l2_lookup[0].index = SJA1105_MAX_L2_LOOKUP_COUNT - 1; 377 378 /* Flood multicast to every port by default */ 379 for (port = 0; port < priv->ds->num_ports; port++) 380 if (!dsa_is_unused_port(priv->ds, port)) 381 l2_lookup[0].destports |= BIT(port); 382 383 return 0; 384 } 385 386 static int sja1105_init_l2_lookup_params(struct sja1105_private *priv) 387 { 388 struct sja1105_l2_lookup_params_entry default_l2_lookup_params = { 389 /* Learned FDB entries are forgotten after 300 seconds */ 390 .maxage = SJA1105_AGEING_TIME_MS(300000), 391 /* All entries within a FDB bin are available for learning */ 392 .dyn_tbsz = SJA1105ET_FDB_BIN_SIZE, 393 /* And the P/Q/R/S equivalent setting: */ 394 .start_dynspc = 0, 395 /* 2^8 + 2^5 + 2^3 + 2^2 + 2^1 + 1 in Koopman notation */ 396 .poly = 0x97, 397 /* Always use Independent VLAN Learning (IVL) */ 398 .shared_learn = false, 399 /* Don't discard management traffic based on ENFPORT - 400 * we don't perform SMAC port enforcement anyway, so 401 * what we are setting here doesn't matter. 402 */ 403 .no_enf_hostprt = false, 404 /* Don't learn SMAC for mac_fltres1 and mac_fltres0. 405 * Maybe correlate with no_linklocal_learn from bridge driver? 406 */ 407 .no_mgmt_learn = true, 408 /* P/Q/R/S only */ 409 .use_static = true, 410 /* Dynamically learned FDB entries can overwrite other (older) 411 * dynamic FDB entries 412 */ 413 .owr_dyn = true, 414 .drpnolearn = true, 415 }; 416 struct dsa_switch *ds = priv->ds; 417 int port, num_used_ports = 0; 418 struct sja1105_table *table; 419 u64 max_fdb_entries; 420 421 for (port = 0; port < ds->num_ports; port++) 422 if (!dsa_is_unused_port(ds, port)) 423 num_used_ports++; 424 425 max_fdb_entries = SJA1105_MAX_L2_LOOKUP_COUNT / num_used_ports; 426 427 for (port = 0; port < ds->num_ports; port++) { 428 if (dsa_is_unused_port(ds, port)) 429 continue; 430 431 default_l2_lookup_params.maxaddrp[port] = max_fdb_entries; 432 } 433 434 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS]; 435 436 if (table->entry_count) { 437 kfree(table->entries); 438 table->entry_count = 0; 439 } 440 441 table->entries = kcalloc(table->ops->max_entry_count, 442 table->ops->unpacked_entry_size, GFP_KERNEL); 443 if (!table->entries) 444 return -ENOMEM; 445 446 table->entry_count = table->ops->max_entry_count; 447 448 /* This table only has a single entry */ 449 ((struct sja1105_l2_lookup_params_entry *)table->entries)[0] = 450 default_l2_lookup_params; 451 452 return 0; 453 } 454 455 /* Set up a default VLAN for untagged traffic injected from the CPU 456 * using management routes (e.g. STP, PTP) as opposed to tag_8021q. 457 * All DT-defined ports are members of this VLAN, and there are no 458 * restrictions on forwarding (since the CPU selects the destination). 459 * Frames from this VLAN will always be transmitted as untagged, and 460 * neither the bridge nor the 8021q module cannot create this VLAN ID. 461 */ 462 static int sja1105_init_static_vlan(struct sja1105_private *priv) 463 { 464 struct sja1105_table *table; 465 struct sja1105_vlan_lookup_entry pvid = { 466 .type_entry = SJA1110_VLAN_D_TAG, 467 .ving_mirr = 0, 468 .vegr_mirr = 0, 469 .vmemb_port = 0, 470 .vlan_bc = 0, 471 .tag_port = 0, 472 .vlanid = SJA1105_DEFAULT_VLAN, 473 }; 474 struct dsa_switch *ds = priv->ds; 475 int port; 476 477 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP]; 478 479 if (table->entry_count) { 480 kfree(table->entries); 481 table->entry_count = 0; 482 } 483 484 table->entries = kzalloc(table->ops->unpacked_entry_size, 485 GFP_KERNEL); 486 if (!table->entries) 487 return -ENOMEM; 488 489 table->entry_count = 1; 490 491 for (port = 0; port < ds->num_ports; port++) { 492 if (dsa_is_unused_port(ds, port)) 493 continue; 494 495 pvid.vmemb_port |= BIT(port); 496 pvid.vlan_bc |= BIT(port); 497 pvid.tag_port &= ~BIT(port); 498 499 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { 500 priv->tag_8021q_pvid[port] = SJA1105_DEFAULT_VLAN; 501 priv->bridge_pvid[port] = SJA1105_DEFAULT_VLAN; 502 } 503 } 504 505 ((struct sja1105_vlan_lookup_entry *)table->entries)[0] = pvid; 506 return 0; 507 } 508 509 static int sja1105_init_l2_forwarding(struct sja1105_private *priv) 510 { 511 struct sja1105_l2_forwarding_entry *l2fwd; 512 struct dsa_switch *ds = priv->ds; 513 struct dsa_switch_tree *dst; 514 struct sja1105_table *table; 515 struct dsa_link *dl; 516 int port, tc; 517 int from, to; 518 519 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING]; 520 521 if (table->entry_count) { 522 kfree(table->entries); 523 table->entry_count = 0; 524 } 525 526 table->entries = kcalloc(table->ops->max_entry_count, 527 table->ops->unpacked_entry_size, GFP_KERNEL); 528 if (!table->entries) 529 return -ENOMEM; 530 531 table->entry_count = table->ops->max_entry_count; 532 533 l2fwd = table->entries; 534 535 /* First 5 entries in the L2 Forwarding Table define the forwarding 536 * rules and the VLAN PCP to ingress queue mapping. 537 * Set up the ingress queue mapping first. 538 */ 539 for (port = 0; port < ds->num_ports; port++) { 540 if (dsa_is_unused_port(ds, port)) 541 continue; 542 543 for (tc = 0; tc < SJA1105_NUM_TC; tc++) 544 l2fwd[port].vlan_pmap[tc] = tc; 545 } 546 547 /* Then manage the forwarding domain for user ports. These can forward 548 * only to the always-on domain (CPU port and DSA links) 549 */ 550 for (from = 0; from < ds->num_ports; from++) { 551 if (!dsa_is_user_port(ds, from)) 552 continue; 553 554 for (to = 0; to < ds->num_ports; to++) { 555 if (!dsa_is_cpu_port(ds, to) && 556 !dsa_is_dsa_port(ds, to)) 557 continue; 558 559 l2fwd[from].bc_domain |= BIT(to); 560 l2fwd[from].fl_domain |= BIT(to); 561 562 sja1105_port_allow_traffic(l2fwd, from, to, true); 563 } 564 } 565 566 /* Then manage the forwarding domain for DSA links and CPU ports (the 567 * always-on domain). These can send packets to any enabled port except 568 * themselves. 569 */ 570 for (from = 0; from < ds->num_ports; from++) { 571 if (!dsa_is_cpu_port(ds, from) && !dsa_is_dsa_port(ds, from)) 572 continue; 573 574 for (to = 0; to < ds->num_ports; to++) { 575 if (dsa_is_unused_port(ds, to)) 576 continue; 577 578 if (from == to) 579 continue; 580 581 l2fwd[from].bc_domain |= BIT(to); 582 l2fwd[from].fl_domain |= BIT(to); 583 584 sja1105_port_allow_traffic(l2fwd, from, to, true); 585 } 586 } 587 588 /* In odd topologies ("H" connections where there is a DSA link to 589 * another switch which also has its own CPU port), TX packets can loop 590 * back into the system (they are flooded from CPU port 1 to the DSA 591 * link, and from there to CPU port 2). Prevent this from happening by 592 * cutting RX from DSA links towards our CPU port, if the remote switch 593 * has its own CPU port and therefore doesn't need ours for network 594 * stack termination. 595 */ 596 dst = ds->dst; 597 598 list_for_each_entry(dl, &dst->rtable, list) { 599 if (dl->dp->ds != ds || dl->link_dp->cpu_dp == dl->dp->cpu_dp) 600 continue; 601 602 from = dl->dp->index; 603 to = dsa_upstream_port(ds, from); 604 605 dev_warn(ds->dev, 606 "H topology detected, cutting RX from DSA link %d to CPU port %d to prevent TX packet loops\n", 607 from, to); 608 609 sja1105_port_allow_traffic(l2fwd, from, to, false); 610 611 l2fwd[from].bc_domain &= ~BIT(to); 612 l2fwd[from].fl_domain &= ~BIT(to); 613 } 614 615 /* Finally, manage the egress flooding domain. All ports start up with 616 * flooding enabled, including the CPU port and DSA links. 617 */ 618 for (port = 0; port < ds->num_ports; port++) { 619 if (dsa_is_unused_port(ds, port)) 620 continue; 621 622 priv->ucast_egress_floods |= BIT(port); 623 priv->bcast_egress_floods |= BIT(port); 624 } 625 626 /* Next 8 entries define VLAN PCP mapping from ingress to egress. 627 * Create a one-to-one mapping. 628 */ 629 for (tc = 0; tc < SJA1105_NUM_TC; tc++) { 630 for (port = 0; port < ds->num_ports; port++) { 631 if (dsa_is_unused_port(ds, port)) 632 continue; 633 634 l2fwd[ds->num_ports + tc].vlan_pmap[port] = tc; 635 } 636 637 l2fwd[ds->num_ports + tc].type_egrpcp2outputq = true; 638 } 639 640 return 0; 641 } 642 643 static int sja1110_init_pcp_remapping(struct sja1105_private *priv) 644 { 645 struct sja1110_pcp_remapping_entry *pcp_remap; 646 struct dsa_switch *ds = priv->ds; 647 struct sja1105_table *table; 648 int port, tc; 649 650 table = &priv->static_config.tables[BLK_IDX_PCP_REMAPPING]; 651 652 /* Nothing to do for SJA1105 */ 653 if (!table->ops->max_entry_count) 654 return 0; 655 656 if (table->entry_count) { 657 kfree(table->entries); 658 table->entry_count = 0; 659 } 660 661 table->entries = kcalloc(table->ops->max_entry_count, 662 table->ops->unpacked_entry_size, GFP_KERNEL); 663 if (!table->entries) 664 return -ENOMEM; 665 666 table->entry_count = table->ops->max_entry_count; 667 668 pcp_remap = table->entries; 669 670 /* Repeat the configuration done for vlan_pmap */ 671 for (port = 0; port < ds->num_ports; port++) { 672 if (dsa_is_unused_port(ds, port)) 673 continue; 674 675 for (tc = 0; tc < SJA1105_NUM_TC; tc++) 676 pcp_remap[port].egrpcp[tc] = tc; 677 } 678 679 return 0; 680 } 681 682 static int sja1105_init_l2_forwarding_params(struct sja1105_private *priv) 683 { 684 struct sja1105_l2_forwarding_params_entry *l2fwd_params; 685 struct sja1105_table *table; 686 687 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS]; 688 689 if (table->entry_count) { 690 kfree(table->entries); 691 table->entry_count = 0; 692 } 693 694 table->entries = kcalloc(table->ops->max_entry_count, 695 table->ops->unpacked_entry_size, GFP_KERNEL); 696 if (!table->entries) 697 return -ENOMEM; 698 699 table->entry_count = table->ops->max_entry_count; 700 701 /* This table only has a single entry */ 702 l2fwd_params = table->entries; 703 704 /* Disallow dynamic reconfiguration of vlan_pmap */ 705 l2fwd_params->max_dynp = 0; 706 /* Use a single memory partition for all ingress queues */ 707 l2fwd_params->part_spc[0] = priv->info->max_frame_mem; 708 709 return 0; 710 } 711 712 void sja1105_frame_memory_partitioning(struct sja1105_private *priv) 713 { 714 struct sja1105_l2_forwarding_params_entry *l2_fwd_params; 715 struct sja1105_vl_forwarding_params_entry *vl_fwd_params; 716 struct sja1105_table *table; 717 718 table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS]; 719 l2_fwd_params = table->entries; 720 l2_fwd_params->part_spc[0] = SJA1105_MAX_FRAME_MEMORY; 721 722 /* If we have any critical-traffic virtual links, we need to reserve 723 * some frame buffer memory for them. At the moment, hardcode the value 724 * at 100 blocks of 128 bytes of memory each. This leaves 829 blocks 725 * remaining for best-effort traffic. TODO: figure out a more flexible 726 * way to perform the frame buffer partitioning. 727 */ 728 if (!priv->static_config.tables[BLK_IDX_VL_FORWARDING].entry_count) 729 return; 730 731 table = &priv->static_config.tables[BLK_IDX_VL_FORWARDING_PARAMS]; 732 vl_fwd_params = table->entries; 733 734 l2_fwd_params->part_spc[0] -= SJA1105_VL_FRAME_MEMORY; 735 vl_fwd_params->partspc[0] = SJA1105_VL_FRAME_MEMORY; 736 } 737 738 /* SJA1110 TDMACONFIGIDX values: 739 * 740 * | 100 Mbps ports | 1Gbps ports | 2.5Gbps ports | Disabled ports 741 * -----+----------------+---------------+---------------+--------------- 742 * 0 | 0, [5:10] | [1:2] | [3:4] | retag 743 * 1 |0, [5:10], retag| [1:2] | [3:4] | - 744 * 2 | 0, [5:10] | [1:3], retag | 4 | - 745 * 3 | 0, [5:10] |[1:2], 4, retag| 3 | - 746 * 4 | 0, 2, [5:10] | 1, retag | [3:4] | - 747 * 5 | 0, 1, [5:10] | 2, retag | [3:4] | - 748 * 14 | 0, [5:10] | [1:4], retag | - | - 749 * 15 | [5:10] | [0:4], retag | - | - 750 */ 751 static void sja1110_select_tdmaconfigidx(struct sja1105_private *priv) 752 { 753 struct sja1105_general_params_entry *general_params; 754 struct sja1105_table *table; 755 bool port_1_is_base_tx; 756 bool port_3_is_2500; 757 bool port_4_is_2500; 758 u64 tdmaconfigidx; 759 760 if (priv->info->device_id != SJA1110_DEVICE_ID) 761 return; 762 763 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS]; 764 general_params = table->entries; 765 766 /* All the settings below are "as opposed to SGMII", which is the 767 * other pinmuxing option. 768 */ 769 port_1_is_base_tx = priv->phy_mode[1] == PHY_INTERFACE_MODE_INTERNAL; 770 port_3_is_2500 = priv->phy_mode[3] == PHY_INTERFACE_MODE_2500BASEX; 771 port_4_is_2500 = priv->phy_mode[4] == PHY_INTERFACE_MODE_2500BASEX; 772 773 if (port_1_is_base_tx) 774 /* Retagging port will operate at 1 Gbps */ 775 tdmaconfigidx = 5; 776 else if (port_3_is_2500 && port_4_is_2500) 777 /* Retagging port will operate at 100 Mbps */ 778 tdmaconfigidx = 1; 779 else if (port_3_is_2500) 780 /* Retagging port will operate at 1 Gbps */ 781 tdmaconfigidx = 3; 782 else if (port_4_is_2500) 783 /* Retagging port will operate at 1 Gbps */ 784 tdmaconfigidx = 2; 785 else 786 /* Retagging port will operate at 1 Gbps */ 787 tdmaconfigidx = 14; 788 789 general_params->tdmaconfigidx = tdmaconfigidx; 790 } 791 792 static int sja1105_init_topology(struct sja1105_private *priv, 793 struct sja1105_general_params_entry *general_params) 794 { 795 struct dsa_switch *ds = priv->ds; 796 int port; 797 798 /* The host port is the destination for traffic matching mac_fltres1 799 * and mac_fltres0 on all ports except itself. Default to an invalid 800 * value. 801 */ 802 general_params->host_port = ds->num_ports; 803 804 /* Link-local traffic received on casc_port will be forwarded 805 * to host_port without embedding the source port and device ID 806 * info in the destination MAC address, and no RX timestamps will be 807 * taken either (presumably because it is a cascaded port and a 808 * downstream SJA switch already did that). 809 * To disable the feature, we need to do different things depending on 810 * switch generation. On SJA1105 we need to set an invalid port, while 811 * on SJA1110 which support multiple cascaded ports, this field is a 812 * bitmask so it must be left zero. 813 */ 814 if (!priv->info->multiple_cascade_ports) 815 general_params->casc_port = ds->num_ports; 816 817 for (port = 0; port < ds->num_ports; port++) { 818 bool is_upstream = dsa_is_upstream_port(ds, port); 819 bool is_dsa_link = dsa_is_dsa_port(ds, port); 820 821 /* Upstream ports can be dedicated CPU ports or 822 * upstream-facing DSA links 823 */ 824 if (is_upstream) { 825 if (general_params->host_port == ds->num_ports) { 826 general_params->host_port = port; 827 } else { 828 dev_err(ds->dev, 829 "Port %llu is already a host port, configuring %d as one too is not supported\n", 830 general_params->host_port, port); 831 return -EINVAL; 832 } 833 } 834 835 /* Cascade ports are downstream-facing DSA links */ 836 if (is_dsa_link && !is_upstream) { 837 if (priv->info->multiple_cascade_ports) { 838 general_params->casc_port |= BIT(port); 839 } else if (general_params->casc_port == ds->num_ports) { 840 general_params->casc_port = port; 841 } else { 842 dev_err(ds->dev, 843 "Port %llu is already a cascade port, configuring %d as one too is not supported\n", 844 general_params->casc_port, port); 845 return -EINVAL; 846 } 847 } 848 } 849 850 if (general_params->host_port == ds->num_ports) { 851 dev_err(ds->dev, "No host port configured\n"); 852 return -EINVAL; 853 } 854 855 return 0; 856 } 857 858 static int sja1105_init_general_params(struct sja1105_private *priv) 859 { 860 struct sja1105_general_params_entry default_general_params = { 861 /* Allow dynamic changing of the mirror port */ 862 .mirr_ptacu = true, 863 .switchid = priv->ds->index, 864 /* Priority queue for link-local management frames 865 * (both ingress to and egress from CPU - PTP, STP etc) 866 */ 867 .hostprio = 7, 868 .mac_fltres1 = SJA1105_LINKLOCAL_FILTER_A, 869 .mac_flt1 = SJA1105_LINKLOCAL_FILTER_A_MASK, 870 .incl_srcpt1 = true, 871 .send_meta1 = true, 872 .mac_fltres0 = SJA1105_LINKLOCAL_FILTER_B, 873 .mac_flt0 = SJA1105_LINKLOCAL_FILTER_B_MASK, 874 .incl_srcpt0 = true, 875 .send_meta0 = true, 876 /* Default to an invalid value */ 877 .mirr_port = priv->ds->num_ports, 878 /* No TTEthernet */ 879 .vllupformat = SJA1105_VL_FORMAT_PSFP, 880 .vlmarker = 0, 881 .vlmask = 0, 882 /* Only update correctionField for 1-step PTP (L2 transport) */ 883 .ignore2stf = 0, 884 /* Forcefully disable VLAN filtering by telling 885 * the switch that VLAN has a different EtherType. 886 */ 887 .tpid = ETH_P_SJA1105, 888 .tpid2 = ETH_P_SJA1105, 889 /* Enable the TTEthernet engine on SJA1110 */ 890 .tte_en = true, 891 /* Set up the EtherType for control packets on SJA1110 */ 892 .header_type = ETH_P_SJA1110, 893 }; 894 struct sja1105_general_params_entry *general_params; 895 struct sja1105_table *table; 896 int rc; 897 898 rc = sja1105_init_topology(priv, &default_general_params); 899 if (rc) 900 return rc; 901 902 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS]; 903 904 if (table->entry_count) { 905 kfree(table->entries); 906 table->entry_count = 0; 907 } 908 909 table->entries = kcalloc(table->ops->max_entry_count, 910 table->ops->unpacked_entry_size, GFP_KERNEL); 911 if (!table->entries) 912 return -ENOMEM; 913 914 table->entry_count = table->ops->max_entry_count; 915 916 general_params = table->entries; 917 918 /* This table only has a single entry */ 919 general_params[0] = default_general_params; 920 921 sja1110_select_tdmaconfigidx(priv); 922 923 return 0; 924 } 925 926 static int sja1105_init_avb_params(struct sja1105_private *priv) 927 { 928 struct sja1105_avb_params_entry *avb; 929 struct sja1105_table *table; 930 931 table = &priv->static_config.tables[BLK_IDX_AVB_PARAMS]; 932 933 /* Discard previous AVB Parameters Table */ 934 if (table->entry_count) { 935 kfree(table->entries); 936 table->entry_count = 0; 937 } 938 939 table->entries = kcalloc(table->ops->max_entry_count, 940 table->ops->unpacked_entry_size, GFP_KERNEL); 941 if (!table->entries) 942 return -ENOMEM; 943 944 table->entry_count = table->ops->max_entry_count; 945 946 avb = table->entries; 947 948 /* Configure the MAC addresses for meta frames */ 949 avb->destmeta = SJA1105_META_DMAC; 950 avb->srcmeta = SJA1105_META_SMAC; 951 /* On P/Q/R/S, configure the direction of the PTP_CLK pin as input by 952 * default. This is because there might be boards with a hardware 953 * layout where enabling the pin as output might cause an electrical 954 * clash. On E/T the pin is always an output, which the board designers 955 * probably already knew, so even if there are going to be electrical 956 * issues, there's nothing we can do. 957 */ 958 avb->cas_master = false; 959 960 return 0; 961 } 962 963 /* The L2 policing table is 2-stage. The table is looked up for each frame 964 * according to the ingress port, whether it was broadcast or not, and the 965 * classified traffic class (given by VLAN PCP). This portion of the lookup is 966 * fixed, and gives access to the SHARINDX, an indirection register pointing 967 * within the policing table itself, which is used to resolve the policer that 968 * will be used for this frame. 969 * 970 * Stage 1 Stage 2 971 * +------------+--------+ +---------------------------------+ 972 * |Port 0 TC 0 |SHARINDX| | Policer 0: Rate, Burst, MTU | 973 * +------------+--------+ +---------------------------------+ 974 * |Port 0 TC 1 |SHARINDX| | Policer 1: Rate, Burst, MTU | 975 * +------------+--------+ +---------------------------------+ 976 * ... | Policer 2: Rate, Burst, MTU | 977 * +------------+--------+ +---------------------------------+ 978 * |Port 0 TC 7 |SHARINDX| | Policer 3: Rate, Burst, MTU | 979 * +------------+--------+ +---------------------------------+ 980 * |Port 1 TC 0 |SHARINDX| | Policer 4: Rate, Burst, MTU | 981 * +------------+--------+ +---------------------------------+ 982 * ... | Policer 5: Rate, Burst, MTU | 983 * +------------+--------+ +---------------------------------+ 984 * |Port 1 TC 7 |SHARINDX| | Policer 6: Rate, Burst, MTU | 985 * +------------+--------+ +---------------------------------+ 986 * ... | Policer 7: Rate, Burst, MTU | 987 * +------------+--------+ +---------------------------------+ 988 * |Port 4 TC 7 |SHARINDX| ... 989 * +------------+--------+ 990 * |Port 0 BCAST|SHARINDX| ... 991 * +------------+--------+ 992 * |Port 1 BCAST|SHARINDX| ... 993 * +------------+--------+ 994 * ... ... 995 * +------------+--------+ +---------------------------------+ 996 * |Port 4 BCAST|SHARINDX| | Policer 44: Rate, Burst, MTU | 997 * +------------+--------+ +---------------------------------+ 998 * 999 * In this driver, we shall use policers 0-4 as statically alocated port 1000 * (matchall) policers. So we need to make the SHARINDX for all lookups 1001 * corresponding to this ingress port (8 VLAN PCP lookups and 1 broadcast 1002 * lookup) equal. 1003 * The remaining policers (40) shall be dynamically allocated for flower 1004 * policers, where the key is either vlan_prio or dst_mac ff:ff:ff:ff:ff:ff. 1005 */ 1006 #define SJA1105_RATE_MBPS(speed) (((speed) * 64000) / 1000) 1007 1008 static int sja1105_init_l2_policing(struct sja1105_private *priv) 1009 { 1010 struct sja1105_l2_policing_entry *policing; 1011 struct dsa_switch *ds = priv->ds; 1012 struct sja1105_table *table; 1013 int port, tc; 1014 1015 table = &priv->static_config.tables[BLK_IDX_L2_POLICING]; 1016 1017 /* Discard previous L2 Policing Table */ 1018 if (table->entry_count) { 1019 kfree(table->entries); 1020 table->entry_count = 0; 1021 } 1022 1023 table->entries = kcalloc(table->ops->max_entry_count, 1024 table->ops->unpacked_entry_size, GFP_KERNEL); 1025 if (!table->entries) 1026 return -ENOMEM; 1027 1028 table->entry_count = table->ops->max_entry_count; 1029 1030 policing = table->entries; 1031 1032 /* Setup shared indices for the matchall policers */ 1033 for (port = 0; port < ds->num_ports; port++) { 1034 int mcast = (ds->num_ports * (SJA1105_NUM_TC + 1)) + port; 1035 int bcast = (ds->num_ports * SJA1105_NUM_TC) + port; 1036 1037 for (tc = 0; tc < SJA1105_NUM_TC; tc++) 1038 policing[port * SJA1105_NUM_TC + tc].sharindx = port; 1039 1040 policing[bcast].sharindx = port; 1041 /* Only SJA1110 has multicast policers */ 1042 if (mcast < table->ops->max_entry_count) 1043 policing[mcast].sharindx = port; 1044 } 1045 1046 /* Setup the matchall policer parameters */ 1047 for (port = 0; port < ds->num_ports; port++) { 1048 int mtu = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; 1049 1050 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1051 mtu += VLAN_HLEN; 1052 1053 policing[port].smax = 65535; /* Burst size in bytes */ 1054 policing[port].rate = SJA1105_RATE_MBPS(1000); 1055 policing[port].maxlen = mtu; 1056 policing[port].partition = 0; 1057 } 1058 1059 return 0; 1060 } 1061 1062 static int sja1105_static_config_load(struct sja1105_private *priv) 1063 { 1064 int rc; 1065 1066 sja1105_static_config_free(&priv->static_config); 1067 rc = sja1105_static_config_init(&priv->static_config, 1068 priv->info->static_ops, 1069 priv->info->device_id); 1070 if (rc) 1071 return rc; 1072 1073 /* Build static configuration */ 1074 rc = sja1105_init_mac_settings(priv); 1075 if (rc < 0) 1076 return rc; 1077 rc = sja1105_init_mii_settings(priv); 1078 if (rc < 0) 1079 return rc; 1080 rc = sja1105_init_static_fdb(priv); 1081 if (rc < 0) 1082 return rc; 1083 rc = sja1105_init_static_vlan(priv); 1084 if (rc < 0) 1085 return rc; 1086 rc = sja1105_init_l2_lookup_params(priv); 1087 if (rc < 0) 1088 return rc; 1089 rc = sja1105_init_l2_forwarding(priv); 1090 if (rc < 0) 1091 return rc; 1092 rc = sja1105_init_l2_forwarding_params(priv); 1093 if (rc < 0) 1094 return rc; 1095 rc = sja1105_init_l2_policing(priv); 1096 if (rc < 0) 1097 return rc; 1098 rc = sja1105_init_general_params(priv); 1099 if (rc < 0) 1100 return rc; 1101 rc = sja1105_init_avb_params(priv); 1102 if (rc < 0) 1103 return rc; 1104 rc = sja1110_init_pcp_remapping(priv); 1105 if (rc < 0) 1106 return rc; 1107 1108 /* Send initial configuration to hardware via SPI */ 1109 return sja1105_static_config_upload(priv); 1110 } 1111 1112 /* This is the "new way" for a MAC driver to configure its RGMII delay lines, 1113 * based on the explicit "rx-internal-delay-ps" and "tx-internal-delay-ps" 1114 * properties. It has the advantage of working with fixed links and with PHYs 1115 * that apply RGMII delays too, and the MAC driver needs not perform any 1116 * special checks. 1117 * 1118 * Previously we were acting upon the "phy-mode" property when we were 1119 * operating in fixed-link, basically acting as a PHY, but with a reversed 1120 * interpretation: PHY_INTERFACE_MODE_RGMII_TXID means that the MAC should 1121 * behave as if it is connected to a PHY which has applied RGMII delays in the 1122 * TX direction. So if anything, RX delays should have been added by the MAC, 1123 * but we were adding TX delays. 1124 * 1125 * If the "{rx,tx}-internal-delay-ps" properties are not specified, we fall 1126 * back to the legacy behavior and apply delays on fixed-link ports based on 1127 * the reverse interpretation of the phy-mode. This is a deviation from the 1128 * expected default behavior which is to simply apply no delays. To achieve 1129 * that behavior with the new bindings, it is mandatory to specify 1130 * "{rx,tx}-internal-delay-ps" with a value of 0. 1131 */ 1132 static int sja1105_parse_rgmii_delays(struct sja1105_private *priv, int port, 1133 struct device_node *port_dn) 1134 { 1135 phy_interface_t phy_mode = priv->phy_mode[port]; 1136 struct device *dev = &priv->spidev->dev; 1137 int rx_delay = -1, tx_delay = -1; 1138 1139 if (!phy_interface_mode_is_rgmii(phy_mode)) 1140 return 0; 1141 1142 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 1143 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 1144 1145 if (rx_delay == -1 && tx_delay == -1 && priv->fixed_link[port]) { 1146 dev_warn(dev, 1147 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 1148 "please update device tree to specify \"rx-internal-delay-ps\" and " 1149 "\"tx-internal-delay-ps\"", 1150 port); 1151 1152 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 1153 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 1154 rx_delay = 2000; 1155 1156 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 1157 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 1158 tx_delay = 2000; 1159 } 1160 1161 if (rx_delay < 0) 1162 rx_delay = 0; 1163 if (tx_delay < 0) 1164 tx_delay = 0; 1165 1166 if ((rx_delay || tx_delay) && !priv->info->setup_rgmii_delay) { 1167 dev_err(dev, "Chip cannot apply RGMII delays\n"); 1168 return -EINVAL; 1169 } 1170 1171 if ((rx_delay && rx_delay < SJA1105_RGMII_DELAY_MIN_PS) || 1172 (tx_delay && tx_delay < SJA1105_RGMII_DELAY_MIN_PS) || 1173 (rx_delay > SJA1105_RGMII_DELAY_MAX_PS) || 1174 (tx_delay > SJA1105_RGMII_DELAY_MAX_PS)) { 1175 dev_err(dev, 1176 "port %d RGMII delay values out of range, must be between %d and %d ps\n", 1177 port, SJA1105_RGMII_DELAY_MIN_PS, SJA1105_RGMII_DELAY_MAX_PS); 1178 return -ERANGE; 1179 } 1180 1181 priv->rgmii_rx_delay_ps[port] = rx_delay; 1182 priv->rgmii_tx_delay_ps[port] = tx_delay; 1183 1184 return 0; 1185 } 1186 1187 static int sja1105_parse_ports_node(struct sja1105_private *priv, 1188 struct device_node *ports_node) 1189 { 1190 struct device *dev = &priv->spidev->dev; 1191 struct device_node *child; 1192 1193 for_each_available_child_of_node(ports_node, child) { 1194 struct device_node *phy_node; 1195 phy_interface_t phy_mode; 1196 u32 index; 1197 int err; 1198 1199 /* Get switch port number from DT */ 1200 if (of_property_read_u32(child, "reg", &index) < 0) { 1201 dev_err(dev, "Port number not defined in device tree " 1202 "(property \"reg\")\n"); 1203 of_node_put(child); 1204 return -ENODEV; 1205 } 1206 1207 /* Get PHY mode from DT */ 1208 err = of_get_phy_mode(child, &phy_mode); 1209 if (err) { 1210 dev_err(dev, "Failed to read phy-mode or " 1211 "phy-interface-type property for port %d\n", 1212 index); 1213 of_node_put(child); 1214 return -ENODEV; 1215 } 1216 1217 phy_node = of_parse_phandle(child, "phy-handle", 0); 1218 if (!phy_node) { 1219 if (!of_phy_is_fixed_link(child)) { 1220 dev_err(dev, "phy-handle or fixed-link " 1221 "properties missing!\n"); 1222 of_node_put(child); 1223 return -ENODEV; 1224 } 1225 /* phy-handle is missing, but fixed-link isn't. 1226 * So it's a fixed link. Default to PHY role. 1227 */ 1228 priv->fixed_link[index] = true; 1229 } else { 1230 of_node_put(phy_node); 1231 } 1232 1233 priv->phy_mode[index] = phy_mode; 1234 1235 err = sja1105_parse_rgmii_delays(priv, index, child); 1236 if (err) { 1237 of_node_put(child); 1238 return err; 1239 } 1240 } 1241 1242 return 0; 1243 } 1244 1245 static int sja1105_parse_dt(struct sja1105_private *priv) 1246 { 1247 struct device *dev = &priv->spidev->dev; 1248 struct device_node *switch_node = dev->of_node; 1249 struct device_node *ports_node; 1250 int rc; 1251 1252 ports_node = of_get_child_by_name(switch_node, "ports"); 1253 if (!ports_node) 1254 ports_node = of_get_child_by_name(switch_node, "ethernet-ports"); 1255 if (!ports_node) { 1256 dev_err(dev, "Incorrect bindings: absent \"ports\" node\n"); 1257 return -ENODEV; 1258 } 1259 1260 rc = sja1105_parse_ports_node(priv, ports_node); 1261 of_node_put(ports_node); 1262 1263 return rc; 1264 } 1265 1266 /* Convert link speed from SJA1105 to ethtool encoding */ 1267 static int sja1105_port_speed_to_ethtool(struct sja1105_private *priv, 1268 u64 speed) 1269 { 1270 if (speed == priv->info->port_speed[SJA1105_SPEED_10MBPS]) 1271 return SPEED_10; 1272 if (speed == priv->info->port_speed[SJA1105_SPEED_100MBPS]) 1273 return SPEED_100; 1274 if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS]) 1275 return SPEED_1000; 1276 if (speed == priv->info->port_speed[SJA1105_SPEED_2500MBPS]) 1277 return SPEED_2500; 1278 return SPEED_UNKNOWN; 1279 } 1280 1281 /* Set link speed in the MAC configuration for a specific port. */ 1282 static int sja1105_adjust_port_config(struct sja1105_private *priv, int port, 1283 int speed_mbps) 1284 { 1285 struct sja1105_mac_config_entry *mac; 1286 struct device *dev = priv->ds->dev; 1287 u64 speed; 1288 int rc; 1289 1290 /* On P/Q/R/S, one can read from the device via the MAC reconfiguration 1291 * tables. On E/T, MAC reconfig tables are not readable, only writable. 1292 * We have to *know* what the MAC looks like. For the sake of keeping 1293 * the code common, we'll use the static configuration tables as a 1294 * reasonable approximation for both E/T and P/Q/R/S. 1295 */ 1296 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; 1297 1298 switch (speed_mbps) { 1299 case SPEED_UNKNOWN: 1300 /* PHYLINK called sja1105_mac_config() to inform us about 1301 * the state->interface, but AN has not completed and the 1302 * speed is not yet valid. UM10944.pdf says that setting 1303 * SJA1105_SPEED_AUTO at runtime disables the port, so that is 1304 * ok for power consumption in case AN will never complete - 1305 * otherwise PHYLINK should come back with a new update. 1306 */ 1307 speed = priv->info->port_speed[SJA1105_SPEED_AUTO]; 1308 break; 1309 case SPEED_10: 1310 speed = priv->info->port_speed[SJA1105_SPEED_10MBPS]; 1311 break; 1312 case SPEED_100: 1313 speed = priv->info->port_speed[SJA1105_SPEED_100MBPS]; 1314 break; 1315 case SPEED_1000: 1316 speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS]; 1317 break; 1318 case SPEED_2500: 1319 speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS]; 1320 break; 1321 default: 1322 dev_err(dev, "Invalid speed %iMbps\n", speed_mbps); 1323 return -EINVAL; 1324 } 1325 1326 /* Overwrite SJA1105_SPEED_AUTO from the static MAC configuration 1327 * table, since this will be used for the clocking setup, and we no 1328 * longer need to store it in the static config (already told hardware 1329 * we want auto during upload phase). 1330 * Actually for the SGMII port, the MAC is fixed at 1 Gbps and 1331 * we need to configure the PCS only (if even that). 1332 */ 1333 if (priv->phy_mode[port] == PHY_INTERFACE_MODE_SGMII) 1334 mac[port].speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS]; 1335 else if (priv->phy_mode[port] == PHY_INTERFACE_MODE_2500BASEX) 1336 mac[port].speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS]; 1337 else 1338 mac[port].speed = speed; 1339 1340 /* Write to the dynamic reconfiguration tables */ 1341 rc = sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port, 1342 &mac[port], true); 1343 if (rc < 0) { 1344 dev_err(dev, "Failed to write MAC config: %d\n", rc); 1345 return rc; 1346 } 1347 1348 /* Reconfigure the PLLs for the RGMII interfaces (required 125 MHz at 1349 * gigabit, 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps). For MII and 1350 * RMII no change of the clock setup is required. Actually, changing 1351 * the clock setup does interrupt the clock signal for a certain time 1352 * which causes trouble for all PHYs relying on this signal. 1353 */ 1354 if (!phy_interface_mode_is_rgmii(priv->phy_mode[port])) 1355 return 0; 1356 1357 return sja1105_clocking_setup_port(priv, port); 1358 } 1359 1360 static struct phylink_pcs * 1361 sja1105_mac_select_pcs(struct phylink_config *config, phy_interface_t iface) 1362 { 1363 struct dsa_port *dp = dsa_phylink_to_port(config); 1364 struct sja1105_private *priv = dp->ds->priv; 1365 struct dw_xpcs *xpcs = priv->xpcs[dp->index]; 1366 1367 if (xpcs) 1368 return &xpcs->pcs; 1369 1370 return NULL; 1371 } 1372 1373 static void sja1105_mac_config(struct phylink_config *config, 1374 unsigned int mode, 1375 const struct phylink_link_state *state) 1376 { 1377 } 1378 1379 static void sja1105_mac_link_down(struct phylink_config *config, 1380 unsigned int mode, 1381 phy_interface_t interface) 1382 { 1383 struct dsa_port *dp = dsa_phylink_to_port(config); 1384 1385 sja1105_inhibit_tx(dp->ds->priv, BIT(dp->index), true); 1386 } 1387 1388 static void sja1105_mac_link_up(struct phylink_config *config, 1389 struct phy_device *phydev, 1390 unsigned int mode, 1391 phy_interface_t interface, 1392 int speed, int duplex, 1393 bool tx_pause, bool rx_pause) 1394 { 1395 struct dsa_port *dp = dsa_phylink_to_port(config); 1396 struct sja1105_private *priv = dp->ds->priv; 1397 int port = dp->index; 1398 1399 sja1105_adjust_port_config(priv, port, speed); 1400 1401 sja1105_inhibit_tx(priv, BIT(port), false); 1402 } 1403 1404 static void sja1105_phylink_get_caps(struct dsa_switch *ds, int port, 1405 struct phylink_config *config) 1406 { 1407 struct sja1105_private *priv = ds->priv; 1408 struct sja1105_xmii_params_entry *mii; 1409 phy_interface_t phy_mode; 1410 1411 phy_mode = priv->phy_mode[port]; 1412 if (phy_mode == PHY_INTERFACE_MODE_SGMII || 1413 phy_mode == PHY_INTERFACE_MODE_2500BASEX) { 1414 /* Changing the PHY mode on SERDES ports is possible and makes 1415 * sense, because that is done through the XPCS. We allow 1416 * changes between SGMII and 2500base-X. 1417 */ 1418 if (priv->info->supports_sgmii[port]) 1419 __set_bit(PHY_INTERFACE_MODE_SGMII, 1420 config->supported_interfaces); 1421 1422 if (priv->info->supports_2500basex[port]) 1423 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 1424 config->supported_interfaces); 1425 } else { 1426 /* The SJA1105 MAC programming model is through the static 1427 * config (the xMII Mode table cannot be dynamically 1428 * reconfigured), and we have to program that early. 1429 */ 1430 __set_bit(phy_mode, config->supported_interfaces); 1431 } 1432 1433 /* The MAC does not support pause frames, and also doesn't 1434 * support half-duplex traffic modes. 1435 */ 1436 config->mac_capabilities = MAC_10FD | MAC_100FD; 1437 1438 mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries; 1439 if (mii->xmii_mode[port] == XMII_MODE_RGMII || 1440 mii->xmii_mode[port] == XMII_MODE_SGMII) 1441 config->mac_capabilities |= MAC_1000FD; 1442 1443 if (priv->info->supports_2500basex[port]) 1444 config->mac_capabilities |= MAC_2500FD; 1445 } 1446 1447 static int 1448 sja1105_find_static_fdb_entry(struct sja1105_private *priv, int port, 1449 const struct sja1105_l2_lookup_entry *requested) 1450 { 1451 struct sja1105_l2_lookup_entry *l2_lookup; 1452 struct sja1105_table *table; 1453 int i; 1454 1455 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP]; 1456 l2_lookup = table->entries; 1457 1458 for (i = 0; i < table->entry_count; i++) 1459 if (l2_lookup[i].macaddr == requested->macaddr && 1460 l2_lookup[i].vlanid == requested->vlanid && 1461 l2_lookup[i].destports & BIT(port)) 1462 return i; 1463 1464 return -1; 1465 } 1466 1467 /* We want FDB entries added statically through the bridge command to persist 1468 * across switch resets, which are a common thing during normal SJA1105 1469 * operation. So we have to back them up in the static configuration tables 1470 * and hence apply them on next static config upload... yay! 1471 */ 1472 static int 1473 sja1105_static_fdb_change(struct sja1105_private *priv, int port, 1474 const struct sja1105_l2_lookup_entry *requested, 1475 bool keep) 1476 { 1477 struct sja1105_l2_lookup_entry *l2_lookup; 1478 struct sja1105_table *table; 1479 int rc, match; 1480 1481 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP]; 1482 1483 match = sja1105_find_static_fdb_entry(priv, port, requested); 1484 if (match < 0) { 1485 /* Can't delete a missing entry. */ 1486 if (!keep) 1487 return 0; 1488 1489 /* No match => new entry */ 1490 rc = sja1105_table_resize(table, table->entry_count + 1); 1491 if (rc) 1492 return rc; 1493 1494 match = table->entry_count - 1; 1495 } 1496 1497 /* Assign pointer after the resize (it may be new memory) */ 1498 l2_lookup = table->entries; 1499 1500 /* We have a match. 1501 * If the job was to add this FDB entry, it's already done (mostly 1502 * anyway, since the port forwarding mask may have changed, case in 1503 * which we update it). 1504 * Otherwise we have to delete it. 1505 */ 1506 if (keep) { 1507 l2_lookup[match] = *requested; 1508 return 0; 1509 } 1510 1511 /* To remove, the strategy is to overwrite the element with 1512 * the last one, and then reduce the array size by 1 1513 */ 1514 l2_lookup[match] = l2_lookup[table->entry_count - 1]; 1515 return sja1105_table_resize(table, table->entry_count - 1); 1516 } 1517 1518 /* First-generation switches have a 4-way set associative TCAM that 1519 * holds the FDB entries. An FDB index spans from 0 to 1023 and is comprised of 1520 * a "bin" (grouping of 4 entries) and a "way" (an entry within a bin). 1521 * For the placement of a newly learnt FDB entry, the switch selects the bin 1522 * based on a hash function, and the way within that bin incrementally. 1523 */ 1524 static int sja1105et_fdb_index(int bin, int way) 1525 { 1526 return bin * SJA1105ET_FDB_BIN_SIZE + way; 1527 } 1528 1529 static int sja1105et_is_fdb_entry_in_bin(struct sja1105_private *priv, int bin, 1530 const u8 *addr, u16 vid, 1531 struct sja1105_l2_lookup_entry *match, 1532 int *last_unused) 1533 { 1534 int way; 1535 1536 for (way = 0; way < SJA1105ET_FDB_BIN_SIZE; way++) { 1537 struct sja1105_l2_lookup_entry l2_lookup = {0}; 1538 int index = sja1105et_fdb_index(bin, way); 1539 1540 /* Skip unused entries, optionally marking them 1541 * into the return value 1542 */ 1543 if (sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, 1544 index, &l2_lookup)) { 1545 if (last_unused) 1546 *last_unused = way; 1547 continue; 1548 } 1549 1550 if (l2_lookup.macaddr == ether_addr_to_u64(addr) && 1551 l2_lookup.vlanid == vid) { 1552 if (match) 1553 *match = l2_lookup; 1554 return way; 1555 } 1556 } 1557 /* Return an invalid entry index if not found */ 1558 return -1; 1559 } 1560 1561 int sja1105et_fdb_add(struct dsa_switch *ds, int port, 1562 const unsigned char *addr, u16 vid) 1563 { 1564 struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp; 1565 struct sja1105_private *priv = ds->priv; 1566 struct device *dev = ds->dev; 1567 int last_unused = -1; 1568 int start, end, i; 1569 int bin, way, rc; 1570 1571 bin = sja1105et_fdb_hash(priv, addr, vid); 1572 1573 way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid, 1574 &l2_lookup, &last_unused); 1575 if (way >= 0) { 1576 /* We have an FDB entry. Is our port in the destination 1577 * mask? If yes, we need to do nothing. If not, we need 1578 * to rewrite the entry by adding this port to it. 1579 */ 1580 if ((l2_lookup.destports & BIT(port)) && l2_lookup.lockeds) 1581 return 0; 1582 l2_lookup.destports |= BIT(port); 1583 } else { 1584 int index = sja1105et_fdb_index(bin, way); 1585 1586 /* We don't have an FDB entry. We construct a new one and 1587 * try to find a place for it within the FDB table. 1588 */ 1589 l2_lookup.macaddr = ether_addr_to_u64(addr); 1590 l2_lookup.destports = BIT(port); 1591 l2_lookup.vlanid = vid; 1592 1593 if (last_unused >= 0) { 1594 way = last_unused; 1595 } else { 1596 /* Bin is full, need to evict somebody. 1597 * Choose victim at random. If you get these messages 1598 * often, you may need to consider changing the 1599 * distribution function: 1600 * static_config[BLK_IDX_L2_LOOKUP_PARAMS].entries->poly 1601 */ 1602 get_random_bytes(&way, sizeof(u8)); 1603 way %= SJA1105ET_FDB_BIN_SIZE; 1604 dev_warn(dev, "Warning, FDB bin %d full while adding entry for %pM. Evicting entry %u.\n", 1605 bin, addr, way); 1606 /* Evict entry */ 1607 sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, 1608 index, NULL, false); 1609 } 1610 } 1611 l2_lookup.lockeds = true; 1612 l2_lookup.index = sja1105et_fdb_index(bin, way); 1613 1614 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, 1615 l2_lookup.index, &l2_lookup, 1616 true); 1617 if (rc < 0) 1618 return rc; 1619 1620 /* Invalidate a dynamically learned entry if that exists */ 1621 start = sja1105et_fdb_index(bin, 0); 1622 end = sja1105et_fdb_index(bin, way); 1623 1624 for (i = start; i < end; i++) { 1625 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, 1626 i, &tmp); 1627 if (rc == -ENOENT) 1628 continue; 1629 if (rc) 1630 return rc; 1631 1632 if (tmp.macaddr != ether_addr_to_u64(addr) || tmp.vlanid != vid) 1633 continue; 1634 1635 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, 1636 i, NULL, false); 1637 if (rc) 1638 return rc; 1639 1640 break; 1641 } 1642 1643 return sja1105_static_fdb_change(priv, port, &l2_lookup, true); 1644 } 1645 1646 int sja1105et_fdb_del(struct dsa_switch *ds, int port, 1647 const unsigned char *addr, u16 vid) 1648 { 1649 struct sja1105_l2_lookup_entry l2_lookup = {0}; 1650 struct sja1105_private *priv = ds->priv; 1651 int index, bin, way, rc; 1652 bool keep; 1653 1654 bin = sja1105et_fdb_hash(priv, addr, vid); 1655 way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid, 1656 &l2_lookup, NULL); 1657 if (way < 0) 1658 return 0; 1659 index = sja1105et_fdb_index(bin, way); 1660 1661 /* We have an FDB entry. Is our port in the destination mask? If yes, 1662 * we need to remove it. If the resulting port mask becomes empty, we 1663 * need to completely evict the FDB entry. 1664 * Otherwise we just write it back. 1665 */ 1666 l2_lookup.destports &= ~BIT(port); 1667 1668 if (l2_lookup.destports) 1669 keep = true; 1670 else 1671 keep = false; 1672 1673 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, 1674 index, &l2_lookup, keep); 1675 if (rc < 0) 1676 return rc; 1677 1678 return sja1105_static_fdb_change(priv, port, &l2_lookup, keep); 1679 } 1680 1681 int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port, 1682 const unsigned char *addr, u16 vid) 1683 { 1684 struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp; 1685 struct sja1105_private *priv = ds->priv; 1686 int rc, i; 1687 1688 /* Search for an existing entry in the FDB table */ 1689 l2_lookup.macaddr = ether_addr_to_u64(addr); 1690 l2_lookup.vlanid = vid; 1691 l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0); 1692 l2_lookup.mask_vlanid = VLAN_VID_MASK; 1693 l2_lookup.destports = BIT(port); 1694 1695 tmp = l2_lookup; 1696 1697 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, 1698 SJA1105_SEARCH, &tmp); 1699 if (rc == 0 && tmp.index != SJA1105_MAX_L2_LOOKUP_COUNT - 1) { 1700 /* Found a static entry and this port is already in the entry's 1701 * port mask => job done 1702 */ 1703 if ((tmp.destports & BIT(port)) && tmp.lockeds) 1704 return 0; 1705 1706 l2_lookup = tmp; 1707 1708 /* l2_lookup.index is populated by the switch in case it 1709 * found something. 1710 */ 1711 l2_lookup.destports |= BIT(port); 1712 goto skip_finding_an_index; 1713 } 1714 1715 /* Not found, so try to find an unused spot in the FDB. 1716 * This is slightly inefficient because the strategy is knock-knock at 1717 * every possible position from 0 to 1023. 1718 */ 1719 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) { 1720 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, 1721 i, NULL); 1722 if (rc < 0) 1723 break; 1724 } 1725 if (i == SJA1105_MAX_L2_LOOKUP_COUNT) { 1726 dev_err(ds->dev, "FDB is full, cannot add entry.\n"); 1727 return -EINVAL; 1728 } 1729 l2_lookup.index = i; 1730 1731 skip_finding_an_index: 1732 l2_lookup.lockeds = true; 1733 1734 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, 1735 l2_lookup.index, &l2_lookup, 1736 true); 1737 if (rc < 0) 1738 return rc; 1739 1740 /* The switch learns dynamic entries and looks up the FDB left to 1741 * right. It is possible that our addition was concurrent with the 1742 * dynamic learning of the same address, so now that the static entry 1743 * has been installed, we are certain that address learning for this 1744 * particular address has been turned off, so the dynamic entry either 1745 * is in the FDB at an index smaller than the static one, or isn't (it 1746 * can also be at a larger index, but in that case it is inactive 1747 * because the static FDB entry will match first, and the dynamic one 1748 * will eventually age out). Search for a dynamically learned address 1749 * prior to our static one and invalidate it. 1750 */ 1751 tmp = l2_lookup; 1752 1753 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, 1754 SJA1105_SEARCH, &tmp); 1755 if (rc < 0) { 1756 dev_err(ds->dev, 1757 "port %d failed to read back entry for %pM vid %d: %pe\n", 1758 port, addr, vid, ERR_PTR(rc)); 1759 return rc; 1760 } 1761 1762 if (tmp.index < l2_lookup.index) { 1763 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, 1764 tmp.index, NULL, false); 1765 if (rc < 0) 1766 return rc; 1767 } 1768 1769 return sja1105_static_fdb_change(priv, port, &l2_lookup, true); 1770 } 1771 1772 int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port, 1773 const unsigned char *addr, u16 vid) 1774 { 1775 struct sja1105_l2_lookup_entry l2_lookup = {0}; 1776 struct sja1105_private *priv = ds->priv; 1777 bool keep; 1778 int rc; 1779 1780 l2_lookup.macaddr = ether_addr_to_u64(addr); 1781 l2_lookup.vlanid = vid; 1782 l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0); 1783 l2_lookup.mask_vlanid = VLAN_VID_MASK; 1784 l2_lookup.destports = BIT(port); 1785 1786 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, 1787 SJA1105_SEARCH, &l2_lookup); 1788 if (rc < 0) 1789 return 0; 1790 1791 l2_lookup.destports &= ~BIT(port); 1792 1793 /* Decide whether we remove just this port from the FDB entry, 1794 * or if we remove it completely. 1795 */ 1796 if (l2_lookup.destports) 1797 keep = true; 1798 else 1799 keep = false; 1800 1801 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, 1802 l2_lookup.index, &l2_lookup, keep); 1803 if (rc < 0) 1804 return rc; 1805 1806 return sja1105_static_fdb_change(priv, port, &l2_lookup, keep); 1807 } 1808 1809 static int sja1105_fdb_add(struct dsa_switch *ds, int port, 1810 const unsigned char *addr, u16 vid, 1811 struct dsa_db db) 1812 { 1813 struct sja1105_private *priv = ds->priv; 1814 int rc; 1815 1816 if (!vid) { 1817 switch (db.type) { 1818 case DSA_DB_PORT: 1819 vid = dsa_tag_8021q_standalone_vid(db.dp); 1820 break; 1821 case DSA_DB_BRIDGE: 1822 vid = dsa_tag_8021q_bridge_vid(db.bridge.num); 1823 break; 1824 default: 1825 return -EOPNOTSUPP; 1826 } 1827 } 1828 1829 mutex_lock(&priv->fdb_lock); 1830 rc = priv->info->fdb_add_cmd(ds, port, addr, vid); 1831 mutex_unlock(&priv->fdb_lock); 1832 1833 return rc; 1834 } 1835 1836 static int __sja1105_fdb_del(struct dsa_switch *ds, int port, 1837 const unsigned char *addr, u16 vid, 1838 struct dsa_db db) 1839 { 1840 struct sja1105_private *priv = ds->priv; 1841 1842 if (!vid) { 1843 switch (db.type) { 1844 case DSA_DB_PORT: 1845 vid = dsa_tag_8021q_standalone_vid(db.dp); 1846 break; 1847 case DSA_DB_BRIDGE: 1848 vid = dsa_tag_8021q_bridge_vid(db.bridge.num); 1849 break; 1850 default: 1851 return -EOPNOTSUPP; 1852 } 1853 } 1854 1855 return priv->info->fdb_del_cmd(ds, port, addr, vid); 1856 } 1857 1858 static int sja1105_fdb_del(struct dsa_switch *ds, int port, 1859 const unsigned char *addr, u16 vid, 1860 struct dsa_db db) 1861 { 1862 struct sja1105_private *priv = ds->priv; 1863 int rc; 1864 1865 mutex_lock(&priv->fdb_lock); 1866 rc = __sja1105_fdb_del(ds, port, addr, vid, db); 1867 mutex_unlock(&priv->fdb_lock); 1868 1869 return rc; 1870 } 1871 1872 static int sja1105_fdb_dump(struct dsa_switch *ds, int port, 1873 dsa_fdb_dump_cb_t *cb, void *data) 1874 { 1875 struct sja1105_private *priv = ds->priv; 1876 struct device *dev = ds->dev; 1877 int i; 1878 1879 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) { 1880 struct sja1105_l2_lookup_entry l2_lookup = {0}; 1881 u8 macaddr[ETH_ALEN]; 1882 int rc; 1883 1884 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, 1885 i, &l2_lookup); 1886 /* No fdb entry at i, not an issue */ 1887 if (rc == -ENOENT) 1888 continue; 1889 if (rc) { 1890 dev_err(dev, "Failed to dump FDB: %d\n", rc); 1891 return rc; 1892 } 1893 1894 /* FDB dump callback is per port. This means we have to 1895 * disregard a valid entry if it's not for this port, even if 1896 * only to revisit it later. This is inefficient because the 1897 * 1024-sized FDB table needs to be traversed 4 times through 1898 * SPI during a 'bridge fdb show' command. 1899 */ 1900 if (!(l2_lookup.destports & BIT(port))) 1901 continue; 1902 1903 u64_to_ether_addr(l2_lookup.macaddr, macaddr); 1904 1905 /* Hardware FDB is shared for fdb and mdb, "bridge fdb show" 1906 * only wants to see unicast 1907 */ 1908 if (is_multicast_ether_addr(macaddr)) 1909 continue; 1910 1911 /* We need to hide the dsa_8021q VLANs from the user. */ 1912 if (vid_is_dsa_8021q(l2_lookup.vlanid)) 1913 l2_lookup.vlanid = 0; 1914 rc = cb(macaddr, l2_lookup.vlanid, l2_lookup.lockeds, data); 1915 if (rc) 1916 return rc; 1917 } 1918 return 0; 1919 } 1920 1921 static void sja1105_fast_age(struct dsa_switch *ds, int port) 1922 { 1923 struct dsa_port *dp = dsa_to_port(ds, port); 1924 struct sja1105_private *priv = ds->priv; 1925 struct dsa_db db = { 1926 .type = DSA_DB_BRIDGE, 1927 .bridge = { 1928 .dev = dsa_port_bridge_dev_get(dp), 1929 .num = dsa_port_bridge_num_get(dp), 1930 }, 1931 }; 1932 int i; 1933 1934 mutex_lock(&priv->fdb_lock); 1935 1936 for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) { 1937 struct sja1105_l2_lookup_entry l2_lookup = {0}; 1938 u8 macaddr[ETH_ALEN]; 1939 int rc; 1940 1941 rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP, 1942 i, &l2_lookup); 1943 /* No fdb entry at i, not an issue */ 1944 if (rc == -ENOENT) 1945 continue; 1946 if (rc) { 1947 dev_err(ds->dev, "Failed to read FDB: %pe\n", 1948 ERR_PTR(rc)); 1949 break; 1950 } 1951 1952 if (!(l2_lookup.destports & BIT(port))) 1953 continue; 1954 1955 /* Don't delete static FDB entries */ 1956 if (l2_lookup.lockeds) 1957 continue; 1958 1959 u64_to_ether_addr(l2_lookup.macaddr, macaddr); 1960 1961 rc = __sja1105_fdb_del(ds, port, macaddr, l2_lookup.vlanid, db); 1962 if (rc) { 1963 dev_err(ds->dev, 1964 "Failed to delete FDB entry %pM vid %lld: %pe\n", 1965 macaddr, l2_lookup.vlanid, ERR_PTR(rc)); 1966 break; 1967 } 1968 } 1969 1970 mutex_unlock(&priv->fdb_lock); 1971 } 1972 1973 static int sja1105_mdb_add(struct dsa_switch *ds, int port, 1974 const struct switchdev_obj_port_mdb *mdb, 1975 struct dsa_db db) 1976 { 1977 return sja1105_fdb_add(ds, port, mdb->addr, mdb->vid, db); 1978 } 1979 1980 static int sja1105_mdb_del(struct dsa_switch *ds, int port, 1981 const struct switchdev_obj_port_mdb *mdb, 1982 struct dsa_db db) 1983 { 1984 return sja1105_fdb_del(ds, port, mdb->addr, mdb->vid, db); 1985 } 1986 1987 /* Common function for unicast and broadcast flood configuration. 1988 * Flooding is configured between each {ingress, egress} port pair, and since 1989 * the bridge's semantics are those of "egress flooding", it means we must 1990 * enable flooding towards this port from all ingress ports that are in the 1991 * same forwarding domain. 1992 */ 1993 static int sja1105_manage_flood_domains(struct sja1105_private *priv) 1994 { 1995 struct sja1105_l2_forwarding_entry *l2_fwd; 1996 struct dsa_switch *ds = priv->ds; 1997 int from, to, rc; 1998 1999 l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries; 2000 2001 for (from = 0; from < ds->num_ports; from++) { 2002 u64 fl_domain = 0, bc_domain = 0; 2003 2004 for (to = 0; to < priv->ds->num_ports; to++) { 2005 if (!sja1105_can_forward(l2_fwd, from, to)) 2006 continue; 2007 2008 if (priv->ucast_egress_floods & BIT(to)) 2009 fl_domain |= BIT(to); 2010 if (priv->bcast_egress_floods & BIT(to)) 2011 bc_domain |= BIT(to); 2012 } 2013 2014 /* Nothing changed, nothing to do */ 2015 if (l2_fwd[from].fl_domain == fl_domain && 2016 l2_fwd[from].bc_domain == bc_domain) 2017 continue; 2018 2019 l2_fwd[from].fl_domain = fl_domain; 2020 l2_fwd[from].bc_domain = bc_domain; 2021 2022 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING, 2023 from, &l2_fwd[from], true); 2024 if (rc < 0) 2025 return rc; 2026 } 2027 2028 return 0; 2029 } 2030 2031 static int sja1105_bridge_member(struct dsa_switch *ds, int port, 2032 struct dsa_bridge bridge, bool member) 2033 { 2034 struct sja1105_l2_forwarding_entry *l2_fwd; 2035 struct sja1105_private *priv = ds->priv; 2036 int i, rc; 2037 2038 l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries; 2039 2040 for (i = 0; i < ds->num_ports; i++) { 2041 /* Add this port to the forwarding matrix of the 2042 * other ports in the same bridge, and viceversa. 2043 */ 2044 if (!dsa_is_user_port(ds, i)) 2045 continue; 2046 /* For the ports already under the bridge, only one thing needs 2047 * to be done, and that is to add this port to their 2048 * reachability domain. So we can perform the SPI write for 2049 * them immediately. However, for this port itself (the one 2050 * that is new to the bridge), we need to add all other ports 2051 * to its reachability domain. So we do that incrementally in 2052 * this loop, and perform the SPI write only at the end, once 2053 * the domain contains all other bridge ports. 2054 */ 2055 if (i == port) 2056 continue; 2057 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 2058 continue; 2059 sja1105_port_allow_traffic(l2_fwd, i, port, member); 2060 sja1105_port_allow_traffic(l2_fwd, port, i, member); 2061 2062 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING, 2063 i, &l2_fwd[i], true); 2064 if (rc < 0) 2065 return rc; 2066 } 2067 2068 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING, 2069 port, &l2_fwd[port], true); 2070 if (rc) 2071 return rc; 2072 2073 rc = sja1105_commit_pvid(ds, port); 2074 if (rc) 2075 return rc; 2076 2077 return sja1105_manage_flood_domains(priv); 2078 } 2079 2080 static void sja1105_bridge_stp_state_set(struct dsa_switch *ds, int port, 2081 u8 state) 2082 { 2083 struct dsa_port *dp = dsa_to_port(ds, port); 2084 struct sja1105_private *priv = ds->priv; 2085 struct sja1105_mac_config_entry *mac; 2086 2087 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; 2088 2089 switch (state) { 2090 case BR_STATE_DISABLED: 2091 case BR_STATE_BLOCKING: 2092 /* From UM10944 description of DRPDTAG (why put this there?): 2093 * "Management traffic flows to the port regardless of the state 2094 * of the INGRESS flag". So BPDUs are still be allowed to pass. 2095 * At the moment no difference between DISABLED and BLOCKING. 2096 */ 2097 mac[port].ingress = false; 2098 mac[port].egress = false; 2099 mac[port].dyn_learn = false; 2100 break; 2101 case BR_STATE_LISTENING: 2102 mac[port].ingress = true; 2103 mac[port].egress = false; 2104 mac[port].dyn_learn = false; 2105 break; 2106 case BR_STATE_LEARNING: 2107 mac[port].ingress = true; 2108 mac[port].egress = false; 2109 mac[port].dyn_learn = dp->learning; 2110 break; 2111 case BR_STATE_FORWARDING: 2112 mac[port].ingress = true; 2113 mac[port].egress = true; 2114 mac[port].dyn_learn = dp->learning; 2115 break; 2116 default: 2117 dev_err(ds->dev, "invalid STP state: %d\n", state); 2118 return; 2119 } 2120 2121 sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port, 2122 &mac[port], true); 2123 } 2124 2125 static int sja1105_bridge_join(struct dsa_switch *ds, int port, 2126 struct dsa_bridge bridge, 2127 bool *tx_fwd_offload, 2128 struct netlink_ext_ack *extack) 2129 { 2130 int rc; 2131 2132 rc = sja1105_bridge_member(ds, port, bridge, true); 2133 if (rc) 2134 return rc; 2135 2136 rc = dsa_tag_8021q_bridge_join(ds, port, bridge, tx_fwd_offload, 2137 extack); 2138 if (rc) { 2139 sja1105_bridge_member(ds, port, bridge, false); 2140 return rc; 2141 } 2142 2143 return 0; 2144 } 2145 2146 static void sja1105_bridge_leave(struct dsa_switch *ds, int port, 2147 struct dsa_bridge bridge) 2148 { 2149 dsa_tag_8021q_bridge_leave(ds, port, bridge); 2150 sja1105_bridge_member(ds, port, bridge, false); 2151 } 2152 2153 /* Port 0 (the uC port) does not have CBS shapers */ 2154 #define SJA1110_FIXED_CBS(port, prio) ((((port) - 1) * SJA1105_NUM_TC) + (prio)) 2155 2156 static int sja1105_find_cbs_shaper(struct sja1105_private *priv, 2157 int port, int prio) 2158 { 2159 int i; 2160 2161 if (priv->info->fixed_cbs_mapping) { 2162 i = SJA1110_FIXED_CBS(port, prio); 2163 if (i >= 0 && i < priv->info->num_cbs_shapers) 2164 return i; 2165 2166 return -1; 2167 } 2168 2169 for (i = 0; i < priv->info->num_cbs_shapers; i++) 2170 if (priv->cbs[i].port == port && priv->cbs[i].prio == prio) 2171 return i; 2172 2173 return -1; 2174 } 2175 2176 static int sja1105_find_unused_cbs_shaper(struct sja1105_private *priv) 2177 { 2178 int i; 2179 2180 if (priv->info->fixed_cbs_mapping) 2181 return -1; 2182 2183 for (i = 0; i < priv->info->num_cbs_shapers; i++) 2184 if (!priv->cbs[i].idle_slope && !priv->cbs[i].send_slope) 2185 return i; 2186 2187 return -1; 2188 } 2189 2190 static int sja1105_delete_cbs_shaper(struct sja1105_private *priv, int port, 2191 int prio) 2192 { 2193 int i; 2194 2195 for (i = 0; i < priv->info->num_cbs_shapers; i++) { 2196 struct sja1105_cbs_entry *cbs = &priv->cbs[i]; 2197 2198 if (cbs->port == port && cbs->prio == prio) { 2199 memset(cbs, 0, sizeof(*cbs)); 2200 return sja1105_dynamic_config_write(priv, BLK_IDX_CBS, 2201 i, cbs, true); 2202 } 2203 } 2204 2205 return 0; 2206 } 2207 2208 static int sja1105_setup_tc_cbs(struct dsa_switch *ds, int port, 2209 struct tc_cbs_qopt_offload *offload) 2210 { 2211 struct sja1105_private *priv = ds->priv; 2212 struct sja1105_cbs_entry *cbs; 2213 s64 port_transmit_rate_kbps; 2214 int index; 2215 2216 if (!offload->enable) 2217 return sja1105_delete_cbs_shaper(priv, port, offload->queue); 2218 2219 /* The user may be replacing an existing shaper */ 2220 index = sja1105_find_cbs_shaper(priv, port, offload->queue); 2221 if (index < 0) { 2222 /* That isn't the case - see if we can allocate a new one */ 2223 index = sja1105_find_unused_cbs_shaper(priv); 2224 if (index < 0) 2225 return -ENOSPC; 2226 } 2227 2228 cbs = &priv->cbs[index]; 2229 cbs->port = port; 2230 cbs->prio = offload->queue; 2231 /* locredit and sendslope are negative by definition. In hardware, 2232 * positive values must be provided, and the negative sign is implicit. 2233 */ 2234 cbs->credit_hi = offload->hicredit; 2235 cbs->credit_lo = abs(offload->locredit); 2236 /* User space is in kbits/sec, while the hardware in bytes/sec times 2237 * link speed. Since the given offload->sendslope is good only for the 2238 * current link speed anyway, and user space is likely to reprogram it 2239 * when that changes, don't even bother to track the port's link speed, 2240 * but deduce the port transmit rate from idleslope - sendslope. 2241 */ 2242 port_transmit_rate_kbps = offload->idleslope - offload->sendslope; 2243 cbs->idle_slope = div_s64(offload->idleslope * BYTES_PER_KBIT, 2244 port_transmit_rate_kbps); 2245 cbs->send_slope = div_s64(abs(offload->sendslope * BYTES_PER_KBIT), 2246 port_transmit_rate_kbps); 2247 /* Convert the negative values from 64-bit 2's complement 2248 * to 32-bit 2's complement (for the case of 0x80000000 whose 2249 * negative is still negative). 2250 */ 2251 cbs->credit_lo &= GENMASK_ULL(31, 0); 2252 cbs->send_slope &= GENMASK_ULL(31, 0); 2253 2254 return sja1105_dynamic_config_write(priv, BLK_IDX_CBS, index, cbs, 2255 true); 2256 } 2257 2258 static int sja1105_reload_cbs(struct sja1105_private *priv) 2259 { 2260 int rc = 0, i; 2261 2262 /* The credit based shapers are only allocated if 2263 * CONFIG_NET_SCH_CBS is enabled. 2264 */ 2265 if (!priv->cbs) 2266 return 0; 2267 2268 for (i = 0; i < priv->info->num_cbs_shapers; i++) { 2269 struct sja1105_cbs_entry *cbs = &priv->cbs[i]; 2270 2271 if (!cbs->idle_slope && !cbs->send_slope) 2272 continue; 2273 2274 rc = sja1105_dynamic_config_write(priv, BLK_IDX_CBS, i, cbs, 2275 true); 2276 if (rc) 2277 break; 2278 } 2279 2280 return rc; 2281 } 2282 2283 static const char * const sja1105_reset_reasons[] = { 2284 [SJA1105_VLAN_FILTERING] = "VLAN filtering", 2285 [SJA1105_AGEING_TIME] = "Ageing time", 2286 [SJA1105_SCHEDULING] = "Time-aware scheduling", 2287 [SJA1105_BEST_EFFORT_POLICING] = "Best-effort policing", 2288 [SJA1105_VIRTUAL_LINKS] = "Virtual links", 2289 }; 2290 2291 /* For situations where we need to change a setting at runtime that is only 2292 * available through the static configuration, resetting the switch in order 2293 * to upload the new static config is unavoidable. Back up the settings we 2294 * modify at runtime (currently only MAC) and restore them after uploading, 2295 * such that this operation is relatively seamless. 2296 */ 2297 int sja1105_static_config_reload(struct sja1105_private *priv, 2298 enum sja1105_reset_reason reason) 2299 { 2300 struct ptp_system_timestamp ptp_sts_before; 2301 struct ptp_system_timestamp ptp_sts_after; 2302 int speed_mbps[SJA1105_MAX_NUM_PORTS]; 2303 u16 bmcr[SJA1105_MAX_NUM_PORTS] = {0}; 2304 struct sja1105_mac_config_entry *mac; 2305 struct dsa_switch *ds = priv->ds; 2306 s64 t1, t2, t3, t4; 2307 s64 t12, t34; 2308 int rc, i; 2309 s64 now; 2310 2311 mutex_lock(&priv->fdb_lock); 2312 mutex_lock(&priv->mgmt_lock); 2313 2314 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; 2315 2316 /* Back up the dynamic link speed changed by sja1105_adjust_port_config 2317 * in order to temporarily restore it to SJA1105_SPEED_AUTO - which the 2318 * switch wants to see in the static config in order to allow us to 2319 * change it through the dynamic interface later. 2320 */ 2321 for (i = 0; i < ds->num_ports; i++) { 2322 speed_mbps[i] = sja1105_port_speed_to_ethtool(priv, 2323 mac[i].speed); 2324 mac[i].speed = priv->info->port_speed[SJA1105_SPEED_AUTO]; 2325 2326 if (priv->xpcs[i]) 2327 bmcr[i] = mdiobus_c45_read(priv->mdio_pcs, i, 2328 MDIO_MMD_VEND2, MDIO_CTRL1); 2329 } 2330 2331 /* No PTP operations can run right now */ 2332 mutex_lock(&priv->ptp_data.lock); 2333 2334 rc = __sja1105_ptp_gettimex(ds, &now, &ptp_sts_before); 2335 if (rc < 0) { 2336 mutex_unlock(&priv->ptp_data.lock); 2337 goto out; 2338 } 2339 2340 /* Reset switch and send updated static configuration */ 2341 rc = sja1105_static_config_upload(priv); 2342 if (rc < 0) { 2343 mutex_unlock(&priv->ptp_data.lock); 2344 goto out; 2345 } 2346 2347 rc = __sja1105_ptp_settime(ds, 0, &ptp_sts_after); 2348 if (rc < 0) { 2349 mutex_unlock(&priv->ptp_data.lock); 2350 goto out; 2351 } 2352 2353 t1 = timespec64_to_ns(&ptp_sts_before.pre_ts); 2354 t2 = timespec64_to_ns(&ptp_sts_before.post_ts); 2355 t3 = timespec64_to_ns(&ptp_sts_after.pre_ts); 2356 t4 = timespec64_to_ns(&ptp_sts_after.post_ts); 2357 /* Mid point, corresponds to pre-reset PTPCLKVAL */ 2358 t12 = t1 + (t2 - t1) / 2; 2359 /* Mid point, corresponds to post-reset PTPCLKVAL, aka 0 */ 2360 t34 = t3 + (t4 - t3) / 2; 2361 /* Advance PTPCLKVAL by the time it took since its readout */ 2362 now += (t34 - t12); 2363 2364 __sja1105_ptp_adjtime(ds, now); 2365 2366 mutex_unlock(&priv->ptp_data.lock); 2367 2368 dev_info(priv->ds->dev, 2369 "Reset switch and programmed static config. Reason: %s\n", 2370 sja1105_reset_reasons[reason]); 2371 2372 /* Configure the CGU (PLLs) for MII and RMII PHYs. 2373 * For these interfaces there is no dynamic configuration 2374 * needed, since PLLs have same settings at all speeds. 2375 */ 2376 if (priv->info->clocking_setup) { 2377 rc = priv->info->clocking_setup(priv); 2378 if (rc < 0) 2379 goto out; 2380 } 2381 2382 for (i = 0; i < ds->num_ports; i++) { 2383 struct dw_xpcs *xpcs = priv->xpcs[i]; 2384 unsigned int neg_mode; 2385 2386 rc = sja1105_adjust_port_config(priv, i, speed_mbps[i]); 2387 if (rc < 0) 2388 goto out; 2389 2390 if (!xpcs) 2391 continue; 2392 2393 if (bmcr[i] & BMCR_ANENABLE) 2394 neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED; 2395 else 2396 neg_mode = PHYLINK_PCS_NEG_OUTBAND; 2397 2398 rc = xpcs_do_config(xpcs, priv->phy_mode[i], NULL, neg_mode); 2399 if (rc < 0) 2400 goto out; 2401 2402 if (neg_mode == PHYLINK_PCS_NEG_OUTBAND) { 2403 int speed = SPEED_UNKNOWN; 2404 2405 if (priv->phy_mode[i] == PHY_INTERFACE_MODE_2500BASEX) 2406 speed = SPEED_2500; 2407 else if (bmcr[i] & BMCR_SPEED1000) 2408 speed = SPEED_1000; 2409 else if (bmcr[i] & BMCR_SPEED100) 2410 speed = SPEED_100; 2411 else 2412 speed = SPEED_10; 2413 2414 xpcs_link_up(&xpcs->pcs, neg_mode, priv->phy_mode[i], 2415 speed, DUPLEX_FULL); 2416 } 2417 } 2418 2419 rc = sja1105_reload_cbs(priv); 2420 if (rc < 0) 2421 goto out; 2422 out: 2423 mutex_unlock(&priv->mgmt_lock); 2424 mutex_unlock(&priv->fdb_lock); 2425 2426 return rc; 2427 } 2428 2429 static enum dsa_tag_protocol 2430 sja1105_get_tag_protocol(struct dsa_switch *ds, int port, 2431 enum dsa_tag_protocol mp) 2432 { 2433 struct sja1105_private *priv = ds->priv; 2434 2435 return priv->info->tag_proto; 2436 } 2437 2438 /* The TPID setting belongs to the General Parameters table, 2439 * which can only be partially reconfigured at runtime (and not the TPID). 2440 * So a switch reset is required. 2441 */ 2442 int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled, 2443 struct netlink_ext_ack *extack) 2444 { 2445 struct sja1105_general_params_entry *general_params; 2446 struct sja1105_private *priv = ds->priv; 2447 struct sja1105_table *table; 2448 struct sja1105_rule *rule; 2449 u16 tpid, tpid2; 2450 int rc; 2451 2452 list_for_each_entry(rule, &priv->flow_block.rules, list) { 2453 if (rule->type == SJA1105_RULE_VL) { 2454 NL_SET_ERR_MSG_MOD(extack, 2455 "Cannot change VLAN filtering with active VL rules"); 2456 return -EBUSY; 2457 } 2458 } 2459 2460 if (enabled) { 2461 /* Enable VLAN filtering. */ 2462 tpid = ETH_P_8021Q; 2463 tpid2 = ETH_P_8021AD; 2464 } else { 2465 /* Disable VLAN filtering. */ 2466 tpid = ETH_P_SJA1105; 2467 tpid2 = ETH_P_SJA1105; 2468 } 2469 2470 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS]; 2471 general_params = table->entries; 2472 /* EtherType used to identify inner tagged (C-tag) VLAN traffic */ 2473 general_params->tpid = tpid; 2474 /* EtherType used to identify outer tagged (S-tag) VLAN traffic */ 2475 general_params->tpid2 = tpid2; 2476 2477 for (port = 0; port < ds->num_ports; port++) { 2478 if (dsa_is_unused_port(ds, port)) 2479 continue; 2480 2481 rc = sja1105_commit_pvid(ds, port); 2482 if (rc) 2483 return rc; 2484 } 2485 2486 rc = sja1105_static_config_reload(priv, SJA1105_VLAN_FILTERING); 2487 if (rc) 2488 NL_SET_ERR_MSG_MOD(extack, "Failed to change VLAN Ethertype"); 2489 2490 return rc; 2491 } 2492 2493 static int sja1105_vlan_add(struct sja1105_private *priv, int port, u16 vid, 2494 u16 flags, bool allowed_ingress) 2495 { 2496 struct sja1105_vlan_lookup_entry *vlan; 2497 struct sja1105_table *table; 2498 int match, rc; 2499 2500 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP]; 2501 2502 match = sja1105_is_vlan_configured(priv, vid); 2503 if (match < 0) { 2504 rc = sja1105_table_resize(table, table->entry_count + 1); 2505 if (rc) 2506 return rc; 2507 match = table->entry_count - 1; 2508 } 2509 2510 /* Assign pointer after the resize (it's new memory) */ 2511 vlan = table->entries; 2512 2513 vlan[match].type_entry = SJA1110_VLAN_D_TAG; 2514 vlan[match].vlanid = vid; 2515 vlan[match].vlan_bc |= BIT(port); 2516 2517 if (allowed_ingress) 2518 vlan[match].vmemb_port |= BIT(port); 2519 else 2520 vlan[match].vmemb_port &= ~BIT(port); 2521 2522 if (flags & BRIDGE_VLAN_INFO_UNTAGGED) 2523 vlan[match].tag_port &= ~BIT(port); 2524 else 2525 vlan[match].tag_port |= BIT(port); 2526 2527 return sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid, 2528 &vlan[match], true); 2529 } 2530 2531 static int sja1105_vlan_del(struct sja1105_private *priv, int port, u16 vid) 2532 { 2533 struct sja1105_vlan_lookup_entry *vlan; 2534 struct sja1105_table *table; 2535 bool keep = true; 2536 int match, rc; 2537 2538 table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP]; 2539 2540 match = sja1105_is_vlan_configured(priv, vid); 2541 /* Can't delete a missing entry. */ 2542 if (match < 0) 2543 return 0; 2544 2545 /* Assign pointer after the resize (it's new memory) */ 2546 vlan = table->entries; 2547 2548 vlan[match].vlanid = vid; 2549 vlan[match].vlan_bc &= ~BIT(port); 2550 vlan[match].vmemb_port &= ~BIT(port); 2551 /* Also unset tag_port, just so we don't have a confusing bitmap 2552 * (no practical purpose). 2553 */ 2554 vlan[match].tag_port &= ~BIT(port); 2555 2556 /* If there's no port left as member of this VLAN, 2557 * it's time for it to go. 2558 */ 2559 if (!vlan[match].vmemb_port) 2560 keep = false; 2561 2562 rc = sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid, 2563 &vlan[match], keep); 2564 if (rc < 0) 2565 return rc; 2566 2567 if (!keep) 2568 return sja1105_table_delete_entry(table, match); 2569 2570 return 0; 2571 } 2572 2573 static int sja1105_bridge_vlan_add(struct dsa_switch *ds, int port, 2574 const struct switchdev_obj_port_vlan *vlan, 2575 struct netlink_ext_ack *extack) 2576 { 2577 struct sja1105_private *priv = ds->priv; 2578 u16 flags = vlan->flags; 2579 int rc; 2580 2581 /* Be sure to deny alterations to the configuration done by tag_8021q. 2582 */ 2583 if (vid_is_dsa_8021q(vlan->vid)) { 2584 NL_SET_ERR_MSG_MOD(extack, 2585 "Range 3072-4095 reserved for dsa_8021q operation"); 2586 return -EBUSY; 2587 } 2588 2589 /* Always install bridge VLANs as egress-tagged on CPU and DSA ports */ 2590 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2591 flags = 0; 2592 2593 rc = sja1105_vlan_add(priv, port, vlan->vid, flags, true); 2594 if (rc) 2595 return rc; 2596 2597 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 2598 priv->bridge_pvid[port] = vlan->vid; 2599 2600 return sja1105_commit_pvid(ds, port); 2601 } 2602 2603 static int sja1105_bridge_vlan_del(struct dsa_switch *ds, int port, 2604 const struct switchdev_obj_port_vlan *vlan) 2605 { 2606 struct sja1105_private *priv = ds->priv; 2607 int rc; 2608 2609 rc = sja1105_vlan_del(priv, port, vlan->vid); 2610 if (rc) 2611 return rc; 2612 2613 /* In case the pvid was deleted, make sure that untagged packets will 2614 * be dropped. 2615 */ 2616 return sja1105_commit_pvid(ds, port); 2617 } 2618 2619 static int sja1105_dsa_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid, 2620 u16 flags) 2621 { 2622 struct sja1105_private *priv = ds->priv; 2623 bool allowed_ingress = true; 2624 int rc; 2625 2626 /* Prevent attackers from trying to inject a DSA tag from 2627 * the outside world. 2628 */ 2629 if (dsa_is_user_port(ds, port)) 2630 allowed_ingress = false; 2631 2632 rc = sja1105_vlan_add(priv, port, vid, flags, allowed_ingress); 2633 if (rc) 2634 return rc; 2635 2636 if (flags & BRIDGE_VLAN_INFO_PVID) 2637 priv->tag_8021q_pvid[port] = vid; 2638 2639 return sja1105_commit_pvid(ds, port); 2640 } 2641 2642 static int sja1105_dsa_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid) 2643 { 2644 struct sja1105_private *priv = ds->priv; 2645 2646 return sja1105_vlan_del(priv, port, vid); 2647 } 2648 2649 static int sja1105_prechangeupper(struct dsa_switch *ds, int port, 2650 struct netdev_notifier_changeupper_info *info) 2651 { 2652 struct netlink_ext_ack *extack = info->info.extack; 2653 struct net_device *upper = info->upper_dev; 2654 struct dsa_switch_tree *dst = ds->dst; 2655 struct dsa_port *dp; 2656 2657 if (is_vlan_dev(upper)) { 2658 NL_SET_ERR_MSG_MOD(extack, "8021q uppers are not supported"); 2659 return -EBUSY; 2660 } 2661 2662 if (netif_is_bridge_master(upper)) { 2663 list_for_each_entry(dp, &dst->ports, list) { 2664 struct net_device *br = dsa_port_bridge_dev_get(dp); 2665 2666 if (br && br != upper && br_vlan_enabled(br)) { 2667 NL_SET_ERR_MSG_MOD(extack, 2668 "Only one VLAN-aware bridge is supported"); 2669 return -EBUSY; 2670 } 2671 } 2672 } 2673 2674 return 0; 2675 } 2676 2677 static int sja1105_mgmt_xmit(struct dsa_switch *ds, int port, int slot, 2678 struct sk_buff *skb, bool takets) 2679 { 2680 struct sja1105_mgmt_entry mgmt_route = {0}; 2681 struct sja1105_private *priv = ds->priv; 2682 struct ethhdr *hdr; 2683 int timeout = 10; 2684 int rc; 2685 2686 hdr = eth_hdr(skb); 2687 2688 mgmt_route.macaddr = ether_addr_to_u64(hdr->h_dest); 2689 mgmt_route.destports = BIT(port); 2690 mgmt_route.enfport = 1; 2691 mgmt_route.tsreg = 0; 2692 mgmt_route.takets = takets; 2693 2694 rc = sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE, 2695 slot, &mgmt_route, true); 2696 if (rc < 0) { 2697 kfree_skb(skb); 2698 return rc; 2699 } 2700 2701 /* Transfer skb to the host port. */ 2702 dsa_enqueue_skb(skb, dsa_to_port(ds, port)->user); 2703 2704 /* Wait until the switch has processed the frame */ 2705 do { 2706 rc = sja1105_dynamic_config_read(priv, BLK_IDX_MGMT_ROUTE, 2707 slot, &mgmt_route); 2708 if (rc < 0) { 2709 dev_err_ratelimited(priv->ds->dev, 2710 "failed to poll for mgmt route\n"); 2711 continue; 2712 } 2713 2714 /* UM10944: The ENFPORT flag of the respective entry is 2715 * cleared when a match is found. The host can use this 2716 * flag as an acknowledgment. 2717 */ 2718 cpu_relax(); 2719 } while (mgmt_route.enfport && --timeout); 2720 2721 if (!timeout) { 2722 /* Clean up the management route so that a follow-up 2723 * frame may not match on it by mistake. 2724 * This is only hardware supported on P/Q/R/S - on E/T it is 2725 * a no-op and we are silently discarding the -EOPNOTSUPP. 2726 */ 2727 sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE, 2728 slot, &mgmt_route, false); 2729 dev_err_ratelimited(priv->ds->dev, "xmit timed out\n"); 2730 } 2731 2732 return NETDEV_TX_OK; 2733 } 2734 2735 #define work_to_xmit_work(w) \ 2736 container_of((w), struct sja1105_deferred_xmit_work, work) 2737 2738 /* Deferred work is unfortunately necessary because setting up the management 2739 * route cannot be done from atomit context (SPI transfer takes a sleepable 2740 * lock on the bus) 2741 */ 2742 static void sja1105_port_deferred_xmit(struct kthread_work *work) 2743 { 2744 struct sja1105_deferred_xmit_work *xmit_work = work_to_xmit_work(work); 2745 struct sk_buff *clone, *skb = xmit_work->skb; 2746 struct dsa_switch *ds = xmit_work->dp->ds; 2747 struct sja1105_private *priv = ds->priv; 2748 int port = xmit_work->dp->index; 2749 2750 clone = SJA1105_SKB_CB(skb)->clone; 2751 2752 mutex_lock(&priv->mgmt_lock); 2753 2754 sja1105_mgmt_xmit(ds, port, 0, skb, !!clone); 2755 2756 /* The clone, if there, was made by dsa_skb_tx_timestamp */ 2757 if (clone) 2758 sja1105_ptp_txtstamp_skb(ds, port, clone); 2759 2760 mutex_unlock(&priv->mgmt_lock); 2761 2762 kfree(xmit_work); 2763 } 2764 2765 static int sja1105_connect_tag_protocol(struct dsa_switch *ds, 2766 enum dsa_tag_protocol proto) 2767 { 2768 struct sja1105_private *priv = ds->priv; 2769 struct sja1105_tagger_data *tagger_data; 2770 2771 if (proto != priv->info->tag_proto) 2772 return -EPROTONOSUPPORT; 2773 2774 tagger_data = sja1105_tagger_data(ds); 2775 tagger_data->xmit_work_fn = sja1105_port_deferred_xmit; 2776 tagger_data->meta_tstamp_handler = sja1110_process_meta_tstamp; 2777 2778 return 0; 2779 } 2780 2781 /* The MAXAGE setting belongs to the L2 Forwarding Parameters table, 2782 * which cannot be reconfigured at runtime. So a switch reset is required. 2783 */ 2784 static int sja1105_set_ageing_time(struct dsa_switch *ds, 2785 unsigned int ageing_time) 2786 { 2787 struct sja1105_l2_lookup_params_entry *l2_lookup_params; 2788 struct sja1105_private *priv = ds->priv; 2789 struct sja1105_table *table; 2790 unsigned int maxage; 2791 2792 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS]; 2793 l2_lookup_params = table->entries; 2794 2795 maxage = SJA1105_AGEING_TIME_MS(ageing_time); 2796 2797 if (l2_lookup_params->maxage == maxage) 2798 return 0; 2799 2800 l2_lookup_params->maxage = maxage; 2801 2802 return sja1105_static_config_reload(priv, SJA1105_AGEING_TIME); 2803 } 2804 2805 static int sja1105_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 2806 { 2807 struct sja1105_l2_policing_entry *policing; 2808 struct sja1105_private *priv = ds->priv; 2809 2810 new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN; 2811 2812 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2813 new_mtu += VLAN_HLEN; 2814 2815 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries; 2816 2817 if (policing[port].maxlen == new_mtu) 2818 return 0; 2819 2820 policing[port].maxlen = new_mtu; 2821 2822 return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING); 2823 } 2824 2825 static int sja1105_get_max_mtu(struct dsa_switch *ds, int port) 2826 { 2827 return 2043 - VLAN_ETH_HLEN - ETH_FCS_LEN; 2828 } 2829 2830 static int sja1105_port_setup_tc(struct dsa_switch *ds, int port, 2831 enum tc_setup_type type, 2832 void *type_data) 2833 { 2834 switch (type) { 2835 case TC_SETUP_QDISC_TAPRIO: 2836 return sja1105_setup_tc_taprio(ds, port, type_data); 2837 case TC_SETUP_QDISC_CBS: 2838 return sja1105_setup_tc_cbs(ds, port, type_data); 2839 default: 2840 return -EOPNOTSUPP; 2841 } 2842 } 2843 2844 /* We have a single mirror (@to) port, but can configure ingress and egress 2845 * mirroring on all other (@from) ports. 2846 * We need to allow mirroring rules only as long as the @to port is always the 2847 * same, and we need to unset the @to port from mirr_port only when there is no 2848 * mirroring rule that references it. 2849 */ 2850 static int sja1105_mirror_apply(struct sja1105_private *priv, int from, int to, 2851 bool ingress, bool enabled) 2852 { 2853 struct sja1105_general_params_entry *general_params; 2854 struct sja1105_mac_config_entry *mac; 2855 struct dsa_switch *ds = priv->ds; 2856 struct sja1105_table *table; 2857 bool already_enabled; 2858 u64 new_mirr_port; 2859 int rc; 2860 2861 table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS]; 2862 general_params = table->entries; 2863 2864 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; 2865 2866 already_enabled = (general_params->mirr_port != ds->num_ports); 2867 if (already_enabled && enabled && general_params->mirr_port != to) { 2868 dev_err(priv->ds->dev, 2869 "Delete mirroring rules towards port %llu first\n", 2870 general_params->mirr_port); 2871 return -EBUSY; 2872 } 2873 2874 new_mirr_port = to; 2875 if (!enabled) { 2876 bool keep = false; 2877 int port; 2878 2879 /* Anybody still referencing mirr_port? */ 2880 for (port = 0; port < ds->num_ports; port++) { 2881 if (mac[port].ing_mirr || mac[port].egr_mirr) { 2882 keep = true; 2883 break; 2884 } 2885 } 2886 /* Unset already_enabled for next time */ 2887 if (!keep) 2888 new_mirr_port = ds->num_ports; 2889 } 2890 if (new_mirr_port != general_params->mirr_port) { 2891 general_params->mirr_port = new_mirr_port; 2892 2893 rc = sja1105_dynamic_config_write(priv, BLK_IDX_GENERAL_PARAMS, 2894 0, general_params, true); 2895 if (rc < 0) 2896 return rc; 2897 } 2898 2899 if (ingress) 2900 mac[from].ing_mirr = enabled; 2901 else 2902 mac[from].egr_mirr = enabled; 2903 2904 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, from, 2905 &mac[from], true); 2906 } 2907 2908 static int sja1105_mirror_add(struct dsa_switch *ds, int port, 2909 struct dsa_mall_mirror_tc_entry *mirror, 2910 bool ingress, struct netlink_ext_ack *extack) 2911 { 2912 return sja1105_mirror_apply(ds->priv, port, mirror->to_local_port, 2913 ingress, true); 2914 } 2915 2916 static void sja1105_mirror_del(struct dsa_switch *ds, int port, 2917 struct dsa_mall_mirror_tc_entry *mirror) 2918 { 2919 sja1105_mirror_apply(ds->priv, port, mirror->to_local_port, 2920 mirror->ingress, false); 2921 } 2922 2923 static int sja1105_port_policer_add(struct dsa_switch *ds, int port, 2924 struct dsa_mall_policer_tc_entry *policer) 2925 { 2926 struct sja1105_l2_policing_entry *policing; 2927 struct sja1105_private *priv = ds->priv; 2928 2929 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries; 2930 2931 /* In hardware, every 8 microseconds the credit level is incremented by 2932 * the value of RATE bytes divided by 64, up to a maximum of SMAX 2933 * bytes. 2934 */ 2935 policing[port].rate = div_u64(512 * policer->rate_bytes_per_sec, 2936 1000000); 2937 policing[port].smax = policer->burst; 2938 2939 return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING); 2940 } 2941 2942 static void sja1105_port_policer_del(struct dsa_switch *ds, int port) 2943 { 2944 struct sja1105_l2_policing_entry *policing; 2945 struct sja1105_private *priv = ds->priv; 2946 2947 policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries; 2948 2949 policing[port].rate = SJA1105_RATE_MBPS(1000); 2950 policing[port].smax = 65535; 2951 2952 sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING); 2953 } 2954 2955 static int sja1105_port_set_learning(struct sja1105_private *priv, int port, 2956 bool enabled) 2957 { 2958 struct sja1105_mac_config_entry *mac; 2959 2960 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; 2961 2962 mac[port].dyn_learn = enabled; 2963 2964 return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port, 2965 &mac[port], true); 2966 } 2967 2968 static int sja1105_port_ucast_bcast_flood(struct sja1105_private *priv, int to, 2969 struct switchdev_brport_flags flags) 2970 { 2971 if (flags.mask & BR_FLOOD) { 2972 if (flags.val & BR_FLOOD) 2973 priv->ucast_egress_floods |= BIT(to); 2974 else 2975 priv->ucast_egress_floods &= ~BIT(to); 2976 } 2977 2978 if (flags.mask & BR_BCAST_FLOOD) { 2979 if (flags.val & BR_BCAST_FLOOD) 2980 priv->bcast_egress_floods |= BIT(to); 2981 else 2982 priv->bcast_egress_floods &= ~BIT(to); 2983 } 2984 2985 return sja1105_manage_flood_domains(priv); 2986 } 2987 2988 static int sja1105_port_mcast_flood(struct sja1105_private *priv, int to, 2989 struct switchdev_brport_flags flags, 2990 struct netlink_ext_ack *extack) 2991 { 2992 struct sja1105_l2_lookup_entry *l2_lookup; 2993 struct sja1105_table *table; 2994 int match, rc; 2995 2996 mutex_lock(&priv->fdb_lock); 2997 2998 table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP]; 2999 l2_lookup = table->entries; 3000 3001 for (match = 0; match < table->entry_count; match++) 3002 if (l2_lookup[match].macaddr == SJA1105_UNKNOWN_MULTICAST && 3003 l2_lookup[match].mask_macaddr == SJA1105_UNKNOWN_MULTICAST) 3004 break; 3005 3006 if (match == table->entry_count) { 3007 NL_SET_ERR_MSG_MOD(extack, 3008 "Could not find FDB entry for unknown multicast"); 3009 rc = -ENOSPC; 3010 goto out; 3011 } 3012 3013 if (flags.val & BR_MCAST_FLOOD) 3014 l2_lookup[match].destports |= BIT(to); 3015 else 3016 l2_lookup[match].destports &= ~BIT(to); 3017 3018 rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP, 3019 l2_lookup[match].index, 3020 &l2_lookup[match], true); 3021 out: 3022 mutex_unlock(&priv->fdb_lock); 3023 3024 return rc; 3025 } 3026 3027 static int sja1105_port_pre_bridge_flags(struct dsa_switch *ds, int port, 3028 struct switchdev_brport_flags flags, 3029 struct netlink_ext_ack *extack) 3030 { 3031 struct sja1105_private *priv = ds->priv; 3032 3033 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 3034 BR_BCAST_FLOOD)) 3035 return -EINVAL; 3036 3037 if (flags.mask & (BR_FLOOD | BR_MCAST_FLOOD) && 3038 !priv->info->can_limit_mcast_flood) { 3039 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 3040 bool unicast = !!(flags.val & BR_FLOOD); 3041 3042 if (unicast != multicast) { 3043 NL_SET_ERR_MSG_MOD(extack, 3044 "This chip cannot configure multicast flooding independently of unicast"); 3045 return -EINVAL; 3046 } 3047 } 3048 3049 return 0; 3050 } 3051 3052 static int sja1105_port_bridge_flags(struct dsa_switch *ds, int port, 3053 struct switchdev_brport_flags flags, 3054 struct netlink_ext_ack *extack) 3055 { 3056 struct sja1105_private *priv = ds->priv; 3057 int rc; 3058 3059 if (flags.mask & BR_LEARNING) { 3060 bool learn_ena = !!(flags.val & BR_LEARNING); 3061 3062 rc = sja1105_port_set_learning(priv, port, learn_ena); 3063 if (rc) 3064 return rc; 3065 } 3066 3067 if (flags.mask & (BR_FLOOD | BR_BCAST_FLOOD)) { 3068 rc = sja1105_port_ucast_bcast_flood(priv, port, flags); 3069 if (rc) 3070 return rc; 3071 } 3072 3073 /* For chips that can't offload BR_MCAST_FLOOD independently, there 3074 * is nothing to do here, we ensured the configuration is in sync by 3075 * offloading BR_FLOOD. 3076 */ 3077 if (flags.mask & BR_MCAST_FLOOD && priv->info->can_limit_mcast_flood) { 3078 rc = sja1105_port_mcast_flood(priv, port, flags, 3079 extack); 3080 if (rc) 3081 return rc; 3082 } 3083 3084 return 0; 3085 } 3086 3087 /* The programming model for the SJA1105 switch is "all-at-once" via static 3088 * configuration tables. Some of these can be dynamically modified at runtime, 3089 * but not the xMII mode parameters table. 3090 * Furthermode, some PHYs may not have crystals for generating their clocks 3091 * (e.g. RMII). Instead, their 50MHz clock is supplied via the SJA1105 port's 3092 * ref_clk pin. So port clocking needs to be initialized early, before 3093 * connecting to PHYs is attempted, otherwise they won't respond through MDIO. 3094 * Setting correct PHY link speed does not matter now. 3095 * But dsa_user_phy_setup is called later than sja1105_setup, so the PHY 3096 * bindings are not yet parsed by DSA core. We need to parse early so that we 3097 * can populate the xMII mode parameters table. 3098 */ 3099 static int sja1105_setup(struct dsa_switch *ds) 3100 { 3101 struct sja1105_private *priv = ds->priv; 3102 int rc; 3103 3104 if (priv->info->disable_microcontroller) { 3105 rc = priv->info->disable_microcontroller(priv); 3106 if (rc < 0) { 3107 dev_err(ds->dev, 3108 "Failed to disable microcontroller: %pe\n", 3109 ERR_PTR(rc)); 3110 return rc; 3111 } 3112 } 3113 3114 /* Create and send configuration down to device */ 3115 rc = sja1105_static_config_load(priv); 3116 if (rc < 0) { 3117 dev_err(ds->dev, "Failed to load static config: %d\n", rc); 3118 return rc; 3119 } 3120 3121 /* Configure the CGU (PHY link modes and speeds) */ 3122 if (priv->info->clocking_setup) { 3123 rc = priv->info->clocking_setup(priv); 3124 if (rc < 0) { 3125 dev_err(ds->dev, 3126 "Failed to configure MII clocking: %pe\n", 3127 ERR_PTR(rc)); 3128 goto out_static_config_free; 3129 } 3130 } 3131 3132 sja1105_tas_setup(ds); 3133 sja1105_flower_setup(ds); 3134 3135 rc = sja1105_ptp_clock_register(ds); 3136 if (rc < 0) { 3137 dev_err(ds->dev, "Failed to register PTP clock: %d\n", rc); 3138 goto out_flower_teardown; 3139 } 3140 3141 rc = sja1105_mdiobus_register(ds); 3142 if (rc < 0) { 3143 dev_err(ds->dev, "Failed to register MDIO bus: %pe\n", 3144 ERR_PTR(rc)); 3145 goto out_ptp_clock_unregister; 3146 } 3147 3148 rc = sja1105_devlink_setup(ds); 3149 if (rc < 0) 3150 goto out_mdiobus_unregister; 3151 3152 rtnl_lock(); 3153 rc = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q)); 3154 rtnl_unlock(); 3155 if (rc) 3156 goto out_devlink_teardown; 3157 3158 /* On SJA1105, VLAN filtering per se is always enabled in hardware. 3159 * The only thing we can do to disable it is lie about what the 802.1Q 3160 * EtherType is. 3161 * So it will still try to apply VLAN filtering, but all ingress 3162 * traffic (except frames received with EtherType of ETH_P_SJA1105) 3163 * will be internally tagged with a distorted VLAN header where the 3164 * TPID is ETH_P_SJA1105, and the VLAN ID is the port pvid. 3165 */ 3166 ds->vlan_filtering_is_global = true; 3167 ds->untag_bridge_pvid = true; 3168 ds->fdb_isolation = true; 3169 ds->max_num_bridges = DSA_TAG_8021Q_MAX_NUM_BRIDGES; 3170 3171 /* Advertise the 8 egress queues */ 3172 ds->num_tx_queues = SJA1105_NUM_TC; 3173 3174 ds->mtu_enforcement_ingress = true; 3175 ds->assisted_learning_on_cpu_port = true; 3176 3177 return 0; 3178 3179 out_devlink_teardown: 3180 sja1105_devlink_teardown(ds); 3181 out_mdiobus_unregister: 3182 sja1105_mdiobus_unregister(ds); 3183 out_ptp_clock_unregister: 3184 sja1105_ptp_clock_unregister(ds); 3185 out_flower_teardown: 3186 sja1105_flower_teardown(ds); 3187 sja1105_tas_teardown(ds); 3188 out_static_config_free: 3189 sja1105_static_config_free(&priv->static_config); 3190 3191 return rc; 3192 } 3193 3194 static void sja1105_teardown(struct dsa_switch *ds) 3195 { 3196 struct sja1105_private *priv = ds->priv; 3197 3198 rtnl_lock(); 3199 dsa_tag_8021q_unregister(ds); 3200 rtnl_unlock(); 3201 3202 sja1105_devlink_teardown(ds); 3203 sja1105_mdiobus_unregister(ds); 3204 sja1105_ptp_clock_unregister(ds); 3205 sja1105_flower_teardown(ds); 3206 sja1105_tas_teardown(ds); 3207 sja1105_static_config_free(&priv->static_config); 3208 } 3209 3210 static const struct phylink_mac_ops sja1105_phylink_mac_ops = { 3211 .mac_select_pcs = sja1105_mac_select_pcs, 3212 .mac_config = sja1105_mac_config, 3213 .mac_link_up = sja1105_mac_link_up, 3214 .mac_link_down = sja1105_mac_link_down, 3215 }; 3216 3217 static const struct dsa_switch_ops sja1105_switch_ops = { 3218 .get_tag_protocol = sja1105_get_tag_protocol, 3219 .connect_tag_protocol = sja1105_connect_tag_protocol, 3220 .setup = sja1105_setup, 3221 .teardown = sja1105_teardown, 3222 .set_ageing_time = sja1105_set_ageing_time, 3223 .port_change_mtu = sja1105_change_mtu, 3224 .port_max_mtu = sja1105_get_max_mtu, 3225 .phylink_get_caps = sja1105_phylink_get_caps, 3226 .get_strings = sja1105_get_strings, 3227 .get_ethtool_stats = sja1105_get_ethtool_stats, 3228 .get_sset_count = sja1105_get_sset_count, 3229 .get_ts_info = sja1105_get_ts_info, 3230 .port_fdb_dump = sja1105_fdb_dump, 3231 .port_fdb_add = sja1105_fdb_add, 3232 .port_fdb_del = sja1105_fdb_del, 3233 .port_fast_age = sja1105_fast_age, 3234 .port_bridge_join = sja1105_bridge_join, 3235 .port_bridge_leave = sja1105_bridge_leave, 3236 .port_pre_bridge_flags = sja1105_port_pre_bridge_flags, 3237 .port_bridge_flags = sja1105_port_bridge_flags, 3238 .port_stp_state_set = sja1105_bridge_stp_state_set, 3239 .port_vlan_filtering = sja1105_vlan_filtering, 3240 .port_vlan_add = sja1105_bridge_vlan_add, 3241 .port_vlan_del = sja1105_bridge_vlan_del, 3242 .port_mdb_add = sja1105_mdb_add, 3243 .port_mdb_del = sja1105_mdb_del, 3244 .port_hwtstamp_get = sja1105_hwtstamp_get, 3245 .port_hwtstamp_set = sja1105_hwtstamp_set, 3246 .port_rxtstamp = sja1105_port_rxtstamp, 3247 .port_txtstamp = sja1105_port_txtstamp, 3248 .port_setup_tc = sja1105_port_setup_tc, 3249 .port_mirror_add = sja1105_mirror_add, 3250 .port_mirror_del = sja1105_mirror_del, 3251 .port_policer_add = sja1105_port_policer_add, 3252 .port_policer_del = sja1105_port_policer_del, 3253 .cls_flower_add = sja1105_cls_flower_add, 3254 .cls_flower_del = sja1105_cls_flower_del, 3255 .cls_flower_stats = sja1105_cls_flower_stats, 3256 .devlink_info_get = sja1105_devlink_info_get, 3257 .tag_8021q_vlan_add = sja1105_dsa_8021q_vlan_add, 3258 .tag_8021q_vlan_del = sja1105_dsa_8021q_vlan_del, 3259 .port_prechangeupper = sja1105_prechangeupper, 3260 }; 3261 3262 static const struct of_device_id sja1105_dt_ids[]; 3263 3264 static int sja1105_check_device_id(struct sja1105_private *priv) 3265 { 3266 const struct sja1105_regs *regs = priv->info->regs; 3267 u8 prod_id[SJA1105_SIZE_DEVICE_ID] = {0}; 3268 struct device *dev = &priv->spidev->dev; 3269 const struct of_device_id *match; 3270 u32 device_id; 3271 u64 part_no; 3272 int rc; 3273 3274 rc = sja1105_xfer_u32(priv, SPI_READ, regs->device_id, &device_id, 3275 NULL); 3276 if (rc < 0) 3277 return rc; 3278 3279 rc = sja1105_xfer_buf(priv, SPI_READ, regs->prod_id, prod_id, 3280 SJA1105_SIZE_DEVICE_ID); 3281 if (rc < 0) 3282 return rc; 3283 3284 sja1105_unpack(prod_id, &part_no, 19, 4, SJA1105_SIZE_DEVICE_ID); 3285 3286 for (match = sja1105_dt_ids; match->compatible[0]; match++) { 3287 const struct sja1105_info *info = match->data; 3288 3289 /* Is what's been probed in our match table at all? */ 3290 if (info->device_id != device_id || info->part_no != part_no) 3291 continue; 3292 3293 /* But is it what's in the device tree? */ 3294 if (priv->info->device_id != device_id || 3295 priv->info->part_no != part_no) { 3296 dev_warn(dev, "Device tree specifies chip %s but found %s, please fix it!\n", 3297 priv->info->name, info->name); 3298 /* It isn't. No problem, pick that up. */ 3299 priv->info = info; 3300 } 3301 3302 return 0; 3303 } 3304 3305 dev_err(dev, "Unexpected {device ID, part number}: 0x%x 0x%llx\n", 3306 device_id, part_no); 3307 3308 return -ENODEV; 3309 } 3310 3311 static int sja1105_probe(struct spi_device *spi) 3312 { 3313 struct device *dev = &spi->dev; 3314 struct sja1105_private *priv; 3315 size_t max_xfer, max_msg; 3316 struct dsa_switch *ds; 3317 int rc; 3318 3319 if (!dev->of_node) { 3320 dev_err(dev, "No DTS bindings for SJA1105 driver\n"); 3321 return -EINVAL; 3322 } 3323 3324 rc = sja1105_hw_reset(dev, 1, 1); 3325 if (rc) 3326 return rc; 3327 3328 priv = devm_kzalloc(dev, sizeof(struct sja1105_private), GFP_KERNEL); 3329 if (!priv) 3330 return -ENOMEM; 3331 3332 /* Populate our driver private structure (priv) based on 3333 * the device tree node that was probed (spi) 3334 */ 3335 priv->spidev = spi; 3336 spi_set_drvdata(spi, priv); 3337 3338 /* Configure the SPI bus */ 3339 spi->bits_per_word = 8; 3340 rc = spi_setup(spi); 3341 if (rc < 0) { 3342 dev_err(dev, "Could not init SPI\n"); 3343 return rc; 3344 } 3345 3346 /* In sja1105_xfer, we send spi_messages composed of two spi_transfers: 3347 * a small one for the message header and another one for the current 3348 * chunk of the packed buffer. 3349 * Check that the restrictions imposed by the SPI controller are 3350 * respected: the chunk buffer is smaller than the max transfer size, 3351 * and the total length of the chunk plus its message header is smaller 3352 * than the max message size. 3353 * We do that during probe time since the maximum transfer size is a 3354 * runtime invariant. 3355 */ 3356 max_xfer = spi_max_transfer_size(spi); 3357 max_msg = spi_max_message_size(spi); 3358 3359 /* We need to send at least one 64-bit word of SPI payload per message 3360 * in order to be able to make useful progress. 3361 */ 3362 if (max_msg < SJA1105_SIZE_SPI_MSG_HEADER + 8) { 3363 dev_err(dev, "SPI master cannot send large enough buffers, aborting\n"); 3364 return -EINVAL; 3365 } 3366 3367 priv->max_xfer_len = SJA1105_SIZE_SPI_MSG_MAXLEN; 3368 if (priv->max_xfer_len > max_xfer) 3369 priv->max_xfer_len = max_xfer; 3370 if (priv->max_xfer_len > max_msg - SJA1105_SIZE_SPI_MSG_HEADER) 3371 priv->max_xfer_len = max_msg - SJA1105_SIZE_SPI_MSG_HEADER; 3372 3373 priv->info = of_device_get_match_data(dev); 3374 3375 /* Detect hardware device */ 3376 rc = sja1105_check_device_id(priv); 3377 if (rc < 0) { 3378 dev_err(dev, "Device ID check failed: %d\n", rc); 3379 return rc; 3380 } 3381 3382 dev_info(dev, "Probed switch chip: %s\n", priv->info->name); 3383 3384 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 3385 if (!ds) 3386 return -ENOMEM; 3387 3388 ds->dev = dev; 3389 ds->num_ports = priv->info->num_ports; 3390 ds->ops = &sja1105_switch_ops; 3391 ds->phylink_mac_ops = &sja1105_phylink_mac_ops; 3392 ds->priv = priv; 3393 priv->ds = ds; 3394 3395 mutex_init(&priv->ptp_data.lock); 3396 mutex_init(&priv->dynamic_config_lock); 3397 mutex_init(&priv->mgmt_lock); 3398 mutex_init(&priv->fdb_lock); 3399 spin_lock_init(&priv->ts_id_lock); 3400 3401 rc = sja1105_parse_dt(priv); 3402 if (rc < 0) { 3403 dev_err(ds->dev, "Failed to parse DT: %d\n", rc); 3404 return rc; 3405 } 3406 3407 if (IS_ENABLED(CONFIG_NET_SCH_CBS)) { 3408 priv->cbs = devm_kcalloc(dev, priv->info->num_cbs_shapers, 3409 sizeof(struct sja1105_cbs_entry), 3410 GFP_KERNEL); 3411 if (!priv->cbs) 3412 return -ENOMEM; 3413 } 3414 3415 return dsa_register_switch(priv->ds); 3416 } 3417 3418 static void sja1105_remove(struct spi_device *spi) 3419 { 3420 struct sja1105_private *priv = spi_get_drvdata(spi); 3421 3422 if (!priv) 3423 return; 3424 3425 dsa_unregister_switch(priv->ds); 3426 } 3427 3428 static void sja1105_shutdown(struct spi_device *spi) 3429 { 3430 struct sja1105_private *priv = spi_get_drvdata(spi); 3431 3432 if (!priv) 3433 return; 3434 3435 dsa_switch_shutdown(priv->ds); 3436 3437 spi_set_drvdata(spi, NULL); 3438 } 3439 3440 static const struct of_device_id sja1105_dt_ids[] = { 3441 { .compatible = "nxp,sja1105e", .data = &sja1105e_info }, 3442 { .compatible = "nxp,sja1105t", .data = &sja1105t_info }, 3443 { .compatible = "nxp,sja1105p", .data = &sja1105p_info }, 3444 { .compatible = "nxp,sja1105q", .data = &sja1105q_info }, 3445 { .compatible = "nxp,sja1105r", .data = &sja1105r_info }, 3446 { .compatible = "nxp,sja1105s", .data = &sja1105s_info }, 3447 { .compatible = "nxp,sja1110a", .data = &sja1110a_info }, 3448 { .compatible = "nxp,sja1110b", .data = &sja1110b_info }, 3449 { .compatible = "nxp,sja1110c", .data = &sja1110c_info }, 3450 { .compatible = "nxp,sja1110d", .data = &sja1110d_info }, 3451 { /* sentinel */ }, 3452 }; 3453 MODULE_DEVICE_TABLE(of, sja1105_dt_ids); 3454 3455 static const struct spi_device_id sja1105_spi_ids[] = { 3456 { "sja1105e" }, 3457 { "sja1105t" }, 3458 { "sja1105p" }, 3459 { "sja1105q" }, 3460 { "sja1105r" }, 3461 { "sja1105s" }, 3462 { "sja1110a" }, 3463 { "sja1110b" }, 3464 { "sja1110c" }, 3465 { "sja1110d" }, 3466 { }, 3467 }; 3468 MODULE_DEVICE_TABLE(spi, sja1105_spi_ids); 3469 3470 static struct spi_driver sja1105_driver = { 3471 .driver = { 3472 .name = "sja1105", 3473 .of_match_table = of_match_ptr(sja1105_dt_ids), 3474 }, 3475 .id_table = sja1105_spi_ids, 3476 .probe = sja1105_probe, 3477 .remove = sja1105_remove, 3478 .shutdown = sja1105_shutdown, 3479 }; 3480 3481 module_spi_driver(sja1105_driver); 3482 3483 MODULE_AUTHOR("Vladimir Oltean <olteanv@gmail.com>"); 3484 MODULE_AUTHOR("Georg Waibel <georg.waibel@sensor-technik.de>"); 3485 MODULE_DESCRIPTION("SJA1105 Driver"); 3486 MODULE_LICENSE("GPL v2"); 3487