1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH 3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com> 4 */ 5 #ifndef _SJA1105_H 6 #define _SJA1105_H 7 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/timecounter.h> 10 #include <linux/dsa/sja1105.h> 11 #include <linux/dsa/8021q.h> 12 #include <net/dsa.h> 13 #include <linux/mutex.h> 14 #include "sja1105_static_config.h" 15 16 #define SJA1105ET_FDB_BIN_SIZE 4 17 /* The hardware value is in multiples of 10 ms. 18 * The passed parameter is in multiples of 1 ms. 19 */ 20 #define SJA1105_AGEING_TIME_MS(ms) ((ms) / 10) 21 #define SJA1105_NUM_L2_POLICERS SJA1110_MAX_L2_POLICING_COUNT 22 23 typedef enum { 24 SPI_READ = 0, 25 SPI_WRITE = 1, 26 } sja1105_spi_rw_mode_t; 27 28 #include "sja1105_tas.h" 29 #include "sja1105_ptp.h" 30 31 enum sja1105_stats_area { 32 MAC, 33 HL1, 34 HL2, 35 ETHER, 36 __MAX_SJA1105_STATS_AREA, 37 }; 38 39 /* Keeps the different addresses between E/T and P/Q/R/S */ 40 struct sja1105_regs { 41 u64 device_id; 42 u64 prod_id; 43 u64 status; 44 u64 port_control; 45 u64 rgu; 46 u64 vl_status; 47 u64 config; 48 u64 rmii_pll1; 49 u64 ptppinst; 50 u64 ptppindur; 51 u64 ptp_control; 52 u64 ptpclkval; 53 u64 ptpclkrate; 54 u64 ptpclkcorp; 55 u64 ptpsyncts; 56 u64 ptpschtm; 57 u64 ptpegr_ts[SJA1105_MAX_NUM_PORTS]; 58 u64 pad_mii_tx[SJA1105_MAX_NUM_PORTS]; 59 u64 pad_mii_rx[SJA1105_MAX_NUM_PORTS]; 60 u64 pad_mii_id[SJA1105_MAX_NUM_PORTS]; 61 u64 cgu_idiv[SJA1105_MAX_NUM_PORTS]; 62 u64 mii_tx_clk[SJA1105_MAX_NUM_PORTS]; 63 u64 mii_rx_clk[SJA1105_MAX_NUM_PORTS]; 64 u64 mii_ext_tx_clk[SJA1105_MAX_NUM_PORTS]; 65 u64 mii_ext_rx_clk[SJA1105_MAX_NUM_PORTS]; 66 u64 rgmii_tx_clk[SJA1105_MAX_NUM_PORTS]; 67 u64 rmii_ref_clk[SJA1105_MAX_NUM_PORTS]; 68 u64 rmii_ext_tx_clk[SJA1105_MAX_NUM_PORTS]; 69 u64 stats[__MAX_SJA1105_STATS_AREA][SJA1105_MAX_NUM_PORTS]; 70 u64 mdio_100base_tx; 71 u64 mdio_100base_t1; 72 }; 73 74 struct sja1105_mdio_private { 75 struct sja1105_private *priv; 76 }; 77 78 enum { 79 SJA1105_SPEED_AUTO, 80 SJA1105_SPEED_10MBPS, 81 SJA1105_SPEED_100MBPS, 82 SJA1105_SPEED_1000MBPS, 83 SJA1105_SPEED_2500MBPS, 84 SJA1105_SPEED_MAX, 85 }; 86 87 enum sja1105_internal_phy_t { 88 SJA1105_NO_PHY = 0, 89 SJA1105_PHY_BASE_TX, 90 SJA1105_PHY_BASE_T1, 91 }; 92 93 struct sja1105_info { 94 u64 device_id; 95 /* Needed for distinction between P and R, and between Q and S 96 * (since the parts with/without SGMII share the same 97 * switch core and device_id) 98 */ 99 u64 part_no; 100 /* E/T and P/Q/R/S have partial timestamps of different sizes. 101 * They must be reconstructed on both families anyway to get the full 102 * 64-bit values back. 103 */ 104 int ptp_ts_bits; 105 /* Also SPI commands are of different sizes to retrieve 106 * the egress timestamps. 107 */ 108 int ptpegr_ts_bytes; 109 int num_cbs_shapers; 110 int max_frame_mem; 111 int num_ports; 112 const struct sja1105_dynamic_table_ops *dyn_ops; 113 const struct sja1105_table_ops *static_ops; 114 const struct sja1105_regs *regs; 115 /* Both E/T and P/Q/R/S have quirks when it comes to popping the S-Tag 116 * from double-tagged frames. E/T will pop it only when it's equal to 117 * TPID from the General Parameters Table, while P/Q/R/S will only 118 * pop it when it's equal to TPID2. 119 */ 120 u16 qinq_tpid; 121 bool can_limit_mcast_flood; 122 int (*reset_cmd)(struct dsa_switch *ds); 123 int (*setup_rgmii_delay)(const void *ctx, int port); 124 /* Prototypes from include/net/dsa.h */ 125 int (*fdb_add_cmd)(struct dsa_switch *ds, int port, 126 const unsigned char *addr, u16 vid); 127 int (*fdb_del_cmd)(struct dsa_switch *ds, int port, 128 const unsigned char *addr, u16 vid); 129 void (*ptp_cmd_packing)(u8 *buf, struct sja1105_ptp_cmd *cmd, 130 enum packing_op op); 131 int (*clocking_setup)(struct sja1105_private *priv); 132 const char *name; 133 bool supports_mii[SJA1105_MAX_NUM_PORTS]; 134 bool supports_rmii[SJA1105_MAX_NUM_PORTS]; 135 bool supports_rgmii[SJA1105_MAX_NUM_PORTS]; 136 bool supports_sgmii[SJA1105_MAX_NUM_PORTS]; 137 bool supports_2500basex[SJA1105_MAX_NUM_PORTS]; 138 enum sja1105_internal_phy_t internal_phy[SJA1105_MAX_NUM_PORTS]; 139 const u64 port_speed[SJA1105_SPEED_MAX]; 140 }; 141 142 enum sja1105_key_type { 143 SJA1105_KEY_BCAST, 144 SJA1105_KEY_TC, 145 SJA1105_KEY_VLAN_UNAWARE_VL, 146 SJA1105_KEY_VLAN_AWARE_VL, 147 }; 148 149 struct sja1105_key { 150 enum sja1105_key_type type; 151 152 union { 153 /* SJA1105_KEY_TC */ 154 struct { 155 int pcp; 156 } tc; 157 158 /* SJA1105_KEY_VLAN_UNAWARE_VL */ 159 /* SJA1105_KEY_VLAN_AWARE_VL */ 160 struct { 161 u64 dmac; 162 u16 vid; 163 u16 pcp; 164 } vl; 165 }; 166 }; 167 168 enum sja1105_rule_type { 169 SJA1105_RULE_BCAST_POLICER, 170 SJA1105_RULE_TC_POLICER, 171 SJA1105_RULE_VL, 172 }; 173 174 enum sja1105_vl_type { 175 SJA1105_VL_NONCRITICAL, 176 SJA1105_VL_RATE_CONSTRAINED, 177 SJA1105_VL_TIME_TRIGGERED, 178 }; 179 180 struct sja1105_rule { 181 struct list_head list; 182 unsigned long cookie; 183 unsigned long port_mask; 184 struct sja1105_key key; 185 enum sja1105_rule_type type; 186 187 /* Action */ 188 union { 189 /* SJA1105_RULE_BCAST_POLICER */ 190 struct { 191 int sharindx; 192 } bcast_pol; 193 194 /* SJA1105_RULE_TC_POLICER */ 195 struct { 196 int sharindx; 197 } tc_pol; 198 199 /* SJA1105_RULE_VL */ 200 struct { 201 enum sja1105_vl_type type; 202 unsigned long destports; 203 int sharindx; 204 int maxlen; 205 int ipv; 206 u64 base_time; 207 u64 cycle_time; 208 int num_entries; 209 struct action_gate_entry *entries; 210 struct flow_stats stats; 211 } vl; 212 }; 213 }; 214 215 struct sja1105_flow_block { 216 struct list_head rules; 217 bool l2_policer_used[SJA1105_NUM_L2_POLICERS]; 218 int num_virtual_links; 219 }; 220 221 struct sja1105_bridge_vlan { 222 struct list_head list; 223 int port; 224 u16 vid; 225 bool pvid; 226 bool untagged; 227 }; 228 229 enum sja1105_vlan_state { 230 SJA1105_VLAN_UNAWARE, 231 SJA1105_VLAN_BEST_EFFORT, 232 SJA1105_VLAN_FILTERING_FULL, 233 }; 234 235 struct sja1105_private { 236 struct sja1105_static_config static_config; 237 bool rgmii_rx_delay[SJA1105_MAX_NUM_PORTS]; 238 bool rgmii_tx_delay[SJA1105_MAX_NUM_PORTS]; 239 phy_interface_t phy_mode[SJA1105_MAX_NUM_PORTS]; 240 bool fixed_link[SJA1105_MAX_NUM_PORTS]; 241 bool best_effort_vlan_filtering; 242 unsigned long learn_ena; 243 unsigned long ucast_egress_floods; 244 unsigned long bcast_egress_floods; 245 const struct sja1105_info *info; 246 size_t max_xfer_len; 247 struct gpio_desc *reset_gpio; 248 struct spi_device *spidev; 249 struct dsa_switch *ds; 250 struct list_head dsa_8021q_vlans; 251 struct list_head bridge_vlans; 252 struct sja1105_flow_block flow_block; 253 struct sja1105_port ports[SJA1105_MAX_NUM_PORTS]; 254 /* Serializes transmission of management frames so that 255 * the switch doesn't confuse them with one another. 256 */ 257 struct mutex mgmt_lock; 258 struct dsa_8021q_context *dsa_8021q_ctx; 259 enum sja1105_vlan_state vlan_state; 260 struct devlink_region **regions; 261 struct sja1105_cbs_entry *cbs; 262 struct mii_bus *mdio_base_t1; 263 struct mii_bus *mdio_base_tx; 264 struct sja1105_tagger_data tagger_data; 265 struct sja1105_ptp_data ptp_data; 266 struct sja1105_tas_data tas_data; 267 }; 268 269 #include "sja1105_dynamic_config.h" 270 271 struct sja1105_spi_message { 272 u64 access; 273 u64 read_count; 274 u64 address; 275 }; 276 277 /* From sja1105_main.c */ 278 enum sja1105_reset_reason { 279 SJA1105_VLAN_FILTERING = 0, 280 SJA1105_RX_HWTSTAMPING, 281 SJA1105_AGEING_TIME, 282 SJA1105_SCHEDULING, 283 SJA1105_BEST_EFFORT_POLICING, 284 SJA1105_VIRTUAL_LINKS, 285 }; 286 287 int sja1105_static_config_reload(struct sja1105_private *priv, 288 enum sja1105_reset_reason reason); 289 int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled, 290 struct netlink_ext_ack *extack); 291 void sja1105_frame_memory_partitioning(struct sja1105_private *priv); 292 293 /* From sja1105_mdio.c */ 294 int sja1105_mdiobus_register(struct dsa_switch *ds); 295 void sja1105_mdiobus_unregister(struct dsa_switch *ds); 296 297 /* From sja1105_devlink.c */ 298 int sja1105_devlink_setup(struct dsa_switch *ds); 299 void sja1105_devlink_teardown(struct dsa_switch *ds); 300 int sja1105_devlink_param_get(struct dsa_switch *ds, u32 id, 301 struct devlink_param_gset_ctx *ctx); 302 int sja1105_devlink_param_set(struct dsa_switch *ds, u32 id, 303 struct devlink_param_gset_ctx *ctx); 304 int sja1105_devlink_info_get(struct dsa_switch *ds, 305 struct devlink_info_req *req, 306 struct netlink_ext_ack *extack); 307 308 /* From sja1105_spi.c */ 309 int sja1105_xfer_buf(const struct sja1105_private *priv, 310 sja1105_spi_rw_mode_t rw, u64 reg_addr, 311 u8 *buf, size_t len); 312 int sja1105_xfer_u32(const struct sja1105_private *priv, 313 sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value, 314 struct ptp_system_timestamp *ptp_sts); 315 int sja1105_xfer_u64(const struct sja1105_private *priv, 316 sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value, 317 struct ptp_system_timestamp *ptp_sts); 318 int static_config_buf_prepare_for_upload(struct sja1105_private *priv, 319 void *config_buf, int buf_len); 320 int sja1105_static_config_upload(struct sja1105_private *priv); 321 int sja1105_inhibit_tx(const struct sja1105_private *priv, 322 unsigned long port_bitmap, bool tx_inhibited); 323 324 extern const struct sja1105_info sja1105e_info; 325 extern const struct sja1105_info sja1105t_info; 326 extern const struct sja1105_info sja1105p_info; 327 extern const struct sja1105_info sja1105q_info; 328 extern const struct sja1105_info sja1105r_info; 329 extern const struct sja1105_info sja1105s_info; 330 extern const struct sja1105_info sja1110a_info; 331 extern const struct sja1105_info sja1110b_info; 332 extern const struct sja1105_info sja1110c_info; 333 extern const struct sja1105_info sja1110d_info; 334 335 /* From sja1105_clocking.c */ 336 337 typedef enum { 338 XMII_MAC = 0, 339 XMII_PHY = 1, 340 } sja1105_mii_role_t; 341 342 typedef enum { 343 XMII_MODE_MII = 0, 344 XMII_MODE_RMII = 1, 345 XMII_MODE_RGMII = 2, 346 XMII_MODE_SGMII = 3, 347 } sja1105_phy_interface_t; 348 349 int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port); 350 int sja1110_setup_rgmii_delay(const void *ctx, int port); 351 int sja1105_clocking_setup_port(struct sja1105_private *priv, int port); 352 int sja1105_clocking_setup(struct sja1105_private *priv); 353 int sja1110_clocking_setup(struct sja1105_private *priv); 354 355 /* From sja1105_ethtool.c */ 356 void sja1105_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data); 357 void sja1105_get_strings(struct dsa_switch *ds, int port, 358 u32 stringset, u8 *data); 359 int sja1105_get_sset_count(struct dsa_switch *ds, int port, int sset); 360 361 /* From sja1105_dynamic_config.c */ 362 int sja1105_dynamic_config_read(struct sja1105_private *priv, 363 enum sja1105_blk_idx blk_idx, 364 int index, void *entry); 365 int sja1105_dynamic_config_write(struct sja1105_private *priv, 366 enum sja1105_blk_idx blk_idx, 367 int index, void *entry, bool keep); 368 369 enum sja1105_iotag { 370 SJA1105_C_TAG = 0, /* Inner VLAN header */ 371 SJA1105_S_TAG = 1, /* Outer VLAN header */ 372 }; 373 374 enum sja1110_vlan_type { 375 SJA1110_VLAN_INVALID = 0, 376 SJA1110_VLAN_C_TAG = 1, /* Single inner VLAN tag */ 377 SJA1110_VLAN_S_TAG = 2, /* Single outer VLAN tag */ 378 SJA1110_VLAN_D_TAG = 3, /* Double tagged, use outer tag for lookup */ 379 }; 380 381 enum sja1110_shaper_type { 382 SJA1110_LEAKY_BUCKET_SHAPER = 0, 383 SJA1110_CBS_SHAPER = 1, 384 }; 385 386 u8 sja1105et_fdb_hash(struct sja1105_private *priv, const u8 *addr, u16 vid); 387 int sja1105et_fdb_add(struct dsa_switch *ds, int port, 388 const unsigned char *addr, u16 vid); 389 int sja1105et_fdb_del(struct dsa_switch *ds, int port, 390 const unsigned char *addr, u16 vid); 391 int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port, 392 const unsigned char *addr, u16 vid); 393 int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port, 394 const unsigned char *addr, u16 vid); 395 396 /* From sja1105_flower.c */ 397 int sja1105_cls_flower_del(struct dsa_switch *ds, int port, 398 struct flow_cls_offload *cls, bool ingress); 399 int sja1105_cls_flower_add(struct dsa_switch *ds, int port, 400 struct flow_cls_offload *cls, bool ingress); 401 int sja1105_cls_flower_stats(struct dsa_switch *ds, int port, 402 struct flow_cls_offload *cls, bool ingress); 403 void sja1105_flower_setup(struct dsa_switch *ds); 404 void sja1105_flower_teardown(struct dsa_switch *ds); 405 struct sja1105_rule *sja1105_rule_find(struct sja1105_private *priv, 406 unsigned long cookie); 407 408 #endif 409