1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH 3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com> 4 */ 5 #ifndef _SJA1105_H 6 #define _SJA1105_H 7 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/timecounter.h> 10 #include <linux/dsa/sja1105.h> 11 #include <linux/dsa/8021q.h> 12 #include <net/dsa.h> 13 #include <linux/mutex.h> 14 #include "sja1105_static_config.h" 15 16 #define SJA1105ET_FDB_BIN_SIZE 4 17 /* The hardware value is in multiples of 10 ms. 18 * The passed parameter is in multiples of 1 ms. 19 */ 20 #define SJA1105_AGEING_TIME_MS(ms) ((ms) / 10) 21 #define SJA1105_NUM_L2_POLICERS SJA1110_MAX_L2_POLICING_COUNT 22 23 typedef enum { 24 SPI_READ = 0, 25 SPI_WRITE = 1, 26 } sja1105_spi_rw_mode_t; 27 28 #include "sja1105_tas.h" 29 #include "sja1105_ptp.h" 30 31 enum sja1105_stats_area { 32 MAC, 33 HL1, 34 HL2, 35 ETHER, 36 __MAX_SJA1105_STATS_AREA, 37 }; 38 39 /* Keeps the different addresses between E/T and P/Q/R/S */ 40 struct sja1105_regs { 41 u64 device_id; 42 u64 prod_id; 43 u64 status; 44 u64 port_control; 45 u64 rgu; 46 u64 vl_status; 47 u64 config; 48 u64 rmii_pll1; 49 u64 ptppinst; 50 u64 ptppindur; 51 u64 ptp_control; 52 u64 ptpclkval; 53 u64 ptpclkrate; 54 u64 ptpclkcorp; 55 u64 ptpsyncts; 56 u64 ptpschtm; 57 u64 ptpegr_ts[SJA1105_MAX_NUM_PORTS]; 58 u64 pad_mii_tx[SJA1105_MAX_NUM_PORTS]; 59 u64 pad_mii_rx[SJA1105_MAX_NUM_PORTS]; 60 u64 pad_mii_id[SJA1105_MAX_NUM_PORTS]; 61 u64 cgu_idiv[SJA1105_MAX_NUM_PORTS]; 62 u64 mii_tx_clk[SJA1105_MAX_NUM_PORTS]; 63 u64 mii_rx_clk[SJA1105_MAX_NUM_PORTS]; 64 u64 mii_ext_tx_clk[SJA1105_MAX_NUM_PORTS]; 65 u64 mii_ext_rx_clk[SJA1105_MAX_NUM_PORTS]; 66 u64 rgmii_tx_clk[SJA1105_MAX_NUM_PORTS]; 67 u64 rmii_ref_clk[SJA1105_MAX_NUM_PORTS]; 68 u64 rmii_ext_tx_clk[SJA1105_MAX_NUM_PORTS]; 69 u64 stats[__MAX_SJA1105_STATS_AREA][SJA1105_MAX_NUM_PORTS]; 70 u64 mdio_100base_tx; 71 u64 mdio_100base_t1; 72 u64 pcs_base[SJA1105_MAX_NUM_PORTS]; 73 }; 74 75 struct sja1105_mdio_private { 76 struct sja1105_private *priv; 77 }; 78 79 enum { 80 SJA1105_SPEED_AUTO, 81 SJA1105_SPEED_10MBPS, 82 SJA1105_SPEED_100MBPS, 83 SJA1105_SPEED_1000MBPS, 84 SJA1105_SPEED_2500MBPS, 85 SJA1105_SPEED_MAX, 86 }; 87 88 enum sja1105_internal_phy_t { 89 SJA1105_NO_PHY = 0, 90 SJA1105_PHY_BASE_TX, 91 SJA1105_PHY_BASE_T1, 92 }; 93 94 struct sja1105_info { 95 u64 device_id; 96 /* Needed for distinction between P and R, and between Q and S 97 * (since the parts with/without SGMII share the same 98 * switch core and device_id) 99 */ 100 u64 part_no; 101 /* E/T and P/Q/R/S have partial timestamps of different sizes. 102 * They must be reconstructed on both families anyway to get the full 103 * 64-bit values back. 104 */ 105 int ptp_ts_bits; 106 /* Also SPI commands are of different sizes to retrieve 107 * the egress timestamps. 108 */ 109 int ptpegr_ts_bytes; 110 int num_cbs_shapers; 111 int max_frame_mem; 112 int num_ports; 113 bool multiple_cascade_ports; 114 enum dsa_tag_protocol tag_proto; 115 const struct sja1105_dynamic_table_ops *dyn_ops; 116 const struct sja1105_table_ops *static_ops; 117 const struct sja1105_regs *regs; 118 /* Both E/T and P/Q/R/S have quirks when it comes to popping the S-Tag 119 * from double-tagged frames. E/T will pop it only when it's equal to 120 * TPID from the General Parameters Table, while P/Q/R/S will only 121 * pop it when it's equal to TPID2. 122 */ 123 u16 qinq_tpid; 124 bool can_limit_mcast_flood; 125 int (*reset_cmd)(struct dsa_switch *ds); 126 int (*setup_rgmii_delay)(const void *ctx, int port); 127 /* Prototypes from include/net/dsa.h */ 128 int (*fdb_add_cmd)(struct dsa_switch *ds, int port, 129 const unsigned char *addr, u16 vid); 130 int (*fdb_del_cmd)(struct dsa_switch *ds, int port, 131 const unsigned char *addr, u16 vid); 132 void (*ptp_cmd_packing)(u8 *buf, struct sja1105_ptp_cmd *cmd, 133 enum packing_op op); 134 bool (*rxtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb); 135 void (*txtstamp)(struct dsa_switch *ds, int port, struct sk_buff *skb); 136 int (*clocking_setup)(struct sja1105_private *priv); 137 int (*pcs_mdio_read)(struct mii_bus *bus, int phy, int reg); 138 int (*pcs_mdio_write)(struct mii_bus *bus, int phy, int reg, u16 val); 139 const char *name; 140 bool supports_mii[SJA1105_MAX_NUM_PORTS]; 141 bool supports_rmii[SJA1105_MAX_NUM_PORTS]; 142 bool supports_rgmii[SJA1105_MAX_NUM_PORTS]; 143 bool supports_sgmii[SJA1105_MAX_NUM_PORTS]; 144 bool supports_2500basex[SJA1105_MAX_NUM_PORTS]; 145 enum sja1105_internal_phy_t internal_phy[SJA1105_MAX_NUM_PORTS]; 146 const u64 port_speed[SJA1105_SPEED_MAX]; 147 }; 148 149 enum sja1105_key_type { 150 SJA1105_KEY_BCAST, 151 SJA1105_KEY_TC, 152 SJA1105_KEY_VLAN_UNAWARE_VL, 153 SJA1105_KEY_VLAN_AWARE_VL, 154 }; 155 156 struct sja1105_key { 157 enum sja1105_key_type type; 158 159 union { 160 /* SJA1105_KEY_TC */ 161 struct { 162 int pcp; 163 } tc; 164 165 /* SJA1105_KEY_VLAN_UNAWARE_VL */ 166 /* SJA1105_KEY_VLAN_AWARE_VL */ 167 struct { 168 u64 dmac; 169 u16 vid; 170 u16 pcp; 171 } vl; 172 }; 173 }; 174 175 enum sja1105_rule_type { 176 SJA1105_RULE_BCAST_POLICER, 177 SJA1105_RULE_TC_POLICER, 178 SJA1105_RULE_VL, 179 }; 180 181 enum sja1105_vl_type { 182 SJA1105_VL_NONCRITICAL, 183 SJA1105_VL_RATE_CONSTRAINED, 184 SJA1105_VL_TIME_TRIGGERED, 185 }; 186 187 struct sja1105_rule { 188 struct list_head list; 189 unsigned long cookie; 190 unsigned long port_mask; 191 struct sja1105_key key; 192 enum sja1105_rule_type type; 193 194 /* Action */ 195 union { 196 /* SJA1105_RULE_BCAST_POLICER */ 197 struct { 198 int sharindx; 199 } bcast_pol; 200 201 /* SJA1105_RULE_TC_POLICER */ 202 struct { 203 int sharindx; 204 } tc_pol; 205 206 /* SJA1105_RULE_VL */ 207 struct { 208 enum sja1105_vl_type type; 209 unsigned long destports; 210 int sharindx; 211 int maxlen; 212 int ipv; 213 u64 base_time; 214 u64 cycle_time; 215 int num_entries; 216 struct action_gate_entry *entries; 217 struct flow_stats stats; 218 } vl; 219 }; 220 }; 221 222 struct sja1105_flow_block { 223 struct list_head rules; 224 bool l2_policer_used[SJA1105_NUM_L2_POLICERS]; 225 int num_virtual_links; 226 }; 227 228 struct sja1105_bridge_vlan { 229 struct list_head list; 230 int port; 231 u16 vid; 232 bool pvid; 233 bool untagged; 234 }; 235 236 enum sja1105_vlan_state { 237 SJA1105_VLAN_UNAWARE, 238 SJA1105_VLAN_BEST_EFFORT, 239 SJA1105_VLAN_FILTERING_FULL, 240 }; 241 242 struct sja1105_private { 243 struct sja1105_static_config static_config; 244 bool rgmii_rx_delay[SJA1105_MAX_NUM_PORTS]; 245 bool rgmii_tx_delay[SJA1105_MAX_NUM_PORTS]; 246 phy_interface_t phy_mode[SJA1105_MAX_NUM_PORTS]; 247 bool fixed_link[SJA1105_MAX_NUM_PORTS]; 248 bool best_effort_vlan_filtering; 249 unsigned long learn_ena; 250 unsigned long ucast_egress_floods; 251 unsigned long bcast_egress_floods; 252 const struct sja1105_info *info; 253 size_t max_xfer_len; 254 struct gpio_desc *reset_gpio; 255 struct spi_device *spidev; 256 struct dsa_switch *ds; 257 struct list_head dsa_8021q_vlans; 258 struct list_head bridge_vlans; 259 struct sja1105_flow_block flow_block; 260 struct sja1105_port ports[SJA1105_MAX_NUM_PORTS]; 261 /* Serializes transmission of management frames so that 262 * the switch doesn't confuse them with one another. 263 */ 264 struct mutex mgmt_lock; 265 struct dsa_8021q_context *dsa_8021q_ctx; 266 enum sja1105_vlan_state vlan_state; 267 struct devlink_region **regions; 268 struct sja1105_cbs_entry *cbs; 269 struct mii_bus *mdio_base_t1; 270 struct mii_bus *mdio_base_tx; 271 struct mii_bus *mdio_pcs; 272 struct dw_xpcs *xpcs[SJA1105_MAX_NUM_PORTS]; 273 struct sja1105_tagger_data tagger_data; 274 struct sja1105_ptp_data ptp_data; 275 struct sja1105_tas_data tas_data; 276 }; 277 278 #include "sja1105_dynamic_config.h" 279 280 struct sja1105_spi_message { 281 u64 access; 282 u64 read_count; 283 u64 address; 284 }; 285 286 /* From sja1105_main.c */ 287 enum sja1105_reset_reason { 288 SJA1105_VLAN_FILTERING = 0, 289 SJA1105_RX_HWTSTAMPING, 290 SJA1105_AGEING_TIME, 291 SJA1105_SCHEDULING, 292 SJA1105_BEST_EFFORT_POLICING, 293 SJA1105_VIRTUAL_LINKS, 294 }; 295 296 int sja1105_static_config_reload(struct sja1105_private *priv, 297 enum sja1105_reset_reason reason); 298 int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled, 299 struct netlink_ext_ack *extack); 300 void sja1105_frame_memory_partitioning(struct sja1105_private *priv); 301 302 /* From sja1105_mdio.c */ 303 int sja1105_mdiobus_register(struct dsa_switch *ds); 304 void sja1105_mdiobus_unregister(struct dsa_switch *ds); 305 int sja1105_pcs_mdio_read(struct mii_bus *bus, int phy, int reg); 306 int sja1105_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val); 307 int sja1110_pcs_mdio_read(struct mii_bus *bus, int phy, int reg); 308 int sja1110_pcs_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val); 309 310 /* From sja1105_devlink.c */ 311 int sja1105_devlink_setup(struct dsa_switch *ds); 312 void sja1105_devlink_teardown(struct dsa_switch *ds); 313 int sja1105_devlink_param_get(struct dsa_switch *ds, u32 id, 314 struct devlink_param_gset_ctx *ctx); 315 int sja1105_devlink_param_set(struct dsa_switch *ds, u32 id, 316 struct devlink_param_gset_ctx *ctx); 317 int sja1105_devlink_info_get(struct dsa_switch *ds, 318 struct devlink_info_req *req, 319 struct netlink_ext_ack *extack); 320 321 /* From sja1105_spi.c */ 322 int sja1105_xfer_buf(const struct sja1105_private *priv, 323 sja1105_spi_rw_mode_t rw, u64 reg_addr, 324 u8 *buf, size_t len); 325 int sja1105_xfer_u32(const struct sja1105_private *priv, 326 sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value, 327 struct ptp_system_timestamp *ptp_sts); 328 int sja1105_xfer_u64(const struct sja1105_private *priv, 329 sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value, 330 struct ptp_system_timestamp *ptp_sts); 331 int static_config_buf_prepare_for_upload(struct sja1105_private *priv, 332 void *config_buf, int buf_len); 333 int sja1105_static_config_upload(struct sja1105_private *priv); 334 int sja1105_inhibit_tx(const struct sja1105_private *priv, 335 unsigned long port_bitmap, bool tx_inhibited); 336 337 extern const struct sja1105_info sja1105e_info; 338 extern const struct sja1105_info sja1105t_info; 339 extern const struct sja1105_info sja1105p_info; 340 extern const struct sja1105_info sja1105q_info; 341 extern const struct sja1105_info sja1105r_info; 342 extern const struct sja1105_info sja1105s_info; 343 extern const struct sja1105_info sja1110a_info; 344 extern const struct sja1105_info sja1110b_info; 345 extern const struct sja1105_info sja1110c_info; 346 extern const struct sja1105_info sja1110d_info; 347 348 /* From sja1105_clocking.c */ 349 350 typedef enum { 351 XMII_MAC = 0, 352 XMII_PHY = 1, 353 } sja1105_mii_role_t; 354 355 typedef enum { 356 XMII_MODE_MII = 0, 357 XMII_MODE_RMII = 1, 358 XMII_MODE_RGMII = 2, 359 XMII_MODE_SGMII = 3, 360 } sja1105_phy_interface_t; 361 362 int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port); 363 int sja1110_setup_rgmii_delay(const void *ctx, int port); 364 int sja1105_clocking_setup_port(struct sja1105_private *priv, int port); 365 int sja1105_clocking_setup(struct sja1105_private *priv); 366 int sja1110_clocking_setup(struct sja1105_private *priv); 367 368 /* From sja1105_ethtool.c */ 369 void sja1105_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data); 370 void sja1105_get_strings(struct dsa_switch *ds, int port, 371 u32 stringset, u8 *data); 372 int sja1105_get_sset_count(struct dsa_switch *ds, int port, int sset); 373 374 /* From sja1105_dynamic_config.c */ 375 int sja1105_dynamic_config_read(struct sja1105_private *priv, 376 enum sja1105_blk_idx blk_idx, 377 int index, void *entry); 378 int sja1105_dynamic_config_write(struct sja1105_private *priv, 379 enum sja1105_blk_idx blk_idx, 380 int index, void *entry, bool keep); 381 382 enum sja1105_iotag { 383 SJA1105_C_TAG = 0, /* Inner VLAN header */ 384 SJA1105_S_TAG = 1, /* Outer VLAN header */ 385 }; 386 387 enum sja1110_vlan_type { 388 SJA1110_VLAN_INVALID = 0, 389 SJA1110_VLAN_C_TAG = 1, /* Single inner VLAN tag */ 390 SJA1110_VLAN_S_TAG = 2, /* Single outer VLAN tag */ 391 SJA1110_VLAN_D_TAG = 3, /* Double tagged, use outer tag for lookup */ 392 }; 393 394 enum sja1110_shaper_type { 395 SJA1110_LEAKY_BUCKET_SHAPER = 0, 396 SJA1110_CBS_SHAPER = 1, 397 }; 398 399 u8 sja1105et_fdb_hash(struct sja1105_private *priv, const u8 *addr, u16 vid); 400 int sja1105et_fdb_add(struct dsa_switch *ds, int port, 401 const unsigned char *addr, u16 vid); 402 int sja1105et_fdb_del(struct dsa_switch *ds, int port, 403 const unsigned char *addr, u16 vid); 404 int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port, 405 const unsigned char *addr, u16 vid); 406 int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port, 407 const unsigned char *addr, u16 vid); 408 409 /* From sja1105_flower.c */ 410 int sja1105_cls_flower_del(struct dsa_switch *ds, int port, 411 struct flow_cls_offload *cls, bool ingress); 412 int sja1105_cls_flower_add(struct dsa_switch *ds, int port, 413 struct flow_cls_offload *cls, bool ingress); 414 int sja1105_cls_flower_stats(struct dsa_switch *ds, int port, 415 struct flow_cls_offload *cls, bool ingress); 416 void sja1105_flower_setup(struct dsa_switch *ds); 417 void sja1105_flower_teardown(struct dsa_switch *ds); 418 struct sja1105_rule *sja1105_rule_find(struct sja1105_private *priv, 419 unsigned long cookie); 420 421 #endif 422