1 // SPDX-License-Identifier: GPL-2.0 2 /* Realtek SMI subdriver for the Realtek RTL8366RB ethernet switch 3 * 4 * This is a sparsely documented chip, the only viable documentation seems 5 * to be a patched up code drop from the vendor that appear in various 6 * GPL source trees. 7 * 8 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> 9 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org> 10 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com> 11 * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv> 12 * Copyright (C) 2011 Colin Leitner <colin.leitner@googlemail.com> 13 */ 14 15 #include <linux/bitops.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <linux/if_vlan.h> 19 #include <linux/interrupt.h> 20 #include <linux/irqdomain.h> 21 #include <linux/irqchip/chained_irq.h> 22 #include <linux/of_irq.h> 23 #include <linux/regmap.h> 24 #include <linux/string_choices.h> 25 26 #include "realtek.h" 27 #include "realtek-smi.h" 28 #include "realtek-mdio.h" 29 #include "rtl83xx.h" 30 #include "rtl8366rb.h" 31 32 /* Switch Global Configuration register */ 33 #define RTL8366RB_SGCR 0x0000 34 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0) 35 #define RTL8366RB_SGCR_MAX_LENGTH(a) ((a) << 4) 36 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3) 37 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0) 38 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1) 39 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2) 40 #define RTL8366RB_SGCR_MAX_LENGTH_16000 RTL8366RB_SGCR_MAX_LENGTH(0x3) 41 #define RTL8366RB_SGCR_EN_VLAN BIT(13) 42 #define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14) 43 44 /* Port Enable Control register */ 45 #define RTL8366RB_PECR 0x0001 46 47 /* Switch per-port learning disablement register */ 48 #define RTL8366RB_PORT_LEARNDIS_CTRL 0x0002 49 50 /* Security control, actually aging register */ 51 #define RTL8366RB_SECURITY_CTRL 0x0003 52 53 #define RTL8366RB_SSCR2 0x0004 54 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0) 55 56 /* Port Mode Control registers */ 57 #define RTL8366RB_PMC0 0x0005 58 #define RTL8366RB_PMC0_SPI BIT(0) 59 #define RTL8366RB_PMC0_EN_AUTOLOAD BIT(1) 60 #define RTL8366RB_PMC0_PROBE BIT(2) 61 #define RTL8366RB_PMC0_DIS_BISR BIT(3) 62 #define RTL8366RB_PMC0_ADCTEST BIT(4) 63 #define RTL8366RB_PMC0_SRAM_DIAG BIT(5) 64 #define RTL8366RB_PMC0_EN_SCAN BIT(6) 65 #define RTL8366RB_PMC0_P4_IOMODE_SHIFT 7 66 #define RTL8366RB_PMC0_P4_IOMODE_MASK GENMASK(9, 7) 67 #define RTL8366RB_PMC0_P5_IOMODE_SHIFT 10 68 #define RTL8366RB_PMC0_P5_IOMODE_MASK GENMASK(12, 10) 69 #define RTL8366RB_PMC0_SDSMODE_SHIFT 13 70 #define RTL8366RB_PMC0_SDSMODE_MASK GENMASK(15, 13) 71 #define RTL8366RB_PMC1 0x0006 72 73 /* Port Mirror Control Register */ 74 #define RTL8366RB_PMCR 0x0007 75 #define RTL8366RB_PMCR_SOURCE_PORT(a) (a) 76 #define RTL8366RB_PMCR_SOURCE_PORT_MASK 0x000f 77 #define RTL8366RB_PMCR_MONITOR_PORT(a) ((a) << 4) 78 #define RTL8366RB_PMCR_MONITOR_PORT_MASK 0x00f0 79 #define RTL8366RB_PMCR_MIRROR_RX BIT(8) 80 #define RTL8366RB_PMCR_MIRROR_TX BIT(9) 81 #define RTL8366RB_PMCR_MIRROR_SPC BIT(10) 82 #define RTL8366RB_PMCR_MIRROR_ISO BIT(11) 83 84 /* bits 0..7 = port 0, bits 8..15 = port 1 */ 85 #define RTL8366RB_PAACR0 0x0010 86 /* bits 0..7 = port 2, bits 8..15 = port 3 */ 87 #define RTL8366RB_PAACR1 0x0011 88 /* bits 0..7 = port 4, bits 8..15 = port 5 */ 89 #define RTL8366RB_PAACR2 0x0012 90 #define RTL8366RB_PAACR_SPEED_10M 0 91 #define RTL8366RB_PAACR_SPEED_100M 1 92 #define RTL8366RB_PAACR_SPEED_1000M 2 93 #define RTL8366RB_PAACR_FULL_DUPLEX BIT(2) 94 #define RTL8366RB_PAACR_LINK_UP BIT(4) 95 #define RTL8366RB_PAACR_TX_PAUSE BIT(5) 96 #define RTL8366RB_PAACR_RX_PAUSE BIT(6) 97 #define RTL8366RB_PAACR_AN BIT(7) 98 99 /* bits 0..7 = port 0, bits 8..15 = port 1 */ 100 #define RTL8366RB_PSTAT0 0x0014 101 /* bits 0..7 = port 2, bits 8..15 = port 3 */ 102 #define RTL8366RB_PSTAT1 0x0015 103 /* bits 0..7 = port 4, bits 8..15 = port 5 */ 104 #define RTL8366RB_PSTAT2 0x0016 105 106 #define RTL8366RB_POWER_SAVING_REG 0x0021 107 108 /* Spanning tree status (STP) control, two bits per port per FID */ 109 #define RTL8366RB_STP_STATE_BASE 0x0050 /* 0x0050..0x0057 */ 110 #define RTL8366RB_STP_STATE_DISABLED 0x0 111 #define RTL8366RB_STP_STATE_BLOCKING 0x1 112 #define RTL8366RB_STP_STATE_LEARNING 0x2 113 #define RTL8366RB_STP_STATE_FORWARDING 0x3 114 #define RTL8366RB_STP_MASK GENMASK(1, 0) 115 #define RTL8366RB_STP_STATE(port, state) \ 116 ((state) << ((port) * 2)) 117 #define RTL8366RB_STP_STATE_MASK(port) \ 118 RTL8366RB_STP_STATE((port), RTL8366RB_STP_MASK) 119 120 /* CPU port control reg */ 121 #define RTL8366RB_CPU_CTRL_REG 0x0061 122 #define RTL8366RB_CPU_PORTS_MSK 0x00FF 123 /* Disables inserting custom tag length/type 0x8899 */ 124 #define RTL8366RB_CPU_NO_TAG BIT(15) 125 #define RTL8366RB_CPU_TAG_SIZE 4 126 127 #define RTL8366RB_SMAR0 0x0070 /* bits 0..15 */ 128 #define RTL8366RB_SMAR1 0x0071 /* bits 16..31 */ 129 #define RTL8366RB_SMAR2 0x0072 /* bits 32..47 */ 130 131 #define RTL8366RB_RESET_CTRL_REG 0x0100 132 #define RTL8366RB_CHIP_CTRL_RESET_HW BIT(0) 133 #define RTL8366RB_CHIP_CTRL_RESET_SW BIT(1) 134 135 #define RTL8366RB_CHIP_ID_REG 0x0509 136 #define RTL8366RB_CHIP_ID_8366 0x5937 137 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A 138 #define RTL8366RB_CHIP_VERSION_MASK 0xf 139 140 /* PHY registers control */ 141 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000 142 #define RTL8366RB_PHY_CTRL_READ BIT(0) 143 #define RTL8366RB_PHY_CTRL_WRITE 0 144 #define RTL8366RB_PHY_ACCESS_BUSY_REG 0x8001 145 #define RTL8366RB_PHY_INT_BUSY BIT(0) 146 #define RTL8366RB_PHY_EXT_BUSY BIT(4) 147 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002 148 #define RTL8366RB_PHY_EXT_CTRL_REG 0x8010 149 #define RTL8366RB_PHY_EXT_WRDATA_REG 0x8011 150 #define RTL8366RB_PHY_EXT_RDDATA_REG 0x8012 151 152 #define RTL8366RB_PHY_REG_MASK 0x1f 153 #define RTL8366RB_PHY_PAGE_OFFSET 5 154 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5) 155 #define RTL8366RB_PHY_NO_OFFSET 9 156 #define RTL8366RB_PHY_NO_MASK (0x1f << 9) 157 158 /* VLAN Ingress Control Register 1, one bit per port. 159 * bit 0 .. 5 will make the switch drop ingress frames without 160 * VID such as untagged or priority-tagged frames for respective 161 * port. 162 * bit 6 .. 11 will make the switch drop ingress frames carrying 163 * a C-tag with VID != 0 for respective port. 164 */ 165 #define RTL8366RB_VLAN_INGRESS_CTRL1_REG 0x037E 166 #define RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) (BIT((port)) | BIT((port) + 6)) 167 168 /* VLAN Ingress Control Register 2, one bit per port. 169 * bit0 .. bit5 will make the switch drop all ingress frames with 170 * a VLAN classification that does not include the port is in its 171 * member set. 172 */ 173 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f 174 175 #define RTL8366RB_MIB_COUNT 33 176 #define RTL8366RB_GLOBAL_MIB_COUNT 1 177 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050 178 #define RTL8366RB_MIB_COUNTER_BASE 0x1000 179 #define RTL8366RB_MIB_CTRL_REG 0x13F0 180 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC 181 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0) 182 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1) 183 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p)) 184 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11) 185 186 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063 187 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \ 188 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4) 189 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf 190 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4)) 191 192 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C 193 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185 194 195 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180 196 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01 197 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01 198 199 #define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3) 200 201 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014 202 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003 203 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004 204 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010 205 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020 206 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040 207 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080 208 209 #define RTL8366RB_NUM_VLANS 16 210 #define RTL8366RB_NUM_VIDS 4096 211 #define RTL8366RB_PRIORITYMAX 7 212 #define RTL8366RB_NUM_FIDS 8 213 #define RTL8366RB_FIDMAX 7 214 215 #define RTL8366RB_PORT_1 BIT(0) /* In userspace port 0 */ 216 #define RTL8366RB_PORT_2 BIT(1) /* In userspace port 1 */ 217 #define RTL8366RB_PORT_3 BIT(2) /* In userspace port 2 */ 218 #define RTL8366RB_PORT_4 BIT(3) /* In userspace port 3 */ 219 #define RTL8366RB_PORT_5 BIT(4) /* In userspace port 4 */ 220 221 #define RTL8366RB_PORT_CPU BIT(5) /* CPU port */ 222 223 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \ 224 RTL8366RB_PORT_2 | \ 225 RTL8366RB_PORT_3 | \ 226 RTL8366RB_PORT_4 | \ 227 RTL8366RB_PORT_5 | \ 228 RTL8366RB_PORT_CPU) 229 230 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \ 231 RTL8366RB_PORT_2 | \ 232 RTL8366RB_PORT_3 | \ 233 RTL8366RB_PORT_4 | \ 234 RTL8366RB_PORT_5) 235 236 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \ 237 RTL8366RB_PORT_2 | \ 238 RTL8366RB_PORT_3 | \ 239 RTL8366RB_PORT_4) 240 241 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU 242 243 /* First configuration word per member config, VID and prio */ 244 #define RTL8366RB_VLAN_VID_MASK 0xfff 245 #define RTL8366RB_VLAN_PRIORITY_SHIFT 12 246 #define RTL8366RB_VLAN_PRIORITY_MASK 0x7 247 /* Second configuration word per member config, member and untagged */ 248 #define RTL8366RB_VLAN_UNTAG_SHIFT 8 249 #define RTL8366RB_VLAN_UNTAG_MASK 0xff 250 #define RTL8366RB_VLAN_MEMBER_MASK 0xff 251 /* Third config word per member config, STAG currently unused */ 252 #define RTL8366RB_VLAN_STAG_MBR_MASK 0xff 253 #define RTL8366RB_VLAN_STAG_MBR_SHIFT 8 254 #define RTL8366RB_VLAN_STAG_IDX_MASK 0x7 255 #define RTL8366RB_VLAN_STAG_IDX_SHIFT 5 256 #define RTL8366RB_VLAN_FID_MASK 0x7 257 258 /* Port ingress bandwidth control */ 259 #define RTL8366RB_IB_BASE 0x0200 260 #define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + (pnum)) 261 #define RTL8366RB_IB_BDTH_MASK 0x3fff 262 #define RTL8366RB_IB_PREIFG BIT(14) 263 264 /* Port egress bandwidth control */ 265 #define RTL8366RB_EB_BASE 0x02d1 266 #define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + (pnum)) 267 #define RTL8366RB_EB_BDTH_MASK 0x3fff 268 #define RTL8366RB_EB_PREIFG_REG 0x02f8 269 #define RTL8366RB_EB_PREIFG BIT(9) 270 271 #define RTL8366RB_BDTH_SW_MAX 1048512 /* 1048576? */ 272 #define RTL8366RB_BDTH_UNIT 64 273 #define RTL8366RB_BDTH_REG_DEFAULT 16383 274 275 /* QOS */ 276 #define RTL8366RB_QOS BIT(15) 277 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */ 278 #define RTL8366RB_QOS_DEFAULT_PREIFG 1 279 280 /* Interrupt handling */ 281 #define RTL8366RB_INTERRUPT_CONTROL_REG 0x0440 282 #define RTL8366RB_INTERRUPT_POLARITY BIT(0) 283 #define RTL8366RB_P4_RGMII_LED BIT(2) 284 #define RTL8366RB_INTERRUPT_MASK_REG 0x0441 285 #define RTL8366RB_INTERRUPT_LINK_CHGALL GENMASK(11, 0) 286 #define RTL8366RB_INTERRUPT_ACLEXCEED BIT(8) 287 #define RTL8366RB_INTERRUPT_STORMEXCEED BIT(9) 288 #define RTL8366RB_INTERRUPT_P4_FIBER BIT(12) 289 #define RTL8366RB_INTERRUPT_P4_UTP BIT(13) 290 #define RTL8366RB_INTERRUPT_VALID (RTL8366RB_INTERRUPT_LINK_CHGALL | \ 291 RTL8366RB_INTERRUPT_ACLEXCEED | \ 292 RTL8366RB_INTERRUPT_STORMEXCEED | \ 293 RTL8366RB_INTERRUPT_P4_FIBER | \ 294 RTL8366RB_INTERRUPT_P4_UTP) 295 #define RTL8366RB_INTERRUPT_STATUS_REG 0x0442 296 #define RTL8366RB_NUM_INTERRUPT 14 /* 0..13 */ 297 298 /* Port isolation registers */ 299 #define RTL8366RB_PORT_ISO_BASE 0x0F08 300 #define RTL8366RB_PORT_ISO(pnum) (RTL8366RB_PORT_ISO_BASE + (pnum)) 301 #define RTL8366RB_PORT_ISO_EN BIT(0) 302 #define RTL8366RB_PORT_ISO_PORTS_MASK GENMASK(7, 1) 303 #define RTL8366RB_PORT_ISO_PORTS(pmask) ((pmask) << 1) 304 305 /* bits 0..5 enable force when cleared */ 306 #define RTL8366RB_MAC_FORCE_CTRL_REG 0x0F11 307 308 #define RTL8366RB_OAM_PARSER_REG 0x0F14 309 #define RTL8366RB_OAM_MULTIPLEXER_REG 0x0F15 310 311 #define RTL8366RB_GREEN_FEATURE_REG 0x0F51 312 #define RTL8366RB_GREEN_FEATURE_MSK 0x0007 313 #define RTL8366RB_GREEN_FEATURE_TX BIT(0) 314 #define RTL8366RB_GREEN_FEATURE_RX BIT(2) 315 316 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = { 317 { 0, 0, 4, "IfInOctets" }, 318 { 0, 4, 4, "EtherStatsOctets" }, 319 { 0, 8, 2, "EtherStatsUnderSizePkts" }, 320 { 0, 10, 2, "EtherFragments" }, 321 { 0, 12, 2, "EtherStatsPkts64Octets" }, 322 { 0, 14, 2, "EtherStatsPkts65to127Octets" }, 323 { 0, 16, 2, "EtherStatsPkts128to255Octets" }, 324 { 0, 18, 2, "EtherStatsPkts256to511Octets" }, 325 { 0, 20, 2, "EtherStatsPkts512to1023Octets" }, 326 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" }, 327 { 0, 24, 2, "EtherOversizeStats" }, 328 { 0, 26, 2, "EtherStatsJabbers" }, 329 { 0, 28, 2, "IfInUcastPkts" }, 330 { 0, 30, 2, "EtherStatsMulticastPkts" }, 331 { 0, 32, 2, "EtherStatsBroadcastPkts" }, 332 { 0, 34, 2, "EtherStatsDropEvents" }, 333 { 0, 36, 2, "Dot3StatsFCSErrors" }, 334 { 0, 38, 2, "Dot3StatsSymbolErrors" }, 335 { 0, 40, 2, "Dot3InPauseFrames" }, 336 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" }, 337 { 0, 44, 4, "IfOutOctets" }, 338 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" }, 339 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" }, 340 { 0, 52, 2, "Dot3sDeferredTransmissions" }, 341 { 0, 54, 2, "Dot3StatsLateCollisions" }, 342 { 0, 56, 2, "EtherStatsCollisions" }, 343 { 0, 58, 2, "Dot3StatsExcessiveCollisions" }, 344 { 0, 60, 2, "Dot3OutPauseFrames" }, 345 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" }, 346 { 0, 64, 2, "Dot1dTpPortInDiscards" }, 347 { 0, 66, 2, "IfOutUcastPkts" }, 348 { 0, 68, 2, "IfOutMulticastPkts" }, 349 { 0, 70, 2, "IfOutBroadcastPkts" }, 350 }; 351 352 static int rtl8366rb_get_mib_counter(struct realtek_priv *priv, 353 int port, 354 struct rtl8366_mib_counter *mib, 355 u64 *mibvalue) 356 { 357 u32 addr, val; 358 int ret; 359 int i; 360 361 addr = RTL8366RB_MIB_COUNTER_BASE + 362 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) + 363 mib->offset; 364 365 /* Writing access counter address first 366 * then ASIC will prepare 64bits counter wait for being retrived 367 */ 368 ret = regmap_write(priv->map, addr, 0); /* Write whatever */ 369 if (ret) 370 return ret; 371 372 /* Read MIB control register */ 373 ret = regmap_read(priv->map, RTL8366RB_MIB_CTRL_REG, &val); 374 if (ret) 375 return -EIO; 376 377 if (val & RTL8366RB_MIB_CTRL_BUSY_MASK) 378 return -EBUSY; 379 380 if (val & RTL8366RB_MIB_CTRL_RESET_MASK) 381 return -EIO; 382 383 /* Read each individual MIB 16 bits at the time */ 384 *mibvalue = 0; 385 for (i = mib->length; i > 0; i--) { 386 ret = regmap_read(priv->map, addr + (i - 1), &val); 387 if (ret) 388 return ret; 389 *mibvalue = (*mibvalue << 16) | (val & 0xFFFF); 390 } 391 return 0; 392 } 393 394 static u32 rtl8366rb_get_irqmask(struct irq_data *d) 395 { 396 int line = irqd_to_hwirq(d); 397 u32 val; 398 399 /* For line interrupts we combine link down in bits 400 * 6..11 with link up in bits 0..5 into one interrupt. 401 */ 402 if (line < 12) 403 val = BIT(line) | BIT(line + 6); 404 else 405 val = BIT(line); 406 return val; 407 } 408 409 static void rtl8366rb_mask_irq(struct irq_data *d) 410 { 411 struct realtek_priv *priv = irq_data_get_irq_chip_data(d); 412 int ret; 413 414 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG, 415 rtl8366rb_get_irqmask(d), 0); 416 if (ret) 417 dev_err(priv->dev, "could not mask IRQ\n"); 418 } 419 420 static void rtl8366rb_unmask_irq(struct irq_data *d) 421 { 422 struct realtek_priv *priv = irq_data_get_irq_chip_data(d); 423 int ret; 424 425 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG, 426 rtl8366rb_get_irqmask(d), 427 rtl8366rb_get_irqmask(d)); 428 if (ret) 429 dev_err(priv->dev, "could not unmask IRQ\n"); 430 } 431 432 static irqreturn_t rtl8366rb_irq(int irq, void *data) 433 { 434 struct realtek_priv *priv = data; 435 u32 stat; 436 int ret; 437 438 /* This clears the IRQ status register */ 439 ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG, 440 &stat); 441 if (ret) { 442 dev_err(priv->dev, "can't read interrupt status\n"); 443 return IRQ_NONE; 444 } 445 stat &= RTL8366RB_INTERRUPT_VALID; 446 if (!stat) 447 return IRQ_NONE; 448 while (stat) { 449 int line = __ffs(stat); 450 int child_irq; 451 452 stat &= ~BIT(line); 453 /* For line interrupts we combine link down in bits 454 * 6..11 with link up in bits 0..5 into one interrupt. 455 */ 456 if (line < 12 && line > 5) 457 line -= 5; 458 child_irq = irq_find_mapping(priv->irqdomain, line); 459 handle_nested_irq(child_irq); 460 } 461 return IRQ_HANDLED; 462 } 463 464 static struct irq_chip rtl8366rb_irq_chip = { 465 .name = "RTL8366RB", 466 .irq_mask = rtl8366rb_mask_irq, 467 .irq_unmask = rtl8366rb_unmask_irq, 468 }; 469 470 static int rtl8366rb_irq_map(struct irq_domain *domain, unsigned int irq, 471 irq_hw_number_t hwirq) 472 { 473 irq_set_chip_data(irq, domain->host_data); 474 irq_set_chip_and_handler(irq, &rtl8366rb_irq_chip, handle_simple_irq); 475 irq_set_nested_thread(irq, 1); 476 irq_set_noprobe(irq); 477 478 return 0; 479 } 480 481 static void rtl8366rb_irq_unmap(struct irq_domain *d, unsigned int irq) 482 { 483 irq_set_nested_thread(irq, 0); 484 irq_set_chip_and_handler(irq, NULL, NULL); 485 irq_set_chip_data(irq, NULL); 486 } 487 488 static const struct irq_domain_ops rtl8366rb_irqdomain_ops = { 489 .map = rtl8366rb_irq_map, 490 .unmap = rtl8366rb_irq_unmap, 491 .xlate = irq_domain_xlate_onecell, 492 }; 493 494 static int rtl8366rb_setup_cascaded_irq(struct realtek_priv *priv) 495 { 496 struct device_node *intc; 497 unsigned long irq_trig; 498 int irq; 499 int ret; 500 u32 val; 501 int i; 502 503 intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller"); 504 if (!intc) { 505 dev_err(priv->dev, "missing child interrupt-controller node\n"); 506 return -EINVAL; 507 } 508 /* RB8366RB IRQs cascade off this one */ 509 irq = of_irq_get(intc, 0); 510 if (irq <= 0) { 511 dev_err(priv->dev, "failed to get parent IRQ\n"); 512 ret = irq ? irq : -EINVAL; 513 goto out_put_node; 514 } 515 516 /* This clears the IRQ status register */ 517 ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG, 518 &val); 519 if (ret) { 520 dev_err(priv->dev, "can't read interrupt status\n"); 521 goto out_put_node; 522 } 523 524 /* Fetch IRQ edge information from the descriptor */ 525 irq_trig = irq_get_trigger_type(irq); 526 switch (irq_trig) { 527 case IRQF_TRIGGER_RISING: 528 case IRQF_TRIGGER_HIGH: 529 dev_info(priv->dev, "active high/rising IRQ\n"); 530 val = 0; 531 break; 532 case IRQF_TRIGGER_FALLING: 533 case IRQF_TRIGGER_LOW: 534 dev_info(priv->dev, "active low/falling IRQ\n"); 535 val = RTL8366RB_INTERRUPT_POLARITY; 536 break; 537 } 538 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_CONTROL_REG, 539 RTL8366RB_INTERRUPT_POLARITY, 540 val); 541 if (ret) { 542 dev_err(priv->dev, "could not configure IRQ polarity\n"); 543 goto out_put_node; 544 } 545 546 ret = devm_request_threaded_irq(priv->dev, irq, NULL, 547 rtl8366rb_irq, IRQF_ONESHOT, 548 "RTL8366RB", priv); 549 if (ret) { 550 dev_err(priv->dev, "unable to request irq: %d\n", ret); 551 goto out_put_node; 552 } 553 priv->irqdomain = irq_domain_create_linear(of_fwnode_handle(intc), RTL8366RB_NUM_INTERRUPT, 554 &rtl8366rb_irqdomain_ops, priv); 555 if (!priv->irqdomain) { 556 dev_err(priv->dev, "failed to create IRQ domain\n"); 557 ret = -EINVAL; 558 goto out_put_node; 559 } 560 for (i = 0; i < priv->num_ports; i++) 561 irq_set_parent(irq_create_mapping(priv->irqdomain, i), irq); 562 563 out_put_node: 564 of_node_put(intc); 565 return ret; 566 } 567 568 static int rtl8366rb_set_addr(struct realtek_priv *priv) 569 { 570 u8 addr[ETH_ALEN]; 571 u16 val; 572 int ret; 573 574 eth_random_addr(addr); 575 576 dev_info(priv->dev, "set MAC: %pM\n", addr); 577 val = addr[0] << 8 | addr[1]; 578 ret = regmap_write(priv->map, RTL8366RB_SMAR0, val); 579 if (ret) 580 return ret; 581 val = addr[2] << 8 | addr[3]; 582 ret = regmap_write(priv->map, RTL8366RB_SMAR1, val); 583 if (ret) 584 return ret; 585 val = addr[4] << 8 | addr[5]; 586 ret = regmap_write(priv->map, RTL8366RB_SMAR2, val); 587 if (ret) 588 return ret; 589 590 return 0; 591 } 592 593 /* Found in a vendor driver */ 594 595 /* Struct for handling the jam tables' entries */ 596 struct rtl8366rb_jam_tbl_entry { 597 u16 reg; 598 u16 val; 599 }; 600 601 /* For the "version 0" early silicon, appear in most source releases */ 602 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_0[] = { 603 {0x000B, 0x0001}, {0x03A6, 0x0100}, {0x03A7, 0x0001}, {0x02D1, 0x3FFF}, 604 {0x02D2, 0x3FFF}, {0x02D3, 0x3FFF}, {0x02D4, 0x3FFF}, {0x02D5, 0x3FFF}, 605 {0x02D6, 0x3FFF}, {0x02D7, 0x3FFF}, {0x02D8, 0x3FFF}, {0x022B, 0x0688}, 606 {0x022C, 0x0FAC}, {0x03D0, 0x4688}, {0x03D1, 0x01F5}, {0x0000, 0x0830}, 607 {0x02F9, 0x0200}, {0x02F7, 0x7FFF}, {0x02F8, 0x03FF}, {0x0080, 0x03E8}, 608 {0x0081, 0x00CE}, {0x0082, 0x00DA}, {0x0083, 0x0230}, {0xBE0F, 0x2000}, 609 {0x0231, 0x422A}, {0x0232, 0x422A}, {0x0233, 0x422A}, {0x0234, 0x422A}, 610 {0x0235, 0x422A}, {0x0236, 0x422A}, {0x0237, 0x422A}, {0x0238, 0x422A}, 611 {0x0239, 0x422A}, {0x023A, 0x422A}, {0x023B, 0x422A}, {0x023C, 0x422A}, 612 {0x023D, 0x422A}, {0x023E, 0x422A}, {0x023F, 0x422A}, {0x0240, 0x422A}, 613 {0x0241, 0x422A}, {0x0242, 0x422A}, {0x0243, 0x422A}, {0x0244, 0x422A}, 614 {0x0245, 0x422A}, {0x0246, 0x422A}, {0x0247, 0x422A}, {0x0248, 0x422A}, 615 {0x0249, 0x0146}, {0x024A, 0x0146}, {0x024B, 0x0146}, {0xBE03, 0xC961}, 616 {0x024D, 0x0146}, {0x024E, 0x0146}, {0x024F, 0x0146}, {0x0250, 0x0146}, 617 {0xBE64, 0x0226}, {0x0252, 0x0146}, {0x0253, 0x0146}, {0x024C, 0x0146}, 618 {0x0251, 0x0146}, {0x0254, 0x0146}, {0xBE62, 0x3FD0}, {0x0084, 0x0320}, 619 {0x0255, 0x0146}, {0x0256, 0x0146}, {0x0257, 0x0146}, {0x0258, 0x0146}, 620 {0x0259, 0x0146}, {0x025A, 0x0146}, {0x025B, 0x0146}, {0x025C, 0x0146}, 621 {0x025D, 0x0146}, {0x025E, 0x0146}, {0x025F, 0x0146}, {0x0260, 0x0146}, 622 {0x0261, 0xA23F}, {0x0262, 0x0294}, {0x0263, 0xA23F}, {0x0264, 0x0294}, 623 {0x0265, 0xA23F}, {0x0266, 0x0294}, {0x0267, 0xA23F}, {0x0268, 0x0294}, 624 {0x0269, 0xA23F}, {0x026A, 0x0294}, {0x026B, 0xA23F}, {0x026C, 0x0294}, 625 {0x026D, 0xA23F}, {0x026E, 0x0294}, {0x026F, 0xA23F}, {0x0270, 0x0294}, 626 {0x02F5, 0x0048}, {0xBE09, 0x0E00}, {0xBE1E, 0x0FA0}, {0xBE14, 0x8448}, 627 {0xBE15, 0x1007}, {0xBE4A, 0xA284}, {0xC454, 0x3F0B}, {0xC474, 0x3F0B}, 628 {0xBE48, 0x3672}, {0xBE4B, 0x17A7}, {0xBE4C, 0x0B15}, {0xBE52, 0x0EDD}, 629 {0xBE49, 0x8C00}, {0xBE5B, 0x785C}, {0xBE5C, 0x785C}, {0xBE5D, 0x785C}, 630 {0xBE61, 0x368A}, {0xBE63, 0x9B84}, {0xC456, 0xCC13}, {0xC476, 0xCC13}, 631 {0xBE65, 0x307D}, {0xBE6D, 0x0005}, {0xBE6E, 0xE120}, {0xBE2E, 0x7BAF}, 632 }; 633 634 /* This v1 init sequence is from Belkin F5D8235 U-Boot release */ 635 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_1[] = { 636 {0x0000, 0x0830}, {0x0001, 0x8000}, {0x0400, 0x8130}, {0xBE78, 0x3C3C}, 637 {0x0431, 0x5432}, {0xBE37, 0x0CE4}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0}, 638 {0xC44C, 0x1585}, {0xC44C, 0x1185}, {0xC44C, 0x1585}, {0xC46C, 0x1585}, 639 {0xC46C, 0x1185}, {0xC46C, 0x1585}, {0xC451, 0x2135}, {0xC471, 0x2135}, 640 {0xBE10, 0x8140}, {0xBE15, 0x0007}, {0xBE6E, 0xE120}, {0xBE69, 0xD20F}, 641 {0xBE6B, 0x0320}, {0xBE24, 0xB000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF20}, 642 {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800}, {0xBE24, 0x0000}, 643 {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60}, {0xBE21, 0x0140}, 644 {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000}, {0xBE2E, 0x7B7A}, 645 {0xBE36, 0x0CE4}, {0x02F5, 0x0048}, {0xBE77, 0x2940}, {0x000A, 0x83E0}, 646 {0xBE79, 0x3C3C}, {0xBE00, 0x1340}, 647 }; 648 649 /* This v2 init sequence is from Belkin F5D8235 U-Boot release */ 650 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_2[] = { 651 {0x0450, 0x0000}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432}, 652 {0xC44F, 0x6250}, {0xC46F, 0x6250}, {0xC456, 0x0C14}, {0xC476, 0x0C14}, 653 {0xC44C, 0x1C85}, {0xC44C, 0x1885}, {0xC44C, 0x1C85}, {0xC46C, 0x1C85}, 654 {0xC46C, 0x1885}, {0xC46C, 0x1C85}, {0xC44C, 0x0885}, {0xC44C, 0x0881}, 655 {0xC44C, 0x0885}, {0xC46C, 0x0885}, {0xC46C, 0x0881}, {0xC46C, 0x0885}, 656 {0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001}, 657 {0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6E, 0x0320}, 658 {0xBE77, 0x2940}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120}, 659 {0x8000, 0x0001}, {0xBE15, 0x1007}, {0x8000, 0x0000}, {0xBE15, 0x1007}, 660 {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160}, {0xBE10, 0x8140}, 661 {0xBE00, 0x1340}, {0x0F51, 0x0010}, 662 }; 663 664 /* Appears in a DDWRT code dump */ 665 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_3[] = { 666 {0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432}, 667 {0x0F51, 0x0017}, {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0}, 668 {0xC456, 0x0C14}, {0xC476, 0x0C14}, {0xC454, 0x3F8B}, {0xC474, 0x3F8B}, 669 {0xC450, 0x2071}, {0xC470, 0x2071}, {0xC451, 0x226B}, {0xC471, 0x226B}, 670 {0xC452, 0xA293}, {0xC472, 0xA293}, {0xC44C, 0x1585}, {0xC44C, 0x1185}, 671 {0xC44C, 0x1585}, {0xC46C, 0x1585}, {0xC46C, 0x1185}, {0xC46C, 0x1585}, 672 {0xC44C, 0x0185}, {0xC44C, 0x0181}, {0xC44C, 0x0185}, {0xC46C, 0x0185}, 673 {0xC46C, 0x0181}, {0xC46C, 0x0185}, {0xBE24, 0xB000}, {0xBE23, 0xFF51}, 674 {0xBE22, 0xDF20}, {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800}, 675 {0xBE24, 0x0000}, {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60}, 676 {0xBE21, 0x0140}, {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000}, 677 {0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001}, 678 {0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6B, 0x0320}, 679 {0xBE77, 0x2800}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120}, 680 {0x8000, 0x0001}, {0xBE10, 0x8140}, {0x8000, 0x0000}, {0xBE10, 0x8140}, 681 {0xBE15, 0x1007}, {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160}, 682 {0xBE10, 0x8140}, {0xBE00, 0x1340}, {0x0450, 0x0000}, {0x0401, 0x0000}, 683 }; 684 685 /* Belkin F5D8235 v1, "belkin,f5d8235-v1" */ 686 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_f5d8235[] = { 687 {0x0242, 0x02BF}, {0x0245, 0x02BF}, {0x0248, 0x02BF}, {0x024B, 0x02BF}, 688 {0x024E, 0x02BF}, {0x0251, 0x02BF}, {0x0254, 0x0A3F}, {0x0256, 0x0A3F}, 689 {0x0258, 0x0A3F}, {0x025A, 0x0A3F}, {0x025C, 0x0A3F}, {0x025E, 0x0A3F}, 690 {0x0263, 0x007C}, {0x0100, 0x0004}, {0xBE5B, 0x3500}, {0x800E, 0x200F}, 691 {0xBE1D, 0x0F00}, {0x8001, 0x5011}, {0x800A, 0xA2F4}, {0x800B, 0x17A3}, 692 {0xBE4B, 0x17A3}, {0xBE41, 0x5011}, {0xBE17, 0x2100}, {0x8000, 0x8304}, 693 {0xBE40, 0x8304}, {0xBE4A, 0xA2F4}, {0x800C, 0xA8D5}, {0x8014, 0x5500}, 694 {0x8015, 0x0004}, {0xBE4C, 0xA8D5}, {0xBE59, 0x0008}, {0xBE09, 0x0E00}, 695 {0xBE36, 0x1036}, {0xBE37, 0x1036}, {0x800D, 0x00FF}, {0xBE4D, 0x00FF}, 696 }; 697 698 /* DGN3500, "netgear,dgn3500", "netgear,dgn3500b" */ 699 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_dgn3500[] = { 700 {0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0F51, 0x0017}, 701 {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0}, {0x0450, 0x0000}, 702 {0x0401, 0x0000}, {0x0431, 0x0960}, 703 }; 704 705 /* This jam table activates "green ethernet", which means low power mode 706 * and is claimed to detect the cable length and not use more power than 707 * necessary, and the ports should enter power saving mode 10 seconds after 708 * a cable is disconnected. Seems to always be the same. 709 */ 710 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_green_jam[] = { 711 {0xBE78, 0x323C}, {0xBE77, 0x5000}, {0xBE2E, 0x7BA7}, 712 {0xBE59, 0x3459}, {0xBE5A, 0x745A}, {0xBE5B, 0x785C}, 713 {0xBE5C, 0x785C}, {0xBE6E, 0xE120}, {0xBE79, 0x323C}, 714 }; 715 716 /* Function that jams the tables in the proper registers */ 717 static int rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry *jam_table, 718 int jam_size, struct realtek_priv *priv, 719 bool write_dbg) 720 { 721 u32 val; 722 int ret; 723 int i; 724 725 for (i = 0; i < jam_size; i++) { 726 if ((jam_table[i].reg & 0xBE00) == 0xBE00) { 727 ret = regmap_read(priv->map, 728 RTL8366RB_PHY_ACCESS_BUSY_REG, 729 &val); 730 if (ret) 731 return ret; 732 if (!(val & RTL8366RB_PHY_INT_BUSY)) { 733 ret = regmap_write(priv->map, 734 RTL8366RB_PHY_ACCESS_CTRL_REG, 735 RTL8366RB_PHY_CTRL_WRITE); 736 if (ret) 737 return ret; 738 } 739 } 740 if (write_dbg) 741 dev_dbg(priv->dev, "jam %04x into register %04x\n", 742 jam_table[i].val, 743 jam_table[i].reg); 744 ret = regmap_write(priv->map, 745 jam_table[i].reg, 746 jam_table[i].val); 747 if (ret) 748 return ret; 749 } 750 return 0; 751 } 752 753 /* This code is used also with LEDs disabled */ 754 int rb8366rb_set_ledgroup_mode(struct realtek_priv *priv, 755 u8 led_group, 756 enum rtl8366_ledgroup_mode mode) 757 { 758 int ret; 759 u32 val; 760 761 val = mode << RTL8366RB_LED_CTRL_OFFSET(led_group); 762 763 ret = regmap_update_bits(priv->map, 764 RTL8366RB_LED_CTRL_REG, 765 RTL8366RB_LED_CTRL_MASK(led_group), 766 val); 767 if (ret) 768 return ret; 769 770 return 0; 771 } 772 773 /* This code is used also with LEDs disabled */ 774 static int rtl8366rb_setup_all_leds_off(struct realtek_priv *priv) 775 { 776 int ret = 0; 777 int i; 778 779 regmap_update_bits(priv->map, 780 RTL8366RB_INTERRUPT_CONTROL_REG, 781 RTL8366RB_P4_RGMII_LED, 782 0); 783 784 for (i = 0; i < RTL8366RB_NUM_LEDGROUPS; i++) { 785 ret = rb8366rb_set_ledgroup_mode(priv, i, 786 RTL8366RB_LEDGROUP_OFF); 787 if (ret) 788 return ret; 789 } 790 791 return ret; 792 } 793 794 static int rtl8366rb_setup(struct dsa_switch *ds) 795 { 796 struct realtek_priv *priv = ds->priv; 797 const struct rtl8366rb_jam_tbl_entry *jam_table; 798 struct rtl8366rb *rb; 799 u32 chip_ver = 0; 800 u32 chip_id = 0; 801 int jam_size; 802 int ret; 803 int i; 804 805 rb = priv->chip_data; 806 807 ret = regmap_read(priv->map, RTL8366RB_CHIP_ID_REG, &chip_id); 808 if (ret) { 809 dev_err(priv->dev, "unable to read chip id\n"); 810 return ret; 811 } 812 813 switch (chip_id) { 814 case RTL8366RB_CHIP_ID_8366: 815 break; 816 default: 817 dev_err(priv->dev, "unknown chip id (%04x)\n", chip_id); 818 return -ENODEV; 819 } 820 821 ret = regmap_read(priv->map, RTL8366RB_CHIP_VERSION_CTRL_REG, 822 &chip_ver); 823 if (ret) { 824 dev_err(priv->dev, "unable to read chip version\n"); 825 return ret; 826 } 827 828 dev_info(priv->dev, "RTL%04x ver %u chip found\n", 829 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK); 830 831 /* Do the init dance using the right jam table */ 832 switch (chip_ver) { 833 case 0: 834 jam_table = rtl8366rb_init_jam_ver_0; 835 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_0); 836 break; 837 case 1: 838 jam_table = rtl8366rb_init_jam_ver_1; 839 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_1); 840 break; 841 case 2: 842 jam_table = rtl8366rb_init_jam_ver_2; 843 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_2); 844 break; 845 default: 846 jam_table = rtl8366rb_init_jam_ver_3; 847 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_3); 848 break; 849 } 850 851 /* Special jam tables for special routers 852 * TODO: are these necessary? Maintainers, please test 853 * without them, using just the off-the-shelf tables. 854 */ 855 if (of_machine_is_compatible("belkin,f5d8235-v1")) { 856 jam_table = rtl8366rb_init_jam_f5d8235; 857 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_f5d8235); 858 } 859 if (of_machine_is_compatible("netgear,dgn3500") || 860 of_machine_is_compatible("netgear,dgn3500b")) { 861 jam_table = rtl8366rb_init_jam_dgn3500; 862 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_dgn3500); 863 } 864 865 ret = rtl8366rb_jam_table(jam_table, jam_size, priv, true); 866 if (ret) 867 return ret; 868 869 /* Isolate all user ports so they can only send packets to itself and the CPU port */ 870 for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) { 871 ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(i), 872 RTL8366RB_PORT_ISO_PORTS(BIT(RTL8366RB_PORT_NUM_CPU)) | 873 RTL8366RB_PORT_ISO_EN); 874 if (ret) 875 return ret; 876 } 877 /* CPU port can send packets to all ports */ 878 ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(RTL8366RB_PORT_NUM_CPU), 879 RTL8366RB_PORT_ISO_PORTS(dsa_user_ports(ds)) | 880 RTL8366RB_PORT_ISO_EN); 881 if (ret) 882 return ret; 883 884 /* Set up the "green ethernet" feature */ 885 ret = rtl8366rb_jam_table(rtl8366rb_green_jam, 886 ARRAY_SIZE(rtl8366rb_green_jam), priv, false); 887 if (ret) 888 return ret; 889 890 ret = regmap_write(priv->map, 891 RTL8366RB_GREEN_FEATURE_REG, 892 (chip_ver == 1) ? 0x0007 : 0x0003); 893 if (ret) 894 return ret; 895 896 /* Vendor driver sets 0x240 in registers 0xc and 0xd (undocumented) */ 897 ret = regmap_write(priv->map, 0x0c, 0x240); 898 if (ret) 899 return ret; 900 ret = regmap_write(priv->map, 0x0d, 0x240); 901 if (ret) 902 return ret; 903 904 /* Set some random MAC address */ 905 ret = rtl8366rb_set_addr(priv); 906 if (ret) 907 return ret; 908 909 /* Enable CPU port with custom DSA tag 8899. 910 * 911 * If you set RTL8366RB_CPU_NO_TAG (bit 15) in this register 912 * the custom tag is turned off. 913 */ 914 ret = regmap_update_bits(priv->map, RTL8366RB_CPU_CTRL_REG, 915 0xFFFF, 916 BIT(priv->cpu_port)); 917 if (ret) 918 return ret; 919 920 /* Make sure we default-enable the fixed CPU port */ 921 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, 922 BIT(priv->cpu_port), 923 0); 924 if (ret) 925 return ret; 926 927 /* Set default maximum packet length to 1536 bytes */ 928 ret = regmap_update_bits(priv->map, RTL8366RB_SGCR, 929 RTL8366RB_SGCR_MAX_LENGTH_MASK, 930 RTL8366RB_SGCR_MAX_LENGTH_1536); 931 if (ret) 932 return ret; 933 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) { 934 if (i == priv->cpu_port) 935 /* CPU port need to also accept the tag */ 936 rb->max_mtu[i] = ETH_DATA_LEN + RTL8366RB_CPU_TAG_SIZE; 937 else 938 rb->max_mtu[i] = ETH_DATA_LEN; 939 } 940 941 /* Disable learning for all ports */ 942 ret = regmap_write(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL, 943 RTL8366RB_PORT_ALL); 944 if (ret) 945 return ret; 946 947 /* Enable auto ageing for all ports */ 948 ret = regmap_write(priv->map, RTL8366RB_SECURITY_CTRL, 0); 949 if (ret) 950 return ret; 951 952 /* Port 4 setup: this enables Port 4, usually the WAN port, 953 * common PHY IO mode is apparently mode 0, and this is not what 954 * the port is initialized to. There is no explanation of the 955 * IO modes in the Realtek source code, if your WAN port is 956 * connected to something exotic such as fiber, then this might 957 * be worth experimenting with. 958 */ 959 ret = regmap_update_bits(priv->map, RTL8366RB_PMC0, 960 RTL8366RB_PMC0_P4_IOMODE_MASK, 961 0 << RTL8366RB_PMC0_P4_IOMODE_SHIFT); 962 if (ret) 963 return ret; 964 965 /* Accept all packets by default, we enable filtering on-demand */ 966 ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG, 967 0); 968 if (ret) 969 return ret; 970 ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG, 971 0); 972 if (ret) 973 return ret; 974 975 /* Don't drop packets whose DA has not been learned */ 976 ret = regmap_update_bits(priv->map, RTL8366RB_SSCR2, 977 RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0); 978 if (ret) 979 return ret; 980 981 /* Set blinking, used by all LED groups using HW triggers. 982 * TODO: make this configurable 983 */ 984 ret = regmap_update_bits(priv->map, RTL8366RB_LED_BLINKRATE_REG, 985 RTL8366RB_LED_BLINKRATE_MASK, 986 RTL8366RB_LED_BLINKRATE_56MS); 987 if (ret) 988 return ret; 989 990 /* Set up LED activity: 991 * Each port has 4 LEDs on fixed groups. Each group shares the same 992 * hardware trigger across all ports. LEDs can only be indiviually 993 * controlled setting the LED group to fixed mode and using the driver 994 * to toggle them LEDs on/off. 995 */ 996 if (priv->leds_disabled) { 997 ret = rtl8366rb_setup_all_leds_off(priv); 998 if (ret) 999 return ret; 1000 } else { 1001 ret = rtl8366rb_setup_leds(priv); 1002 if (ret) 1003 return ret; 1004 } 1005 1006 ret = rtl8366_reset_vlan(priv); 1007 if (ret) 1008 return ret; 1009 1010 ret = rtl8366rb_setup_cascaded_irq(priv); 1011 if (ret) 1012 dev_info(priv->dev, "no interrupt support\n"); 1013 1014 ret = rtl83xx_setup_user_mdio(ds); 1015 if (ret) { 1016 dev_err(priv->dev, "could not set up MDIO bus\n"); 1017 return -ENODEV; 1018 } 1019 1020 return 0; 1021 } 1022 1023 static enum dsa_tag_protocol rtl8366_get_tag_protocol(struct dsa_switch *ds, 1024 int port, 1025 enum dsa_tag_protocol mp) 1026 { 1027 /* This switch uses the 4 byte protocol A Realtek DSA tag */ 1028 return DSA_TAG_PROTO_RTL4_A; 1029 } 1030 1031 static void rtl8366rb_phylink_get_caps(struct dsa_switch *ds, int port, 1032 struct phylink_config *config) 1033 { 1034 unsigned long *interfaces = config->supported_interfaces; 1035 struct realtek_priv *priv = ds->priv; 1036 1037 if (port == priv->cpu_port) { 1038 __set_bit(PHY_INTERFACE_MODE_MII, interfaces); 1039 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces); 1040 /* REVMII only supports 100M FD */ 1041 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces); 1042 /* RGMII only supports 1G FD */ 1043 phy_interface_set_rgmii(interfaces); 1044 1045 config->mac_capabilities = MAC_1000 | MAC_100 | 1046 MAC_SYM_PAUSE; 1047 } else { 1048 /* RSGMII port, but we don't have that, and we don't 1049 * specify in DT, so phylib uses the default of GMII 1050 */ 1051 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces); 1052 config->mac_capabilities = MAC_1000 | MAC_100 | MAC_10 | 1053 MAC_SYM_PAUSE | MAC_ASYM_PAUSE; 1054 } 1055 } 1056 1057 static void 1058 rtl8366rb_mac_config(struct phylink_config *config, unsigned int mode, 1059 const struct phylink_link_state *state) 1060 { 1061 } 1062 1063 static void 1064 rtl8366rb_mac_link_up(struct phylink_config *config, struct phy_device *phydev, 1065 unsigned int mode, phy_interface_t interface, 1066 int speed, int duplex, bool tx_pause, bool rx_pause) 1067 { 1068 struct dsa_port *dp = dsa_phylink_to_port(config); 1069 struct realtek_priv *priv = dp->ds->priv; 1070 int port = dp->index; 1071 unsigned int val; 1072 int ret; 1073 1074 /* Allow forcing the mode on the fixed CPU port, no autonegotiation. 1075 * We assume autonegotiation works on the PHY-facing ports. 1076 */ 1077 if (port != priv->cpu_port) 1078 return; 1079 1080 dev_dbg(priv->dev, "MAC link up on CPU port (%d)\n", port); 1081 1082 ret = regmap_update_bits(priv->map, RTL8366RB_MAC_FORCE_CTRL_REG, 1083 BIT(port), BIT(port)); 1084 if (ret) { 1085 dev_err(priv->dev, "failed to force CPU port\n"); 1086 return; 1087 } 1088 1089 /* Conjure port config */ 1090 switch (speed) { 1091 case SPEED_10: 1092 val = RTL8366RB_PAACR_SPEED_10M; 1093 break; 1094 case SPEED_100: 1095 val = RTL8366RB_PAACR_SPEED_100M; 1096 break; 1097 case SPEED_1000: 1098 val = RTL8366RB_PAACR_SPEED_1000M; 1099 break; 1100 default: 1101 val = RTL8366RB_PAACR_SPEED_1000M; 1102 break; 1103 } 1104 1105 if (duplex == DUPLEX_FULL) 1106 val |= RTL8366RB_PAACR_FULL_DUPLEX; 1107 1108 if (tx_pause) 1109 val |= RTL8366RB_PAACR_TX_PAUSE; 1110 1111 if (rx_pause) 1112 val |= RTL8366RB_PAACR_RX_PAUSE; 1113 1114 val |= RTL8366RB_PAACR_LINK_UP; 1115 1116 ret = regmap_update_bits(priv->map, RTL8366RB_PAACR2, 1117 0xFF00U, 1118 val << 8); 1119 if (ret) { 1120 dev_err(priv->dev, "failed to set PAACR on CPU port\n"); 1121 return; 1122 } 1123 1124 dev_dbg(priv->dev, "set PAACR to %04x\n", val); 1125 1126 /* Enable the CPU port */ 1127 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port), 1128 0); 1129 if (ret) { 1130 dev_err(priv->dev, "failed to enable the CPU port\n"); 1131 return; 1132 } 1133 } 1134 1135 static void 1136 rtl8366rb_mac_link_down(struct phylink_config *config, unsigned int mode, 1137 phy_interface_t interface) 1138 { 1139 struct dsa_port *dp = dsa_phylink_to_port(config); 1140 struct realtek_priv *priv = dp->ds->priv; 1141 int port = dp->index; 1142 int ret; 1143 1144 if (port != priv->cpu_port) 1145 return; 1146 1147 dev_dbg(priv->dev, "MAC link down on CPU port (%d)\n", port); 1148 1149 /* Disable the CPU port */ 1150 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port), 1151 BIT(port)); 1152 if (ret) { 1153 dev_err(priv->dev, "failed to disable the CPU port\n"); 1154 return; 1155 } 1156 } 1157 1158 static int 1159 rtl8366rb_port_enable(struct dsa_switch *ds, int port, 1160 struct phy_device *phy) 1161 { 1162 struct realtek_priv *priv = ds->priv; 1163 int ret; 1164 1165 dev_dbg(priv->dev, "enable port %d\n", port); 1166 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port), 1167 0); 1168 if (ret) 1169 return ret; 1170 1171 return 0; 1172 } 1173 1174 static void 1175 rtl8366rb_port_disable(struct dsa_switch *ds, int port) 1176 { 1177 struct realtek_priv *priv = ds->priv; 1178 int ret; 1179 1180 dev_dbg(priv->dev, "disable port %d\n", port); 1181 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port), 1182 BIT(port)); 1183 if (ret) 1184 return; 1185 } 1186 1187 static int 1188 rtl8366rb_port_bridge_join(struct dsa_switch *ds, int port, 1189 struct dsa_bridge bridge, 1190 bool *tx_fwd_offload, 1191 struct netlink_ext_ack *extack) 1192 { 1193 struct realtek_priv *priv = ds->priv; 1194 unsigned int port_bitmap = 0; 1195 int ret, i; 1196 1197 /* Loop over all other ports than the current one */ 1198 for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) { 1199 /* Current port handled last */ 1200 if (i == port) 1201 continue; 1202 /* Not on this bridge */ 1203 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 1204 continue; 1205 /* Join this port to each other port on the bridge */ 1206 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i), 1207 RTL8366RB_PORT_ISO_PORTS(BIT(port)), 1208 RTL8366RB_PORT_ISO_PORTS(BIT(port))); 1209 if (ret) 1210 dev_err(priv->dev, "failed to join port %d\n", port); 1211 1212 port_bitmap |= BIT(i); 1213 } 1214 1215 /* Set the bits for the ports we can access */ 1216 return regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port), 1217 RTL8366RB_PORT_ISO_PORTS(port_bitmap), 1218 RTL8366RB_PORT_ISO_PORTS(port_bitmap)); 1219 } 1220 1221 static void 1222 rtl8366rb_port_bridge_leave(struct dsa_switch *ds, int port, 1223 struct dsa_bridge bridge) 1224 { 1225 struct realtek_priv *priv = ds->priv; 1226 unsigned int port_bitmap = 0; 1227 int ret, i; 1228 1229 /* Loop over all other ports than this one */ 1230 for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) { 1231 /* Current port handled last */ 1232 if (i == port) 1233 continue; 1234 /* Not on this bridge */ 1235 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 1236 continue; 1237 /* Remove this port from any other port on the bridge */ 1238 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i), 1239 RTL8366RB_PORT_ISO_PORTS(BIT(port)), 0); 1240 if (ret) 1241 dev_err(priv->dev, "failed to leave port %d\n", port); 1242 1243 port_bitmap |= BIT(i); 1244 } 1245 1246 /* Clear the bits for the ports we can not access, leave ourselves */ 1247 regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port), 1248 RTL8366RB_PORT_ISO_PORTS(port_bitmap), 0); 1249 } 1250 1251 /** 1252 * rtl8366rb_drop_untagged() - make the switch drop untagged and C-tagged frames 1253 * @priv: SMI state container 1254 * @port: the port to drop untagged and C-tagged frames on 1255 * @drop: whether to drop or pass untagged and C-tagged frames 1256 * 1257 * Return: zero for success, a negative number on error. 1258 */ 1259 static int rtl8366rb_drop_untagged(struct realtek_priv *priv, int port, bool drop) 1260 { 1261 return regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG, 1262 RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port), 1263 drop ? RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) : 0); 1264 } 1265 1266 static int rtl8366rb_vlan_filtering(struct dsa_switch *ds, int port, 1267 bool vlan_filtering, 1268 struct netlink_ext_ack *extack) 1269 { 1270 struct realtek_priv *priv = ds->priv; 1271 struct rtl8366rb *rb; 1272 int ret; 1273 1274 rb = priv->chip_data; 1275 1276 dev_dbg(priv->dev, "port %d: %s VLAN filtering\n", port, 1277 str_enable_disable(vlan_filtering)); 1278 1279 /* If the port is not in the member set, the frame will be dropped */ 1280 ret = regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG, 1281 BIT(port), vlan_filtering ? BIT(port) : 0); 1282 if (ret) 1283 return ret; 1284 1285 /* If VLAN filtering is enabled and PVID is also enabled, we must 1286 * not drop any untagged or C-tagged frames. If we turn off VLAN 1287 * filtering on a port, we need to accept any frames. 1288 */ 1289 if (vlan_filtering) 1290 ret = rtl8366rb_drop_untagged(priv, port, !rb->pvid_enabled[port]); 1291 else 1292 ret = rtl8366rb_drop_untagged(priv, port, false); 1293 1294 return ret; 1295 } 1296 1297 static int 1298 rtl8366rb_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1299 struct switchdev_brport_flags flags, 1300 struct netlink_ext_ack *extack) 1301 { 1302 /* We support enabling/disabling learning */ 1303 if (flags.mask & ~(BR_LEARNING)) 1304 return -EINVAL; 1305 1306 return 0; 1307 } 1308 1309 static int 1310 rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port, 1311 struct switchdev_brport_flags flags, 1312 struct netlink_ext_ack *extack) 1313 { 1314 struct realtek_priv *priv = ds->priv; 1315 int ret; 1316 1317 if (flags.mask & BR_LEARNING) { 1318 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL, 1319 BIT(port), 1320 (flags.val & BR_LEARNING) ? 0 : BIT(port)); 1321 if (ret) 1322 return ret; 1323 } 1324 1325 return 0; 1326 } 1327 1328 static void 1329 rtl8366rb_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1330 { 1331 struct realtek_priv *priv = ds->priv; 1332 u32 val; 1333 int i; 1334 1335 switch (state) { 1336 case BR_STATE_DISABLED: 1337 val = RTL8366RB_STP_STATE_DISABLED; 1338 break; 1339 case BR_STATE_BLOCKING: 1340 case BR_STATE_LISTENING: 1341 val = RTL8366RB_STP_STATE_BLOCKING; 1342 break; 1343 case BR_STATE_LEARNING: 1344 val = RTL8366RB_STP_STATE_LEARNING; 1345 break; 1346 case BR_STATE_FORWARDING: 1347 val = RTL8366RB_STP_STATE_FORWARDING; 1348 break; 1349 default: 1350 dev_err(priv->dev, "unknown bridge state requested\n"); 1351 return; 1352 } 1353 1354 /* Set the same status for the port on all the FIDs */ 1355 for (i = 0; i < RTL8366RB_NUM_FIDS; i++) { 1356 regmap_update_bits(priv->map, RTL8366RB_STP_STATE_BASE + i, 1357 RTL8366RB_STP_STATE_MASK(port), 1358 RTL8366RB_STP_STATE(port, val)); 1359 } 1360 } 1361 1362 static void 1363 rtl8366rb_port_fast_age(struct dsa_switch *ds, int port) 1364 { 1365 struct realtek_priv *priv = ds->priv; 1366 1367 /* This will age out any learned L2 entries */ 1368 regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL, 1369 BIT(port), BIT(port)); 1370 /* Restore the normal state of things */ 1371 regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL, 1372 BIT(port), 0); 1373 } 1374 1375 static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1376 { 1377 struct realtek_priv *priv = ds->priv; 1378 struct rtl8366rb *rb; 1379 unsigned int max_mtu; 1380 u32 len; 1381 int i; 1382 1383 /* Cache the per-port MTU setting */ 1384 rb = priv->chip_data; 1385 rb->max_mtu[port] = new_mtu; 1386 1387 /* Roof out the MTU for the entire switch to the greatest 1388 * common denominator: the biggest set for any one port will 1389 * be the biggest MTU for the switch. 1390 */ 1391 max_mtu = ETH_DATA_LEN; 1392 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) { 1393 if (rb->max_mtu[i] > max_mtu) 1394 max_mtu = rb->max_mtu[i]; 1395 } 1396 1397 /* Translate to layer 2 size. 1398 * Add ethernet and (possible) VLAN headers, and checksum to the size. 1399 * For ETH_DATA_LEN (1500 bytes) this will add up to 1522 bytes. 1400 */ 1401 max_mtu += VLAN_ETH_HLEN; 1402 max_mtu += ETH_FCS_LEN; 1403 1404 if (max_mtu <= 1522) 1405 len = RTL8366RB_SGCR_MAX_LENGTH_1522; 1406 else if (max_mtu > 1522 && max_mtu <= 1536) 1407 /* This will be the most common default if using VLAN and 1408 * CPU tagging on a port as both VLAN and CPU tag will 1409 * result in 1518 + 4 + 4 = 1526 bytes. 1410 */ 1411 len = RTL8366RB_SGCR_MAX_LENGTH_1536; 1412 else if (max_mtu > 1536 && max_mtu <= 1552) 1413 len = RTL8366RB_SGCR_MAX_LENGTH_1552; 1414 else 1415 len = RTL8366RB_SGCR_MAX_LENGTH_16000; 1416 1417 return regmap_update_bits(priv->map, RTL8366RB_SGCR, 1418 RTL8366RB_SGCR_MAX_LENGTH_MASK, 1419 len); 1420 } 1421 1422 static int rtl8366rb_max_mtu(struct dsa_switch *ds, int port) 1423 { 1424 /* The max MTU is 16000 bytes, so we subtract the ethernet 1425 * headers with VLAN and checksum and arrive at 1426 * 16000 - 18 - 4 = 15978. This does not include the CPU tag 1427 * since that is added to the requested MTU by the DSA framework. 1428 */ 1429 return 16000 - VLAN_ETH_HLEN - ETH_FCS_LEN; 1430 } 1431 1432 static int rtl8366rb_get_vlan_4k(struct realtek_priv *priv, u32 vid, 1433 struct rtl8366_vlan_4k *vlan4k) 1434 { 1435 u32 data[3]; 1436 int ret; 1437 int i; 1438 1439 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k)); 1440 1441 if (vid >= RTL8366RB_NUM_VIDS) 1442 return -EINVAL; 1443 1444 /* write VID */ 1445 ret = regmap_write(priv->map, RTL8366RB_VLAN_TABLE_WRITE_BASE, 1446 vid & RTL8366RB_VLAN_VID_MASK); 1447 if (ret) 1448 return ret; 1449 1450 /* write table access control word */ 1451 ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG, 1452 RTL8366RB_TABLE_VLAN_READ_CTRL); 1453 if (ret) 1454 return ret; 1455 1456 for (i = 0; i < 3; i++) { 1457 ret = regmap_read(priv->map, 1458 RTL8366RB_VLAN_TABLE_READ_BASE + i, 1459 &data[i]); 1460 if (ret) 1461 return ret; 1462 } 1463 1464 vlan4k->vid = vid; 1465 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) & 1466 RTL8366RB_VLAN_UNTAG_MASK; 1467 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK; 1468 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK; 1469 1470 return 0; 1471 } 1472 1473 static int rtl8366rb_set_vlan_4k(struct realtek_priv *priv, 1474 const struct rtl8366_vlan_4k *vlan4k) 1475 { 1476 u32 data[3]; 1477 int ret; 1478 int i; 1479 1480 if (vlan4k->vid >= RTL8366RB_NUM_VIDS || 1481 vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK || 1482 vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK || 1483 vlan4k->fid > RTL8366RB_FIDMAX) 1484 return -EINVAL; 1485 1486 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK; 1487 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) | 1488 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) << 1489 RTL8366RB_VLAN_UNTAG_SHIFT); 1490 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK; 1491 1492 for (i = 0; i < 3; i++) { 1493 ret = regmap_write(priv->map, 1494 RTL8366RB_VLAN_TABLE_WRITE_BASE + i, 1495 data[i]); 1496 if (ret) 1497 return ret; 1498 } 1499 1500 /* write table access control word */ 1501 ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG, 1502 RTL8366RB_TABLE_VLAN_WRITE_CTRL); 1503 1504 return ret; 1505 } 1506 1507 static int rtl8366rb_get_vlan_mc(struct realtek_priv *priv, u32 index, 1508 struct rtl8366_vlan_mc *vlanmc) 1509 { 1510 u32 data[3]; 1511 int ret; 1512 int i; 1513 1514 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc)); 1515 1516 if (index >= RTL8366RB_NUM_VLANS) 1517 return -EINVAL; 1518 1519 for (i = 0; i < 3; i++) { 1520 ret = regmap_read(priv->map, 1521 RTL8366RB_VLAN_MC_BASE(index) + i, 1522 &data[i]); 1523 if (ret) 1524 return ret; 1525 } 1526 1527 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK; 1528 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) & 1529 RTL8366RB_VLAN_PRIORITY_MASK; 1530 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) & 1531 RTL8366RB_VLAN_UNTAG_MASK; 1532 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK; 1533 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK; 1534 1535 return 0; 1536 } 1537 1538 static int rtl8366rb_set_vlan_mc(struct realtek_priv *priv, u32 index, 1539 const struct rtl8366_vlan_mc *vlanmc) 1540 { 1541 u32 data[3]; 1542 int ret; 1543 int i; 1544 1545 if (index >= RTL8366RB_NUM_VLANS || 1546 vlanmc->vid >= RTL8366RB_NUM_VIDS || 1547 vlanmc->priority > RTL8366RB_PRIORITYMAX || 1548 vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK || 1549 vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK || 1550 vlanmc->fid > RTL8366RB_FIDMAX) 1551 return -EINVAL; 1552 1553 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) | 1554 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) << 1555 RTL8366RB_VLAN_PRIORITY_SHIFT); 1556 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) | 1557 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) << 1558 RTL8366RB_VLAN_UNTAG_SHIFT); 1559 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK; 1560 1561 for (i = 0; i < 3; i++) { 1562 ret = regmap_write(priv->map, 1563 RTL8366RB_VLAN_MC_BASE(index) + i, 1564 data[i]); 1565 if (ret) 1566 return ret; 1567 } 1568 1569 return 0; 1570 } 1571 1572 static int rtl8366rb_get_mc_index(struct realtek_priv *priv, int port, int *val) 1573 { 1574 u32 data; 1575 int ret; 1576 1577 if (port >= priv->num_ports) 1578 return -EINVAL; 1579 1580 ret = regmap_read(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port), 1581 &data); 1582 if (ret) 1583 return ret; 1584 1585 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) & 1586 RTL8366RB_PORT_VLAN_CTRL_MASK; 1587 1588 return 0; 1589 } 1590 1591 static int rtl8366rb_set_mc_index(struct realtek_priv *priv, int port, int index) 1592 { 1593 struct dsa_switch *ds = &priv->ds; 1594 struct rtl8366rb *rb; 1595 bool pvid_enabled; 1596 int ret; 1597 1598 rb = priv->chip_data; 1599 pvid_enabled = !!index; 1600 1601 if (port >= priv->num_ports || index >= RTL8366RB_NUM_VLANS) 1602 return -EINVAL; 1603 1604 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port), 1605 RTL8366RB_PORT_VLAN_CTRL_MASK << 1606 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port), 1607 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) << 1608 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)); 1609 if (ret) 1610 return ret; 1611 1612 rb->pvid_enabled[port] = pvid_enabled; 1613 1614 /* If VLAN filtering is enabled and PVID is also enabled, we must 1615 * not drop any untagged or C-tagged frames. Make sure to update the 1616 * filtering setting. 1617 */ 1618 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1619 ret = rtl8366rb_drop_untagged(priv, port, !pvid_enabled); 1620 1621 return ret; 1622 } 1623 1624 static bool rtl8366rb_is_vlan_valid(struct realtek_priv *priv, unsigned int vlan) 1625 { 1626 unsigned int max = RTL8366RB_NUM_VLANS - 1; 1627 1628 if (priv->vlan4k_enabled) 1629 max = RTL8366RB_NUM_VIDS - 1; 1630 1631 if (vlan > max) 1632 return false; 1633 1634 return true; 1635 } 1636 1637 static int rtl8366rb_enable_vlan(struct realtek_priv *priv, bool enable) 1638 { 1639 dev_dbg(priv->dev, "%s VLAN\n", str_enable_disable(enable)); 1640 return regmap_update_bits(priv->map, 1641 RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN, 1642 enable ? RTL8366RB_SGCR_EN_VLAN : 0); 1643 } 1644 1645 static int rtl8366rb_enable_vlan4k(struct realtek_priv *priv, bool enable) 1646 { 1647 dev_dbg(priv->dev, "%s VLAN 4k\n", str_enable_disable(enable)); 1648 return regmap_update_bits(priv->map, RTL8366RB_SGCR, 1649 RTL8366RB_SGCR_EN_VLAN_4KTB, 1650 enable ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0); 1651 } 1652 1653 static int rtl8366rb_phy_read(struct realtek_priv *priv, int phy, int regnum) 1654 { 1655 u32 val; 1656 u32 reg; 1657 int ret; 1658 1659 if (phy > RTL8366RB_PHY_NO_MAX) 1660 return -EINVAL; 1661 1662 rtl83xx_lock(priv); 1663 1664 ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG, 1665 RTL8366RB_PHY_CTRL_READ); 1666 if (ret) 1667 goto out; 1668 1669 reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum; 1670 1671 ret = regmap_write(priv->map_nolock, reg, 0); 1672 if (ret) { 1673 dev_err(priv->dev, 1674 "failed to write PHY%d reg %04x @ %04x, ret %d\n", 1675 phy, regnum, reg, ret); 1676 goto out; 1677 } 1678 1679 ret = regmap_read(priv->map_nolock, RTL8366RB_PHY_ACCESS_DATA_REG, 1680 &val); 1681 if (ret) 1682 goto out; 1683 1684 ret = val; 1685 1686 dev_dbg(priv->dev, "read PHY%d register 0x%04x @ %08x, val <- %04x\n", 1687 phy, regnum, reg, val); 1688 1689 out: 1690 rtl83xx_unlock(priv); 1691 1692 return ret; 1693 } 1694 1695 static int rtl8366rb_phy_write(struct realtek_priv *priv, int phy, int regnum, 1696 u16 val) 1697 { 1698 u32 reg; 1699 int ret; 1700 1701 if (phy > RTL8366RB_PHY_NO_MAX) 1702 return -EINVAL; 1703 1704 rtl83xx_lock(priv); 1705 1706 ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG, 1707 RTL8366RB_PHY_CTRL_WRITE); 1708 if (ret) 1709 goto out; 1710 1711 reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum; 1712 1713 dev_dbg(priv->dev, "write PHY%d register 0x%04x @ %04x, val -> %04x\n", 1714 phy, regnum, reg, val); 1715 1716 ret = regmap_write(priv->map_nolock, reg, val); 1717 if (ret) 1718 goto out; 1719 1720 out: 1721 rtl83xx_unlock(priv); 1722 1723 return ret; 1724 } 1725 1726 static int rtl8366rb_reset_chip(struct realtek_priv *priv) 1727 { 1728 int timeout = 10; 1729 u32 val; 1730 int ret; 1731 1732 priv->write_reg_noack(priv, RTL8366RB_RESET_CTRL_REG, 1733 RTL8366RB_CHIP_CTRL_RESET_HW); 1734 do { 1735 usleep_range(20000, 25000); 1736 ret = regmap_read(priv->map, RTL8366RB_RESET_CTRL_REG, &val); 1737 if (ret) 1738 return ret; 1739 1740 if (!(val & RTL8366RB_CHIP_CTRL_RESET_HW)) 1741 break; 1742 } while (--timeout); 1743 1744 if (!timeout) { 1745 dev_err(priv->dev, "timeout waiting for the switch to reset\n"); 1746 return -EIO; 1747 } 1748 1749 return 0; 1750 } 1751 1752 static int rtl8366rb_detect(struct realtek_priv *priv) 1753 { 1754 struct device *dev = priv->dev; 1755 int ret; 1756 u32 val; 1757 1758 /* Detect device */ 1759 ret = regmap_read(priv->map, 0x5c, &val); 1760 if (ret) { 1761 dev_err(dev, "can't get chip ID (%d)\n", ret); 1762 return ret; 1763 } 1764 1765 switch (val) { 1766 case 0x6027: 1767 dev_info(dev, "found an RTL8366S switch\n"); 1768 dev_err(dev, "this switch is not yet supported, submit patches!\n"); 1769 return -ENODEV; 1770 case 0x5937: 1771 dev_info(dev, "found an RTL8366RB switch\n"); 1772 priv->cpu_port = RTL8366RB_PORT_NUM_CPU; 1773 priv->num_ports = RTL8366RB_NUM_PORTS; 1774 priv->num_vlan_mc = RTL8366RB_NUM_VLANS; 1775 priv->mib_counters = rtl8366rb_mib_counters; 1776 priv->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters); 1777 break; 1778 default: 1779 dev_info(dev, "found an Unknown Realtek switch (id=0x%04x)\n", 1780 val); 1781 break; 1782 } 1783 1784 ret = rtl8366rb_reset_chip(priv); 1785 if (ret) 1786 return ret; 1787 1788 return 0; 1789 } 1790 1791 static const struct phylink_mac_ops rtl8366rb_phylink_mac_ops = { 1792 .mac_config = rtl8366rb_mac_config, 1793 .mac_link_down = rtl8366rb_mac_link_down, 1794 .mac_link_up = rtl8366rb_mac_link_up, 1795 }; 1796 1797 static const struct dsa_switch_ops rtl8366rb_switch_ops = { 1798 .get_tag_protocol = rtl8366_get_tag_protocol, 1799 .setup = rtl8366rb_setup, 1800 .phylink_get_caps = rtl8366rb_phylink_get_caps, 1801 .get_strings = rtl8366_get_strings, 1802 .get_ethtool_stats = rtl8366_get_ethtool_stats, 1803 .get_sset_count = rtl8366_get_sset_count, 1804 .port_bridge_join = rtl8366rb_port_bridge_join, 1805 .port_bridge_leave = rtl8366rb_port_bridge_leave, 1806 .port_vlan_filtering = rtl8366rb_vlan_filtering, 1807 .port_vlan_add = rtl8366_vlan_add, 1808 .port_vlan_del = rtl8366_vlan_del, 1809 .port_enable = rtl8366rb_port_enable, 1810 .port_disable = rtl8366rb_port_disable, 1811 .port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags, 1812 .port_bridge_flags = rtl8366rb_port_bridge_flags, 1813 .port_stp_state_set = rtl8366rb_port_stp_state_set, 1814 .port_fast_age = rtl8366rb_port_fast_age, 1815 .port_change_mtu = rtl8366rb_change_mtu, 1816 .port_max_mtu = rtl8366rb_max_mtu, 1817 .port_hsr_join = dsa_port_simple_hsr_join, 1818 .port_hsr_leave = dsa_port_simple_hsr_leave, 1819 }; 1820 1821 static const struct realtek_ops rtl8366rb_ops = { 1822 .detect = rtl8366rb_detect, 1823 .get_vlan_mc = rtl8366rb_get_vlan_mc, 1824 .set_vlan_mc = rtl8366rb_set_vlan_mc, 1825 .get_vlan_4k = rtl8366rb_get_vlan_4k, 1826 .set_vlan_4k = rtl8366rb_set_vlan_4k, 1827 .get_mc_index = rtl8366rb_get_mc_index, 1828 .set_mc_index = rtl8366rb_set_mc_index, 1829 .get_mib_counter = rtl8366rb_get_mib_counter, 1830 .is_vlan_valid = rtl8366rb_is_vlan_valid, 1831 .enable_vlan = rtl8366rb_enable_vlan, 1832 .enable_vlan4k = rtl8366rb_enable_vlan4k, 1833 .phy_read = rtl8366rb_phy_read, 1834 .phy_write = rtl8366rb_phy_write, 1835 }; 1836 1837 const struct realtek_variant rtl8366rb_variant = { 1838 .ds_ops = &rtl8366rb_switch_ops, 1839 .ops = &rtl8366rb_ops, 1840 .phylink_mac_ops = &rtl8366rb_phylink_mac_ops, 1841 .clk_delay = 10, 1842 .cmd_read = 0xa9, 1843 .cmd_write = 0xa8, 1844 .chip_data_sz = sizeof(struct rtl8366rb), 1845 }; 1846 1847 static const struct of_device_id rtl8366rb_of_match[] = { 1848 { .compatible = "realtek,rtl8366rb", .data = &rtl8366rb_variant, }, 1849 { /* sentinel */ }, 1850 }; 1851 MODULE_DEVICE_TABLE(of, rtl8366rb_of_match); 1852 1853 static struct platform_driver rtl8366rb_smi_driver = { 1854 .driver = { 1855 .name = "rtl8366rb-smi", 1856 .of_match_table = rtl8366rb_of_match, 1857 }, 1858 .probe = realtek_smi_probe, 1859 .remove = realtek_smi_remove, 1860 .shutdown = realtek_smi_shutdown, 1861 }; 1862 1863 static struct mdio_driver rtl8366rb_mdio_driver = { 1864 .mdiodrv.driver = { 1865 .name = "rtl8366rb-mdio", 1866 .of_match_table = rtl8366rb_of_match, 1867 }, 1868 .probe = realtek_mdio_probe, 1869 .remove = realtek_mdio_remove, 1870 .shutdown = realtek_mdio_shutdown, 1871 }; 1872 1873 static int rtl8366rb_init(void) 1874 { 1875 int ret; 1876 1877 ret = realtek_mdio_driver_register(&rtl8366rb_mdio_driver); 1878 if (ret) 1879 return ret; 1880 1881 ret = realtek_smi_driver_register(&rtl8366rb_smi_driver); 1882 if (ret) { 1883 realtek_mdio_driver_unregister(&rtl8366rb_mdio_driver); 1884 return ret; 1885 } 1886 1887 return 0; 1888 } 1889 module_init(rtl8366rb_init); 1890 1891 static void __exit rtl8366rb_exit(void) 1892 { 1893 realtek_smi_driver_unregister(&rtl8366rb_smi_driver); 1894 realtek_mdio_driver_unregister(&rtl8366rb_mdio_driver); 1895 } 1896 module_exit(rtl8366rb_exit); 1897 1898 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>"); 1899 MODULE_DESCRIPTION("Driver for RTL8366RB ethernet switch"); 1900 MODULE_LICENSE("GPL"); 1901 MODULE_IMPORT_NS("REALTEK_DSA"); 1902