1 // SPDX-License-Identifier: GPL-2.0 2 /* Realtek SMI subdriver for the Realtek RTL8366RB ethernet switch 3 * 4 * This is a sparsely documented chip, the only viable documentation seems 5 * to be a patched up code drop from the vendor that appear in various 6 * GPL source trees. 7 * 8 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> 9 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org> 10 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com> 11 * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv> 12 * Copyright (C) 2011 Colin Leitner <colin.leitner@googlemail.com> 13 */ 14 15 #include <linux/bitops.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <linux/interrupt.h> 19 #include <linux/irqdomain.h> 20 #include <linux/irqchip/chained_irq.h> 21 #include <linux/of_irq.h> 22 #include <linux/regmap.h> 23 24 #include "realtek.h" 25 26 #define RTL8366RB_PORT_NUM_CPU 5 27 #define RTL8366RB_NUM_PORTS 6 28 #define RTL8366RB_PHY_NO_MAX 4 29 #define RTL8366RB_PHY_ADDR_MAX 31 30 31 /* Switch Global Configuration register */ 32 #define RTL8366RB_SGCR 0x0000 33 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL BIT(0) 34 #define RTL8366RB_SGCR_MAX_LENGTH(a) ((a) << 4) 35 #define RTL8366RB_SGCR_MAX_LENGTH_MASK RTL8366RB_SGCR_MAX_LENGTH(0x3) 36 #define RTL8366RB_SGCR_MAX_LENGTH_1522 RTL8366RB_SGCR_MAX_LENGTH(0x0) 37 #define RTL8366RB_SGCR_MAX_LENGTH_1536 RTL8366RB_SGCR_MAX_LENGTH(0x1) 38 #define RTL8366RB_SGCR_MAX_LENGTH_1552 RTL8366RB_SGCR_MAX_LENGTH(0x2) 39 #define RTL8366RB_SGCR_MAX_LENGTH_16000 RTL8366RB_SGCR_MAX_LENGTH(0x3) 40 #define RTL8366RB_SGCR_EN_VLAN BIT(13) 41 #define RTL8366RB_SGCR_EN_VLAN_4KTB BIT(14) 42 43 /* Port Enable Control register */ 44 #define RTL8366RB_PECR 0x0001 45 46 /* Switch per-port learning disablement register */ 47 #define RTL8366RB_PORT_LEARNDIS_CTRL 0x0002 48 49 /* Security control, actually aging register */ 50 #define RTL8366RB_SECURITY_CTRL 0x0003 51 52 #define RTL8366RB_SSCR2 0x0004 53 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA BIT(0) 54 55 /* Port Mode Control registers */ 56 #define RTL8366RB_PMC0 0x0005 57 #define RTL8366RB_PMC0_SPI BIT(0) 58 #define RTL8366RB_PMC0_EN_AUTOLOAD BIT(1) 59 #define RTL8366RB_PMC0_PROBE BIT(2) 60 #define RTL8366RB_PMC0_DIS_BISR BIT(3) 61 #define RTL8366RB_PMC0_ADCTEST BIT(4) 62 #define RTL8366RB_PMC0_SRAM_DIAG BIT(5) 63 #define RTL8366RB_PMC0_EN_SCAN BIT(6) 64 #define RTL8366RB_PMC0_P4_IOMODE_SHIFT 7 65 #define RTL8366RB_PMC0_P4_IOMODE_MASK GENMASK(9, 7) 66 #define RTL8366RB_PMC0_P5_IOMODE_SHIFT 10 67 #define RTL8366RB_PMC0_P5_IOMODE_MASK GENMASK(12, 10) 68 #define RTL8366RB_PMC0_SDSMODE_SHIFT 13 69 #define RTL8366RB_PMC0_SDSMODE_MASK GENMASK(15, 13) 70 #define RTL8366RB_PMC1 0x0006 71 72 /* Port Mirror Control Register */ 73 #define RTL8366RB_PMCR 0x0007 74 #define RTL8366RB_PMCR_SOURCE_PORT(a) (a) 75 #define RTL8366RB_PMCR_SOURCE_PORT_MASK 0x000f 76 #define RTL8366RB_PMCR_MONITOR_PORT(a) ((a) << 4) 77 #define RTL8366RB_PMCR_MONITOR_PORT_MASK 0x00f0 78 #define RTL8366RB_PMCR_MIRROR_RX BIT(8) 79 #define RTL8366RB_PMCR_MIRROR_TX BIT(9) 80 #define RTL8366RB_PMCR_MIRROR_SPC BIT(10) 81 #define RTL8366RB_PMCR_MIRROR_ISO BIT(11) 82 83 /* bits 0..7 = port 0, bits 8..15 = port 1 */ 84 #define RTL8366RB_PAACR0 0x0010 85 /* bits 0..7 = port 2, bits 8..15 = port 3 */ 86 #define RTL8366RB_PAACR1 0x0011 87 /* bits 0..7 = port 4, bits 8..15 = port 5 */ 88 #define RTL8366RB_PAACR2 0x0012 89 #define RTL8366RB_PAACR_SPEED_10M 0 90 #define RTL8366RB_PAACR_SPEED_100M 1 91 #define RTL8366RB_PAACR_SPEED_1000M 2 92 #define RTL8366RB_PAACR_FULL_DUPLEX BIT(2) 93 #define RTL8366RB_PAACR_LINK_UP BIT(4) 94 #define RTL8366RB_PAACR_TX_PAUSE BIT(5) 95 #define RTL8366RB_PAACR_RX_PAUSE BIT(6) 96 #define RTL8366RB_PAACR_AN BIT(7) 97 98 /* bits 0..7 = port 0, bits 8..15 = port 1 */ 99 #define RTL8366RB_PSTAT0 0x0014 100 /* bits 0..7 = port 2, bits 8..15 = port 3 */ 101 #define RTL8366RB_PSTAT1 0x0015 102 /* bits 0..7 = port 4, bits 8..15 = port 5 */ 103 #define RTL8366RB_PSTAT2 0x0016 104 105 #define RTL8366RB_POWER_SAVING_REG 0x0021 106 107 /* Spanning tree status (STP) control, two bits per port per FID */ 108 #define RTL8366RB_STP_STATE_BASE 0x0050 /* 0x0050..0x0057 */ 109 #define RTL8366RB_STP_STATE_DISABLED 0x0 110 #define RTL8366RB_STP_STATE_BLOCKING 0x1 111 #define RTL8366RB_STP_STATE_LEARNING 0x2 112 #define RTL8366RB_STP_STATE_FORWARDING 0x3 113 #define RTL8366RB_STP_MASK GENMASK(1, 0) 114 #define RTL8366RB_STP_STATE(port, state) \ 115 ((state) << ((port) * 2)) 116 #define RTL8366RB_STP_STATE_MASK(port) \ 117 RTL8366RB_STP_STATE((port), RTL8366RB_STP_MASK) 118 119 /* CPU port control reg */ 120 #define RTL8368RB_CPU_CTRL_REG 0x0061 121 #define RTL8368RB_CPU_PORTS_MSK 0x00FF 122 /* Disables inserting custom tag length/type 0x8899 */ 123 #define RTL8368RB_CPU_NO_TAG BIT(15) 124 125 #define RTL8366RB_SMAR0 0x0070 /* bits 0..15 */ 126 #define RTL8366RB_SMAR1 0x0071 /* bits 16..31 */ 127 #define RTL8366RB_SMAR2 0x0072 /* bits 32..47 */ 128 129 #define RTL8366RB_RESET_CTRL_REG 0x0100 130 #define RTL8366RB_CHIP_CTRL_RESET_HW BIT(0) 131 #define RTL8366RB_CHIP_CTRL_RESET_SW BIT(1) 132 133 #define RTL8366RB_CHIP_ID_REG 0x0509 134 #define RTL8366RB_CHIP_ID_8366 0x5937 135 #define RTL8366RB_CHIP_VERSION_CTRL_REG 0x050A 136 #define RTL8366RB_CHIP_VERSION_MASK 0xf 137 138 /* PHY registers control */ 139 #define RTL8366RB_PHY_ACCESS_CTRL_REG 0x8000 140 #define RTL8366RB_PHY_CTRL_READ BIT(0) 141 #define RTL8366RB_PHY_CTRL_WRITE 0 142 #define RTL8366RB_PHY_ACCESS_BUSY_REG 0x8001 143 #define RTL8366RB_PHY_INT_BUSY BIT(0) 144 #define RTL8366RB_PHY_EXT_BUSY BIT(4) 145 #define RTL8366RB_PHY_ACCESS_DATA_REG 0x8002 146 #define RTL8366RB_PHY_EXT_CTRL_REG 0x8010 147 #define RTL8366RB_PHY_EXT_WRDATA_REG 0x8011 148 #define RTL8366RB_PHY_EXT_RDDATA_REG 0x8012 149 150 #define RTL8366RB_PHY_REG_MASK 0x1f 151 #define RTL8366RB_PHY_PAGE_OFFSET 5 152 #define RTL8366RB_PHY_PAGE_MASK (0xf << 5) 153 #define RTL8366RB_PHY_NO_OFFSET 9 154 #define RTL8366RB_PHY_NO_MASK (0x1f << 9) 155 156 /* VLAN Ingress Control Register 1, one bit per port. 157 * bit 0 .. 5 will make the switch drop ingress frames without 158 * VID such as untagged or priority-tagged frames for respective 159 * port. 160 * bit 6 .. 11 will make the switch drop ingress frames carrying 161 * a C-tag with VID != 0 for respective port. 162 */ 163 #define RTL8366RB_VLAN_INGRESS_CTRL1_REG 0x037E 164 #define RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) (BIT((port)) | BIT((port) + 6)) 165 166 /* VLAN Ingress Control Register 2, one bit per port. 167 * bit0 .. bit5 will make the switch drop all ingress frames with 168 * a VLAN classification that does not include the port is in its 169 * member set. 170 */ 171 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG 0x037f 172 173 /* LED control registers */ 174 #define RTL8366RB_LED_BLINKRATE_REG 0x0430 175 #define RTL8366RB_LED_BLINKRATE_MASK 0x0007 176 #define RTL8366RB_LED_BLINKRATE_28MS 0x0000 177 #define RTL8366RB_LED_BLINKRATE_56MS 0x0001 178 #define RTL8366RB_LED_BLINKRATE_84MS 0x0002 179 #define RTL8366RB_LED_BLINKRATE_111MS 0x0003 180 #define RTL8366RB_LED_BLINKRATE_222MS 0x0004 181 #define RTL8366RB_LED_BLINKRATE_446MS 0x0005 182 183 #define RTL8366RB_LED_CTRL_REG 0x0431 184 #define RTL8366RB_LED_OFF 0x0 185 #define RTL8366RB_LED_DUP_COL 0x1 186 #define RTL8366RB_LED_LINK_ACT 0x2 187 #define RTL8366RB_LED_SPD1000 0x3 188 #define RTL8366RB_LED_SPD100 0x4 189 #define RTL8366RB_LED_SPD10 0x5 190 #define RTL8366RB_LED_SPD1000_ACT 0x6 191 #define RTL8366RB_LED_SPD100_ACT 0x7 192 #define RTL8366RB_LED_SPD10_ACT 0x8 193 #define RTL8366RB_LED_SPD100_10_ACT 0x9 194 #define RTL8366RB_LED_FIBER 0xa 195 #define RTL8366RB_LED_AN_FAULT 0xb 196 #define RTL8366RB_LED_LINK_RX 0xc 197 #define RTL8366RB_LED_LINK_TX 0xd 198 #define RTL8366RB_LED_MASTER 0xe 199 #define RTL8366RB_LED_FORCE 0xf 200 #define RTL8366RB_LED_0_1_CTRL_REG 0x0432 201 #define RTL8366RB_LED_1_OFFSET 6 202 #define RTL8366RB_LED_2_3_CTRL_REG 0x0433 203 #define RTL8366RB_LED_3_OFFSET 6 204 205 #define RTL8366RB_MIB_COUNT 33 206 #define RTL8366RB_GLOBAL_MIB_COUNT 1 207 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET 0x0050 208 #define RTL8366RB_MIB_COUNTER_BASE 0x1000 209 #define RTL8366RB_MIB_CTRL_REG 0x13F0 210 #define RTL8366RB_MIB_CTRL_USER_MASK 0x0FFC 211 #define RTL8366RB_MIB_CTRL_BUSY_MASK BIT(0) 212 #define RTL8366RB_MIB_CTRL_RESET_MASK BIT(1) 213 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p) BIT(2 + (_p)) 214 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET BIT(11) 215 216 #define RTL8366RB_PORT_VLAN_CTRL_BASE 0x0063 217 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p) \ 218 (RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4) 219 #define RTL8366RB_PORT_VLAN_CTRL_MASK 0xf 220 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4)) 221 222 #define RTL8366RB_VLAN_TABLE_READ_BASE 0x018C 223 #define RTL8366RB_VLAN_TABLE_WRITE_BASE 0x0185 224 225 #define RTL8366RB_TABLE_ACCESS_CTRL_REG 0x0180 226 #define RTL8366RB_TABLE_VLAN_READ_CTRL 0x0E01 227 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL 0x0F01 228 229 #define RTL8366RB_VLAN_MC_BASE(_x) (0x0020 + (_x) * 3) 230 231 #define RTL8366RB_PORT_LINK_STATUS_BASE 0x0014 232 #define RTL8366RB_PORT_STATUS_SPEED_MASK 0x0003 233 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK 0x0004 234 #define RTL8366RB_PORT_STATUS_LINK_MASK 0x0010 235 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK 0x0020 236 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK 0x0040 237 #define RTL8366RB_PORT_STATUS_AN_MASK 0x0080 238 239 #define RTL8366RB_NUM_VLANS 16 240 #define RTL8366RB_NUM_LEDGROUPS 4 241 #define RTL8366RB_NUM_VIDS 4096 242 #define RTL8366RB_PRIORITYMAX 7 243 #define RTL8366RB_NUM_FIDS 8 244 #define RTL8366RB_FIDMAX 7 245 246 #define RTL8366RB_PORT_1 BIT(0) /* In userspace port 0 */ 247 #define RTL8366RB_PORT_2 BIT(1) /* In userspace port 1 */ 248 #define RTL8366RB_PORT_3 BIT(2) /* In userspace port 2 */ 249 #define RTL8366RB_PORT_4 BIT(3) /* In userspace port 3 */ 250 #define RTL8366RB_PORT_5 BIT(4) /* In userspace port 4 */ 251 252 #define RTL8366RB_PORT_CPU BIT(5) /* CPU port */ 253 254 #define RTL8366RB_PORT_ALL (RTL8366RB_PORT_1 | \ 255 RTL8366RB_PORT_2 | \ 256 RTL8366RB_PORT_3 | \ 257 RTL8366RB_PORT_4 | \ 258 RTL8366RB_PORT_5 | \ 259 RTL8366RB_PORT_CPU) 260 261 #define RTL8366RB_PORT_ALL_BUT_CPU (RTL8366RB_PORT_1 | \ 262 RTL8366RB_PORT_2 | \ 263 RTL8366RB_PORT_3 | \ 264 RTL8366RB_PORT_4 | \ 265 RTL8366RB_PORT_5) 266 267 #define RTL8366RB_PORT_ALL_EXTERNAL (RTL8366RB_PORT_1 | \ 268 RTL8366RB_PORT_2 | \ 269 RTL8366RB_PORT_3 | \ 270 RTL8366RB_PORT_4) 271 272 #define RTL8366RB_PORT_ALL_INTERNAL RTL8366RB_PORT_CPU 273 274 /* First configuration word per member config, VID and prio */ 275 #define RTL8366RB_VLAN_VID_MASK 0xfff 276 #define RTL8366RB_VLAN_PRIORITY_SHIFT 12 277 #define RTL8366RB_VLAN_PRIORITY_MASK 0x7 278 /* Second configuration word per member config, member and untagged */ 279 #define RTL8366RB_VLAN_UNTAG_SHIFT 8 280 #define RTL8366RB_VLAN_UNTAG_MASK 0xff 281 #define RTL8366RB_VLAN_MEMBER_MASK 0xff 282 /* Third config word per member config, STAG currently unused */ 283 #define RTL8366RB_VLAN_STAG_MBR_MASK 0xff 284 #define RTL8366RB_VLAN_STAG_MBR_SHIFT 8 285 #define RTL8366RB_VLAN_STAG_IDX_MASK 0x7 286 #define RTL8366RB_VLAN_STAG_IDX_SHIFT 5 287 #define RTL8366RB_VLAN_FID_MASK 0x7 288 289 /* Port ingress bandwidth control */ 290 #define RTL8366RB_IB_BASE 0x0200 291 #define RTL8366RB_IB_REG(pnum) (RTL8366RB_IB_BASE + (pnum)) 292 #define RTL8366RB_IB_BDTH_MASK 0x3fff 293 #define RTL8366RB_IB_PREIFG BIT(14) 294 295 /* Port egress bandwidth control */ 296 #define RTL8366RB_EB_BASE 0x02d1 297 #define RTL8366RB_EB_REG(pnum) (RTL8366RB_EB_BASE + (pnum)) 298 #define RTL8366RB_EB_BDTH_MASK 0x3fff 299 #define RTL8366RB_EB_PREIFG_REG 0x02f8 300 #define RTL8366RB_EB_PREIFG BIT(9) 301 302 #define RTL8366RB_BDTH_SW_MAX 1048512 /* 1048576? */ 303 #define RTL8366RB_BDTH_UNIT 64 304 #define RTL8366RB_BDTH_REG_DEFAULT 16383 305 306 /* QOS */ 307 #define RTL8366RB_QOS BIT(15) 308 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */ 309 #define RTL8366RB_QOS_DEFAULT_PREIFG 1 310 311 /* Interrupt handling */ 312 #define RTL8366RB_INTERRUPT_CONTROL_REG 0x0440 313 #define RTL8366RB_INTERRUPT_POLARITY BIT(0) 314 #define RTL8366RB_P4_RGMII_LED BIT(2) 315 #define RTL8366RB_INTERRUPT_MASK_REG 0x0441 316 #define RTL8366RB_INTERRUPT_LINK_CHGALL GENMASK(11, 0) 317 #define RTL8366RB_INTERRUPT_ACLEXCEED BIT(8) 318 #define RTL8366RB_INTERRUPT_STORMEXCEED BIT(9) 319 #define RTL8366RB_INTERRUPT_P4_FIBER BIT(12) 320 #define RTL8366RB_INTERRUPT_P4_UTP BIT(13) 321 #define RTL8366RB_INTERRUPT_VALID (RTL8366RB_INTERRUPT_LINK_CHGALL | \ 322 RTL8366RB_INTERRUPT_ACLEXCEED | \ 323 RTL8366RB_INTERRUPT_STORMEXCEED | \ 324 RTL8366RB_INTERRUPT_P4_FIBER | \ 325 RTL8366RB_INTERRUPT_P4_UTP) 326 #define RTL8366RB_INTERRUPT_STATUS_REG 0x0442 327 #define RTL8366RB_NUM_INTERRUPT 14 /* 0..13 */ 328 329 /* Port isolation registers */ 330 #define RTL8366RB_PORT_ISO_BASE 0x0F08 331 #define RTL8366RB_PORT_ISO(pnum) (RTL8366RB_PORT_ISO_BASE + (pnum)) 332 #define RTL8366RB_PORT_ISO_EN BIT(0) 333 #define RTL8366RB_PORT_ISO_PORTS_MASK GENMASK(7, 1) 334 #define RTL8366RB_PORT_ISO_PORTS(pmask) ((pmask) << 1) 335 336 /* bits 0..5 enable force when cleared */ 337 #define RTL8366RB_MAC_FORCE_CTRL_REG 0x0F11 338 339 #define RTL8366RB_OAM_PARSER_REG 0x0F14 340 #define RTL8366RB_OAM_MULTIPLEXER_REG 0x0F15 341 342 #define RTL8366RB_GREEN_FEATURE_REG 0x0F51 343 #define RTL8366RB_GREEN_FEATURE_MSK 0x0007 344 #define RTL8366RB_GREEN_FEATURE_TX BIT(0) 345 #define RTL8366RB_GREEN_FEATURE_RX BIT(2) 346 347 /** 348 * struct rtl8366rb - RTL8366RB-specific data 349 * @max_mtu: per-port max MTU setting 350 * @pvid_enabled: if PVID is set for respective port 351 */ 352 struct rtl8366rb { 353 unsigned int max_mtu[RTL8366RB_NUM_PORTS]; 354 bool pvid_enabled[RTL8366RB_NUM_PORTS]; 355 }; 356 357 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = { 358 { 0, 0, 4, "IfInOctets" }, 359 { 0, 4, 4, "EtherStatsOctets" }, 360 { 0, 8, 2, "EtherStatsUnderSizePkts" }, 361 { 0, 10, 2, "EtherFragments" }, 362 { 0, 12, 2, "EtherStatsPkts64Octets" }, 363 { 0, 14, 2, "EtherStatsPkts65to127Octets" }, 364 { 0, 16, 2, "EtherStatsPkts128to255Octets" }, 365 { 0, 18, 2, "EtherStatsPkts256to511Octets" }, 366 { 0, 20, 2, "EtherStatsPkts512to1023Octets" }, 367 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" }, 368 { 0, 24, 2, "EtherOversizeStats" }, 369 { 0, 26, 2, "EtherStatsJabbers" }, 370 { 0, 28, 2, "IfInUcastPkts" }, 371 { 0, 30, 2, "EtherStatsMulticastPkts" }, 372 { 0, 32, 2, "EtherStatsBroadcastPkts" }, 373 { 0, 34, 2, "EtherStatsDropEvents" }, 374 { 0, 36, 2, "Dot3StatsFCSErrors" }, 375 { 0, 38, 2, "Dot3StatsSymbolErrors" }, 376 { 0, 40, 2, "Dot3InPauseFrames" }, 377 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" }, 378 { 0, 44, 4, "IfOutOctets" }, 379 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" }, 380 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" }, 381 { 0, 52, 2, "Dot3sDeferredTransmissions" }, 382 { 0, 54, 2, "Dot3StatsLateCollisions" }, 383 { 0, 56, 2, "EtherStatsCollisions" }, 384 { 0, 58, 2, "Dot3StatsExcessiveCollisions" }, 385 { 0, 60, 2, "Dot3OutPauseFrames" }, 386 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" }, 387 { 0, 64, 2, "Dot1dTpPortInDiscards" }, 388 { 0, 66, 2, "IfOutUcastPkts" }, 389 { 0, 68, 2, "IfOutMulticastPkts" }, 390 { 0, 70, 2, "IfOutBroadcastPkts" }, 391 }; 392 393 static int rtl8366rb_get_mib_counter(struct realtek_priv *priv, 394 int port, 395 struct rtl8366_mib_counter *mib, 396 u64 *mibvalue) 397 { 398 u32 addr, val; 399 int ret; 400 int i; 401 402 addr = RTL8366RB_MIB_COUNTER_BASE + 403 RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) + 404 mib->offset; 405 406 /* Writing access counter address first 407 * then ASIC will prepare 64bits counter wait for being retrived 408 */ 409 ret = regmap_write(priv->map, addr, 0); /* Write whatever */ 410 if (ret) 411 return ret; 412 413 /* Read MIB control register */ 414 ret = regmap_read(priv->map, RTL8366RB_MIB_CTRL_REG, &val); 415 if (ret) 416 return -EIO; 417 418 if (val & RTL8366RB_MIB_CTRL_BUSY_MASK) 419 return -EBUSY; 420 421 if (val & RTL8366RB_MIB_CTRL_RESET_MASK) 422 return -EIO; 423 424 /* Read each individual MIB 16 bits at the time */ 425 *mibvalue = 0; 426 for (i = mib->length; i > 0; i--) { 427 ret = regmap_read(priv->map, addr + (i - 1), &val); 428 if (ret) 429 return ret; 430 *mibvalue = (*mibvalue << 16) | (val & 0xFFFF); 431 } 432 return 0; 433 } 434 435 static u32 rtl8366rb_get_irqmask(struct irq_data *d) 436 { 437 int line = irqd_to_hwirq(d); 438 u32 val; 439 440 /* For line interrupts we combine link down in bits 441 * 6..11 with link up in bits 0..5 into one interrupt. 442 */ 443 if (line < 12) 444 val = BIT(line) | BIT(line + 6); 445 else 446 val = BIT(line); 447 return val; 448 } 449 450 static void rtl8366rb_mask_irq(struct irq_data *d) 451 { 452 struct realtek_priv *priv = irq_data_get_irq_chip_data(d); 453 int ret; 454 455 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG, 456 rtl8366rb_get_irqmask(d), 0); 457 if (ret) 458 dev_err(priv->dev, "could not mask IRQ\n"); 459 } 460 461 static void rtl8366rb_unmask_irq(struct irq_data *d) 462 { 463 struct realtek_priv *priv = irq_data_get_irq_chip_data(d); 464 int ret; 465 466 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG, 467 rtl8366rb_get_irqmask(d), 468 rtl8366rb_get_irqmask(d)); 469 if (ret) 470 dev_err(priv->dev, "could not unmask IRQ\n"); 471 } 472 473 static irqreturn_t rtl8366rb_irq(int irq, void *data) 474 { 475 struct realtek_priv *priv = data; 476 u32 stat; 477 int ret; 478 479 /* This clears the IRQ status register */ 480 ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG, 481 &stat); 482 if (ret) { 483 dev_err(priv->dev, "can't read interrupt status\n"); 484 return IRQ_NONE; 485 } 486 stat &= RTL8366RB_INTERRUPT_VALID; 487 if (!stat) 488 return IRQ_NONE; 489 while (stat) { 490 int line = __ffs(stat); 491 int child_irq; 492 493 stat &= ~BIT(line); 494 /* For line interrupts we combine link down in bits 495 * 6..11 with link up in bits 0..5 into one interrupt. 496 */ 497 if (line < 12 && line > 5) 498 line -= 5; 499 child_irq = irq_find_mapping(priv->irqdomain, line); 500 handle_nested_irq(child_irq); 501 } 502 return IRQ_HANDLED; 503 } 504 505 static struct irq_chip rtl8366rb_irq_chip = { 506 .name = "RTL8366RB", 507 .irq_mask = rtl8366rb_mask_irq, 508 .irq_unmask = rtl8366rb_unmask_irq, 509 }; 510 511 static int rtl8366rb_irq_map(struct irq_domain *domain, unsigned int irq, 512 irq_hw_number_t hwirq) 513 { 514 irq_set_chip_data(irq, domain->host_data); 515 irq_set_chip_and_handler(irq, &rtl8366rb_irq_chip, handle_simple_irq); 516 irq_set_nested_thread(irq, 1); 517 irq_set_noprobe(irq); 518 519 return 0; 520 } 521 522 static void rtl8366rb_irq_unmap(struct irq_domain *d, unsigned int irq) 523 { 524 irq_set_nested_thread(irq, 0); 525 irq_set_chip_and_handler(irq, NULL, NULL); 526 irq_set_chip_data(irq, NULL); 527 } 528 529 static const struct irq_domain_ops rtl8366rb_irqdomain_ops = { 530 .map = rtl8366rb_irq_map, 531 .unmap = rtl8366rb_irq_unmap, 532 .xlate = irq_domain_xlate_onecell, 533 }; 534 535 static int rtl8366rb_setup_cascaded_irq(struct realtek_priv *priv) 536 { 537 struct device_node *intc; 538 unsigned long irq_trig; 539 int irq; 540 int ret; 541 u32 val; 542 int i; 543 544 intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller"); 545 if (!intc) { 546 dev_err(priv->dev, "missing child interrupt-controller node\n"); 547 return -EINVAL; 548 } 549 /* RB8366RB IRQs cascade off this one */ 550 irq = of_irq_get(intc, 0); 551 if (irq <= 0) { 552 dev_err(priv->dev, "failed to get parent IRQ\n"); 553 ret = irq ? irq : -EINVAL; 554 goto out_put_node; 555 } 556 557 /* This clears the IRQ status register */ 558 ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG, 559 &val); 560 if (ret) { 561 dev_err(priv->dev, "can't read interrupt status\n"); 562 goto out_put_node; 563 } 564 565 /* Fetch IRQ edge information from the descriptor */ 566 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq)); 567 switch (irq_trig) { 568 case IRQF_TRIGGER_RISING: 569 case IRQF_TRIGGER_HIGH: 570 dev_info(priv->dev, "active high/rising IRQ\n"); 571 val = 0; 572 break; 573 case IRQF_TRIGGER_FALLING: 574 case IRQF_TRIGGER_LOW: 575 dev_info(priv->dev, "active low/falling IRQ\n"); 576 val = RTL8366RB_INTERRUPT_POLARITY; 577 break; 578 } 579 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_CONTROL_REG, 580 RTL8366RB_INTERRUPT_POLARITY, 581 val); 582 if (ret) { 583 dev_err(priv->dev, "could not configure IRQ polarity\n"); 584 goto out_put_node; 585 } 586 587 ret = devm_request_threaded_irq(priv->dev, irq, NULL, 588 rtl8366rb_irq, IRQF_ONESHOT, 589 "RTL8366RB", priv); 590 if (ret) { 591 dev_err(priv->dev, "unable to request irq: %d\n", ret); 592 goto out_put_node; 593 } 594 priv->irqdomain = irq_domain_add_linear(intc, 595 RTL8366RB_NUM_INTERRUPT, 596 &rtl8366rb_irqdomain_ops, 597 priv); 598 if (!priv->irqdomain) { 599 dev_err(priv->dev, "failed to create IRQ domain\n"); 600 ret = -EINVAL; 601 goto out_put_node; 602 } 603 for (i = 0; i < priv->num_ports; i++) 604 irq_set_parent(irq_create_mapping(priv->irqdomain, i), irq); 605 606 out_put_node: 607 of_node_put(intc); 608 return ret; 609 } 610 611 static int rtl8366rb_set_addr(struct realtek_priv *priv) 612 { 613 u8 addr[ETH_ALEN]; 614 u16 val; 615 int ret; 616 617 eth_random_addr(addr); 618 619 dev_info(priv->dev, "set MAC: %02X:%02X:%02X:%02X:%02X:%02X\n", 620 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 621 val = addr[0] << 8 | addr[1]; 622 ret = regmap_write(priv->map, RTL8366RB_SMAR0, val); 623 if (ret) 624 return ret; 625 val = addr[2] << 8 | addr[3]; 626 ret = regmap_write(priv->map, RTL8366RB_SMAR1, val); 627 if (ret) 628 return ret; 629 val = addr[4] << 8 | addr[5]; 630 ret = regmap_write(priv->map, RTL8366RB_SMAR2, val); 631 if (ret) 632 return ret; 633 634 return 0; 635 } 636 637 /* Found in a vendor driver */ 638 639 /* Struct for handling the jam tables' entries */ 640 struct rtl8366rb_jam_tbl_entry { 641 u16 reg; 642 u16 val; 643 }; 644 645 /* For the "version 0" early silicon, appear in most source releases */ 646 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_0[] = { 647 {0x000B, 0x0001}, {0x03A6, 0x0100}, {0x03A7, 0x0001}, {0x02D1, 0x3FFF}, 648 {0x02D2, 0x3FFF}, {0x02D3, 0x3FFF}, {0x02D4, 0x3FFF}, {0x02D5, 0x3FFF}, 649 {0x02D6, 0x3FFF}, {0x02D7, 0x3FFF}, {0x02D8, 0x3FFF}, {0x022B, 0x0688}, 650 {0x022C, 0x0FAC}, {0x03D0, 0x4688}, {0x03D1, 0x01F5}, {0x0000, 0x0830}, 651 {0x02F9, 0x0200}, {0x02F7, 0x7FFF}, {0x02F8, 0x03FF}, {0x0080, 0x03E8}, 652 {0x0081, 0x00CE}, {0x0082, 0x00DA}, {0x0083, 0x0230}, {0xBE0F, 0x2000}, 653 {0x0231, 0x422A}, {0x0232, 0x422A}, {0x0233, 0x422A}, {0x0234, 0x422A}, 654 {0x0235, 0x422A}, {0x0236, 0x422A}, {0x0237, 0x422A}, {0x0238, 0x422A}, 655 {0x0239, 0x422A}, {0x023A, 0x422A}, {0x023B, 0x422A}, {0x023C, 0x422A}, 656 {0x023D, 0x422A}, {0x023E, 0x422A}, {0x023F, 0x422A}, {0x0240, 0x422A}, 657 {0x0241, 0x422A}, {0x0242, 0x422A}, {0x0243, 0x422A}, {0x0244, 0x422A}, 658 {0x0245, 0x422A}, {0x0246, 0x422A}, {0x0247, 0x422A}, {0x0248, 0x422A}, 659 {0x0249, 0x0146}, {0x024A, 0x0146}, {0x024B, 0x0146}, {0xBE03, 0xC961}, 660 {0x024D, 0x0146}, {0x024E, 0x0146}, {0x024F, 0x0146}, {0x0250, 0x0146}, 661 {0xBE64, 0x0226}, {0x0252, 0x0146}, {0x0253, 0x0146}, {0x024C, 0x0146}, 662 {0x0251, 0x0146}, {0x0254, 0x0146}, {0xBE62, 0x3FD0}, {0x0084, 0x0320}, 663 {0x0255, 0x0146}, {0x0256, 0x0146}, {0x0257, 0x0146}, {0x0258, 0x0146}, 664 {0x0259, 0x0146}, {0x025A, 0x0146}, {0x025B, 0x0146}, {0x025C, 0x0146}, 665 {0x025D, 0x0146}, {0x025E, 0x0146}, {0x025F, 0x0146}, {0x0260, 0x0146}, 666 {0x0261, 0xA23F}, {0x0262, 0x0294}, {0x0263, 0xA23F}, {0x0264, 0x0294}, 667 {0x0265, 0xA23F}, {0x0266, 0x0294}, {0x0267, 0xA23F}, {0x0268, 0x0294}, 668 {0x0269, 0xA23F}, {0x026A, 0x0294}, {0x026B, 0xA23F}, {0x026C, 0x0294}, 669 {0x026D, 0xA23F}, {0x026E, 0x0294}, {0x026F, 0xA23F}, {0x0270, 0x0294}, 670 {0x02F5, 0x0048}, {0xBE09, 0x0E00}, {0xBE1E, 0x0FA0}, {0xBE14, 0x8448}, 671 {0xBE15, 0x1007}, {0xBE4A, 0xA284}, {0xC454, 0x3F0B}, {0xC474, 0x3F0B}, 672 {0xBE48, 0x3672}, {0xBE4B, 0x17A7}, {0xBE4C, 0x0B15}, {0xBE52, 0x0EDD}, 673 {0xBE49, 0x8C00}, {0xBE5B, 0x785C}, {0xBE5C, 0x785C}, {0xBE5D, 0x785C}, 674 {0xBE61, 0x368A}, {0xBE63, 0x9B84}, {0xC456, 0xCC13}, {0xC476, 0xCC13}, 675 {0xBE65, 0x307D}, {0xBE6D, 0x0005}, {0xBE6E, 0xE120}, {0xBE2E, 0x7BAF}, 676 }; 677 678 /* This v1 init sequence is from Belkin F5D8235 U-Boot release */ 679 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_1[] = { 680 {0x0000, 0x0830}, {0x0001, 0x8000}, {0x0400, 0x8130}, {0xBE78, 0x3C3C}, 681 {0x0431, 0x5432}, {0xBE37, 0x0CE4}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0}, 682 {0xC44C, 0x1585}, {0xC44C, 0x1185}, {0xC44C, 0x1585}, {0xC46C, 0x1585}, 683 {0xC46C, 0x1185}, {0xC46C, 0x1585}, {0xC451, 0x2135}, {0xC471, 0x2135}, 684 {0xBE10, 0x8140}, {0xBE15, 0x0007}, {0xBE6E, 0xE120}, {0xBE69, 0xD20F}, 685 {0xBE6B, 0x0320}, {0xBE24, 0xB000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF20}, 686 {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800}, {0xBE24, 0x0000}, 687 {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60}, {0xBE21, 0x0140}, 688 {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000}, {0xBE2E, 0x7B7A}, 689 {0xBE36, 0x0CE4}, {0x02F5, 0x0048}, {0xBE77, 0x2940}, {0x000A, 0x83E0}, 690 {0xBE79, 0x3C3C}, {0xBE00, 0x1340}, 691 }; 692 693 /* This v2 init sequence is from Belkin F5D8235 U-Boot release */ 694 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_2[] = { 695 {0x0450, 0x0000}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432}, 696 {0xC44F, 0x6250}, {0xC46F, 0x6250}, {0xC456, 0x0C14}, {0xC476, 0x0C14}, 697 {0xC44C, 0x1C85}, {0xC44C, 0x1885}, {0xC44C, 0x1C85}, {0xC46C, 0x1C85}, 698 {0xC46C, 0x1885}, {0xC46C, 0x1C85}, {0xC44C, 0x0885}, {0xC44C, 0x0881}, 699 {0xC44C, 0x0885}, {0xC46C, 0x0885}, {0xC46C, 0x0881}, {0xC46C, 0x0885}, 700 {0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001}, 701 {0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6E, 0x0320}, 702 {0xBE77, 0x2940}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120}, 703 {0x8000, 0x0001}, {0xBE15, 0x1007}, {0x8000, 0x0000}, {0xBE15, 0x1007}, 704 {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160}, {0xBE10, 0x8140}, 705 {0xBE00, 0x1340}, {0x0F51, 0x0010}, 706 }; 707 708 /* Appears in a DDWRT code dump */ 709 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_3[] = { 710 {0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432}, 711 {0x0F51, 0x0017}, {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0}, 712 {0xC456, 0x0C14}, {0xC476, 0x0C14}, {0xC454, 0x3F8B}, {0xC474, 0x3F8B}, 713 {0xC450, 0x2071}, {0xC470, 0x2071}, {0xC451, 0x226B}, {0xC471, 0x226B}, 714 {0xC452, 0xA293}, {0xC472, 0xA293}, {0xC44C, 0x1585}, {0xC44C, 0x1185}, 715 {0xC44C, 0x1585}, {0xC46C, 0x1585}, {0xC46C, 0x1185}, {0xC46C, 0x1585}, 716 {0xC44C, 0x0185}, {0xC44C, 0x0181}, {0xC44C, 0x0185}, {0xC46C, 0x0185}, 717 {0xC46C, 0x0181}, {0xC46C, 0x0185}, {0xBE24, 0xB000}, {0xBE23, 0xFF51}, 718 {0xBE22, 0xDF20}, {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800}, 719 {0xBE24, 0x0000}, {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60}, 720 {0xBE21, 0x0140}, {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000}, 721 {0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001}, 722 {0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6B, 0x0320}, 723 {0xBE77, 0x2800}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120}, 724 {0x8000, 0x0001}, {0xBE10, 0x8140}, {0x8000, 0x0000}, {0xBE10, 0x8140}, 725 {0xBE15, 0x1007}, {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160}, 726 {0xBE10, 0x8140}, {0xBE00, 0x1340}, {0x0450, 0x0000}, {0x0401, 0x0000}, 727 }; 728 729 /* Belkin F5D8235 v1, "belkin,f5d8235-v1" */ 730 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_f5d8235[] = { 731 {0x0242, 0x02BF}, {0x0245, 0x02BF}, {0x0248, 0x02BF}, {0x024B, 0x02BF}, 732 {0x024E, 0x02BF}, {0x0251, 0x02BF}, {0x0254, 0x0A3F}, {0x0256, 0x0A3F}, 733 {0x0258, 0x0A3F}, {0x025A, 0x0A3F}, {0x025C, 0x0A3F}, {0x025E, 0x0A3F}, 734 {0x0263, 0x007C}, {0x0100, 0x0004}, {0xBE5B, 0x3500}, {0x800E, 0x200F}, 735 {0xBE1D, 0x0F00}, {0x8001, 0x5011}, {0x800A, 0xA2F4}, {0x800B, 0x17A3}, 736 {0xBE4B, 0x17A3}, {0xBE41, 0x5011}, {0xBE17, 0x2100}, {0x8000, 0x8304}, 737 {0xBE40, 0x8304}, {0xBE4A, 0xA2F4}, {0x800C, 0xA8D5}, {0x8014, 0x5500}, 738 {0x8015, 0x0004}, {0xBE4C, 0xA8D5}, {0xBE59, 0x0008}, {0xBE09, 0x0E00}, 739 {0xBE36, 0x1036}, {0xBE37, 0x1036}, {0x800D, 0x00FF}, {0xBE4D, 0x00FF}, 740 }; 741 742 /* DGN3500, "netgear,dgn3500", "netgear,dgn3500b" */ 743 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_dgn3500[] = { 744 {0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0F51, 0x0017}, 745 {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0}, {0x0450, 0x0000}, 746 {0x0401, 0x0000}, {0x0431, 0x0960}, 747 }; 748 749 /* This jam table activates "green ethernet", which means low power mode 750 * and is claimed to detect the cable length and not use more power than 751 * necessary, and the ports should enter power saving mode 10 seconds after 752 * a cable is disconnected. Seems to always be the same. 753 */ 754 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_green_jam[] = { 755 {0xBE78, 0x323C}, {0xBE77, 0x5000}, {0xBE2E, 0x7BA7}, 756 {0xBE59, 0x3459}, {0xBE5A, 0x745A}, {0xBE5B, 0x785C}, 757 {0xBE5C, 0x785C}, {0xBE6E, 0xE120}, {0xBE79, 0x323C}, 758 }; 759 760 /* Function that jams the tables in the proper registers */ 761 static int rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry *jam_table, 762 int jam_size, struct realtek_priv *priv, 763 bool write_dbg) 764 { 765 u32 val; 766 int ret; 767 int i; 768 769 for (i = 0; i < jam_size; i++) { 770 if ((jam_table[i].reg & 0xBE00) == 0xBE00) { 771 ret = regmap_read(priv->map, 772 RTL8366RB_PHY_ACCESS_BUSY_REG, 773 &val); 774 if (ret) 775 return ret; 776 if (!(val & RTL8366RB_PHY_INT_BUSY)) { 777 ret = regmap_write(priv->map, 778 RTL8366RB_PHY_ACCESS_CTRL_REG, 779 RTL8366RB_PHY_CTRL_WRITE); 780 if (ret) 781 return ret; 782 } 783 } 784 if (write_dbg) 785 dev_dbg(priv->dev, "jam %04x into register %04x\n", 786 jam_table[i].val, 787 jam_table[i].reg); 788 ret = regmap_write(priv->map, 789 jam_table[i].reg, 790 jam_table[i].val); 791 if (ret) 792 return ret; 793 } 794 return 0; 795 } 796 797 static int rtl8366rb_setup(struct dsa_switch *ds) 798 { 799 struct realtek_priv *priv = ds->priv; 800 const struct rtl8366rb_jam_tbl_entry *jam_table; 801 struct rtl8366rb *rb; 802 u32 chip_ver = 0; 803 u32 chip_id = 0; 804 int jam_size; 805 u32 val; 806 int ret; 807 int i; 808 809 rb = priv->chip_data; 810 811 ret = regmap_read(priv->map, RTL8366RB_CHIP_ID_REG, &chip_id); 812 if (ret) { 813 dev_err(priv->dev, "unable to read chip id\n"); 814 return ret; 815 } 816 817 switch (chip_id) { 818 case RTL8366RB_CHIP_ID_8366: 819 break; 820 default: 821 dev_err(priv->dev, "unknown chip id (%04x)\n", chip_id); 822 return -ENODEV; 823 } 824 825 ret = regmap_read(priv->map, RTL8366RB_CHIP_VERSION_CTRL_REG, 826 &chip_ver); 827 if (ret) { 828 dev_err(priv->dev, "unable to read chip version\n"); 829 return ret; 830 } 831 832 dev_info(priv->dev, "RTL%04x ver %u chip found\n", 833 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK); 834 835 /* Do the init dance using the right jam table */ 836 switch (chip_ver) { 837 case 0: 838 jam_table = rtl8366rb_init_jam_ver_0; 839 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_0); 840 break; 841 case 1: 842 jam_table = rtl8366rb_init_jam_ver_1; 843 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_1); 844 break; 845 case 2: 846 jam_table = rtl8366rb_init_jam_ver_2; 847 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_2); 848 break; 849 default: 850 jam_table = rtl8366rb_init_jam_ver_3; 851 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_3); 852 break; 853 } 854 855 /* Special jam tables for special routers 856 * TODO: are these necessary? Maintainers, please test 857 * without them, using just the off-the-shelf tables. 858 */ 859 if (of_machine_is_compatible("belkin,f5d8235-v1")) { 860 jam_table = rtl8366rb_init_jam_f5d8235; 861 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_f5d8235); 862 } 863 if (of_machine_is_compatible("netgear,dgn3500") || 864 of_machine_is_compatible("netgear,dgn3500b")) { 865 jam_table = rtl8366rb_init_jam_dgn3500; 866 jam_size = ARRAY_SIZE(rtl8366rb_init_jam_dgn3500); 867 } 868 869 ret = rtl8366rb_jam_table(jam_table, jam_size, priv, true); 870 if (ret) 871 return ret; 872 873 /* Isolate all user ports so they can only send packets to itself and the CPU port */ 874 for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) { 875 ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(i), 876 RTL8366RB_PORT_ISO_PORTS(BIT(RTL8366RB_PORT_NUM_CPU)) | 877 RTL8366RB_PORT_ISO_EN); 878 if (ret) 879 return ret; 880 } 881 /* CPU port can send packets to all ports */ 882 ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(RTL8366RB_PORT_NUM_CPU), 883 RTL8366RB_PORT_ISO_PORTS(dsa_user_ports(ds)) | 884 RTL8366RB_PORT_ISO_EN); 885 if (ret) 886 return ret; 887 888 /* Set up the "green ethernet" feature */ 889 ret = rtl8366rb_jam_table(rtl8366rb_green_jam, 890 ARRAY_SIZE(rtl8366rb_green_jam), priv, false); 891 if (ret) 892 return ret; 893 894 ret = regmap_write(priv->map, 895 RTL8366RB_GREEN_FEATURE_REG, 896 (chip_ver == 1) ? 0x0007 : 0x0003); 897 if (ret) 898 return ret; 899 900 /* Vendor driver sets 0x240 in registers 0xc and 0xd (undocumented) */ 901 ret = regmap_write(priv->map, 0x0c, 0x240); 902 if (ret) 903 return ret; 904 ret = regmap_write(priv->map, 0x0d, 0x240); 905 if (ret) 906 return ret; 907 908 /* Set some random MAC address */ 909 ret = rtl8366rb_set_addr(priv); 910 if (ret) 911 return ret; 912 913 /* Enable CPU port with custom DSA tag 8899. 914 * 915 * If you set RTL8368RB_CPU_NO_TAG (bit 15) in this registers 916 * the custom tag is turned off. 917 */ 918 ret = regmap_update_bits(priv->map, RTL8368RB_CPU_CTRL_REG, 919 0xFFFF, 920 BIT(priv->cpu_port)); 921 if (ret) 922 return ret; 923 924 /* Make sure we default-enable the fixed CPU port */ 925 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, 926 BIT(priv->cpu_port), 927 0); 928 if (ret) 929 return ret; 930 931 /* Set maximum packet length to 1536 bytes */ 932 ret = regmap_update_bits(priv->map, RTL8366RB_SGCR, 933 RTL8366RB_SGCR_MAX_LENGTH_MASK, 934 RTL8366RB_SGCR_MAX_LENGTH_1536); 935 if (ret) 936 return ret; 937 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) 938 /* layer 2 size, see rtl8366rb_change_mtu() */ 939 rb->max_mtu[i] = 1532; 940 941 /* Disable learning for all ports */ 942 ret = regmap_write(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL, 943 RTL8366RB_PORT_ALL); 944 if (ret) 945 return ret; 946 947 /* Enable auto ageing for all ports */ 948 ret = regmap_write(priv->map, RTL8366RB_SECURITY_CTRL, 0); 949 if (ret) 950 return ret; 951 952 /* Port 4 setup: this enables Port 4, usually the WAN port, 953 * common PHY IO mode is apparently mode 0, and this is not what 954 * the port is initialized to. There is no explanation of the 955 * IO modes in the Realtek source code, if your WAN port is 956 * connected to something exotic such as fiber, then this might 957 * be worth experimenting with. 958 */ 959 ret = regmap_update_bits(priv->map, RTL8366RB_PMC0, 960 RTL8366RB_PMC0_P4_IOMODE_MASK, 961 0 << RTL8366RB_PMC0_P4_IOMODE_SHIFT); 962 if (ret) 963 return ret; 964 965 /* Accept all packets by default, we enable filtering on-demand */ 966 ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG, 967 0); 968 if (ret) 969 return ret; 970 ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG, 971 0); 972 if (ret) 973 return ret; 974 975 /* Don't drop packets whose DA has not been learned */ 976 ret = regmap_update_bits(priv->map, RTL8366RB_SSCR2, 977 RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0); 978 if (ret) 979 return ret; 980 981 /* Set blinking, TODO: make this configurable */ 982 ret = regmap_update_bits(priv->map, RTL8366RB_LED_BLINKRATE_REG, 983 RTL8366RB_LED_BLINKRATE_MASK, 984 RTL8366RB_LED_BLINKRATE_56MS); 985 if (ret) 986 return ret; 987 988 /* Set up LED activity: 989 * Each port has 4 LEDs, we configure all ports to the same 990 * behaviour (no individual config) but we can set up each 991 * LED separately. 992 */ 993 if (priv->leds_disabled) { 994 /* Turn everything off */ 995 regmap_update_bits(priv->map, 996 RTL8366RB_LED_0_1_CTRL_REG, 997 0x0FFF, 0); 998 regmap_update_bits(priv->map, 999 RTL8366RB_LED_2_3_CTRL_REG, 1000 0x0FFF, 0); 1001 regmap_update_bits(priv->map, 1002 RTL8366RB_INTERRUPT_CONTROL_REG, 1003 RTL8366RB_P4_RGMII_LED, 1004 0); 1005 val = RTL8366RB_LED_OFF; 1006 } else { 1007 /* TODO: make this configurable per LED */ 1008 val = RTL8366RB_LED_FORCE; 1009 } 1010 for (i = 0; i < 4; i++) { 1011 ret = regmap_update_bits(priv->map, 1012 RTL8366RB_LED_CTRL_REG, 1013 0xf << (i * 4), 1014 val << (i * 4)); 1015 if (ret) 1016 return ret; 1017 } 1018 1019 ret = rtl8366_reset_vlan(priv); 1020 if (ret) 1021 return ret; 1022 1023 ret = rtl8366rb_setup_cascaded_irq(priv); 1024 if (ret) 1025 dev_info(priv->dev, "no interrupt support\n"); 1026 1027 if (priv->setup_interface) { 1028 ret = priv->setup_interface(ds); 1029 if (ret) { 1030 dev_err(priv->dev, "could not set up MDIO bus\n"); 1031 return -ENODEV; 1032 } 1033 } 1034 1035 return 0; 1036 } 1037 1038 static enum dsa_tag_protocol rtl8366_get_tag_protocol(struct dsa_switch *ds, 1039 int port, 1040 enum dsa_tag_protocol mp) 1041 { 1042 /* This switch uses the 4 byte protocol A Realtek DSA tag */ 1043 return DSA_TAG_PROTO_RTL4_A; 1044 } 1045 1046 static void rtl8366rb_phylink_get_caps(struct dsa_switch *ds, int port, 1047 struct phylink_config *config) 1048 { 1049 unsigned long *interfaces = config->supported_interfaces; 1050 struct realtek_priv *priv = ds->priv; 1051 1052 if (port == priv->cpu_port) { 1053 __set_bit(PHY_INTERFACE_MODE_MII, interfaces); 1054 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces); 1055 /* REVMII only supports 100M FD */ 1056 __set_bit(PHY_INTERFACE_MODE_REVMII, interfaces); 1057 /* RGMII only supports 1G FD */ 1058 phy_interface_set_rgmii(interfaces); 1059 1060 config->mac_capabilities = MAC_1000 | MAC_100 | 1061 MAC_SYM_PAUSE; 1062 } else { 1063 /* RSGMII port, but we don't have that, and we don't 1064 * specify in DT, so phylib uses the default of GMII 1065 */ 1066 __set_bit(PHY_INTERFACE_MODE_GMII, interfaces); 1067 config->mac_capabilities = MAC_1000 | MAC_100 | MAC_10 | 1068 MAC_SYM_PAUSE | MAC_ASYM_PAUSE; 1069 } 1070 } 1071 1072 static void 1073 rtl8366rb_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode, 1074 phy_interface_t interface, struct phy_device *phydev, 1075 int speed, int duplex, bool tx_pause, bool rx_pause) 1076 { 1077 struct realtek_priv *priv = ds->priv; 1078 unsigned int val; 1079 int ret; 1080 1081 /* Allow forcing the mode on the fixed CPU port, no autonegotiation. 1082 * We assume autonegotiation works on the PHY-facing ports. 1083 */ 1084 if (port != priv->cpu_port) 1085 return; 1086 1087 dev_dbg(priv->dev, "MAC link up on CPU port (%d)\n", port); 1088 1089 ret = regmap_update_bits(priv->map, RTL8366RB_MAC_FORCE_CTRL_REG, 1090 BIT(port), BIT(port)); 1091 if (ret) { 1092 dev_err(priv->dev, "failed to force CPU port\n"); 1093 return; 1094 } 1095 1096 /* Conjure port config */ 1097 switch (speed) { 1098 case SPEED_10: 1099 val = RTL8366RB_PAACR_SPEED_10M; 1100 break; 1101 case SPEED_100: 1102 val = RTL8366RB_PAACR_SPEED_100M; 1103 break; 1104 case SPEED_1000: 1105 val = RTL8366RB_PAACR_SPEED_1000M; 1106 break; 1107 default: 1108 val = RTL8366RB_PAACR_SPEED_1000M; 1109 break; 1110 } 1111 1112 if (duplex == DUPLEX_FULL) 1113 val |= RTL8366RB_PAACR_FULL_DUPLEX; 1114 1115 if (tx_pause) 1116 val |= RTL8366RB_PAACR_TX_PAUSE; 1117 1118 if (rx_pause) 1119 val |= RTL8366RB_PAACR_RX_PAUSE; 1120 1121 val |= RTL8366RB_PAACR_LINK_UP; 1122 1123 ret = regmap_update_bits(priv->map, RTL8366RB_PAACR2, 1124 0xFF00U, 1125 val << 8); 1126 if (ret) { 1127 dev_err(priv->dev, "failed to set PAACR on CPU port\n"); 1128 return; 1129 } 1130 1131 dev_dbg(priv->dev, "set PAACR to %04x\n", val); 1132 1133 /* Enable the CPU port */ 1134 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port), 1135 0); 1136 if (ret) { 1137 dev_err(priv->dev, "failed to enable the CPU port\n"); 1138 return; 1139 } 1140 } 1141 1142 static void 1143 rtl8366rb_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode, 1144 phy_interface_t interface) 1145 { 1146 struct realtek_priv *priv = ds->priv; 1147 int ret; 1148 1149 if (port != priv->cpu_port) 1150 return; 1151 1152 dev_dbg(priv->dev, "MAC link down on CPU port (%d)\n", port); 1153 1154 /* Disable the CPU port */ 1155 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port), 1156 BIT(port)); 1157 if (ret) { 1158 dev_err(priv->dev, "failed to disable the CPU port\n"); 1159 return; 1160 } 1161 } 1162 1163 static void rb8366rb_set_port_led(struct realtek_priv *priv, 1164 int port, bool enable) 1165 { 1166 u16 val = enable ? 0x3f : 0; 1167 int ret; 1168 1169 if (priv->leds_disabled) 1170 return; 1171 1172 switch (port) { 1173 case 0: 1174 ret = regmap_update_bits(priv->map, 1175 RTL8366RB_LED_0_1_CTRL_REG, 1176 0x3F, val); 1177 break; 1178 case 1: 1179 ret = regmap_update_bits(priv->map, 1180 RTL8366RB_LED_0_1_CTRL_REG, 1181 0x3F << RTL8366RB_LED_1_OFFSET, 1182 val << RTL8366RB_LED_1_OFFSET); 1183 break; 1184 case 2: 1185 ret = regmap_update_bits(priv->map, 1186 RTL8366RB_LED_2_3_CTRL_REG, 1187 0x3F, val); 1188 break; 1189 case 3: 1190 ret = regmap_update_bits(priv->map, 1191 RTL8366RB_LED_2_3_CTRL_REG, 1192 0x3F << RTL8366RB_LED_3_OFFSET, 1193 val << RTL8366RB_LED_3_OFFSET); 1194 break; 1195 case 4: 1196 ret = regmap_update_bits(priv->map, 1197 RTL8366RB_INTERRUPT_CONTROL_REG, 1198 RTL8366RB_P4_RGMII_LED, 1199 enable ? RTL8366RB_P4_RGMII_LED : 0); 1200 break; 1201 default: 1202 dev_err(priv->dev, "no LED for port %d\n", port); 1203 return; 1204 } 1205 if (ret) 1206 dev_err(priv->dev, "error updating LED on port %d\n", port); 1207 } 1208 1209 static int 1210 rtl8366rb_port_enable(struct dsa_switch *ds, int port, 1211 struct phy_device *phy) 1212 { 1213 struct realtek_priv *priv = ds->priv; 1214 int ret; 1215 1216 dev_dbg(priv->dev, "enable port %d\n", port); 1217 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port), 1218 0); 1219 if (ret) 1220 return ret; 1221 1222 rb8366rb_set_port_led(priv, port, true); 1223 return 0; 1224 } 1225 1226 static void 1227 rtl8366rb_port_disable(struct dsa_switch *ds, int port) 1228 { 1229 struct realtek_priv *priv = ds->priv; 1230 int ret; 1231 1232 dev_dbg(priv->dev, "disable port %d\n", port); 1233 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port), 1234 BIT(port)); 1235 if (ret) 1236 return; 1237 1238 rb8366rb_set_port_led(priv, port, false); 1239 } 1240 1241 static int 1242 rtl8366rb_port_bridge_join(struct dsa_switch *ds, int port, 1243 struct dsa_bridge bridge, 1244 bool *tx_fwd_offload, 1245 struct netlink_ext_ack *extack) 1246 { 1247 struct realtek_priv *priv = ds->priv; 1248 unsigned int port_bitmap = 0; 1249 int ret, i; 1250 1251 /* Loop over all other ports than the current one */ 1252 for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) { 1253 /* Current port handled last */ 1254 if (i == port) 1255 continue; 1256 /* Not on this bridge */ 1257 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 1258 continue; 1259 /* Join this port to each other port on the bridge */ 1260 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i), 1261 RTL8366RB_PORT_ISO_PORTS(BIT(port)), 1262 RTL8366RB_PORT_ISO_PORTS(BIT(port))); 1263 if (ret) 1264 dev_err(priv->dev, "failed to join port %d\n", port); 1265 1266 port_bitmap |= BIT(i); 1267 } 1268 1269 /* Set the bits for the ports we can access */ 1270 return regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port), 1271 RTL8366RB_PORT_ISO_PORTS(port_bitmap), 1272 RTL8366RB_PORT_ISO_PORTS(port_bitmap)); 1273 } 1274 1275 static void 1276 rtl8366rb_port_bridge_leave(struct dsa_switch *ds, int port, 1277 struct dsa_bridge bridge) 1278 { 1279 struct realtek_priv *priv = ds->priv; 1280 unsigned int port_bitmap = 0; 1281 int ret, i; 1282 1283 /* Loop over all other ports than this one */ 1284 for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) { 1285 /* Current port handled last */ 1286 if (i == port) 1287 continue; 1288 /* Not on this bridge */ 1289 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 1290 continue; 1291 /* Remove this port from any other port on the bridge */ 1292 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i), 1293 RTL8366RB_PORT_ISO_PORTS(BIT(port)), 0); 1294 if (ret) 1295 dev_err(priv->dev, "failed to leave port %d\n", port); 1296 1297 port_bitmap |= BIT(i); 1298 } 1299 1300 /* Clear the bits for the ports we can not access, leave ourselves */ 1301 regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port), 1302 RTL8366RB_PORT_ISO_PORTS(port_bitmap), 0); 1303 } 1304 1305 /** 1306 * rtl8366rb_drop_untagged() - make the switch drop untagged and C-tagged frames 1307 * @priv: SMI state container 1308 * @port: the port to drop untagged and C-tagged frames on 1309 * @drop: whether to drop or pass untagged and C-tagged frames 1310 * 1311 * Return: zero for success, a negative number on error. 1312 */ 1313 static int rtl8366rb_drop_untagged(struct realtek_priv *priv, int port, bool drop) 1314 { 1315 return regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG, 1316 RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port), 1317 drop ? RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) : 0); 1318 } 1319 1320 static int rtl8366rb_vlan_filtering(struct dsa_switch *ds, int port, 1321 bool vlan_filtering, 1322 struct netlink_ext_ack *extack) 1323 { 1324 struct realtek_priv *priv = ds->priv; 1325 struct rtl8366rb *rb; 1326 int ret; 1327 1328 rb = priv->chip_data; 1329 1330 dev_dbg(priv->dev, "port %d: %s VLAN filtering\n", port, 1331 vlan_filtering ? "enable" : "disable"); 1332 1333 /* If the port is not in the member set, the frame will be dropped */ 1334 ret = regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG, 1335 BIT(port), vlan_filtering ? BIT(port) : 0); 1336 if (ret) 1337 return ret; 1338 1339 /* If VLAN filtering is enabled and PVID is also enabled, we must 1340 * not drop any untagged or C-tagged frames. If we turn off VLAN 1341 * filtering on a port, we need to accept any frames. 1342 */ 1343 if (vlan_filtering) 1344 ret = rtl8366rb_drop_untagged(priv, port, !rb->pvid_enabled[port]); 1345 else 1346 ret = rtl8366rb_drop_untagged(priv, port, false); 1347 1348 return ret; 1349 } 1350 1351 static int 1352 rtl8366rb_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1353 struct switchdev_brport_flags flags, 1354 struct netlink_ext_ack *extack) 1355 { 1356 /* We support enabling/disabling learning */ 1357 if (flags.mask & ~(BR_LEARNING)) 1358 return -EINVAL; 1359 1360 return 0; 1361 } 1362 1363 static int 1364 rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port, 1365 struct switchdev_brport_flags flags, 1366 struct netlink_ext_ack *extack) 1367 { 1368 struct realtek_priv *priv = ds->priv; 1369 int ret; 1370 1371 if (flags.mask & BR_LEARNING) { 1372 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL, 1373 BIT(port), 1374 (flags.val & BR_LEARNING) ? 0 : BIT(port)); 1375 if (ret) 1376 return ret; 1377 } 1378 1379 return 0; 1380 } 1381 1382 static void 1383 rtl8366rb_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1384 { 1385 struct realtek_priv *priv = ds->priv; 1386 u32 val; 1387 int i; 1388 1389 switch (state) { 1390 case BR_STATE_DISABLED: 1391 val = RTL8366RB_STP_STATE_DISABLED; 1392 break; 1393 case BR_STATE_BLOCKING: 1394 case BR_STATE_LISTENING: 1395 val = RTL8366RB_STP_STATE_BLOCKING; 1396 break; 1397 case BR_STATE_LEARNING: 1398 val = RTL8366RB_STP_STATE_LEARNING; 1399 break; 1400 case BR_STATE_FORWARDING: 1401 val = RTL8366RB_STP_STATE_FORWARDING; 1402 break; 1403 default: 1404 dev_err(priv->dev, "unknown bridge state requested\n"); 1405 return; 1406 } 1407 1408 /* Set the same status for the port on all the FIDs */ 1409 for (i = 0; i < RTL8366RB_NUM_FIDS; i++) { 1410 regmap_update_bits(priv->map, RTL8366RB_STP_STATE_BASE + i, 1411 RTL8366RB_STP_STATE_MASK(port), 1412 RTL8366RB_STP_STATE(port, val)); 1413 } 1414 } 1415 1416 static void 1417 rtl8366rb_port_fast_age(struct dsa_switch *ds, int port) 1418 { 1419 struct realtek_priv *priv = ds->priv; 1420 1421 /* This will age out any learned L2 entries */ 1422 regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL, 1423 BIT(port), BIT(port)); 1424 /* Restore the normal state of things */ 1425 regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL, 1426 BIT(port), 0); 1427 } 1428 1429 static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1430 { 1431 struct realtek_priv *priv = ds->priv; 1432 struct rtl8366rb *rb; 1433 unsigned int max_mtu; 1434 u32 len; 1435 int i; 1436 1437 /* Cache the per-port MTU setting */ 1438 rb = priv->chip_data; 1439 rb->max_mtu[port] = new_mtu; 1440 1441 /* Roof out the MTU for the entire switch to the greatest 1442 * common denominator: the biggest set for any one port will 1443 * be the biggest MTU for the switch. 1444 * 1445 * The first setting, 1522 bytes, is max IP packet 1500 bytes, 1446 * plus ethernet header, 1518 bytes, plus CPU tag, 4 bytes. 1447 * This function should consider the parameter an SDU, so the 1448 * MTU passed for this setting is 1518 bytes. The same logic 1449 * of subtracting the DSA tag of 4 bytes apply to the other 1450 * settings. 1451 */ 1452 max_mtu = 1518; 1453 for (i = 0; i < RTL8366RB_NUM_PORTS; i++) { 1454 if (rb->max_mtu[i] > max_mtu) 1455 max_mtu = rb->max_mtu[i]; 1456 } 1457 if (max_mtu <= 1518) 1458 len = RTL8366RB_SGCR_MAX_LENGTH_1522; 1459 else if (max_mtu > 1518 && max_mtu <= 1532) 1460 len = RTL8366RB_SGCR_MAX_LENGTH_1536; 1461 else if (max_mtu > 1532 && max_mtu <= 1548) 1462 len = RTL8366RB_SGCR_MAX_LENGTH_1552; 1463 else 1464 len = RTL8366RB_SGCR_MAX_LENGTH_16000; 1465 1466 return regmap_update_bits(priv->map, RTL8366RB_SGCR, 1467 RTL8366RB_SGCR_MAX_LENGTH_MASK, 1468 len); 1469 } 1470 1471 static int rtl8366rb_max_mtu(struct dsa_switch *ds, int port) 1472 { 1473 /* The max MTU is 16000 bytes, so we subtract the CPU tag 1474 * and the max presented to the system is 15996 bytes. 1475 */ 1476 return 15996; 1477 } 1478 1479 static int rtl8366rb_get_vlan_4k(struct realtek_priv *priv, u32 vid, 1480 struct rtl8366_vlan_4k *vlan4k) 1481 { 1482 u32 data[3]; 1483 int ret; 1484 int i; 1485 1486 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k)); 1487 1488 if (vid >= RTL8366RB_NUM_VIDS) 1489 return -EINVAL; 1490 1491 /* write VID */ 1492 ret = regmap_write(priv->map, RTL8366RB_VLAN_TABLE_WRITE_BASE, 1493 vid & RTL8366RB_VLAN_VID_MASK); 1494 if (ret) 1495 return ret; 1496 1497 /* write table access control word */ 1498 ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG, 1499 RTL8366RB_TABLE_VLAN_READ_CTRL); 1500 if (ret) 1501 return ret; 1502 1503 for (i = 0; i < 3; i++) { 1504 ret = regmap_read(priv->map, 1505 RTL8366RB_VLAN_TABLE_READ_BASE + i, 1506 &data[i]); 1507 if (ret) 1508 return ret; 1509 } 1510 1511 vlan4k->vid = vid; 1512 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) & 1513 RTL8366RB_VLAN_UNTAG_MASK; 1514 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK; 1515 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK; 1516 1517 return 0; 1518 } 1519 1520 static int rtl8366rb_set_vlan_4k(struct realtek_priv *priv, 1521 const struct rtl8366_vlan_4k *vlan4k) 1522 { 1523 u32 data[3]; 1524 int ret; 1525 int i; 1526 1527 if (vlan4k->vid >= RTL8366RB_NUM_VIDS || 1528 vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK || 1529 vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK || 1530 vlan4k->fid > RTL8366RB_FIDMAX) 1531 return -EINVAL; 1532 1533 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK; 1534 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) | 1535 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) << 1536 RTL8366RB_VLAN_UNTAG_SHIFT); 1537 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK; 1538 1539 for (i = 0; i < 3; i++) { 1540 ret = regmap_write(priv->map, 1541 RTL8366RB_VLAN_TABLE_WRITE_BASE + i, 1542 data[i]); 1543 if (ret) 1544 return ret; 1545 } 1546 1547 /* write table access control word */ 1548 ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG, 1549 RTL8366RB_TABLE_VLAN_WRITE_CTRL); 1550 1551 return ret; 1552 } 1553 1554 static int rtl8366rb_get_vlan_mc(struct realtek_priv *priv, u32 index, 1555 struct rtl8366_vlan_mc *vlanmc) 1556 { 1557 u32 data[3]; 1558 int ret; 1559 int i; 1560 1561 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc)); 1562 1563 if (index >= RTL8366RB_NUM_VLANS) 1564 return -EINVAL; 1565 1566 for (i = 0; i < 3; i++) { 1567 ret = regmap_read(priv->map, 1568 RTL8366RB_VLAN_MC_BASE(index) + i, 1569 &data[i]); 1570 if (ret) 1571 return ret; 1572 } 1573 1574 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK; 1575 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) & 1576 RTL8366RB_VLAN_PRIORITY_MASK; 1577 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) & 1578 RTL8366RB_VLAN_UNTAG_MASK; 1579 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK; 1580 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK; 1581 1582 return 0; 1583 } 1584 1585 static int rtl8366rb_set_vlan_mc(struct realtek_priv *priv, u32 index, 1586 const struct rtl8366_vlan_mc *vlanmc) 1587 { 1588 u32 data[3]; 1589 int ret; 1590 int i; 1591 1592 if (index >= RTL8366RB_NUM_VLANS || 1593 vlanmc->vid >= RTL8366RB_NUM_VIDS || 1594 vlanmc->priority > RTL8366RB_PRIORITYMAX || 1595 vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK || 1596 vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK || 1597 vlanmc->fid > RTL8366RB_FIDMAX) 1598 return -EINVAL; 1599 1600 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) | 1601 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) << 1602 RTL8366RB_VLAN_PRIORITY_SHIFT); 1603 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) | 1604 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) << 1605 RTL8366RB_VLAN_UNTAG_SHIFT); 1606 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK; 1607 1608 for (i = 0; i < 3; i++) { 1609 ret = regmap_write(priv->map, 1610 RTL8366RB_VLAN_MC_BASE(index) + i, 1611 data[i]); 1612 if (ret) 1613 return ret; 1614 } 1615 1616 return 0; 1617 } 1618 1619 static int rtl8366rb_get_mc_index(struct realtek_priv *priv, int port, int *val) 1620 { 1621 u32 data; 1622 int ret; 1623 1624 if (port >= priv->num_ports) 1625 return -EINVAL; 1626 1627 ret = regmap_read(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port), 1628 &data); 1629 if (ret) 1630 return ret; 1631 1632 *val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) & 1633 RTL8366RB_PORT_VLAN_CTRL_MASK; 1634 1635 return 0; 1636 } 1637 1638 static int rtl8366rb_set_mc_index(struct realtek_priv *priv, int port, int index) 1639 { 1640 struct rtl8366rb *rb; 1641 bool pvid_enabled; 1642 int ret; 1643 1644 rb = priv->chip_data; 1645 pvid_enabled = !!index; 1646 1647 if (port >= priv->num_ports || index >= RTL8366RB_NUM_VLANS) 1648 return -EINVAL; 1649 1650 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port), 1651 RTL8366RB_PORT_VLAN_CTRL_MASK << 1652 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port), 1653 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) << 1654 RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)); 1655 if (ret) 1656 return ret; 1657 1658 rb->pvid_enabled[port] = pvid_enabled; 1659 1660 /* If VLAN filtering is enabled and PVID is also enabled, we must 1661 * not drop any untagged or C-tagged frames. Make sure to update the 1662 * filtering setting. 1663 */ 1664 if (dsa_port_is_vlan_filtering(dsa_to_port(priv->ds, port))) 1665 ret = rtl8366rb_drop_untagged(priv, port, !pvid_enabled); 1666 1667 return ret; 1668 } 1669 1670 static bool rtl8366rb_is_vlan_valid(struct realtek_priv *priv, unsigned int vlan) 1671 { 1672 unsigned int max = RTL8366RB_NUM_VLANS - 1; 1673 1674 if (priv->vlan4k_enabled) 1675 max = RTL8366RB_NUM_VIDS - 1; 1676 1677 if (vlan > max) 1678 return false; 1679 1680 return true; 1681 } 1682 1683 static int rtl8366rb_enable_vlan(struct realtek_priv *priv, bool enable) 1684 { 1685 dev_dbg(priv->dev, "%s VLAN\n", enable ? "enable" : "disable"); 1686 return regmap_update_bits(priv->map, 1687 RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN, 1688 enable ? RTL8366RB_SGCR_EN_VLAN : 0); 1689 } 1690 1691 static int rtl8366rb_enable_vlan4k(struct realtek_priv *priv, bool enable) 1692 { 1693 dev_dbg(priv->dev, "%s VLAN 4k\n", enable ? "enable" : "disable"); 1694 return regmap_update_bits(priv->map, RTL8366RB_SGCR, 1695 RTL8366RB_SGCR_EN_VLAN_4KTB, 1696 enable ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0); 1697 } 1698 1699 static int rtl8366rb_phy_read(struct realtek_priv *priv, int phy, int regnum) 1700 { 1701 u32 val; 1702 u32 reg; 1703 int ret; 1704 1705 if (phy > RTL8366RB_PHY_NO_MAX) 1706 return -EINVAL; 1707 1708 mutex_lock(&priv->map_lock); 1709 1710 ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG, 1711 RTL8366RB_PHY_CTRL_READ); 1712 if (ret) 1713 goto out; 1714 1715 reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum; 1716 1717 ret = regmap_write(priv->map_nolock, reg, 0); 1718 if (ret) { 1719 dev_err(priv->dev, 1720 "failed to write PHY%d reg %04x @ %04x, ret %d\n", 1721 phy, regnum, reg, ret); 1722 goto out; 1723 } 1724 1725 ret = regmap_read(priv->map_nolock, RTL8366RB_PHY_ACCESS_DATA_REG, 1726 &val); 1727 if (ret) 1728 goto out; 1729 1730 ret = val; 1731 1732 dev_dbg(priv->dev, "read PHY%d register 0x%04x @ %08x, val <- %04x\n", 1733 phy, regnum, reg, val); 1734 1735 out: 1736 mutex_unlock(&priv->map_lock); 1737 1738 return ret; 1739 } 1740 1741 static int rtl8366rb_phy_write(struct realtek_priv *priv, int phy, int regnum, 1742 u16 val) 1743 { 1744 u32 reg; 1745 int ret; 1746 1747 if (phy > RTL8366RB_PHY_NO_MAX) 1748 return -EINVAL; 1749 1750 mutex_lock(&priv->map_lock); 1751 1752 ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG, 1753 RTL8366RB_PHY_CTRL_WRITE); 1754 if (ret) 1755 goto out; 1756 1757 reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum; 1758 1759 dev_dbg(priv->dev, "write PHY%d register 0x%04x @ %04x, val -> %04x\n", 1760 phy, regnum, reg, val); 1761 1762 ret = regmap_write(priv->map_nolock, reg, val); 1763 if (ret) 1764 goto out; 1765 1766 out: 1767 mutex_unlock(&priv->map_lock); 1768 1769 return ret; 1770 } 1771 1772 static int rtl8366rb_dsa_phy_read(struct dsa_switch *ds, int phy, int regnum) 1773 { 1774 return rtl8366rb_phy_read(ds->priv, phy, regnum); 1775 } 1776 1777 static int rtl8366rb_dsa_phy_write(struct dsa_switch *ds, int phy, int regnum, 1778 u16 val) 1779 { 1780 return rtl8366rb_phy_write(ds->priv, phy, regnum, val); 1781 } 1782 1783 static int rtl8366rb_reset_chip(struct realtek_priv *priv) 1784 { 1785 int timeout = 10; 1786 u32 val; 1787 int ret; 1788 1789 priv->write_reg_noack(priv, RTL8366RB_RESET_CTRL_REG, 1790 RTL8366RB_CHIP_CTRL_RESET_HW); 1791 do { 1792 usleep_range(20000, 25000); 1793 ret = regmap_read(priv->map, RTL8366RB_RESET_CTRL_REG, &val); 1794 if (ret) 1795 return ret; 1796 1797 if (!(val & RTL8366RB_CHIP_CTRL_RESET_HW)) 1798 break; 1799 } while (--timeout); 1800 1801 if (!timeout) { 1802 dev_err(priv->dev, "timeout waiting for the switch to reset\n"); 1803 return -EIO; 1804 } 1805 1806 return 0; 1807 } 1808 1809 static int rtl8366rb_detect(struct realtek_priv *priv) 1810 { 1811 struct device *dev = priv->dev; 1812 int ret; 1813 u32 val; 1814 1815 /* Detect device */ 1816 ret = regmap_read(priv->map, 0x5c, &val); 1817 if (ret) { 1818 dev_err(dev, "can't get chip ID (%d)\n", ret); 1819 return ret; 1820 } 1821 1822 switch (val) { 1823 case 0x6027: 1824 dev_info(dev, "found an RTL8366S switch\n"); 1825 dev_err(dev, "this switch is not yet supported, submit patches!\n"); 1826 return -ENODEV; 1827 case 0x5937: 1828 dev_info(dev, "found an RTL8366RB switch\n"); 1829 priv->cpu_port = RTL8366RB_PORT_NUM_CPU; 1830 priv->num_ports = RTL8366RB_NUM_PORTS; 1831 priv->num_vlan_mc = RTL8366RB_NUM_VLANS; 1832 priv->mib_counters = rtl8366rb_mib_counters; 1833 priv->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters); 1834 break; 1835 default: 1836 dev_info(dev, "found an Unknown Realtek switch (id=0x%04x)\n", 1837 val); 1838 break; 1839 } 1840 1841 ret = rtl8366rb_reset_chip(priv); 1842 if (ret) 1843 return ret; 1844 1845 return 0; 1846 } 1847 1848 static const struct dsa_switch_ops rtl8366rb_switch_ops_smi = { 1849 .get_tag_protocol = rtl8366_get_tag_protocol, 1850 .setup = rtl8366rb_setup, 1851 .phylink_get_caps = rtl8366rb_phylink_get_caps, 1852 .phylink_mac_link_up = rtl8366rb_mac_link_up, 1853 .phylink_mac_link_down = rtl8366rb_mac_link_down, 1854 .get_strings = rtl8366_get_strings, 1855 .get_ethtool_stats = rtl8366_get_ethtool_stats, 1856 .get_sset_count = rtl8366_get_sset_count, 1857 .port_bridge_join = rtl8366rb_port_bridge_join, 1858 .port_bridge_leave = rtl8366rb_port_bridge_leave, 1859 .port_vlan_filtering = rtl8366rb_vlan_filtering, 1860 .port_vlan_add = rtl8366_vlan_add, 1861 .port_vlan_del = rtl8366_vlan_del, 1862 .port_enable = rtl8366rb_port_enable, 1863 .port_disable = rtl8366rb_port_disable, 1864 .port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags, 1865 .port_bridge_flags = rtl8366rb_port_bridge_flags, 1866 .port_stp_state_set = rtl8366rb_port_stp_state_set, 1867 .port_fast_age = rtl8366rb_port_fast_age, 1868 .port_change_mtu = rtl8366rb_change_mtu, 1869 .port_max_mtu = rtl8366rb_max_mtu, 1870 }; 1871 1872 static const struct dsa_switch_ops rtl8366rb_switch_ops_mdio = { 1873 .get_tag_protocol = rtl8366_get_tag_protocol, 1874 .setup = rtl8366rb_setup, 1875 .phy_read = rtl8366rb_dsa_phy_read, 1876 .phy_write = rtl8366rb_dsa_phy_write, 1877 .phylink_get_caps = rtl8366rb_phylink_get_caps, 1878 .phylink_mac_link_up = rtl8366rb_mac_link_up, 1879 .phylink_mac_link_down = rtl8366rb_mac_link_down, 1880 .get_strings = rtl8366_get_strings, 1881 .get_ethtool_stats = rtl8366_get_ethtool_stats, 1882 .get_sset_count = rtl8366_get_sset_count, 1883 .port_bridge_join = rtl8366rb_port_bridge_join, 1884 .port_bridge_leave = rtl8366rb_port_bridge_leave, 1885 .port_vlan_filtering = rtl8366rb_vlan_filtering, 1886 .port_vlan_add = rtl8366_vlan_add, 1887 .port_vlan_del = rtl8366_vlan_del, 1888 .port_enable = rtl8366rb_port_enable, 1889 .port_disable = rtl8366rb_port_disable, 1890 .port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags, 1891 .port_bridge_flags = rtl8366rb_port_bridge_flags, 1892 .port_stp_state_set = rtl8366rb_port_stp_state_set, 1893 .port_fast_age = rtl8366rb_port_fast_age, 1894 .port_change_mtu = rtl8366rb_change_mtu, 1895 .port_max_mtu = rtl8366rb_max_mtu, 1896 }; 1897 1898 static const struct realtek_ops rtl8366rb_ops = { 1899 .detect = rtl8366rb_detect, 1900 .get_vlan_mc = rtl8366rb_get_vlan_mc, 1901 .set_vlan_mc = rtl8366rb_set_vlan_mc, 1902 .get_vlan_4k = rtl8366rb_get_vlan_4k, 1903 .set_vlan_4k = rtl8366rb_set_vlan_4k, 1904 .get_mc_index = rtl8366rb_get_mc_index, 1905 .set_mc_index = rtl8366rb_set_mc_index, 1906 .get_mib_counter = rtl8366rb_get_mib_counter, 1907 .is_vlan_valid = rtl8366rb_is_vlan_valid, 1908 .enable_vlan = rtl8366rb_enable_vlan, 1909 .enable_vlan4k = rtl8366rb_enable_vlan4k, 1910 .phy_read = rtl8366rb_phy_read, 1911 .phy_write = rtl8366rb_phy_write, 1912 }; 1913 1914 const struct realtek_variant rtl8366rb_variant = { 1915 .ds_ops_smi = &rtl8366rb_switch_ops_smi, 1916 .ds_ops_mdio = &rtl8366rb_switch_ops_mdio, 1917 .ops = &rtl8366rb_ops, 1918 .clk_delay = 10, 1919 .cmd_read = 0xa9, 1920 .cmd_write = 0xa8, 1921 .chip_data_sz = sizeof(struct rtl8366rb), 1922 }; 1923 EXPORT_SYMBOL_GPL(rtl8366rb_variant); 1924 1925 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>"); 1926 MODULE_DESCRIPTION("Driver for RTL8366RB ethernet switch"); 1927 MODULE_LICENSE("GPL"); 1928