1 // SPDX-License-Identifier: GPL-2.0 2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch. 3 * 4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk> 5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk> 6 * 7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4 8 * integrated PHYs for the user facing ports, and an extension interface which 9 * can be connected to the CPU - or another PHY - via either MII, RMII, or 10 * RGMII. The switch is configured via the Realtek Simple Management Interface 11 * (SMI), which uses the MDIO/MDC lines. 12 * 13 * Below is a simplified block diagram of the chip and its relevant interfaces. 14 * 15 * .-----------------------------------. 16 * | | 17 * UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC | 18 * UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC | 19 * UTP <---------------> Giga PHY <-> PCS <-> P2 GMAC | 20 * UTP <---------------> Giga PHY <-> PCS <-> P3 GMAC | 21 * | | 22 * CPU/PHY <-MII/RMII/RGMII---> Extension <---> Extension | 23 * | interface 1 GMAC 1 | 24 * | | 25 * SMI driver/ <-MDC/SCL---> Management ~~~~~~~~~~~~~~ | 26 * EEPROM <-MDIO/SDA--> interface ~REALTEK ~~~~~ | 27 * | ~RTL8365MB ~~~ | 28 * | ~GXXXC TAIWAN~ | 29 * GPIO <--------------> Reset ~~~~~~~~~~~~~~ | 30 * | | 31 * Interrupt <----------> Link UP/DOWN events | 32 * controller | | 33 * '-----------------------------------' 34 * 35 * The driver uses DSA to integrate the 4 user and 1 extension ports into the 36 * kernel. Netdevices are created for the user ports, as are PHY devices for 37 * their integrated PHYs. The device tree firmware should also specify the link 38 * partner of the extension port - either via a fixed-link or other phy-handle. 39 * See the device tree bindings for more detailed information. Note that the 40 * driver has only been tested with a fixed-link, but in principle it should not 41 * matter. 42 * 43 * NOTE: Currently, only the RGMII interface is implemented in this driver. 44 * 45 * The interrupt line is asserted on link UP/DOWN events. The driver creates a 46 * custom irqchip to handle this interrupt and demultiplex the events by reading 47 * the status registers via SMI. Interrupts are then propagated to the relevant 48 * PHY device. 49 * 50 * The EEPROM contains initial register values which the chip will read over I2C 51 * upon hardware reset. It is also possible to omit the EEPROM. In both cases, 52 * the driver will manually reprogram some registers using jam tables to reach 53 * an initial state defined by the vendor driver. 54 * 55 * This Linux driver is written based on an OS-agnostic vendor driver from 56 * Realtek. The reference GPL-licensed sources can be found in the OpenWrt 57 * source tree under the name rtl8367c. The vendor driver claims to support a 58 * number of similar switch controllers from Realtek, but the only hardware we 59 * have is the RTL8365MB-VC. Moreover, there does not seem to be any chip under 60 * the name RTL8367C. Although one wishes that the 'C' stood for some kind of 61 * common hardware revision, there exist examples of chips with the suffix -VC 62 * which are explicitly not supported by the rtl8367c driver and which instead 63 * require the rtl8367d vendor driver. With all this uncertainty, the driver has 64 * been modestly named rtl8365mb. Future implementors may wish to rename things 65 * accordingly. 66 * 67 * In the same family of chips, some carry up to 8 user ports and up to 2 68 * extension ports. Where possible this driver tries to make things generic, but 69 * more work must be done to support these configurations. According to 70 * documentation from Realtek, the family should include the following chips: 71 * 72 * - RTL8363NB 73 * - RTL8363NB-VB 74 * - RTL8363SC 75 * - RTL8363SC-VB 76 * - RTL8364NB 77 * - RTL8364NB-VB 78 * - RTL8365MB-VC 79 * - RTL8366SC 80 * - RTL8367RB-VB 81 * - RTL8367SB 82 * - RTL8367S 83 * - RTL8370MB 84 * - RTL8310SR 85 * 86 * Some of the register logic for these additional chips has been skipped over 87 * while implementing this driver. It is therefore not possible to assume that 88 * things will work out-of-the-box for other chips, and a careful review of the 89 * vendor driver may be needed to expand support. The RTL8365MB-VC seems to be 90 * one of the simpler chips. 91 */ 92 93 #include <linux/bitfield.h> 94 #include <linux/bitops.h> 95 #include <linux/interrupt.h> 96 #include <linux/irqdomain.h> 97 #include <linux/mutex.h> 98 #include <linux/of_irq.h> 99 #include <linux/regmap.h> 100 #include <linux/if_bridge.h> 101 102 #include "realtek.h" 103 104 /* Chip-specific data and limits */ 105 #define RTL8365MB_CHIP_ID_8365MB_VC 0x6367 106 #define RTL8365MB_CHIP_VER_8365MB_VC 0x0040 107 108 #define RTL8365MB_CHIP_ID_8367S 0x6367 109 #define RTL8365MB_CHIP_VER_8367S 0x00A0 110 111 #define RTL8365MB_CHIP_ID_8367RB 0x6367 112 #define RTL8365MB_CHIP_VER_8367RB 0x0020 113 114 /* Family-specific data and limits */ 115 #define RTL8365MB_PHYADDRMAX 7 116 #define RTL8365MB_NUM_PHYREGS 32 117 #define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1) 118 /* RTL8370MB and RTL8310SR, possibly suportable by this driver, have 10 ports */ 119 #define RTL8365MB_MAX_NUM_PORTS 10 120 #define RTL8365MB_LEARN_LIMIT_MAX 2112 121 122 /* valid for all 6-port or less variants */ 123 static const int rtl8365mb_extint_port_map[] = { -1, -1, -1, -1, -1, -1, 1, 2, -1, -1}; 124 125 /* Chip identification registers */ 126 #define RTL8365MB_CHIP_ID_REG 0x1300 127 128 #define RTL8365MB_CHIP_VER_REG 0x1301 129 130 #define RTL8365MB_MAGIC_REG 0x13C2 131 #define RTL8365MB_MAGIC_VALUE 0x0249 132 133 /* Chip reset register */ 134 #define RTL8365MB_CHIP_RESET_REG 0x1322 135 #define RTL8365MB_CHIP_RESET_SW_MASK 0x0002 136 #define RTL8365MB_CHIP_RESET_HW_MASK 0x0001 137 138 /* Interrupt polarity register */ 139 #define RTL8365MB_INTR_POLARITY_REG 0x1100 140 #define RTL8365MB_INTR_POLARITY_MASK 0x0001 141 #define RTL8365MB_INTR_POLARITY_HIGH 0 142 #define RTL8365MB_INTR_POLARITY_LOW 1 143 144 /* Interrupt control/status register - enable/check specific interrupt types */ 145 #define RTL8365MB_INTR_CTRL_REG 0x1101 146 #define RTL8365MB_INTR_STATUS_REG 0x1102 147 #define RTL8365MB_INTR_SLIENT_START_2_MASK 0x1000 148 #define RTL8365MB_INTR_SLIENT_START_MASK 0x0800 149 #define RTL8365MB_INTR_ACL_ACTION_MASK 0x0200 150 #define RTL8365MB_INTR_CABLE_DIAG_FIN_MASK 0x0100 151 #define RTL8365MB_INTR_INTERRUPT_8051_MASK 0x0080 152 #define RTL8365MB_INTR_LOOP_DETECTION_MASK 0x0040 153 #define RTL8365MB_INTR_GREEN_TIMER_MASK 0x0020 154 #define RTL8365MB_INTR_SPECIAL_CONGEST_MASK 0x0010 155 #define RTL8365MB_INTR_SPEED_CHANGE_MASK 0x0008 156 #define RTL8365MB_INTR_LEARN_OVER_MASK 0x0004 157 #define RTL8365MB_INTR_METER_EXCEEDED_MASK 0x0002 158 #define RTL8365MB_INTR_LINK_CHANGE_MASK 0x0001 159 #define RTL8365MB_INTR_ALL_MASK \ 160 (RTL8365MB_INTR_SLIENT_START_2_MASK | \ 161 RTL8365MB_INTR_SLIENT_START_MASK | \ 162 RTL8365MB_INTR_ACL_ACTION_MASK | \ 163 RTL8365MB_INTR_CABLE_DIAG_FIN_MASK | \ 164 RTL8365MB_INTR_INTERRUPT_8051_MASK | \ 165 RTL8365MB_INTR_LOOP_DETECTION_MASK | \ 166 RTL8365MB_INTR_GREEN_TIMER_MASK | \ 167 RTL8365MB_INTR_SPECIAL_CONGEST_MASK | \ 168 RTL8365MB_INTR_SPEED_CHANGE_MASK | \ 169 RTL8365MB_INTR_LEARN_OVER_MASK | \ 170 RTL8365MB_INTR_METER_EXCEEDED_MASK | \ 171 RTL8365MB_INTR_LINK_CHANGE_MASK) 172 173 /* Per-port interrupt type status registers */ 174 #define RTL8365MB_PORT_LINKDOWN_IND_REG 0x1106 175 #define RTL8365MB_PORT_LINKDOWN_IND_MASK 0x07FF 176 177 #define RTL8365MB_PORT_LINKUP_IND_REG 0x1107 178 #define RTL8365MB_PORT_LINKUP_IND_MASK 0x07FF 179 180 /* PHY indirect access registers */ 181 #define RTL8365MB_INDIRECT_ACCESS_CTRL_REG 0x1F00 182 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK 0x0002 183 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ 0 184 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE 1 185 #define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK 0x0001 186 #define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE 1 187 #define RTL8365MB_INDIRECT_ACCESS_STATUS_REG 0x1F01 188 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG 0x1F02 189 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK GENMASK(4, 0) 190 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK GENMASK(7, 5) 191 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK GENMASK(11, 8) 192 #define RTL8365MB_PHY_BASE 0x2000 193 #define RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG 0x1F03 194 #define RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG 0x1F04 195 196 /* PHY OCP address prefix register */ 197 #define RTL8365MB_GPHY_OCP_MSB_0_REG 0x1D15 198 #define RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK 0x0FC0 199 #define RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK 0xFC00 200 201 /* The PHY OCP addresses of PHY registers 0~31 start here */ 202 #define RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE 0xA400 203 204 /* EXT interface port mode values - used in DIGITAL_INTERFACE_SELECT */ 205 #define RTL8365MB_EXT_PORT_MODE_DISABLE 0 206 #define RTL8365MB_EXT_PORT_MODE_RGMII 1 207 #define RTL8365MB_EXT_PORT_MODE_MII_MAC 2 208 #define RTL8365MB_EXT_PORT_MODE_MII_PHY 3 209 #define RTL8365MB_EXT_PORT_MODE_TMII_MAC 4 210 #define RTL8365MB_EXT_PORT_MODE_TMII_PHY 5 211 #define RTL8365MB_EXT_PORT_MODE_GMII 6 212 #define RTL8365MB_EXT_PORT_MODE_RMII_MAC 7 213 #define RTL8365MB_EXT_PORT_MODE_RMII_PHY 8 214 #define RTL8365MB_EXT_PORT_MODE_SGMII 9 215 #define RTL8365MB_EXT_PORT_MODE_HSGMII 10 216 #define RTL8365MB_EXT_PORT_MODE_1000X_100FX 11 217 #define RTL8365MB_EXT_PORT_MODE_1000X 12 218 #define RTL8365MB_EXT_PORT_MODE_100FX 13 219 220 /* Realtek docs and driver uses logic number as EXT_PORT0=16, EXT_PORT1=17, 221 * EXT_PORT2=18, to interact with switch ports. That logic number is internally 222 * converted to either a physical port number (0..9) or an external interface id (0..2), 223 * depending on which function was called. The external interface id is calculated as 224 * (ext_id=logic_port-15), while the logical to physical map depends on the chip id/version. 225 * 226 * EXT_PORT0 mentioned in datasheets and rtl8367c driver is used in this driver 227 * as extid==1, EXT_PORT2, mentioned in Realtek rtl8367c driver for 10-port switches, 228 * would have an ext_id of 3 (out of range for most extint macros) and ext_id 0 does 229 * not seem to be used as well for this family. 230 */ 231 232 /* EXT interface mode configuration registers 0~1 */ 233 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 0x1305 /* EXT1 */ 234 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 0x13C3 /* EXT2 */ 235 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(_extint) \ 236 ((_extint) == 1 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 : \ 237 (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 : \ 238 0x0) 239 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(_extint) \ 240 (0xF << (((_extint) % 2))) 241 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(_extint) \ 242 (((_extint) % 2) * 4) 243 244 /* EXT interface RGMII TX/RX delay configuration registers 0~2 */ 245 #define RTL8365MB_EXT_RGMXF_REG0 0x1306 /* EXT0 */ 246 #define RTL8365MB_EXT_RGMXF_REG1 0x1307 /* EXT1 */ 247 #define RTL8365MB_EXT_RGMXF_REG2 0x13C5 /* EXT2 */ 248 #define RTL8365MB_EXT_RGMXF_REG(_extint) \ 249 ((_extint) == 0 ? RTL8365MB_EXT_RGMXF_REG0 : \ 250 (_extint) == 1 ? RTL8365MB_EXT_RGMXF_REG1 : \ 251 (_extint) == 2 ? RTL8365MB_EXT_RGMXF_REG2 : \ 252 0x0) 253 #define RTL8365MB_EXT_RGMXF_RXDELAY_MASK 0x0007 254 #define RTL8365MB_EXT_RGMXF_TXDELAY_MASK 0x0008 255 256 /* External interface port speed values - used in DIGITAL_INTERFACE_FORCE */ 257 #define RTL8365MB_PORT_SPEED_10M 0 258 #define RTL8365MB_PORT_SPEED_100M 1 259 #define RTL8365MB_PORT_SPEED_1000M 2 260 261 /* EXT interface force configuration registers 0~2 */ 262 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 0x1310 /* EXT0 */ 263 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 0x1311 /* EXT1 */ 264 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 0x13C4 /* EXT2 */ 265 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(_extint) \ 266 ((_extint) == 0 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 : \ 267 (_extint) == 1 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 : \ 268 (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 : \ 269 0x0) 270 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK 0x1000 271 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_NWAY_MASK 0x0080 272 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK 0x0040 273 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK 0x0020 274 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK 0x0010 275 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK 0x0004 276 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK 0x0003 277 278 /* CPU port mask register - controls which ports are treated as CPU ports */ 279 #define RTL8365MB_CPU_PORT_MASK_REG 0x1219 280 #define RTL8365MB_CPU_PORT_MASK_MASK 0x07FF 281 282 /* CPU control register */ 283 #define RTL8365MB_CPU_CTRL_REG 0x121A 284 #define RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK 0x0400 285 #define RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK 0x0200 286 #define RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK 0x0080 287 #define RTL8365MB_CPU_CTRL_TAG_POSITION_MASK 0x0040 288 #define RTL8365MB_CPU_CTRL_TRAP_PORT_MASK 0x0038 289 #define RTL8365MB_CPU_CTRL_INSERTMODE_MASK 0x0006 290 #define RTL8365MB_CPU_CTRL_EN_MASK 0x0001 291 292 /* Maximum packet length register */ 293 #define RTL8365MB_CFG0_MAX_LEN_REG 0x088C 294 #define RTL8365MB_CFG0_MAX_LEN_MASK 0x3FFF 295 296 /* Port learning limit registers */ 297 #define RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE 0x0A20 298 #define RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(_physport) \ 299 (RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE + (_physport)) 300 301 /* Port isolation (forwarding mask) registers */ 302 #define RTL8365MB_PORT_ISOLATION_REG_BASE 0x08A2 303 #define RTL8365MB_PORT_ISOLATION_REG(_physport) \ 304 (RTL8365MB_PORT_ISOLATION_REG_BASE + (_physport)) 305 #define RTL8365MB_PORT_ISOLATION_MASK 0x07FF 306 307 /* MSTP port state registers - indexed by tree instance */ 308 #define RTL8365MB_MSTI_CTRL_BASE 0x0A00 309 #define RTL8365MB_MSTI_CTRL_REG(_msti, _physport) \ 310 (RTL8365MB_MSTI_CTRL_BASE + ((_msti) << 1) + ((_physport) >> 3)) 311 #define RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(_physport) ((_physport) << 1) 312 #define RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(_physport) \ 313 (0x3 << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET((_physport))) 314 315 /* MIB counter value registers */ 316 #define RTL8365MB_MIB_COUNTER_BASE 0x1000 317 #define RTL8365MB_MIB_COUNTER_REG(_x) (RTL8365MB_MIB_COUNTER_BASE + (_x)) 318 319 /* MIB counter address register */ 320 #define RTL8365MB_MIB_ADDRESS_REG 0x1004 321 #define RTL8365MB_MIB_ADDRESS_PORT_OFFSET 0x007C 322 #define RTL8365MB_MIB_ADDRESS(_p, _x) \ 323 (((RTL8365MB_MIB_ADDRESS_PORT_OFFSET) * (_p) + (_x)) >> 2) 324 325 #define RTL8365MB_MIB_CTRL0_REG 0x1005 326 #define RTL8365MB_MIB_CTRL0_RESET_MASK 0x0002 327 #define RTL8365MB_MIB_CTRL0_BUSY_MASK 0x0001 328 329 /* The DSA callback .get_stats64 runs in atomic context, so we are not allowed 330 * to block. On the other hand, accessing MIB counters absolutely requires us to 331 * block. The solution is thus to schedule work which polls the MIB counters 332 * asynchronously and updates some private data, which the callback can then 333 * fetch atomically. Three seconds should be a good enough polling interval. 334 */ 335 #define RTL8365MB_STATS_INTERVAL_JIFFIES (3 * HZ) 336 337 enum rtl8365mb_mib_counter_index { 338 RTL8365MB_MIB_ifInOctets, 339 RTL8365MB_MIB_dot3StatsFCSErrors, 340 RTL8365MB_MIB_dot3StatsSymbolErrors, 341 RTL8365MB_MIB_dot3InPauseFrames, 342 RTL8365MB_MIB_dot3ControlInUnknownOpcodes, 343 RTL8365MB_MIB_etherStatsFragments, 344 RTL8365MB_MIB_etherStatsJabbers, 345 RTL8365MB_MIB_ifInUcastPkts, 346 RTL8365MB_MIB_etherStatsDropEvents, 347 RTL8365MB_MIB_ifInMulticastPkts, 348 RTL8365MB_MIB_ifInBroadcastPkts, 349 RTL8365MB_MIB_inMldChecksumError, 350 RTL8365MB_MIB_inIgmpChecksumError, 351 RTL8365MB_MIB_inMldSpecificQuery, 352 RTL8365MB_MIB_inMldGeneralQuery, 353 RTL8365MB_MIB_inIgmpSpecificQuery, 354 RTL8365MB_MIB_inIgmpGeneralQuery, 355 RTL8365MB_MIB_inMldLeaves, 356 RTL8365MB_MIB_inIgmpLeaves, 357 RTL8365MB_MIB_etherStatsOctets, 358 RTL8365MB_MIB_etherStatsUnderSizePkts, 359 RTL8365MB_MIB_etherOversizeStats, 360 RTL8365MB_MIB_etherStatsPkts64Octets, 361 RTL8365MB_MIB_etherStatsPkts65to127Octets, 362 RTL8365MB_MIB_etherStatsPkts128to255Octets, 363 RTL8365MB_MIB_etherStatsPkts256to511Octets, 364 RTL8365MB_MIB_etherStatsPkts512to1023Octets, 365 RTL8365MB_MIB_etherStatsPkts1024to1518Octets, 366 RTL8365MB_MIB_ifOutOctets, 367 RTL8365MB_MIB_dot3StatsSingleCollisionFrames, 368 RTL8365MB_MIB_dot3StatsMultipleCollisionFrames, 369 RTL8365MB_MIB_dot3StatsDeferredTransmissions, 370 RTL8365MB_MIB_dot3StatsLateCollisions, 371 RTL8365MB_MIB_etherStatsCollisions, 372 RTL8365MB_MIB_dot3StatsExcessiveCollisions, 373 RTL8365MB_MIB_dot3OutPauseFrames, 374 RTL8365MB_MIB_ifOutDiscards, 375 RTL8365MB_MIB_dot1dTpPortInDiscards, 376 RTL8365MB_MIB_ifOutUcastPkts, 377 RTL8365MB_MIB_ifOutMulticastPkts, 378 RTL8365MB_MIB_ifOutBroadcastPkts, 379 RTL8365MB_MIB_outOampduPkts, 380 RTL8365MB_MIB_inOampduPkts, 381 RTL8365MB_MIB_inIgmpJoinsSuccess, 382 RTL8365MB_MIB_inIgmpJoinsFail, 383 RTL8365MB_MIB_inMldJoinsSuccess, 384 RTL8365MB_MIB_inMldJoinsFail, 385 RTL8365MB_MIB_inReportSuppressionDrop, 386 RTL8365MB_MIB_inLeaveSuppressionDrop, 387 RTL8365MB_MIB_outIgmpReports, 388 RTL8365MB_MIB_outIgmpLeaves, 389 RTL8365MB_MIB_outIgmpGeneralQuery, 390 RTL8365MB_MIB_outIgmpSpecificQuery, 391 RTL8365MB_MIB_outMldReports, 392 RTL8365MB_MIB_outMldLeaves, 393 RTL8365MB_MIB_outMldGeneralQuery, 394 RTL8365MB_MIB_outMldSpecificQuery, 395 RTL8365MB_MIB_inKnownMulticastPkts, 396 RTL8365MB_MIB_END, 397 }; 398 399 struct rtl8365mb_mib_counter { 400 u32 offset; 401 u32 length; 402 const char *name; 403 }; 404 405 #define RTL8365MB_MAKE_MIB_COUNTER(_offset, _length, _name) \ 406 [RTL8365MB_MIB_ ## _name] = { _offset, _length, #_name } 407 408 static struct rtl8365mb_mib_counter rtl8365mb_mib_counters[] = { 409 RTL8365MB_MAKE_MIB_COUNTER(0, 4, ifInOctets), 410 RTL8365MB_MAKE_MIB_COUNTER(4, 2, dot3StatsFCSErrors), 411 RTL8365MB_MAKE_MIB_COUNTER(6, 2, dot3StatsSymbolErrors), 412 RTL8365MB_MAKE_MIB_COUNTER(8, 2, dot3InPauseFrames), 413 RTL8365MB_MAKE_MIB_COUNTER(10, 2, dot3ControlInUnknownOpcodes), 414 RTL8365MB_MAKE_MIB_COUNTER(12, 2, etherStatsFragments), 415 RTL8365MB_MAKE_MIB_COUNTER(14, 2, etherStatsJabbers), 416 RTL8365MB_MAKE_MIB_COUNTER(16, 2, ifInUcastPkts), 417 RTL8365MB_MAKE_MIB_COUNTER(18, 2, etherStatsDropEvents), 418 RTL8365MB_MAKE_MIB_COUNTER(20, 2, ifInMulticastPkts), 419 RTL8365MB_MAKE_MIB_COUNTER(22, 2, ifInBroadcastPkts), 420 RTL8365MB_MAKE_MIB_COUNTER(24, 2, inMldChecksumError), 421 RTL8365MB_MAKE_MIB_COUNTER(26, 2, inIgmpChecksumError), 422 RTL8365MB_MAKE_MIB_COUNTER(28, 2, inMldSpecificQuery), 423 RTL8365MB_MAKE_MIB_COUNTER(30, 2, inMldGeneralQuery), 424 RTL8365MB_MAKE_MIB_COUNTER(32, 2, inIgmpSpecificQuery), 425 RTL8365MB_MAKE_MIB_COUNTER(34, 2, inIgmpGeneralQuery), 426 RTL8365MB_MAKE_MIB_COUNTER(36, 2, inMldLeaves), 427 RTL8365MB_MAKE_MIB_COUNTER(38, 2, inIgmpLeaves), 428 RTL8365MB_MAKE_MIB_COUNTER(40, 4, etherStatsOctets), 429 RTL8365MB_MAKE_MIB_COUNTER(44, 2, etherStatsUnderSizePkts), 430 RTL8365MB_MAKE_MIB_COUNTER(46, 2, etherOversizeStats), 431 RTL8365MB_MAKE_MIB_COUNTER(48, 2, etherStatsPkts64Octets), 432 RTL8365MB_MAKE_MIB_COUNTER(50, 2, etherStatsPkts65to127Octets), 433 RTL8365MB_MAKE_MIB_COUNTER(52, 2, etherStatsPkts128to255Octets), 434 RTL8365MB_MAKE_MIB_COUNTER(54, 2, etherStatsPkts256to511Octets), 435 RTL8365MB_MAKE_MIB_COUNTER(56, 2, etherStatsPkts512to1023Octets), 436 RTL8365MB_MAKE_MIB_COUNTER(58, 2, etherStatsPkts1024to1518Octets), 437 RTL8365MB_MAKE_MIB_COUNTER(60, 4, ifOutOctets), 438 RTL8365MB_MAKE_MIB_COUNTER(64, 2, dot3StatsSingleCollisionFrames), 439 RTL8365MB_MAKE_MIB_COUNTER(66, 2, dot3StatsMultipleCollisionFrames), 440 RTL8365MB_MAKE_MIB_COUNTER(68, 2, dot3StatsDeferredTransmissions), 441 RTL8365MB_MAKE_MIB_COUNTER(70, 2, dot3StatsLateCollisions), 442 RTL8365MB_MAKE_MIB_COUNTER(72, 2, etherStatsCollisions), 443 RTL8365MB_MAKE_MIB_COUNTER(74, 2, dot3StatsExcessiveCollisions), 444 RTL8365MB_MAKE_MIB_COUNTER(76, 2, dot3OutPauseFrames), 445 RTL8365MB_MAKE_MIB_COUNTER(78, 2, ifOutDiscards), 446 RTL8365MB_MAKE_MIB_COUNTER(80, 2, dot1dTpPortInDiscards), 447 RTL8365MB_MAKE_MIB_COUNTER(82, 2, ifOutUcastPkts), 448 RTL8365MB_MAKE_MIB_COUNTER(84, 2, ifOutMulticastPkts), 449 RTL8365MB_MAKE_MIB_COUNTER(86, 2, ifOutBroadcastPkts), 450 RTL8365MB_MAKE_MIB_COUNTER(88, 2, outOampduPkts), 451 RTL8365MB_MAKE_MIB_COUNTER(90, 2, inOampduPkts), 452 RTL8365MB_MAKE_MIB_COUNTER(92, 4, inIgmpJoinsSuccess), 453 RTL8365MB_MAKE_MIB_COUNTER(96, 2, inIgmpJoinsFail), 454 RTL8365MB_MAKE_MIB_COUNTER(98, 2, inMldJoinsSuccess), 455 RTL8365MB_MAKE_MIB_COUNTER(100, 2, inMldJoinsFail), 456 RTL8365MB_MAKE_MIB_COUNTER(102, 2, inReportSuppressionDrop), 457 RTL8365MB_MAKE_MIB_COUNTER(104, 2, inLeaveSuppressionDrop), 458 RTL8365MB_MAKE_MIB_COUNTER(106, 2, outIgmpReports), 459 RTL8365MB_MAKE_MIB_COUNTER(108, 2, outIgmpLeaves), 460 RTL8365MB_MAKE_MIB_COUNTER(110, 2, outIgmpGeneralQuery), 461 RTL8365MB_MAKE_MIB_COUNTER(112, 2, outIgmpSpecificQuery), 462 RTL8365MB_MAKE_MIB_COUNTER(114, 2, outMldReports), 463 RTL8365MB_MAKE_MIB_COUNTER(116, 2, outMldLeaves), 464 RTL8365MB_MAKE_MIB_COUNTER(118, 2, outMldGeneralQuery), 465 RTL8365MB_MAKE_MIB_COUNTER(120, 2, outMldSpecificQuery), 466 RTL8365MB_MAKE_MIB_COUNTER(122, 2, inKnownMulticastPkts), 467 }; 468 469 static_assert(ARRAY_SIZE(rtl8365mb_mib_counters) == RTL8365MB_MIB_END); 470 471 struct rtl8365mb_jam_tbl_entry { 472 u16 reg; 473 u16 val; 474 }; 475 476 /* Lifted from the vendor driver sources */ 477 static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_8365mb_vc[] = { 478 { 0x13EB, 0x15BB }, { 0x1303, 0x06D6 }, { 0x1304, 0x0700 }, 479 { 0x13E2, 0x003F }, { 0x13F9, 0x0090 }, { 0x121E, 0x03CA }, 480 { 0x1233, 0x0352 }, { 0x1237, 0x00A0 }, { 0x123A, 0x0030 }, 481 { 0x1239, 0x0084 }, { 0x0301, 0x1000 }, { 0x1349, 0x001F }, 482 { 0x18E0, 0x4004 }, { 0x122B, 0x241C }, { 0x1305, 0xC000 }, 483 { 0x13F0, 0x0000 }, 484 }; 485 486 static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_common[] = { 487 { 0x1200, 0x7FCB }, { 0x0884, 0x0003 }, { 0x06EB, 0x0001 }, 488 { 0x03Fa, 0x0007 }, { 0x08C8, 0x00C0 }, { 0x0A30, 0x020E }, 489 { 0x0800, 0x0000 }, { 0x0802, 0x0000 }, { 0x09DA, 0x0013 }, 490 { 0x1D32, 0x0002 }, 491 }; 492 493 enum rtl8365mb_stp_state { 494 RTL8365MB_STP_STATE_DISABLED = 0, 495 RTL8365MB_STP_STATE_BLOCKING = 1, 496 RTL8365MB_STP_STATE_LEARNING = 2, 497 RTL8365MB_STP_STATE_FORWARDING = 3, 498 }; 499 500 enum rtl8365mb_cpu_insert { 501 RTL8365MB_CPU_INSERT_TO_ALL = 0, 502 RTL8365MB_CPU_INSERT_TO_TRAPPING = 1, 503 RTL8365MB_CPU_INSERT_TO_NONE = 2, 504 }; 505 506 enum rtl8365mb_cpu_position { 507 RTL8365MB_CPU_POS_AFTER_SA = 0, 508 RTL8365MB_CPU_POS_BEFORE_CRC = 1, 509 }; 510 511 enum rtl8365mb_cpu_format { 512 RTL8365MB_CPU_FORMAT_8BYTES = 0, 513 RTL8365MB_CPU_FORMAT_4BYTES = 1, 514 }; 515 516 enum rtl8365mb_cpu_rxlen { 517 RTL8365MB_CPU_RXLEN_72BYTES = 0, 518 RTL8365MB_CPU_RXLEN_64BYTES = 1, 519 }; 520 521 /** 522 * struct rtl8365mb_cpu - CPU port configuration 523 * @enable: enable/disable hardware insertion of CPU tag in switch->CPU frames 524 * @mask: port mask of ports that parse should parse CPU tags 525 * @trap_port: forward trapped frames to this port 526 * @insert: CPU tag insertion mode in switch->CPU frames 527 * @position: position of CPU tag in frame 528 * @rx_length: minimum CPU RX length 529 * @format: CPU tag format 530 * 531 * Represents the CPU tagging and CPU port configuration of the switch. These 532 * settings are configurable at runtime. 533 */ 534 struct rtl8365mb_cpu { 535 bool enable; 536 u32 mask; 537 u32 trap_port; 538 enum rtl8365mb_cpu_insert insert; 539 enum rtl8365mb_cpu_position position; 540 enum rtl8365mb_cpu_rxlen rx_length; 541 enum rtl8365mb_cpu_format format; 542 }; 543 544 /** 545 * struct rtl8365mb_port - private per-port data 546 * @priv: pointer to parent realtek_priv data 547 * @index: DSA port index, same as dsa_port::index 548 * @stats: link statistics populated by rtl8365mb_stats_poll, ready for atomic 549 * access via rtl8365mb_get_stats64 550 * @stats_lock: protect the stats structure during read/update 551 * @mib_work: delayed work for polling MIB counters 552 */ 553 struct rtl8365mb_port { 554 struct realtek_priv *priv; 555 unsigned int index; 556 struct rtnl_link_stats64 stats; 557 spinlock_t stats_lock; 558 struct delayed_work mib_work; 559 }; 560 561 /** 562 * struct rtl8365mb - private chip-specific driver data 563 * @priv: pointer to parent realtek_priv data 564 * @irq: registered IRQ or zero 565 * @chip_id: chip identifier 566 * @chip_ver: chip silicon revision 567 * @port_mask: mask of all ports 568 * @learn_limit_max: maximum number of L2 addresses the chip can learn 569 * @mib_lock: prevent concurrent reads of MIB counters 570 * @ports: per-port data 571 * @jam_table: chip-specific initialization jam table 572 * @jam_size: size of the chip's jam table 573 * 574 * Private data for this driver. 575 */ 576 struct rtl8365mb { 577 struct realtek_priv *priv; 578 int irq; 579 u32 chip_id; 580 u32 chip_ver; 581 u32 port_mask; 582 u32 learn_limit_max; 583 struct mutex mib_lock; 584 struct rtl8365mb_port ports[RTL8365MB_MAX_NUM_PORTS]; 585 const struct rtl8365mb_jam_tbl_entry *jam_table; 586 size_t jam_size; 587 }; 588 589 static int rtl8365mb_phy_poll_busy(struct realtek_priv *priv) 590 { 591 u32 val; 592 593 return regmap_read_poll_timeout(priv->map_nolock, 594 RTL8365MB_INDIRECT_ACCESS_STATUS_REG, 595 val, !val, 10, 100); 596 } 597 598 static int rtl8365mb_phy_ocp_prepare(struct realtek_priv *priv, int phy, 599 u32 ocp_addr) 600 { 601 u32 val; 602 int ret; 603 604 /* Set OCP prefix */ 605 val = FIELD_GET(RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK, ocp_addr); 606 ret = regmap_update_bits( 607 priv->map_nolock, RTL8365MB_GPHY_OCP_MSB_0_REG, 608 RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, 609 FIELD_PREP(RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, val)); 610 if (ret) 611 return ret; 612 613 /* Set PHY register address */ 614 val = RTL8365MB_PHY_BASE; 615 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK, phy); 616 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK, 617 ocp_addr >> 1); 618 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK, 619 ocp_addr >> 6); 620 ret = regmap_write(priv->map_nolock, 621 RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG, val); 622 if (ret) 623 return ret; 624 625 return 0; 626 } 627 628 static int rtl8365mb_phy_ocp_read(struct realtek_priv *priv, int phy, 629 u32 ocp_addr, u16 *data) 630 { 631 u32 val; 632 int ret; 633 634 mutex_lock(&priv->map_lock); 635 636 ret = rtl8365mb_phy_poll_busy(priv); 637 if (ret) 638 goto out; 639 640 ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr); 641 if (ret) 642 goto out; 643 644 /* Execute read operation */ 645 val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK, 646 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) | 647 FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK, 648 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ); 649 ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, 650 val); 651 if (ret) 652 goto out; 653 654 ret = rtl8365mb_phy_poll_busy(priv); 655 if (ret) 656 goto out; 657 658 /* Get PHY register data */ 659 ret = regmap_read(priv->map_nolock, 660 RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, &val); 661 if (ret) 662 goto out; 663 664 *data = val & 0xFFFF; 665 666 out: 667 mutex_unlock(&priv->map_lock); 668 669 return ret; 670 } 671 672 static int rtl8365mb_phy_ocp_write(struct realtek_priv *priv, int phy, 673 u32 ocp_addr, u16 data) 674 { 675 u32 val; 676 int ret; 677 678 mutex_lock(&priv->map_lock); 679 680 ret = rtl8365mb_phy_poll_busy(priv); 681 if (ret) 682 goto out; 683 684 ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr); 685 if (ret) 686 goto out; 687 688 /* Set PHY register data */ 689 ret = regmap_write(priv->map_nolock, 690 RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG, data); 691 if (ret) 692 goto out; 693 694 /* Execute write operation */ 695 val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK, 696 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) | 697 FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK, 698 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE); 699 ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, 700 val); 701 if (ret) 702 goto out; 703 704 ret = rtl8365mb_phy_poll_busy(priv); 705 if (ret) 706 goto out; 707 708 out: 709 mutex_unlock(&priv->map_lock); 710 711 return 0; 712 } 713 714 static int rtl8365mb_phy_read(struct realtek_priv *priv, int phy, int regnum) 715 { 716 u32 ocp_addr; 717 u16 val; 718 int ret; 719 720 if (phy > RTL8365MB_PHYADDRMAX) 721 return -EINVAL; 722 723 if (regnum > RTL8365MB_PHYREGMAX) 724 return -EINVAL; 725 726 ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; 727 728 ret = rtl8365mb_phy_ocp_read(priv, phy, ocp_addr, &val); 729 if (ret) { 730 dev_err(priv->dev, 731 "failed to read PHY%d reg %02x @ %04x, ret %d\n", phy, 732 regnum, ocp_addr, ret); 733 return ret; 734 } 735 736 dev_dbg(priv->dev, "read PHY%d register 0x%02x @ %04x, val <- %04x\n", 737 phy, regnum, ocp_addr, val); 738 739 return val; 740 } 741 742 static int rtl8365mb_phy_write(struct realtek_priv *priv, int phy, int regnum, 743 u16 val) 744 { 745 u32 ocp_addr; 746 int ret; 747 748 if (phy > RTL8365MB_PHYADDRMAX) 749 return -EINVAL; 750 751 if (regnum > RTL8365MB_PHYREGMAX) 752 return -EINVAL; 753 754 ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; 755 756 ret = rtl8365mb_phy_ocp_write(priv, phy, ocp_addr, val); 757 if (ret) { 758 dev_err(priv->dev, 759 "failed to write PHY%d reg %02x @ %04x, ret %d\n", phy, 760 regnum, ocp_addr, ret); 761 return ret; 762 } 763 764 dev_dbg(priv->dev, "write PHY%d register 0x%02x @ %04x, val -> %04x\n", 765 phy, regnum, ocp_addr, val); 766 767 return 0; 768 } 769 770 static int rtl8365mb_dsa_phy_read(struct dsa_switch *ds, int phy, int regnum) 771 { 772 return rtl8365mb_phy_read(ds->priv, phy, regnum); 773 } 774 775 static int rtl8365mb_dsa_phy_write(struct dsa_switch *ds, int phy, int regnum, 776 u16 val) 777 { 778 return rtl8365mb_phy_write(ds->priv, phy, regnum, val); 779 } 780 781 static enum dsa_tag_protocol 782 rtl8365mb_get_tag_protocol(struct dsa_switch *ds, int port, 783 enum dsa_tag_protocol mp) 784 { 785 return DSA_TAG_PROTO_RTL8_4; 786 } 787 788 static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, 789 phy_interface_t interface) 790 { 791 struct device_node *dn; 792 struct dsa_port *dp; 793 int tx_delay = 0; 794 int rx_delay = 0; 795 int ext_int; 796 u32 val; 797 int ret; 798 799 ext_int = rtl8365mb_extint_port_map[port]; 800 801 if (ext_int <= 0) { 802 dev_err(priv->dev, "Port %d is not an external interface port\n", port); 803 return -EINVAL; 804 } 805 806 dp = dsa_to_port(priv->ds, port); 807 dn = dp->dn; 808 809 /* Set the RGMII TX/RX delay 810 * 811 * The Realtek vendor driver indicates the following possible 812 * configuration settings: 813 * 814 * TX delay: 815 * 0 = no delay, 1 = 2 ns delay 816 * RX delay: 817 * 0 = no delay, 7 = maximum delay 818 * Each step is approximately 0.3 ns, so the maximum delay is about 819 * 2.1 ns. 820 * 821 * The vendor driver also states that this must be configured *before* 822 * forcing the external interface into a particular mode, which is done 823 * in the rtl8365mb_phylink_mac_link_{up,down} functions. 824 * 825 * Only configure an RGMII TX (resp. RX) delay if the 826 * tx-internal-delay-ps (resp. rx-internal-delay-ps) OF property is 827 * specified. We ignore the detail of the RGMII interface mode 828 * (RGMII_{RXID, TXID, etc.}), as this is considered to be a PHY-only 829 * property. 830 */ 831 if (!of_property_read_u32(dn, "tx-internal-delay-ps", &val)) { 832 val = val / 1000; /* convert to ns */ 833 834 if (val == 0 || val == 2) 835 tx_delay = val / 2; 836 else 837 dev_warn(priv->dev, 838 "EXT interface TX delay must be 0 or 2 ns\n"); 839 } 840 841 if (!of_property_read_u32(dn, "rx-internal-delay-ps", &val)) { 842 val = DIV_ROUND_CLOSEST(val, 300); /* convert to 0.3 ns step */ 843 844 if (val <= 7) 845 rx_delay = val; 846 else 847 dev_warn(priv->dev, 848 "EXT interface RX delay must be 0 to 2.1 ns\n"); 849 } 850 851 ret = regmap_update_bits( 852 priv->map, RTL8365MB_EXT_RGMXF_REG(ext_int), 853 RTL8365MB_EXT_RGMXF_TXDELAY_MASK | 854 RTL8365MB_EXT_RGMXF_RXDELAY_MASK, 855 FIELD_PREP(RTL8365MB_EXT_RGMXF_TXDELAY_MASK, tx_delay) | 856 FIELD_PREP(RTL8365MB_EXT_RGMXF_RXDELAY_MASK, rx_delay)); 857 if (ret) 858 return ret; 859 860 ret = regmap_update_bits( 861 priv->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(ext_int), 862 RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(ext_int), 863 RTL8365MB_EXT_PORT_MODE_RGMII 864 << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET( 865 ext_int)); 866 if (ret) 867 return ret; 868 869 return 0; 870 } 871 872 static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, 873 bool link, int speed, int duplex, 874 bool tx_pause, bool rx_pause) 875 { 876 u32 r_tx_pause; 877 u32 r_rx_pause; 878 u32 r_duplex; 879 u32 r_speed; 880 u32 r_link; 881 int ext_int; 882 int val; 883 int ret; 884 885 ext_int = rtl8365mb_extint_port_map[port]; 886 887 if (ext_int <= 0) { 888 dev_err(priv->dev, "Port %d is not an external interface port\n", port); 889 return -EINVAL; 890 } 891 892 if (link) { 893 /* Force the link up with the desired configuration */ 894 r_link = 1; 895 r_rx_pause = rx_pause ? 1 : 0; 896 r_tx_pause = tx_pause ? 1 : 0; 897 898 if (speed == SPEED_1000) { 899 r_speed = RTL8365MB_PORT_SPEED_1000M; 900 } else if (speed == SPEED_100) { 901 r_speed = RTL8365MB_PORT_SPEED_100M; 902 } else if (speed == SPEED_10) { 903 r_speed = RTL8365MB_PORT_SPEED_10M; 904 } else { 905 dev_err(priv->dev, "unsupported port speed %s\n", 906 phy_speed_to_str(speed)); 907 return -EINVAL; 908 } 909 910 if (duplex == DUPLEX_FULL) { 911 r_duplex = 1; 912 } else if (duplex == DUPLEX_HALF) { 913 r_duplex = 0; 914 } else { 915 dev_err(priv->dev, "unsupported duplex %s\n", 916 phy_duplex_to_str(duplex)); 917 return -EINVAL; 918 } 919 } else { 920 /* Force the link down and reset any programmed configuration */ 921 r_link = 0; 922 r_tx_pause = 0; 923 r_rx_pause = 0; 924 r_speed = 0; 925 r_duplex = 0; 926 } 927 928 val = FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK, 1) | 929 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK, 930 r_tx_pause) | 931 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK, 932 r_rx_pause) | 933 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK, r_link) | 934 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK, 935 r_duplex) | 936 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK, r_speed); 937 ret = regmap_write(priv->map, 938 RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(ext_int), 939 val); 940 if (ret) 941 return ret; 942 943 return 0; 944 } 945 946 static bool rtl8365mb_phy_mode_supported(struct dsa_switch *ds, int port, 947 phy_interface_t interface) 948 { 949 int ext_int; 950 951 ext_int = rtl8365mb_extint_port_map[port]; 952 953 if (ext_int < 0 && 954 (interface == PHY_INTERFACE_MODE_NA || 955 interface == PHY_INTERFACE_MODE_INTERNAL || 956 interface == PHY_INTERFACE_MODE_GMII)) 957 /* Internal PHY */ 958 return true; 959 else if ((ext_int >= 1) && 960 phy_interface_mode_is_rgmii(interface)) 961 /* Extension MAC */ 962 return true; 963 964 return false; 965 } 966 967 static void rtl8365mb_phylink_get_caps(struct dsa_switch *ds, int port, 968 struct phylink_config *config) 969 { 970 if (dsa_is_user_port(ds, port)) 971 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 972 config->supported_interfaces); 973 else if (dsa_is_cpu_port(ds, port)) 974 phy_interface_set_rgmii(config->supported_interfaces); 975 976 config->mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | 977 MAC_10 | MAC_100 | MAC_1000FD; 978 } 979 980 static void rtl8365mb_phylink_mac_config(struct dsa_switch *ds, int port, 981 unsigned int mode, 982 const struct phylink_link_state *state) 983 { 984 struct realtek_priv *priv = ds->priv; 985 int ret; 986 987 if (!rtl8365mb_phy_mode_supported(ds, port, state->interface)) { 988 dev_err(priv->dev, "phy mode %s is unsupported on port %d\n", 989 phy_modes(state->interface), port); 990 return; 991 } 992 993 if (mode != MLO_AN_PHY && mode != MLO_AN_FIXED) { 994 dev_err(priv->dev, 995 "port %d supports only conventional PHY or fixed-link\n", 996 port); 997 return; 998 } 999 1000 if (phy_interface_mode_is_rgmii(state->interface)) { 1001 ret = rtl8365mb_ext_config_rgmii(priv, port, state->interface); 1002 if (ret) 1003 dev_err(priv->dev, 1004 "failed to configure RGMII mode on port %d: %d\n", 1005 port, ret); 1006 return; 1007 } 1008 1009 /* TODO: Implement MII and RMII modes, which the RTL8365MB-VC also 1010 * supports 1011 */ 1012 } 1013 1014 static void rtl8365mb_phylink_mac_link_down(struct dsa_switch *ds, int port, 1015 unsigned int mode, 1016 phy_interface_t interface) 1017 { 1018 struct realtek_priv *priv = ds->priv; 1019 struct rtl8365mb_port *p; 1020 struct rtl8365mb *mb; 1021 int ret; 1022 1023 mb = priv->chip_data; 1024 p = &mb->ports[port]; 1025 cancel_delayed_work_sync(&p->mib_work); 1026 1027 if (phy_interface_mode_is_rgmii(interface)) { 1028 ret = rtl8365mb_ext_config_forcemode(priv, port, false, 0, 0, 1029 false, false); 1030 if (ret) 1031 dev_err(priv->dev, 1032 "failed to reset forced mode on port %d: %d\n", 1033 port, ret); 1034 1035 return; 1036 } 1037 } 1038 1039 static void rtl8365mb_phylink_mac_link_up(struct dsa_switch *ds, int port, 1040 unsigned int mode, 1041 phy_interface_t interface, 1042 struct phy_device *phydev, int speed, 1043 int duplex, bool tx_pause, 1044 bool rx_pause) 1045 { 1046 struct realtek_priv *priv = ds->priv; 1047 struct rtl8365mb_port *p; 1048 struct rtl8365mb *mb; 1049 int ret; 1050 1051 mb = priv->chip_data; 1052 p = &mb->ports[port]; 1053 schedule_delayed_work(&p->mib_work, 0); 1054 1055 if (phy_interface_mode_is_rgmii(interface)) { 1056 ret = rtl8365mb_ext_config_forcemode(priv, port, true, speed, 1057 duplex, tx_pause, 1058 rx_pause); 1059 if (ret) 1060 dev_err(priv->dev, 1061 "failed to force mode on port %d: %d\n", port, 1062 ret); 1063 1064 return; 1065 } 1066 } 1067 1068 static void rtl8365mb_port_stp_state_set(struct dsa_switch *ds, int port, 1069 u8 state) 1070 { 1071 struct realtek_priv *priv = ds->priv; 1072 enum rtl8365mb_stp_state val; 1073 int msti = 0; 1074 1075 switch (state) { 1076 case BR_STATE_DISABLED: 1077 val = RTL8365MB_STP_STATE_DISABLED; 1078 break; 1079 case BR_STATE_BLOCKING: 1080 case BR_STATE_LISTENING: 1081 val = RTL8365MB_STP_STATE_BLOCKING; 1082 break; 1083 case BR_STATE_LEARNING: 1084 val = RTL8365MB_STP_STATE_LEARNING; 1085 break; 1086 case BR_STATE_FORWARDING: 1087 val = RTL8365MB_STP_STATE_FORWARDING; 1088 break; 1089 default: 1090 dev_err(priv->dev, "invalid STP state: %u\n", state); 1091 return; 1092 } 1093 1094 regmap_update_bits(priv->map, RTL8365MB_MSTI_CTRL_REG(msti, port), 1095 RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(port), 1096 val << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(port)); 1097 } 1098 1099 static int rtl8365mb_port_set_learning(struct realtek_priv *priv, int port, 1100 bool enable) 1101 { 1102 struct rtl8365mb *mb = priv->chip_data; 1103 1104 /* Enable/disable learning by limiting the number of L2 addresses the 1105 * port can learn. Realtek documentation states that a limit of zero 1106 * disables learning. When enabling learning, set it to the chip's 1107 * maximum. 1108 */ 1109 return regmap_write(priv->map, RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(port), 1110 enable ? mb->learn_limit_max : 0); 1111 } 1112 1113 static int rtl8365mb_port_set_isolation(struct realtek_priv *priv, int port, 1114 u32 mask) 1115 { 1116 return regmap_write(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), mask); 1117 } 1118 1119 static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port, 1120 u32 offset, u32 length, u64 *mibvalue) 1121 { 1122 u64 tmpvalue = 0; 1123 u32 val; 1124 int ret; 1125 int i; 1126 1127 /* The MIB address is an SRAM address. We request a particular address 1128 * and then poll the control register before reading the value from some 1129 * counter registers. 1130 */ 1131 ret = regmap_write(priv->map, RTL8365MB_MIB_ADDRESS_REG, 1132 RTL8365MB_MIB_ADDRESS(port, offset)); 1133 if (ret) 1134 return ret; 1135 1136 /* Poll for completion */ 1137 ret = regmap_read_poll_timeout(priv->map, RTL8365MB_MIB_CTRL0_REG, val, 1138 !(val & RTL8365MB_MIB_CTRL0_BUSY_MASK), 1139 10, 100); 1140 if (ret) 1141 return ret; 1142 1143 /* Presumably this indicates a MIB counter read failure */ 1144 if (val & RTL8365MB_MIB_CTRL0_RESET_MASK) 1145 return -EIO; 1146 1147 /* There are four MIB counter registers each holding a 16 bit word of a 1148 * MIB counter. Depending on the offset, we should read from the upper 1149 * two or lower two registers. In case the MIB counter is 4 words, we 1150 * read from all four registers. 1151 */ 1152 if (length == 4) 1153 offset = 3; 1154 else 1155 offset = (offset + 1) % 4; 1156 1157 /* Read the MIB counter 16 bits at a time */ 1158 for (i = 0; i < length; i++) { 1159 ret = regmap_read(priv->map, 1160 RTL8365MB_MIB_COUNTER_REG(offset - i), &val); 1161 if (ret) 1162 return ret; 1163 1164 tmpvalue = ((tmpvalue) << 16) | (val & 0xFFFF); 1165 } 1166 1167 /* Only commit the result if no error occurred */ 1168 *mibvalue = tmpvalue; 1169 1170 return 0; 1171 } 1172 1173 static void rtl8365mb_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data) 1174 { 1175 struct realtek_priv *priv = ds->priv; 1176 struct rtl8365mb *mb; 1177 int ret; 1178 int i; 1179 1180 mb = priv->chip_data; 1181 1182 mutex_lock(&mb->mib_lock); 1183 for (i = 0; i < RTL8365MB_MIB_END; i++) { 1184 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; 1185 1186 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset, 1187 mib->length, &data[i]); 1188 if (ret) { 1189 dev_err(priv->dev, 1190 "failed to read port %d counters: %d\n", port, 1191 ret); 1192 break; 1193 } 1194 } 1195 mutex_unlock(&mb->mib_lock); 1196 } 1197 1198 static void rtl8365mb_get_strings(struct dsa_switch *ds, int port, u32 stringset, u8 *data) 1199 { 1200 int i; 1201 1202 if (stringset != ETH_SS_STATS) 1203 return; 1204 1205 for (i = 0; i < RTL8365MB_MIB_END; i++) { 1206 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; 1207 1208 strncpy(data + i * ETH_GSTRING_LEN, mib->name, ETH_GSTRING_LEN); 1209 } 1210 } 1211 1212 static int rtl8365mb_get_sset_count(struct dsa_switch *ds, int port, int sset) 1213 { 1214 if (sset != ETH_SS_STATS) 1215 return -EOPNOTSUPP; 1216 1217 return RTL8365MB_MIB_END; 1218 } 1219 1220 static void rtl8365mb_get_phy_stats(struct dsa_switch *ds, int port, 1221 struct ethtool_eth_phy_stats *phy_stats) 1222 { 1223 struct realtek_priv *priv = ds->priv; 1224 struct rtl8365mb_mib_counter *mib; 1225 struct rtl8365mb *mb; 1226 1227 mb = priv->chip_data; 1228 mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3StatsSymbolErrors]; 1229 1230 mutex_lock(&mb->mib_lock); 1231 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, 1232 &phy_stats->SymbolErrorDuringCarrier); 1233 mutex_unlock(&mb->mib_lock); 1234 } 1235 1236 static void rtl8365mb_get_mac_stats(struct dsa_switch *ds, int port, 1237 struct ethtool_eth_mac_stats *mac_stats) 1238 { 1239 u64 cnt[RTL8365MB_MIB_END] = { 1240 [RTL8365MB_MIB_ifOutOctets] = 1, 1241 [RTL8365MB_MIB_ifOutUcastPkts] = 1, 1242 [RTL8365MB_MIB_ifOutMulticastPkts] = 1, 1243 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1, 1244 [RTL8365MB_MIB_dot3OutPauseFrames] = 1, 1245 [RTL8365MB_MIB_ifOutDiscards] = 1, 1246 [RTL8365MB_MIB_ifInOctets] = 1, 1247 [RTL8365MB_MIB_ifInUcastPkts] = 1, 1248 [RTL8365MB_MIB_ifInMulticastPkts] = 1, 1249 [RTL8365MB_MIB_ifInBroadcastPkts] = 1, 1250 [RTL8365MB_MIB_dot3InPauseFrames] = 1, 1251 [RTL8365MB_MIB_dot3StatsSingleCollisionFrames] = 1, 1252 [RTL8365MB_MIB_dot3StatsMultipleCollisionFrames] = 1, 1253 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1, 1254 [RTL8365MB_MIB_dot3StatsDeferredTransmissions] = 1, 1255 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1, 1256 [RTL8365MB_MIB_dot3StatsExcessiveCollisions] = 1, 1257 1258 }; 1259 struct realtek_priv *priv = ds->priv; 1260 struct rtl8365mb *mb; 1261 int ret; 1262 int i; 1263 1264 mb = priv->chip_data; 1265 1266 mutex_lock(&mb->mib_lock); 1267 for (i = 0; i < RTL8365MB_MIB_END; i++) { 1268 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; 1269 1270 /* Only fetch required MIB counters (marked = 1 above) */ 1271 if (!cnt[i]) 1272 continue; 1273 1274 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset, 1275 mib->length, &cnt[i]); 1276 if (ret) 1277 break; 1278 } 1279 mutex_unlock(&mb->mib_lock); 1280 1281 /* The RTL8365MB-VC exposes MIB objects, which we have to translate into 1282 * IEEE 802.3 Managed Objects. This is not always completely faithful, 1283 * but we try out best. See RFC 3635 for a detailed treatment of the 1284 * subject. 1285 */ 1286 1287 mac_stats->FramesTransmittedOK = cnt[RTL8365MB_MIB_ifOutUcastPkts] + 1288 cnt[RTL8365MB_MIB_ifOutMulticastPkts] + 1289 cnt[RTL8365MB_MIB_ifOutBroadcastPkts] + 1290 cnt[RTL8365MB_MIB_dot3OutPauseFrames] - 1291 cnt[RTL8365MB_MIB_ifOutDiscards]; 1292 mac_stats->SingleCollisionFrames = 1293 cnt[RTL8365MB_MIB_dot3StatsSingleCollisionFrames]; 1294 mac_stats->MultipleCollisionFrames = 1295 cnt[RTL8365MB_MIB_dot3StatsMultipleCollisionFrames]; 1296 mac_stats->FramesReceivedOK = cnt[RTL8365MB_MIB_ifInUcastPkts] + 1297 cnt[RTL8365MB_MIB_ifInMulticastPkts] + 1298 cnt[RTL8365MB_MIB_ifInBroadcastPkts] + 1299 cnt[RTL8365MB_MIB_dot3InPauseFrames]; 1300 mac_stats->FrameCheckSequenceErrors = 1301 cnt[RTL8365MB_MIB_dot3StatsFCSErrors]; 1302 mac_stats->OctetsTransmittedOK = cnt[RTL8365MB_MIB_ifOutOctets] - 1303 18 * mac_stats->FramesTransmittedOK; 1304 mac_stats->FramesWithDeferredXmissions = 1305 cnt[RTL8365MB_MIB_dot3StatsDeferredTransmissions]; 1306 mac_stats->LateCollisions = cnt[RTL8365MB_MIB_dot3StatsLateCollisions]; 1307 mac_stats->FramesAbortedDueToXSColls = 1308 cnt[RTL8365MB_MIB_dot3StatsExcessiveCollisions]; 1309 mac_stats->OctetsReceivedOK = cnt[RTL8365MB_MIB_ifInOctets] - 1310 18 * mac_stats->FramesReceivedOK; 1311 mac_stats->MulticastFramesXmittedOK = 1312 cnt[RTL8365MB_MIB_ifOutMulticastPkts]; 1313 mac_stats->BroadcastFramesXmittedOK = 1314 cnt[RTL8365MB_MIB_ifOutBroadcastPkts]; 1315 mac_stats->MulticastFramesReceivedOK = 1316 cnt[RTL8365MB_MIB_ifInMulticastPkts]; 1317 mac_stats->BroadcastFramesReceivedOK = 1318 cnt[RTL8365MB_MIB_ifInBroadcastPkts]; 1319 } 1320 1321 static void rtl8365mb_get_ctrl_stats(struct dsa_switch *ds, int port, 1322 struct ethtool_eth_ctrl_stats *ctrl_stats) 1323 { 1324 struct realtek_priv *priv = ds->priv; 1325 struct rtl8365mb_mib_counter *mib; 1326 struct rtl8365mb *mb; 1327 1328 mb = priv->chip_data; 1329 mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3ControlInUnknownOpcodes]; 1330 1331 mutex_lock(&mb->mib_lock); 1332 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, 1333 &ctrl_stats->UnsupportedOpcodesReceived); 1334 mutex_unlock(&mb->mib_lock); 1335 } 1336 1337 static void rtl8365mb_stats_update(struct realtek_priv *priv, int port) 1338 { 1339 u64 cnt[RTL8365MB_MIB_END] = { 1340 [RTL8365MB_MIB_ifOutOctets] = 1, 1341 [RTL8365MB_MIB_ifOutUcastPkts] = 1, 1342 [RTL8365MB_MIB_ifOutMulticastPkts] = 1, 1343 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1, 1344 [RTL8365MB_MIB_ifOutDiscards] = 1, 1345 [RTL8365MB_MIB_ifInOctets] = 1, 1346 [RTL8365MB_MIB_ifInUcastPkts] = 1, 1347 [RTL8365MB_MIB_ifInMulticastPkts] = 1, 1348 [RTL8365MB_MIB_ifInBroadcastPkts] = 1, 1349 [RTL8365MB_MIB_etherStatsDropEvents] = 1, 1350 [RTL8365MB_MIB_etherStatsCollisions] = 1, 1351 [RTL8365MB_MIB_etherStatsFragments] = 1, 1352 [RTL8365MB_MIB_etherStatsJabbers] = 1, 1353 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1, 1354 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1, 1355 }; 1356 struct rtl8365mb *mb = priv->chip_data; 1357 struct rtnl_link_stats64 *stats; 1358 int ret; 1359 int i; 1360 1361 stats = &mb->ports[port].stats; 1362 1363 mutex_lock(&mb->mib_lock); 1364 for (i = 0; i < RTL8365MB_MIB_END; i++) { 1365 struct rtl8365mb_mib_counter *c = &rtl8365mb_mib_counters[i]; 1366 1367 /* Only fetch required MIB counters (marked = 1 above) */ 1368 if (!cnt[i]) 1369 continue; 1370 1371 ret = rtl8365mb_mib_counter_read(priv, port, c->offset, 1372 c->length, &cnt[i]); 1373 if (ret) 1374 break; 1375 } 1376 mutex_unlock(&mb->mib_lock); 1377 1378 /* Don't update statistics if there was an error reading the counters */ 1379 if (ret) 1380 return; 1381 1382 spin_lock(&mb->ports[port].stats_lock); 1383 1384 stats->rx_packets = cnt[RTL8365MB_MIB_ifInUcastPkts] + 1385 cnt[RTL8365MB_MIB_ifInMulticastPkts] + 1386 cnt[RTL8365MB_MIB_ifInBroadcastPkts] - 1387 cnt[RTL8365MB_MIB_ifOutDiscards]; 1388 1389 stats->tx_packets = cnt[RTL8365MB_MIB_ifOutUcastPkts] + 1390 cnt[RTL8365MB_MIB_ifOutMulticastPkts] + 1391 cnt[RTL8365MB_MIB_ifOutBroadcastPkts]; 1392 1393 /* if{In,Out}Octets includes FCS - remove it */ 1394 stats->rx_bytes = cnt[RTL8365MB_MIB_ifInOctets] - 4 * stats->rx_packets; 1395 stats->tx_bytes = 1396 cnt[RTL8365MB_MIB_ifOutOctets] - 4 * stats->tx_packets; 1397 1398 stats->rx_dropped = cnt[RTL8365MB_MIB_etherStatsDropEvents]; 1399 stats->tx_dropped = cnt[RTL8365MB_MIB_ifOutDiscards]; 1400 1401 stats->multicast = cnt[RTL8365MB_MIB_ifInMulticastPkts]; 1402 stats->collisions = cnt[RTL8365MB_MIB_etherStatsCollisions]; 1403 1404 stats->rx_length_errors = cnt[RTL8365MB_MIB_etherStatsFragments] + 1405 cnt[RTL8365MB_MIB_etherStatsJabbers]; 1406 stats->rx_crc_errors = cnt[RTL8365MB_MIB_dot3StatsFCSErrors]; 1407 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors; 1408 1409 stats->tx_aborted_errors = cnt[RTL8365MB_MIB_ifOutDiscards]; 1410 stats->tx_window_errors = cnt[RTL8365MB_MIB_dot3StatsLateCollisions]; 1411 stats->tx_errors = stats->tx_aborted_errors + stats->tx_window_errors; 1412 1413 spin_unlock(&mb->ports[port].stats_lock); 1414 } 1415 1416 static void rtl8365mb_stats_poll(struct work_struct *work) 1417 { 1418 struct rtl8365mb_port *p = container_of(to_delayed_work(work), 1419 struct rtl8365mb_port, 1420 mib_work); 1421 struct realtek_priv *priv = p->priv; 1422 1423 rtl8365mb_stats_update(priv, p->index); 1424 1425 schedule_delayed_work(&p->mib_work, RTL8365MB_STATS_INTERVAL_JIFFIES); 1426 } 1427 1428 static void rtl8365mb_get_stats64(struct dsa_switch *ds, int port, 1429 struct rtnl_link_stats64 *s) 1430 { 1431 struct realtek_priv *priv = ds->priv; 1432 struct rtl8365mb_port *p; 1433 struct rtl8365mb *mb; 1434 1435 mb = priv->chip_data; 1436 p = &mb->ports[port]; 1437 1438 spin_lock(&p->stats_lock); 1439 memcpy(s, &p->stats, sizeof(*s)); 1440 spin_unlock(&p->stats_lock); 1441 } 1442 1443 static void rtl8365mb_stats_setup(struct realtek_priv *priv) 1444 { 1445 struct rtl8365mb *mb = priv->chip_data; 1446 int i; 1447 1448 /* Per-chip global mutex to protect MIB counter access, since doing 1449 * so requires accessing a series of registers in a particular order. 1450 */ 1451 mutex_init(&mb->mib_lock); 1452 1453 for (i = 0; i < priv->num_ports; i++) { 1454 struct rtl8365mb_port *p = &mb->ports[i]; 1455 1456 if (dsa_is_unused_port(priv->ds, i)) 1457 continue; 1458 1459 /* Per-port spinlock to protect the stats64 data */ 1460 spin_lock_init(&p->stats_lock); 1461 1462 /* This work polls the MIB counters and keeps the stats64 data 1463 * up-to-date. 1464 */ 1465 INIT_DELAYED_WORK(&p->mib_work, rtl8365mb_stats_poll); 1466 } 1467 } 1468 1469 static void rtl8365mb_stats_teardown(struct realtek_priv *priv) 1470 { 1471 struct rtl8365mb *mb = priv->chip_data; 1472 int i; 1473 1474 for (i = 0; i < priv->num_ports; i++) { 1475 struct rtl8365mb_port *p = &mb->ports[i]; 1476 1477 if (dsa_is_unused_port(priv->ds, i)) 1478 continue; 1479 1480 cancel_delayed_work_sync(&p->mib_work); 1481 } 1482 } 1483 1484 static int rtl8365mb_get_and_clear_status_reg(struct realtek_priv *priv, u32 reg, 1485 u32 *val) 1486 { 1487 int ret; 1488 1489 ret = regmap_read(priv->map, reg, val); 1490 if (ret) 1491 return ret; 1492 1493 return regmap_write(priv->map, reg, *val); 1494 } 1495 1496 static irqreturn_t rtl8365mb_irq(int irq, void *data) 1497 { 1498 struct realtek_priv *priv = data; 1499 unsigned long line_changes = 0; 1500 struct rtl8365mb *mb; 1501 u32 stat; 1502 int line; 1503 int ret; 1504 1505 mb = priv->chip_data; 1506 1507 ret = rtl8365mb_get_and_clear_status_reg(priv, RTL8365MB_INTR_STATUS_REG, 1508 &stat); 1509 if (ret) 1510 goto out_error; 1511 1512 if (stat & RTL8365MB_INTR_LINK_CHANGE_MASK) { 1513 u32 linkdown_ind; 1514 u32 linkup_ind; 1515 u32 val; 1516 1517 ret = rtl8365mb_get_and_clear_status_reg( 1518 priv, RTL8365MB_PORT_LINKUP_IND_REG, &val); 1519 if (ret) 1520 goto out_error; 1521 1522 linkup_ind = FIELD_GET(RTL8365MB_PORT_LINKUP_IND_MASK, val); 1523 1524 ret = rtl8365mb_get_and_clear_status_reg( 1525 priv, RTL8365MB_PORT_LINKDOWN_IND_REG, &val); 1526 if (ret) 1527 goto out_error; 1528 1529 linkdown_ind = FIELD_GET(RTL8365MB_PORT_LINKDOWN_IND_MASK, val); 1530 1531 line_changes = (linkup_ind | linkdown_ind) & mb->port_mask; 1532 } 1533 1534 if (!line_changes) 1535 goto out_none; 1536 1537 for_each_set_bit(line, &line_changes, priv->num_ports) { 1538 int child_irq = irq_find_mapping(priv->irqdomain, line); 1539 1540 handle_nested_irq(child_irq); 1541 } 1542 1543 return IRQ_HANDLED; 1544 1545 out_error: 1546 dev_err(priv->dev, "failed to read interrupt status: %d\n", ret); 1547 1548 out_none: 1549 return IRQ_NONE; 1550 } 1551 1552 static struct irq_chip rtl8365mb_irq_chip = { 1553 .name = "rtl8365mb", 1554 /* The hardware doesn't support masking IRQs on a per-port basis */ 1555 }; 1556 1557 static int rtl8365mb_irq_map(struct irq_domain *domain, unsigned int irq, 1558 irq_hw_number_t hwirq) 1559 { 1560 irq_set_chip_data(irq, domain->host_data); 1561 irq_set_chip_and_handler(irq, &rtl8365mb_irq_chip, handle_simple_irq); 1562 irq_set_nested_thread(irq, 1); 1563 irq_set_noprobe(irq); 1564 1565 return 0; 1566 } 1567 1568 static void rtl8365mb_irq_unmap(struct irq_domain *d, unsigned int irq) 1569 { 1570 irq_set_nested_thread(irq, 0); 1571 irq_set_chip_and_handler(irq, NULL, NULL); 1572 irq_set_chip_data(irq, NULL); 1573 } 1574 1575 static const struct irq_domain_ops rtl8365mb_irqdomain_ops = { 1576 .map = rtl8365mb_irq_map, 1577 .unmap = rtl8365mb_irq_unmap, 1578 .xlate = irq_domain_xlate_onecell, 1579 }; 1580 1581 static int rtl8365mb_set_irq_enable(struct realtek_priv *priv, bool enable) 1582 { 1583 return regmap_update_bits(priv->map, RTL8365MB_INTR_CTRL_REG, 1584 RTL8365MB_INTR_LINK_CHANGE_MASK, 1585 FIELD_PREP(RTL8365MB_INTR_LINK_CHANGE_MASK, 1586 enable ? 1 : 0)); 1587 } 1588 1589 static int rtl8365mb_irq_enable(struct realtek_priv *priv) 1590 { 1591 return rtl8365mb_set_irq_enable(priv, true); 1592 } 1593 1594 static int rtl8365mb_irq_disable(struct realtek_priv *priv) 1595 { 1596 return rtl8365mb_set_irq_enable(priv, false); 1597 } 1598 1599 static int rtl8365mb_irq_setup(struct realtek_priv *priv) 1600 { 1601 struct rtl8365mb *mb = priv->chip_data; 1602 struct device_node *intc; 1603 u32 irq_trig; 1604 int virq; 1605 int irq; 1606 u32 val; 1607 int ret; 1608 int i; 1609 1610 intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller"); 1611 if (!intc) { 1612 dev_err(priv->dev, "missing child interrupt-controller node\n"); 1613 return -EINVAL; 1614 } 1615 1616 /* rtl8365mb IRQs cascade off this one */ 1617 irq = of_irq_get(intc, 0); 1618 if (irq <= 0) { 1619 if (irq != -EPROBE_DEFER) 1620 dev_err(priv->dev, "failed to get parent irq: %d\n", 1621 irq); 1622 ret = irq ? irq : -EINVAL; 1623 goto out_put_node; 1624 } 1625 1626 priv->irqdomain = irq_domain_add_linear(intc, priv->num_ports, 1627 &rtl8365mb_irqdomain_ops, priv); 1628 if (!priv->irqdomain) { 1629 dev_err(priv->dev, "failed to add irq domain\n"); 1630 ret = -ENOMEM; 1631 goto out_put_node; 1632 } 1633 1634 for (i = 0; i < priv->num_ports; i++) { 1635 virq = irq_create_mapping(priv->irqdomain, i); 1636 if (!virq) { 1637 dev_err(priv->dev, 1638 "failed to create irq domain mapping\n"); 1639 ret = -EINVAL; 1640 goto out_remove_irqdomain; 1641 } 1642 1643 irq_set_parent(virq, irq); 1644 } 1645 1646 /* Configure chip interrupt signal polarity */ 1647 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq)); 1648 switch (irq_trig) { 1649 case IRQF_TRIGGER_RISING: 1650 case IRQF_TRIGGER_HIGH: 1651 val = RTL8365MB_INTR_POLARITY_HIGH; 1652 break; 1653 case IRQF_TRIGGER_FALLING: 1654 case IRQF_TRIGGER_LOW: 1655 val = RTL8365MB_INTR_POLARITY_LOW; 1656 break; 1657 default: 1658 dev_err(priv->dev, "unsupported irq trigger type %u\n", 1659 irq_trig); 1660 ret = -EINVAL; 1661 goto out_remove_irqdomain; 1662 } 1663 1664 ret = regmap_update_bits(priv->map, RTL8365MB_INTR_POLARITY_REG, 1665 RTL8365MB_INTR_POLARITY_MASK, 1666 FIELD_PREP(RTL8365MB_INTR_POLARITY_MASK, val)); 1667 if (ret) 1668 goto out_remove_irqdomain; 1669 1670 /* Disable the interrupt in case the chip has it enabled on reset */ 1671 ret = rtl8365mb_irq_disable(priv); 1672 if (ret) 1673 goto out_remove_irqdomain; 1674 1675 /* Clear the interrupt status register */ 1676 ret = regmap_write(priv->map, RTL8365MB_INTR_STATUS_REG, 1677 RTL8365MB_INTR_ALL_MASK); 1678 if (ret) 1679 goto out_remove_irqdomain; 1680 1681 ret = request_threaded_irq(irq, NULL, rtl8365mb_irq, IRQF_ONESHOT, 1682 "rtl8365mb", priv); 1683 if (ret) { 1684 dev_err(priv->dev, "failed to request irq: %d\n", ret); 1685 goto out_remove_irqdomain; 1686 } 1687 1688 /* Store the irq so that we know to free it during teardown */ 1689 mb->irq = irq; 1690 1691 ret = rtl8365mb_irq_enable(priv); 1692 if (ret) 1693 goto out_free_irq; 1694 1695 of_node_put(intc); 1696 1697 return 0; 1698 1699 out_free_irq: 1700 free_irq(mb->irq, priv); 1701 mb->irq = 0; 1702 1703 out_remove_irqdomain: 1704 for (i = 0; i < priv->num_ports; i++) { 1705 virq = irq_find_mapping(priv->irqdomain, i); 1706 irq_dispose_mapping(virq); 1707 } 1708 1709 irq_domain_remove(priv->irqdomain); 1710 priv->irqdomain = NULL; 1711 1712 out_put_node: 1713 of_node_put(intc); 1714 1715 return ret; 1716 } 1717 1718 static void rtl8365mb_irq_teardown(struct realtek_priv *priv) 1719 { 1720 struct rtl8365mb *mb = priv->chip_data; 1721 int virq; 1722 int i; 1723 1724 if (mb->irq) { 1725 free_irq(mb->irq, priv); 1726 mb->irq = 0; 1727 } 1728 1729 if (priv->irqdomain) { 1730 for (i = 0; i < priv->num_ports; i++) { 1731 virq = irq_find_mapping(priv->irqdomain, i); 1732 irq_dispose_mapping(virq); 1733 } 1734 1735 irq_domain_remove(priv->irqdomain); 1736 priv->irqdomain = NULL; 1737 } 1738 } 1739 1740 static int rtl8365mb_cpu_config(struct realtek_priv *priv, const struct rtl8365mb_cpu *cpu) 1741 { 1742 u32 val; 1743 int ret; 1744 1745 ret = regmap_update_bits(priv->map, RTL8365MB_CPU_PORT_MASK_REG, 1746 RTL8365MB_CPU_PORT_MASK_MASK, 1747 FIELD_PREP(RTL8365MB_CPU_PORT_MASK_MASK, 1748 cpu->mask)); 1749 if (ret) 1750 return ret; 1751 1752 val = FIELD_PREP(RTL8365MB_CPU_CTRL_EN_MASK, cpu->enable ? 1 : 0) | 1753 FIELD_PREP(RTL8365MB_CPU_CTRL_INSERTMODE_MASK, cpu->insert) | 1754 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_POSITION_MASK, cpu->position) | 1755 FIELD_PREP(RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK, cpu->rx_length) | 1756 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK, cpu->format) | 1757 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_MASK, cpu->trap_port & 0x7) | 1758 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK, 1759 cpu->trap_port >> 3 & 0x1); 1760 ret = regmap_write(priv->map, RTL8365MB_CPU_CTRL_REG, val); 1761 if (ret) 1762 return ret; 1763 1764 return 0; 1765 } 1766 1767 static int rtl8365mb_switch_init(struct realtek_priv *priv) 1768 { 1769 struct rtl8365mb *mb = priv->chip_data; 1770 int ret; 1771 int i; 1772 1773 /* Do any chip-specific init jam before getting to the common stuff */ 1774 if (mb->jam_table) { 1775 for (i = 0; i < mb->jam_size; i++) { 1776 ret = regmap_write(priv->map, mb->jam_table[i].reg, 1777 mb->jam_table[i].val); 1778 if (ret) 1779 return ret; 1780 } 1781 } 1782 1783 /* Common init jam */ 1784 for (i = 0; i < ARRAY_SIZE(rtl8365mb_init_jam_common); i++) { 1785 ret = regmap_write(priv->map, rtl8365mb_init_jam_common[i].reg, 1786 rtl8365mb_init_jam_common[i].val); 1787 if (ret) 1788 return ret; 1789 } 1790 1791 return 0; 1792 } 1793 1794 static int rtl8365mb_reset_chip(struct realtek_priv *priv) 1795 { 1796 u32 val; 1797 1798 priv->write_reg_noack(priv, RTL8365MB_CHIP_RESET_REG, 1799 FIELD_PREP(RTL8365MB_CHIP_RESET_HW_MASK, 1)); 1800 1801 /* Realtek documentation says the chip needs 1 second to reset. Sleep 1802 * for 100 ms before accessing any registers to prevent ACK timeouts. 1803 */ 1804 msleep(100); 1805 return regmap_read_poll_timeout(priv->map, RTL8365MB_CHIP_RESET_REG, val, 1806 !(val & RTL8365MB_CHIP_RESET_HW_MASK), 1807 20000, 1e6); 1808 } 1809 1810 static int rtl8365mb_setup(struct dsa_switch *ds) 1811 { 1812 struct realtek_priv *priv = ds->priv; 1813 struct rtl8365mb_cpu cpu = {0}; 1814 struct dsa_port *cpu_dp; 1815 struct rtl8365mb *mb; 1816 int ret; 1817 int i; 1818 1819 mb = priv->chip_data; 1820 1821 ret = rtl8365mb_reset_chip(priv); 1822 if (ret) { 1823 dev_err(priv->dev, "failed to reset chip: %d\n", ret); 1824 goto out_error; 1825 } 1826 1827 /* Configure switch to vendor-defined initial state */ 1828 ret = rtl8365mb_switch_init(priv); 1829 if (ret) { 1830 dev_err(priv->dev, "failed to initialize switch: %d\n", ret); 1831 goto out_error; 1832 } 1833 1834 /* Set up cascading IRQs */ 1835 ret = rtl8365mb_irq_setup(priv); 1836 if (ret == -EPROBE_DEFER) 1837 return ret; 1838 else if (ret) 1839 dev_info(priv->dev, "no interrupt support\n"); 1840 1841 /* Configure CPU tagging */ 1842 cpu.trap_port = RTL8365MB_MAX_NUM_PORTS; 1843 dsa_switch_for_each_cpu_port(cpu_dp, priv->ds) { 1844 cpu.mask |= BIT(cpu_dp->index); 1845 1846 if (cpu.trap_port == RTL8365MB_MAX_NUM_PORTS) 1847 cpu.trap_port = cpu_dp->index; 1848 } 1849 1850 cpu.enable = cpu.mask > 0; 1851 cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL; 1852 cpu.position = RTL8365MB_CPU_POS_AFTER_SA; 1853 cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES; 1854 cpu.format = RTL8365MB_CPU_FORMAT_8BYTES; 1855 1856 ret = rtl8365mb_cpu_config(priv, &cpu); 1857 if (ret) 1858 goto out_teardown_irq; 1859 1860 /* Configure ports */ 1861 for (i = 0; i < priv->num_ports; i++) { 1862 struct rtl8365mb_port *p = &mb->ports[i]; 1863 1864 if (dsa_is_unused_port(priv->ds, i)) 1865 continue; 1866 1867 /* Forward only to the CPU */ 1868 ret = rtl8365mb_port_set_isolation(priv, i, cpu.mask); 1869 if (ret) 1870 goto out_teardown_irq; 1871 1872 /* Disable learning */ 1873 ret = rtl8365mb_port_set_learning(priv, i, false); 1874 if (ret) 1875 goto out_teardown_irq; 1876 1877 /* Set the initial STP state of all ports to DISABLED, otherwise 1878 * ports will still forward frames to the CPU despite being 1879 * administratively down by default. 1880 */ 1881 rtl8365mb_port_stp_state_set(priv->ds, i, BR_STATE_DISABLED); 1882 1883 /* Set up per-port private data */ 1884 p->priv = priv; 1885 p->index = i; 1886 } 1887 1888 /* Set maximum packet length to 1536 bytes */ 1889 ret = regmap_update_bits(priv->map, RTL8365MB_CFG0_MAX_LEN_REG, 1890 RTL8365MB_CFG0_MAX_LEN_MASK, 1891 FIELD_PREP(RTL8365MB_CFG0_MAX_LEN_MASK, 1536)); 1892 if (ret) 1893 goto out_teardown_irq; 1894 1895 if (priv->setup_interface) { 1896 ret = priv->setup_interface(ds); 1897 if (ret) { 1898 dev_err(priv->dev, "could not set up MDIO bus\n"); 1899 goto out_teardown_irq; 1900 } 1901 } 1902 1903 /* Start statistics counter polling */ 1904 rtl8365mb_stats_setup(priv); 1905 1906 return 0; 1907 1908 out_teardown_irq: 1909 rtl8365mb_irq_teardown(priv); 1910 1911 out_error: 1912 return ret; 1913 } 1914 1915 static void rtl8365mb_teardown(struct dsa_switch *ds) 1916 { 1917 struct realtek_priv *priv = ds->priv; 1918 1919 rtl8365mb_stats_teardown(priv); 1920 rtl8365mb_irq_teardown(priv); 1921 } 1922 1923 static int rtl8365mb_get_chip_id_and_ver(struct regmap *map, u32 *id, u32 *ver) 1924 { 1925 int ret; 1926 1927 /* For some reason we have to write a magic value to an arbitrary 1928 * register whenever accessing the chip ID/version registers. 1929 */ 1930 ret = regmap_write(map, RTL8365MB_MAGIC_REG, RTL8365MB_MAGIC_VALUE); 1931 if (ret) 1932 return ret; 1933 1934 ret = regmap_read(map, RTL8365MB_CHIP_ID_REG, id); 1935 if (ret) 1936 return ret; 1937 1938 ret = regmap_read(map, RTL8365MB_CHIP_VER_REG, ver); 1939 if (ret) 1940 return ret; 1941 1942 /* Reset magic register */ 1943 ret = regmap_write(map, RTL8365MB_MAGIC_REG, 0); 1944 if (ret) 1945 return ret; 1946 1947 return 0; 1948 } 1949 1950 static int rtl8365mb_detect(struct realtek_priv *priv) 1951 { 1952 struct rtl8365mb *mb = priv->chip_data; 1953 u32 chip_id; 1954 u32 chip_ver; 1955 int ret; 1956 1957 ret = rtl8365mb_get_chip_id_and_ver(priv->map, &chip_id, &chip_ver); 1958 if (ret) { 1959 dev_err(priv->dev, "failed to read chip id and version: %d\n", 1960 ret); 1961 return ret; 1962 } 1963 1964 switch (chip_id) { 1965 case RTL8365MB_CHIP_ID_8365MB_VC: 1966 switch (chip_ver) { 1967 case RTL8365MB_CHIP_VER_8365MB_VC: 1968 dev_info(priv->dev, 1969 "found an RTL8365MB-VC switch (ver=0x%04x)\n", 1970 chip_ver); 1971 break; 1972 case RTL8365MB_CHIP_VER_8367RB: 1973 dev_info(priv->dev, 1974 "found an RTL8367RB-VB switch (ver=0x%04x)\n", 1975 chip_ver); 1976 break; 1977 case RTL8365MB_CHIP_VER_8367S: 1978 dev_info(priv->dev, 1979 "found an RTL8367S switch (ver=0x%04x)\n", 1980 chip_ver); 1981 break; 1982 default: 1983 dev_err(priv->dev, "unrecognized switch version (ver=0x%04x)", 1984 chip_ver); 1985 return -ENODEV; 1986 } 1987 1988 priv->num_ports = RTL8365MB_MAX_NUM_PORTS; 1989 1990 mb->priv = priv; 1991 mb->chip_id = chip_id; 1992 mb->chip_ver = chip_ver; 1993 mb->port_mask = GENMASK(priv->num_ports - 1, 0); 1994 mb->learn_limit_max = RTL8365MB_LEARN_LIMIT_MAX; 1995 mb->jam_table = rtl8365mb_init_jam_8365mb_vc; 1996 mb->jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc); 1997 1998 break; 1999 default: 2000 dev_err(priv->dev, 2001 "found an unknown Realtek switch (id=0x%04x, ver=0x%04x)\n", 2002 chip_id, chip_ver); 2003 return -ENODEV; 2004 } 2005 2006 return 0; 2007 } 2008 2009 static const struct dsa_switch_ops rtl8365mb_switch_ops_smi = { 2010 .get_tag_protocol = rtl8365mb_get_tag_protocol, 2011 .setup = rtl8365mb_setup, 2012 .teardown = rtl8365mb_teardown, 2013 .phylink_get_caps = rtl8365mb_phylink_get_caps, 2014 .phylink_mac_config = rtl8365mb_phylink_mac_config, 2015 .phylink_mac_link_down = rtl8365mb_phylink_mac_link_down, 2016 .phylink_mac_link_up = rtl8365mb_phylink_mac_link_up, 2017 .port_stp_state_set = rtl8365mb_port_stp_state_set, 2018 .get_strings = rtl8365mb_get_strings, 2019 .get_ethtool_stats = rtl8365mb_get_ethtool_stats, 2020 .get_sset_count = rtl8365mb_get_sset_count, 2021 .get_eth_phy_stats = rtl8365mb_get_phy_stats, 2022 .get_eth_mac_stats = rtl8365mb_get_mac_stats, 2023 .get_eth_ctrl_stats = rtl8365mb_get_ctrl_stats, 2024 .get_stats64 = rtl8365mb_get_stats64, 2025 }; 2026 2027 static const struct dsa_switch_ops rtl8365mb_switch_ops_mdio = { 2028 .get_tag_protocol = rtl8365mb_get_tag_protocol, 2029 .setup = rtl8365mb_setup, 2030 .teardown = rtl8365mb_teardown, 2031 .phylink_get_caps = rtl8365mb_phylink_get_caps, 2032 .phylink_mac_config = rtl8365mb_phylink_mac_config, 2033 .phylink_mac_link_down = rtl8365mb_phylink_mac_link_down, 2034 .phylink_mac_link_up = rtl8365mb_phylink_mac_link_up, 2035 .phy_read = rtl8365mb_dsa_phy_read, 2036 .phy_write = rtl8365mb_dsa_phy_write, 2037 .port_stp_state_set = rtl8365mb_port_stp_state_set, 2038 .get_strings = rtl8365mb_get_strings, 2039 .get_ethtool_stats = rtl8365mb_get_ethtool_stats, 2040 .get_sset_count = rtl8365mb_get_sset_count, 2041 .get_eth_phy_stats = rtl8365mb_get_phy_stats, 2042 .get_eth_mac_stats = rtl8365mb_get_mac_stats, 2043 .get_eth_ctrl_stats = rtl8365mb_get_ctrl_stats, 2044 .get_stats64 = rtl8365mb_get_stats64, 2045 }; 2046 2047 static const struct realtek_ops rtl8365mb_ops = { 2048 .detect = rtl8365mb_detect, 2049 .phy_read = rtl8365mb_phy_read, 2050 .phy_write = rtl8365mb_phy_write, 2051 }; 2052 2053 const struct realtek_variant rtl8365mb_variant = { 2054 .ds_ops_smi = &rtl8365mb_switch_ops_smi, 2055 .ds_ops_mdio = &rtl8365mb_switch_ops_mdio, 2056 .ops = &rtl8365mb_ops, 2057 .clk_delay = 10, 2058 .cmd_read = 0xb9, 2059 .cmd_write = 0xb8, 2060 .chip_data_sz = sizeof(struct rtl8365mb), 2061 }; 2062 EXPORT_SYMBOL_GPL(rtl8365mb_variant); 2063 2064 MODULE_AUTHOR("Alvin Šipraga <alsi@bang-olufsen.dk>"); 2065 MODULE_DESCRIPTION("Driver for RTL8365MB-VC ethernet switch"); 2066 MODULE_LICENSE("GPL"); 2067