1 // SPDX-License-Identifier: GPL-2.0 2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch. 3 * 4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk> 5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk> 6 * 7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4 8 * integrated PHYs for the user facing ports, and an extension interface which 9 * can be connected to the CPU - or another PHY - via either MII, RMII, or 10 * RGMII. The switch is configured via the Realtek Simple Management Interface 11 * (SMI), which uses the MDIO/MDC lines. 12 * 13 * Below is a simplified block diagram of the chip and its relevant interfaces. 14 * 15 * .-----------------------------------. 16 * | | 17 * UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC | 18 * UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC | 19 * UTP <---------------> Giga PHY <-> PCS <-> P2 GMAC | 20 * UTP <---------------> Giga PHY <-> PCS <-> P3 GMAC | 21 * | | 22 * CPU/PHY <-MII/RMII/RGMII---> Extension <---> Extension | 23 * | interface 1 GMAC 1 | 24 * | | 25 * SMI driver/ <-MDC/SCL---> Management ~~~~~~~~~~~~~~ | 26 * EEPROM <-MDIO/SDA--> interface ~REALTEK ~~~~~ | 27 * | ~RTL8365MB ~~~ | 28 * | ~GXXXC TAIWAN~ | 29 * GPIO <--------------> Reset ~~~~~~~~~~~~~~ | 30 * | | 31 * Interrupt <----------> Link UP/DOWN events | 32 * controller | | 33 * '-----------------------------------' 34 * 35 * The driver uses DSA to integrate the 4 user and 1 extension ports into the 36 * kernel. Netdevices are created for the user ports, as are PHY devices for 37 * their integrated PHYs. The device tree firmware should also specify the link 38 * partner of the extension port - either via a fixed-link or other phy-handle. 39 * See the device tree bindings for more detailed information. Note that the 40 * driver has only been tested with a fixed-link, but in principle it should not 41 * matter. 42 * 43 * NOTE: Currently, only the RGMII interface is implemented in this driver. 44 * 45 * The interrupt line is asserted on link UP/DOWN events. The driver creates a 46 * custom irqchip to handle this interrupt and demultiplex the events by reading 47 * the status registers via SMI. Interrupts are then propagated to the relevant 48 * PHY device. 49 * 50 * The EEPROM contains initial register values which the chip will read over I2C 51 * upon hardware reset. It is also possible to omit the EEPROM. In both cases, 52 * the driver will manually reprogram some registers using jam tables to reach 53 * an initial state defined by the vendor driver. 54 * 55 * This Linux driver is written based on an OS-agnostic vendor driver from 56 * Realtek. The reference GPL-licensed sources can be found in the OpenWrt 57 * source tree under the name rtl8367c. The vendor driver claims to support a 58 * number of similar switch controllers from Realtek, but the only hardware we 59 * have is the RTL8365MB-VC. Moreover, there does not seem to be any chip under 60 * the name RTL8367C. Although one wishes that the 'C' stood for some kind of 61 * common hardware revision, there exist examples of chips with the suffix -VC 62 * which are explicitly not supported by the rtl8367c driver and which instead 63 * require the rtl8367d vendor driver. With all this uncertainty, the driver has 64 * been modestly named rtl8365mb. Future implementors may wish to rename things 65 * accordingly. 66 * 67 * In the same family of chips, some carry up to 8 user ports and up to 2 68 * extension ports. Where possible this driver tries to make things generic, but 69 * more work must be done to support these configurations. According to 70 * documentation from Realtek, the family should include the following chips: 71 * 72 * - RTL8363NB 73 * - RTL8363NB-VB 74 * - RTL8363SC 75 * - RTL8363SC-VB 76 * - RTL8364NB 77 * - RTL8364NB-VB 78 * - RTL8365MB-VC 79 * - RTL8366SC 80 * - RTL8367RB-VB 81 * - RTL8367SB 82 * - RTL8367S 83 * - RTL8370MB 84 * - RTL8310SR 85 * 86 * Some of the register logic for these additional chips has been skipped over 87 * while implementing this driver. It is therefore not possible to assume that 88 * things will work out-of-the-box for other chips, and a careful review of the 89 * vendor driver may be needed to expand support. The RTL8365MB-VC seems to be 90 * one of the simpler chips. 91 */ 92 93 #include <linux/bitfield.h> 94 #include <linux/bitops.h> 95 #include <linux/interrupt.h> 96 #include <linux/irqdomain.h> 97 #include <linux/mutex.h> 98 #include <linux/of_irq.h> 99 #include <linux/regmap.h> 100 #include <linux/if_bridge.h> 101 102 #include "realtek.h" 103 104 /* Chip-specific data and limits */ 105 #define RTL8365MB_CHIP_ID_8365MB_VC 0x6367 106 #define RTL8365MB_CHIP_VER_8365MB_VC 0x0040 107 108 #define RTL8365MB_CHIP_ID_8367S 0x6367 109 #define RTL8365MB_CHIP_VER_8367S 0x00A0 110 111 #define RTL8365MB_CHIP_ID_8367RB 0x6367 112 #define RTL8365MB_CHIP_VER_8367RB 0x0020 113 114 /* Family-specific data and limits */ 115 #define RTL8365MB_PHYADDRMAX 7 116 #define RTL8365MB_NUM_PHYREGS 32 117 #define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1) 118 /* RTL8370MB and RTL8310SR, possibly suportable by this driver, have 10 ports */ 119 #define RTL8365MB_MAX_NUM_PORTS 10 120 #define RTL8365MB_LEARN_LIMIT_MAX 2112 121 122 /* valid for all 6-port or less variants */ 123 static const int rtl8365mb_extint_port_map[] = { -1, -1, -1, -1, -1, -1, 1, 2, -1, -1}; 124 125 /* Chip identification registers */ 126 #define RTL8365MB_CHIP_ID_REG 0x1300 127 128 #define RTL8365MB_CHIP_VER_REG 0x1301 129 130 #define RTL8365MB_MAGIC_REG 0x13C2 131 #define RTL8365MB_MAGIC_VALUE 0x0249 132 133 /* Chip reset register */ 134 #define RTL8365MB_CHIP_RESET_REG 0x1322 135 #define RTL8365MB_CHIP_RESET_SW_MASK 0x0002 136 #define RTL8365MB_CHIP_RESET_HW_MASK 0x0001 137 138 /* Interrupt polarity register */ 139 #define RTL8365MB_INTR_POLARITY_REG 0x1100 140 #define RTL8365MB_INTR_POLARITY_MASK 0x0001 141 #define RTL8365MB_INTR_POLARITY_HIGH 0 142 #define RTL8365MB_INTR_POLARITY_LOW 1 143 144 /* Interrupt control/status register - enable/check specific interrupt types */ 145 #define RTL8365MB_INTR_CTRL_REG 0x1101 146 #define RTL8365MB_INTR_STATUS_REG 0x1102 147 #define RTL8365MB_INTR_SLIENT_START_2_MASK 0x1000 148 #define RTL8365MB_INTR_SLIENT_START_MASK 0x0800 149 #define RTL8365MB_INTR_ACL_ACTION_MASK 0x0200 150 #define RTL8365MB_INTR_CABLE_DIAG_FIN_MASK 0x0100 151 #define RTL8365MB_INTR_INTERRUPT_8051_MASK 0x0080 152 #define RTL8365MB_INTR_LOOP_DETECTION_MASK 0x0040 153 #define RTL8365MB_INTR_GREEN_TIMER_MASK 0x0020 154 #define RTL8365MB_INTR_SPECIAL_CONGEST_MASK 0x0010 155 #define RTL8365MB_INTR_SPEED_CHANGE_MASK 0x0008 156 #define RTL8365MB_INTR_LEARN_OVER_MASK 0x0004 157 #define RTL8365MB_INTR_METER_EXCEEDED_MASK 0x0002 158 #define RTL8365MB_INTR_LINK_CHANGE_MASK 0x0001 159 #define RTL8365MB_INTR_ALL_MASK \ 160 (RTL8365MB_INTR_SLIENT_START_2_MASK | \ 161 RTL8365MB_INTR_SLIENT_START_MASK | \ 162 RTL8365MB_INTR_ACL_ACTION_MASK | \ 163 RTL8365MB_INTR_CABLE_DIAG_FIN_MASK | \ 164 RTL8365MB_INTR_INTERRUPT_8051_MASK | \ 165 RTL8365MB_INTR_LOOP_DETECTION_MASK | \ 166 RTL8365MB_INTR_GREEN_TIMER_MASK | \ 167 RTL8365MB_INTR_SPECIAL_CONGEST_MASK | \ 168 RTL8365MB_INTR_SPEED_CHANGE_MASK | \ 169 RTL8365MB_INTR_LEARN_OVER_MASK | \ 170 RTL8365MB_INTR_METER_EXCEEDED_MASK | \ 171 RTL8365MB_INTR_LINK_CHANGE_MASK) 172 173 /* Per-port interrupt type status registers */ 174 #define RTL8365MB_PORT_LINKDOWN_IND_REG 0x1106 175 #define RTL8365MB_PORT_LINKDOWN_IND_MASK 0x07FF 176 177 #define RTL8365MB_PORT_LINKUP_IND_REG 0x1107 178 #define RTL8365MB_PORT_LINKUP_IND_MASK 0x07FF 179 180 /* PHY indirect access registers */ 181 #define RTL8365MB_INDIRECT_ACCESS_CTRL_REG 0x1F00 182 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK 0x0002 183 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ 0 184 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE 1 185 #define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK 0x0001 186 #define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE 1 187 #define RTL8365MB_INDIRECT_ACCESS_STATUS_REG 0x1F01 188 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG 0x1F02 189 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK GENMASK(4, 0) 190 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK GENMASK(7, 5) 191 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK GENMASK(11, 8) 192 #define RTL8365MB_PHY_BASE 0x2000 193 #define RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG 0x1F03 194 #define RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG 0x1F04 195 196 /* PHY OCP address prefix register */ 197 #define RTL8365MB_GPHY_OCP_MSB_0_REG 0x1D15 198 #define RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK 0x0FC0 199 #define RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK 0xFC00 200 201 /* The PHY OCP addresses of PHY registers 0~31 start here */ 202 #define RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE 0xA400 203 204 /* EXT interface port mode values - used in DIGITAL_INTERFACE_SELECT */ 205 #define RTL8365MB_EXT_PORT_MODE_DISABLE 0 206 #define RTL8365MB_EXT_PORT_MODE_RGMII 1 207 #define RTL8365MB_EXT_PORT_MODE_MII_MAC 2 208 #define RTL8365MB_EXT_PORT_MODE_MII_PHY 3 209 #define RTL8365MB_EXT_PORT_MODE_TMII_MAC 4 210 #define RTL8365MB_EXT_PORT_MODE_TMII_PHY 5 211 #define RTL8365MB_EXT_PORT_MODE_GMII 6 212 #define RTL8365MB_EXT_PORT_MODE_RMII_MAC 7 213 #define RTL8365MB_EXT_PORT_MODE_RMII_PHY 8 214 #define RTL8365MB_EXT_PORT_MODE_SGMII 9 215 #define RTL8365MB_EXT_PORT_MODE_HSGMII 10 216 #define RTL8365MB_EXT_PORT_MODE_1000X_100FX 11 217 #define RTL8365MB_EXT_PORT_MODE_1000X 12 218 #define RTL8365MB_EXT_PORT_MODE_100FX 13 219 220 /* Realtek docs and driver uses logic number as EXT_PORT0=16, EXT_PORT1=17, 221 * EXT_PORT2=18, to interact with switch ports. That logic number is internally 222 * converted to either a physical port number (0..9) or an external interface id (0..2), 223 * depending on which function was called. The external interface id is calculated as 224 * (ext_id=logic_port-15), while the logical to physical map depends on the chip id/version. 225 * 226 * EXT_PORT0 mentioned in datasheets and rtl8367c driver is used in this driver 227 * as extid==1, EXT_PORT2, mentioned in Realtek rtl8367c driver for 10-port switches, 228 * would have an ext_id of 3 (out of range for most extint macros) and ext_id 0 does 229 * not seem to be used as well for this family. 230 */ 231 232 /* EXT interface mode configuration registers 0~1 */ 233 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 0x1305 /* EXT1 */ 234 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 0x13C3 /* EXT2 */ 235 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(_extint) \ 236 ((_extint) == 1 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 : \ 237 (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 : \ 238 0x0) 239 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(_extint) \ 240 (0xF << (((_extint) % 2))) 241 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(_extint) \ 242 (((_extint) % 2) * 4) 243 244 /* EXT interface RGMII TX/RX delay configuration registers 0~2 */ 245 #define RTL8365MB_EXT_RGMXF_REG0 0x1306 /* EXT0 */ 246 #define RTL8365MB_EXT_RGMXF_REG1 0x1307 /* EXT1 */ 247 #define RTL8365MB_EXT_RGMXF_REG2 0x13C5 /* EXT2 */ 248 #define RTL8365MB_EXT_RGMXF_REG(_extint) \ 249 ((_extint) == 0 ? RTL8365MB_EXT_RGMXF_REG0 : \ 250 (_extint) == 1 ? RTL8365MB_EXT_RGMXF_REG1 : \ 251 (_extint) == 2 ? RTL8365MB_EXT_RGMXF_REG2 : \ 252 0x0) 253 #define RTL8365MB_EXT_RGMXF_RXDELAY_MASK 0x0007 254 #define RTL8365MB_EXT_RGMXF_TXDELAY_MASK 0x0008 255 256 /* External interface port speed values - used in DIGITAL_INTERFACE_FORCE */ 257 #define RTL8365MB_PORT_SPEED_10M 0 258 #define RTL8365MB_PORT_SPEED_100M 1 259 #define RTL8365MB_PORT_SPEED_1000M 2 260 261 /* EXT interface force configuration registers 0~2 */ 262 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 0x1310 /* EXT0 */ 263 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 0x1311 /* EXT1 */ 264 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 0x13C4 /* EXT2 */ 265 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(_extint) \ 266 ((_extint) == 0 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 : \ 267 (_extint) == 1 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 : \ 268 (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 : \ 269 0x0) 270 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK 0x1000 271 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_NWAY_MASK 0x0080 272 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK 0x0040 273 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK 0x0020 274 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK 0x0010 275 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK 0x0004 276 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK 0x0003 277 278 /* CPU port mask register - controls which ports are treated as CPU ports */ 279 #define RTL8365MB_CPU_PORT_MASK_REG 0x1219 280 #define RTL8365MB_CPU_PORT_MASK_MASK 0x07FF 281 282 /* CPU control register */ 283 #define RTL8365MB_CPU_CTRL_REG 0x121A 284 #define RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK 0x0400 285 #define RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK 0x0200 286 #define RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK 0x0080 287 #define RTL8365MB_CPU_CTRL_TAG_POSITION_MASK 0x0040 288 #define RTL8365MB_CPU_CTRL_TRAP_PORT_MASK 0x0038 289 #define RTL8365MB_CPU_CTRL_INSERTMODE_MASK 0x0006 290 #define RTL8365MB_CPU_CTRL_EN_MASK 0x0001 291 292 /* Maximum packet length register */ 293 #define RTL8365MB_CFG0_MAX_LEN_REG 0x088C 294 #define RTL8365MB_CFG0_MAX_LEN_MASK 0x3FFF 295 296 /* Port learning limit registers */ 297 #define RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE 0x0A20 298 #define RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(_physport) \ 299 (RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE + (_physport)) 300 301 /* Port isolation (forwarding mask) registers */ 302 #define RTL8365MB_PORT_ISOLATION_REG_BASE 0x08A2 303 #define RTL8365MB_PORT_ISOLATION_REG(_physport) \ 304 (RTL8365MB_PORT_ISOLATION_REG_BASE + (_physport)) 305 #define RTL8365MB_PORT_ISOLATION_MASK 0x07FF 306 307 /* MSTP port state registers - indexed by tree instance */ 308 #define RTL8365MB_MSTI_CTRL_BASE 0x0A00 309 #define RTL8365MB_MSTI_CTRL_REG(_msti, _physport) \ 310 (RTL8365MB_MSTI_CTRL_BASE + ((_msti) << 1) + ((_physport) >> 3)) 311 #define RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(_physport) ((_physport) << 1) 312 #define RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(_physport) \ 313 (0x3 << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET((_physport))) 314 315 /* MIB counter value registers */ 316 #define RTL8365MB_MIB_COUNTER_BASE 0x1000 317 #define RTL8365MB_MIB_COUNTER_REG(_x) (RTL8365MB_MIB_COUNTER_BASE + (_x)) 318 319 /* MIB counter address register */ 320 #define RTL8365MB_MIB_ADDRESS_REG 0x1004 321 #define RTL8365MB_MIB_ADDRESS_PORT_OFFSET 0x007C 322 #define RTL8365MB_MIB_ADDRESS(_p, _x) \ 323 (((RTL8365MB_MIB_ADDRESS_PORT_OFFSET) * (_p) + (_x)) >> 2) 324 325 #define RTL8365MB_MIB_CTRL0_REG 0x1005 326 #define RTL8365MB_MIB_CTRL0_RESET_MASK 0x0002 327 #define RTL8365MB_MIB_CTRL0_BUSY_MASK 0x0001 328 329 /* The DSA callback .get_stats64 runs in atomic context, so we are not allowed 330 * to block. On the other hand, accessing MIB counters absolutely requires us to 331 * block. The solution is thus to schedule work which polls the MIB counters 332 * asynchronously and updates some private data, which the callback can then 333 * fetch atomically. Three seconds should be a good enough polling interval. 334 */ 335 #define RTL8365MB_STATS_INTERVAL_JIFFIES (3 * HZ) 336 337 enum rtl8365mb_mib_counter_index { 338 RTL8365MB_MIB_ifInOctets, 339 RTL8365MB_MIB_dot3StatsFCSErrors, 340 RTL8365MB_MIB_dot3StatsSymbolErrors, 341 RTL8365MB_MIB_dot3InPauseFrames, 342 RTL8365MB_MIB_dot3ControlInUnknownOpcodes, 343 RTL8365MB_MIB_etherStatsFragments, 344 RTL8365MB_MIB_etherStatsJabbers, 345 RTL8365MB_MIB_ifInUcastPkts, 346 RTL8365MB_MIB_etherStatsDropEvents, 347 RTL8365MB_MIB_ifInMulticastPkts, 348 RTL8365MB_MIB_ifInBroadcastPkts, 349 RTL8365MB_MIB_inMldChecksumError, 350 RTL8365MB_MIB_inIgmpChecksumError, 351 RTL8365MB_MIB_inMldSpecificQuery, 352 RTL8365MB_MIB_inMldGeneralQuery, 353 RTL8365MB_MIB_inIgmpSpecificQuery, 354 RTL8365MB_MIB_inIgmpGeneralQuery, 355 RTL8365MB_MIB_inMldLeaves, 356 RTL8365MB_MIB_inIgmpLeaves, 357 RTL8365MB_MIB_etherStatsOctets, 358 RTL8365MB_MIB_etherStatsUnderSizePkts, 359 RTL8365MB_MIB_etherOversizeStats, 360 RTL8365MB_MIB_etherStatsPkts64Octets, 361 RTL8365MB_MIB_etherStatsPkts65to127Octets, 362 RTL8365MB_MIB_etherStatsPkts128to255Octets, 363 RTL8365MB_MIB_etherStatsPkts256to511Octets, 364 RTL8365MB_MIB_etherStatsPkts512to1023Octets, 365 RTL8365MB_MIB_etherStatsPkts1024to1518Octets, 366 RTL8365MB_MIB_ifOutOctets, 367 RTL8365MB_MIB_dot3StatsSingleCollisionFrames, 368 RTL8365MB_MIB_dot3StatsMultipleCollisionFrames, 369 RTL8365MB_MIB_dot3StatsDeferredTransmissions, 370 RTL8365MB_MIB_dot3StatsLateCollisions, 371 RTL8365MB_MIB_etherStatsCollisions, 372 RTL8365MB_MIB_dot3StatsExcessiveCollisions, 373 RTL8365MB_MIB_dot3OutPauseFrames, 374 RTL8365MB_MIB_ifOutDiscards, 375 RTL8365MB_MIB_dot1dTpPortInDiscards, 376 RTL8365MB_MIB_ifOutUcastPkts, 377 RTL8365MB_MIB_ifOutMulticastPkts, 378 RTL8365MB_MIB_ifOutBroadcastPkts, 379 RTL8365MB_MIB_outOampduPkts, 380 RTL8365MB_MIB_inOampduPkts, 381 RTL8365MB_MIB_inIgmpJoinsSuccess, 382 RTL8365MB_MIB_inIgmpJoinsFail, 383 RTL8365MB_MIB_inMldJoinsSuccess, 384 RTL8365MB_MIB_inMldJoinsFail, 385 RTL8365MB_MIB_inReportSuppressionDrop, 386 RTL8365MB_MIB_inLeaveSuppressionDrop, 387 RTL8365MB_MIB_outIgmpReports, 388 RTL8365MB_MIB_outIgmpLeaves, 389 RTL8365MB_MIB_outIgmpGeneralQuery, 390 RTL8365MB_MIB_outIgmpSpecificQuery, 391 RTL8365MB_MIB_outMldReports, 392 RTL8365MB_MIB_outMldLeaves, 393 RTL8365MB_MIB_outMldGeneralQuery, 394 RTL8365MB_MIB_outMldSpecificQuery, 395 RTL8365MB_MIB_inKnownMulticastPkts, 396 RTL8365MB_MIB_END, 397 }; 398 399 struct rtl8365mb_mib_counter { 400 u32 offset; 401 u32 length; 402 const char *name; 403 }; 404 405 #define RTL8365MB_MAKE_MIB_COUNTER(_offset, _length, _name) \ 406 [RTL8365MB_MIB_ ## _name] = { _offset, _length, #_name } 407 408 static struct rtl8365mb_mib_counter rtl8365mb_mib_counters[] = { 409 RTL8365MB_MAKE_MIB_COUNTER(0, 4, ifInOctets), 410 RTL8365MB_MAKE_MIB_COUNTER(4, 2, dot3StatsFCSErrors), 411 RTL8365MB_MAKE_MIB_COUNTER(6, 2, dot3StatsSymbolErrors), 412 RTL8365MB_MAKE_MIB_COUNTER(8, 2, dot3InPauseFrames), 413 RTL8365MB_MAKE_MIB_COUNTER(10, 2, dot3ControlInUnknownOpcodes), 414 RTL8365MB_MAKE_MIB_COUNTER(12, 2, etherStatsFragments), 415 RTL8365MB_MAKE_MIB_COUNTER(14, 2, etherStatsJabbers), 416 RTL8365MB_MAKE_MIB_COUNTER(16, 2, ifInUcastPkts), 417 RTL8365MB_MAKE_MIB_COUNTER(18, 2, etherStatsDropEvents), 418 RTL8365MB_MAKE_MIB_COUNTER(20, 2, ifInMulticastPkts), 419 RTL8365MB_MAKE_MIB_COUNTER(22, 2, ifInBroadcastPkts), 420 RTL8365MB_MAKE_MIB_COUNTER(24, 2, inMldChecksumError), 421 RTL8365MB_MAKE_MIB_COUNTER(26, 2, inIgmpChecksumError), 422 RTL8365MB_MAKE_MIB_COUNTER(28, 2, inMldSpecificQuery), 423 RTL8365MB_MAKE_MIB_COUNTER(30, 2, inMldGeneralQuery), 424 RTL8365MB_MAKE_MIB_COUNTER(32, 2, inIgmpSpecificQuery), 425 RTL8365MB_MAKE_MIB_COUNTER(34, 2, inIgmpGeneralQuery), 426 RTL8365MB_MAKE_MIB_COUNTER(36, 2, inMldLeaves), 427 RTL8365MB_MAKE_MIB_COUNTER(38, 2, inIgmpLeaves), 428 RTL8365MB_MAKE_MIB_COUNTER(40, 4, etherStatsOctets), 429 RTL8365MB_MAKE_MIB_COUNTER(44, 2, etherStatsUnderSizePkts), 430 RTL8365MB_MAKE_MIB_COUNTER(46, 2, etherOversizeStats), 431 RTL8365MB_MAKE_MIB_COUNTER(48, 2, etherStatsPkts64Octets), 432 RTL8365MB_MAKE_MIB_COUNTER(50, 2, etherStatsPkts65to127Octets), 433 RTL8365MB_MAKE_MIB_COUNTER(52, 2, etherStatsPkts128to255Octets), 434 RTL8365MB_MAKE_MIB_COUNTER(54, 2, etherStatsPkts256to511Octets), 435 RTL8365MB_MAKE_MIB_COUNTER(56, 2, etherStatsPkts512to1023Octets), 436 RTL8365MB_MAKE_MIB_COUNTER(58, 2, etherStatsPkts1024to1518Octets), 437 RTL8365MB_MAKE_MIB_COUNTER(60, 4, ifOutOctets), 438 RTL8365MB_MAKE_MIB_COUNTER(64, 2, dot3StatsSingleCollisionFrames), 439 RTL8365MB_MAKE_MIB_COUNTER(66, 2, dot3StatsMultipleCollisionFrames), 440 RTL8365MB_MAKE_MIB_COUNTER(68, 2, dot3StatsDeferredTransmissions), 441 RTL8365MB_MAKE_MIB_COUNTER(70, 2, dot3StatsLateCollisions), 442 RTL8365MB_MAKE_MIB_COUNTER(72, 2, etherStatsCollisions), 443 RTL8365MB_MAKE_MIB_COUNTER(74, 2, dot3StatsExcessiveCollisions), 444 RTL8365MB_MAKE_MIB_COUNTER(76, 2, dot3OutPauseFrames), 445 RTL8365MB_MAKE_MIB_COUNTER(78, 2, ifOutDiscards), 446 RTL8365MB_MAKE_MIB_COUNTER(80, 2, dot1dTpPortInDiscards), 447 RTL8365MB_MAKE_MIB_COUNTER(82, 2, ifOutUcastPkts), 448 RTL8365MB_MAKE_MIB_COUNTER(84, 2, ifOutMulticastPkts), 449 RTL8365MB_MAKE_MIB_COUNTER(86, 2, ifOutBroadcastPkts), 450 RTL8365MB_MAKE_MIB_COUNTER(88, 2, outOampduPkts), 451 RTL8365MB_MAKE_MIB_COUNTER(90, 2, inOampduPkts), 452 RTL8365MB_MAKE_MIB_COUNTER(92, 4, inIgmpJoinsSuccess), 453 RTL8365MB_MAKE_MIB_COUNTER(96, 2, inIgmpJoinsFail), 454 RTL8365MB_MAKE_MIB_COUNTER(98, 2, inMldJoinsSuccess), 455 RTL8365MB_MAKE_MIB_COUNTER(100, 2, inMldJoinsFail), 456 RTL8365MB_MAKE_MIB_COUNTER(102, 2, inReportSuppressionDrop), 457 RTL8365MB_MAKE_MIB_COUNTER(104, 2, inLeaveSuppressionDrop), 458 RTL8365MB_MAKE_MIB_COUNTER(106, 2, outIgmpReports), 459 RTL8365MB_MAKE_MIB_COUNTER(108, 2, outIgmpLeaves), 460 RTL8365MB_MAKE_MIB_COUNTER(110, 2, outIgmpGeneralQuery), 461 RTL8365MB_MAKE_MIB_COUNTER(112, 2, outIgmpSpecificQuery), 462 RTL8365MB_MAKE_MIB_COUNTER(114, 2, outMldReports), 463 RTL8365MB_MAKE_MIB_COUNTER(116, 2, outMldLeaves), 464 RTL8365MB_MAKE_MIB_COUNTER(118, 2, outMldGeneralQuery), 465 RTL8365MB_MAKE_MIB_COUNTER(120, 2, outMldSpecificQuery), 466 RTL8365MB_MAKE_MIB_COUNTER(122, 2, inKnownMulticastPkts), 467 }; 468 469 static_assert(ARRAY_SIZE(rtl8365mb_mib_counters) == RTL8365MB_MIB_END); 470 471 struct rtl8365mb_jam_tbl_entry { 472 u16 reg; 473 u16 val; 474 }; 475 476 /* Lifted from the vendor driver sources */ 477 static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_8365mb_vc[] = { 478 { 0x13EB, 0x15BB }, { 0x1303, 0x06D6 }, { 0x1304, 0x0700 }, 479 { 0x13E2, 0x003F }, { 0x13F9, 0x0090 }, { 0x121E, 0x03CA }, 480 { 0x1233, 0x0352 }, { 0x1237, 0x00A0 }, { 0x123A, 0x0030 }, 481 { 0x1239, 0x0084 }, { 0x0301, 0x1000 }, { 0x1349, 0x001F }, 482 { 0x18E0, 0x4004 }, { 0x122B, 0x241C }, { 0x1305, 0xC000 }, 483 { 0x13F0, 0x0000 }, 484 }; 485 486 static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_common[] = { 487 { 0x1200, 0x7FCB }, { 0x0884, 0x0003 }, { 0x06EB, 0x0001 }, 488 { 0x03Fa, 0x0007 }, { 0x08C8, 0x00C0 }, { 0x0A30, 0x020E }, 489 { 0x0800, 0x0000 }, { 0x0802, 0x0000 }, { 0x09DA, 0x0013 }, 490 { 0x1D32, 0x0002 }, 491 }; 492 493 enum rtl8365mb_stp_state { 494 RTL8365MB_STP_STATE_DISABLED = 0, 495 RTL8365MB_STP_STATE_BLOCKING = 1, 496 RTL8365MB_STP_STATE_LEARNING = 2, 497 RTL8365MB_STP_STATE_FORWARDING = 3, 498 }; 499 500 enum rtl8365mb_cpu_insert { 501 RTL8365MB_CPU_INSERT_TO_ALL = 0, 502 RTL8365MB_CPU_INSERT_TO_TRAPPING = 1, 503 RTL8365MB_CPU_INSERT_TO_NONE = 2, 504 }; 505 506 enum rtl8365mb_cpu_position { 507 RTL8365MB_CPU_POS_AFTER_SA = 0, 508 RTL8365MB_CPU_POS_BEFORE_CRC = 1, 509 }; 510 511 enum rtl8365mb_cpu_format { 512 RTL8365MB_CPU_FORMAT_8BYTES = 0, 513 RTL8365MB_CPU_FORMAT_4BYTES = 1, 514 }; 515 516 enum rtl8365mb_cpu_rxlen { 517 RTL8365MB_CPU_RXLEN_72BYTES = 0, 518 RTL8365MB_CPU_RXLEN_64BYTES = 1, 519 }; 520 521 /** 522 * struct rtl8365mb_cpu - CPU port configuration 523 * @enable: enable/disable hardware insertion of CPU tag in switch->CPU frames 524 * @mask: port mask of ports that parse should parse CPU tags 525 * @trap_port: forward trapped frames to this port 526 * @insert: CPU tag insertion mode in switch->CPU frames 527 * @position: position of CPU tag in frame 528 * @rx_length: minimum CPU RX length 529 * @format: CPU tag format 530 * 531 * Represents the CPU tagging and CPU port configuration of the switch. These 532 * settings are configurable at runtime. 533 */ 534 struct rtl8365mb_cpu { 535 bool enable; 536 u32 mask; 537 u32 trap_port; 538 enum rtl8365mb_cpu_insert insert; 539 enum rtl8365mb_cpu_position position; 540 enum rtl8365mb_cpu_rxlen rx_length; 541 enum rtl8365mb_cpu_format format; 542 }; 543 544 /** 545 * struct rtl8365mb_port - private per-port data 546 * @priv: pointer to parent realtek_priv data 547 * @index: DSA port index, same as dsa_port::index 548 * @stats: link statistics populated by rtl8365mb_stats_poll, ready for atomic 549 * access via rtl8365mb_get_stats64 550 * @stats_lock: protect the stats structure during read/update 551 * @mib_work: delayed work for polling MIB counters 552 */ 553 struct rtl8365mb_port { 554 struct realtek_priv *priv; 555 unsigned int index; 556 struct rtnl_link_stats64 stats; 557 spinlock_t stats_lock; 558 struct delayed_work mib_work; 559 }; 560 561 /** 562 * struct rtl8365mb - private chip-specific driver data 563 * @priv: pointer to parent realtek_priv data 564 * @irq: registered IRQ or zero 565 * @chip_id: chip identifier 566 * @chip_ver: chip silicon revision 567 * @port_mask: mask of all ports 568 * @learn_limit_max: maximum number of L2 addresses the chip can learn 569 * @mib_lock: prevent concurrent reads of MIB counters 570 * @ports: per-port data 571 * @jam_table: chip-specific initialization jam table 572 * @jam_size: size of the chip's jam table 573 * 574 * Private data for this driver. 575 */ 576 struct rtl8365mb { 577 struct realtek_priv *priv; 578 int irq; 579 u32 chip_id; 580 u32 chip_ver; 581 u32 port_mask; 582 u32 learn_limit_max; 583 struct mutex mib_lock; 584 struct rtl8365mb_port ports[RTL8365MB_MAX_NUM_PORTS]; 585 const struct rtl8365mb_jam_tbl_entry *jam_table; 586 size_t jam_size; 587 }; 588 589 static int rtl8365mb_phy_poll_busy(struct realtek_priv *priv) 590 { 591 u32 val; 592 593 return regmap_read_poll_timeout(priv->map, 594 RTL8365MB_INDIRECT_ACCESS_STATUS_REG, 595 val, !val, 10, 100); 596 } 597 598 static int rtl8365mb_phy_ocp_prepare(struct realtek_priv *priv, int phy, 599 u32 ocp_addr) 600 { 601 u32 val; 602 int ret; 603 604 /* Set OCP prefix */ 605 val = FIELD_GET(RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK, ocp_addr); 606 ret = regmap_update_bits( 607 priv->map, RTL8365MB_GPHY_OCP_MSB_0_REG, 608 RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, 609 FIELD_PREP(RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, val)); 610 if (ret) 611 return ret; 612 613 /* Set PHY register address */ 614 val = RTL8365MB_PHY_BASE; 615 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK, phy); 616 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK, 617 ocp_addr >> 1); 618 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK, 619 ocp_addr >> 6); 620 ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG, 621 val); 622 if (ret) 623 return ret; 624 625 return 0; 626 } 627 628 static int rtl8365mb_phy_ocp_read(struct realtek_priv *priv, int phy, 629 u32 ocp_addr, u16 *data) 630 { 631 u32 val; 632 int ret; 633 634 ret = rtl8365mb_phy_poll_busy(priv); 635 if (ret) 636 return ret; 637 638 ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr); 639 if (ret) 640 return ret; 641 642 /* Execute read operation */ 643 val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK, 644 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) | 645 FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK, 646 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ); 647 ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, val); 648 if (ret) 649 return ret; 650 651 ret = rtl8365mb_phy_poll_busy(priv); 652 if (ret) 653 return ret; 654 655 /* Get PHY register data */ 656 ret = regmap_read(priv->map, RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, 657 &val); 658 if (ret) 659 return ret; 660 661 *data = val & 0xFFFF; 662 663 return 0; 664 } 665 666 static int rtl8365mb_phy_ocp_write(struct realtek_priv *priv, int phy, 667 u32 ocp_addr, u16 data) 668 { 669 u32 val; 670 int ret; 671 672 ret = rtl8365mb_phy_poll_busy(priv); 673 if (ret) 674 return ret; 675 676 ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr); 677 if (ret) 678 return ret; 679 680 /* Set PHY register data */ 681 ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG, 682 data); 683 if (ret) 684 return ret; 685 686 /* Execute write operation */ 687 val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK, 688 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) | 689 FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK, 690 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE); 691 ret = regmap_write(priv->map, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, val); 692 if (ret) 693 return ret; 694 695 ret = rtl8365mb_phy_poll_busy(priv); 696 if (ret) 697 return ret; 698 699 return 0; 700 } 701 702 static int rtl8365mb_phy_read(struct realtek_priv *priv, int phy, int regnum) 703 { 704 u32 ocp_addr; 705 u16 val; 706 int ret; 707 708 if (phy > RTL8365MB_PHYADDRMAX) 709 return -EINVAL; 710 711 if (regnum > RTL8365MB_PHYREGMAX) 712 return -EINVAL; 713 714 ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; 715 716 ret = rtl8365mb_phy_ocp_read(priv, phy, ocp_addr, &val); 717 if (ret) { 718 dev_err(priv->dev, 719 "failed to read PHY%d reg %02x @ %04x, ret %d\n", phy, 720 regnum, ocp_addr, ret); 721 return ret; 722 } 723 724 dev_dbg(priv->dev, "read PHY%d register 0x%02x @ %04x, val <- %04x\n", 725 phy, regnum, ocp_addr, val); 726 727 return val; 728 } 729 730 static int rtl8365mb_phy_write(struct realtek_priv *priv, int phy, int regnum, 731 u16 val) 732 { 733 u32 ocp_addr; 734 int ret; 735 736 if (phy > RTL8365MB_PHYADDRMAX) 737 return -EINVAL; 738 739 if (regnum > RTL8365MB_PHYREGMAX) 740 return -EINVAL; 741 742 ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; 743 744 ret = rtl8365mb_phy_ocp_write(priv, phy, ocp_addr, val); 745 if (ret) { 746 dev_err(priv->dev, 747 "failed to write PHY%d reg %02x @ %04x, ret %d\n", phy, 748 regnum, ocp_addr, ret); 749 return ret; 750 } 751 752 dev_dbg(priv->dev, "write PHY%d register 0x%02x @ %04x, val -> %04x\n", 753 phy, regnum, ocp_addr, val); 754 755 return 0; 756 } 757 758 static int rtl8365mb_dsa_phy_read(struct dsa_switch *ds, int phy, int regnum) 759 { 760 return rtl8365mb_phy_read(ds->priv, phy, regnum); 761 } 762 763 static int rtl8365mb_dsa_phy_write(struct dsa_switch *ds, int phy, int regnum, 764 u16 val) 765 { 766 return rtl8365mb_phy_write(ds->priv, phy, regnum, val); 767 } 768 769 static enum dsa_tag_protocol 770 rtl8365mb_get_tag_protocol(struct dsa_switch *ds, int port, 771 enum dsa_tag_protocol mp) 772 { 773 return DSA_TAG_PROTO_RTL8_4; 774 } 775 776 static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, 777 phy_interface_t interface) 778 { 779 struct device_node *dn; 780 struct dsa_port *dp; 781 int tx_delay = 0; 782 int rx_delay = 0; 783 int ext_int; 784 u32 val; 785 int ret; 786 787 ext_int = rtl8365mb_extint_port_map[port]; 788 789 if (ext_int <= 0) { 790 dev_err(priv->dev, "Port %d is not an external interface port\n", port); 791 return -EINVAL; 792 } 793 794 dp = dsa_to_port(priv->ds, port); 795 dn = dp->dn; 796 797 /* Set the RGMII TX/RX delay 798 * 799 * The Realtek vendor driver indicates the following possible 800 * configuration settings: 801 * 802 * TX delay: 803 * 0 = no delay, 1 = 2 ns delay 804 * RX delay: 805 * 0 = no delay, 7 = maximum delay 806 * Each step is approximately 0.3 ns, so the maximum delay is about 807 * 2.1 ns. 808 * 809 * The vendor driver also states that this must be configured *before* 810 * forcing the external interface into a particular mode, which is done 811 * in the rtl8365mb_phylink_mac_link_{up,down} functions. 812 * 813 * Only configure an RGMII TX (resp. RX) delay if the 814 * tx-internal-delay-ps (resp. rx-internal-delay-ps) OF property is 815 * specified. We ignore the detail of the RGMII interface mode 816 * (RGMII_{RXID, TXID, etc.}), as this is considered to be a PHY-only 817 * property. 818 */ 819 if (!of_property_read_u32(dn, "tx-internal-delay-ps", &val)) { 820 val = val / 1000; /* convert to ns */ 821 822 if (val == 0 || val == 2) 823 tx_delay = val / 2; 824 else 825 dev_warn(priv->dev, 826 "EXT interface TX delay must be 0 or 2 ns\n"); 827 } 828 829 if (!of_property_read_u32(dn, "rx-internal-delay-ps", &val)) { 830 val = DIV_ROUND_CLOSEST(val, 300); /* convert to 0.3 ns step */ 831 832 if (val <= 7) 833 rx_delay = val; 834 else 835 dev_warn(priv->dev, 836 "EXT interface RX delay must be 0 to 2.1 ns\n"); 837 } 838 839 ret = regmap_update_bits( 840 priv->map, RTL8365MB_EXT_RGMXF_REG(ext_int), 841 RTL8365MB_EXT_RGMXF_TXDELAY_MASK | 842 RTL8365MB_EXT_RGMXF_RXDELAY_MASK, 843 FIELD_PREP(RTL8365MB_EXT_RGMXF_TXDELAY_MASK, tx_delay) | 844 FIELD_PREP(RTL8365MB_EXT_RGMXF_RXDELAY_MASK, rx_delay)); 845 if (ret) 846 return ret; 847 848 ret = regmap_update_bits( 849 priv->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(ext_int), 850 RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(ext_int), 851 RTL8365MB_EXT_PORT_MODE_RGMII 852 << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET( 853 ext_int)); 854 if (ret) 855 return ret; 856 857 return 0; 858 } 859 860 static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, 861 bool link, int speed, int duplex, 862 bool tx_pause, bool rx_pause) 863 { 864 u32 r_tx_pause; 865 u32 r_rx_pause; 866 u32 r_duplex; 867 u32 r_speed; 868 u32 r_link; 869 int ext_int; 870 int val; 871 int ret; 872 873 ext_int = rtl8365mb_extint_port_map[port]; 874 875 if (ext_int <= 0) { 876 dev_err(priv->dev, "Port %d is not an external interface port\n", port); 877 return -EINVAL; 878 } 879 880 if (link) { 881 /* Force the link up with the desired configuration */ 882 r_link = 1; 883 r_rx_pause = rx_pause ? 1 : 0; 884 r_tx_pause = tx_pause ? 1 : 0; 885 886 if (speed == SPEED_1000) { 887 r_speed = RTL8365MB_PORT_SPEED_1000M; 888 } else if (speed == SPEED_100) { 889 r_speed = RTL8365MB_PORT_SPEED_100M; 890 } else if (speed == SPEED_10) { 891 r_speed = RTL8365MB_PORT_SPEED_10M; 892 } else { 893 dev_err(priv->dev, "unsupported port speed %s\n", 894 phy_speed_to_str(speed)); 895 return -EINVAL; 896 } 897 898 if (duplex == DUPLEX_FULL) { 899 r_duplex = 1; 900 } else if (duplex == DUPLEX_HALF) { 901 r_duplex = 0; 902 } else { 903 dev_err(priv->dev, "unsupported duplex %s\n", 904 phy_duplex_to_str(duplex)); 905 return -EINVAL; 906 } 907 } else { 908 /* Force the link down and reset any programmed configuration */ 909 r_link = 0; 910 r_tx_pause = 0; 911 r_rx_pause = 0; 912 r_speed = 0; 913 r_duplex = 0; 914 } 915 916 val = FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK, 1) | 917 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK, 918 r_tx_pause) | 919 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK, 920 r_rx_pause) | 921 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK, r_link) | 922 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK, 923 r_duplex) | 924 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK, r_speed); 925 ret = regmap_write(priv->map, 926 RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(ext_int), 927 val); 928 if (ret) 929 return ret; 930 931 return 0; 932 } 933 934 static bool rtl8365mb_phy_mode_supported(struct dsa_switch *ds, int port, 935 phy_interface_t interface) 936 { 937 int ext_int; 938 939 ext_int = rtl8365mb_extint_port_map[port]; 940 941 if (ext_int < 0 && 942 (interface == PHY_INTERFACE_MODE_NA || 943 interface == PHY_INTERFACE_MODE_INTERNAL || 944 interface == PHY_INTERFACE_MODE_GMII)) 945 /* Internal PHY */ 946 return true; 947 else if ((ext_int >= 1) && 948 phy_interface_mode_is_rgmii(interface)) 949 /* Extension MAC */ 950 return true; 951 952 return false; 953 } 954 955 static void rtl8365mb_phylink_validate(struct dsa_switch *ds, int port, 956 unsigned long *supported, 957 struct phylink_link_state *state) 958 { 959 struct realtek_priv *priv = ds->priv; 960 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0 }; 961 962 /* include/linux/phylink.h says: 963 * When @state->interface is %PHY_INTERFACE_MODE_NA, phylink 964 * expects the MAC driver to return all supported link modes. 965 */ 966 if (state->interface != PHY_INTERFACE_MODE_NA && 967 !rtl8365mb_phy_mode_supported(ds, port, state->interface)) { 968 dev_err(priv->dev, "phy mode %s is unsupported on port %d\n", 969 phy_modes(state->interface), port); 970 linkmode_zero(supported); 971 return; 972 } 973 974 phylink_set_port_modes(mask); 975 976 phylink_set(mask, Autoneg); 977 phylink_set(mask, Pause); 978 phylink_set(mask, Asym_Pause); 979 980 phylink_set(mask, 10baseT_Half); 981 phylink_set(mask, 10baseT_Full); 982 phylink_set(mask, 100baseT_Half); 983 phylink_set(mask, 100baseT_Full); 984 phylink_set(mask, 1000baseT_Full); 985 986 linkmode_and(supported, supported, mask); 987 linkmode_and(state->advertising, state->advertising, mask); 988 } 989 990 static void rtl8365mb_phylink_mac_config(struct dsa_switch *ds, int port, 991 unsigned int mode, 992 const struct phylink_link_state *state) 993 { 994 struct realtek_priv *priv = ds->priv; 995 int ret; 996 997 if (!rtl8365mb_phy_mode_supported(ds, port, state->interface)) { 998 dev_err(priv->dev, "phy mode %s is unsupported on port %d\n", 999 phy_modes(state->interface), port); 1000 return; 1001 } 1002 1003 if (mode != MLO_AN_PHY && mode != MLO_AN_FIXED) { 1004 dev_err(priv->dev, 1005 "port %d supports only conventional PHY or fixed-link\n", 1006 port); 1007 return; 1008 } 1009 1010 if (phy_interface_mode_is_rgmii(state->interface)) { 1011 ret = rtl8365mb_ext_config_rgmii(priv, port, state->interface); 1012 if (ret) 1013 dev_err(priv->dev, 1014 "failed to configure RGMII mode on port %d: %d\n", 1015 port, ret); 1016 return; 1017 } 1018 1019 /* TODO: Implement MII and RMII modes, which the RTL8365MB-VC also 1020 * supports 1021 */ 1022 } 1023 1024 static void rtl8365mb_phylink_mac_link_down(struct dsa_switch *ds, int port, 1025 unsigned int mode, 1026 phy_interface_t interface) 1027 { 1028 struct realtek_priv *priv = ds->priv; 1029 struct rtl8365mb_port *p; 1030 struct rtl8365mb *mb; 1031 int ret; 1032 1033 mb = priv->chip_data; 1034 p = &mb->ports[port]; 1035 cancel_delayed_work_sync(&p->mib_work); 1036 1037 if (phy_interface_mode_is_rgmii(interface)) { 1038 ret = rtl8365mb_ext_config_forcemode(priv, port, false, 0, 0, 1039 false, false); 1040 if (ret) 1041 dev_err(priv->dev, 1042 "failed to reset forced mode on port %d: %d\n", 1043 port, ret); 1044 1045 return; 1046 } 1047 } 1048 1049 static void rtl8365mb_phylink_mac_link_up(struct dsa_switch *ds, int port, 1050 unsigned int mode, 1051 phy_interface_t interface, 1052 struct phy_device *phydev, int speed, 1053 int duplex, bool tx_pause, 1054 bool rx_pause) 1055 { 1056 struct realtek_priv *priv = ds->priv; 1057 struct rtl8365mb_port *p; 1058 struct rtl8365mb *mb; 1059 int ret; 1060 1061 mb = priv->chip_data; 1062 p = &mb->ports[port]; 1063 schedule_delayed_work(&p->mib_work, 0); 1064 1065 if (phy_interface_mode_is_rgmii(interface)) { 1066 ret = rtl8365mb_ext_config_forcemode(priv, port, true, speed, 1067 duplex, tx_pause, 1068 rx_pause); 1069 if (ret) 1070 dev_err(priv->dev, 1071 "failed to force mode on port %d: %d\n", port, 1072 ret); 1073 1074 return; 1075 } 1076 } 1077 1078 static void rtl8365mb_port_stp_state_set(struct dsa_switch *ds, int port, 1079 u8 state) 1080 { 1081 struct realtek_priv *priv = ds->priv; 1082 enum rtl8365mb_stp_state val; 1083 int msti = 0; 1084 1085 switch (state) { 1086 case BR_STATE_DISABLED: 1087 val = RTL8365MB_STP_STATE_DISABLED; 1088 break; 1089 case BR_STATE_BLOCKING: 1090 case BR_STATE_LISTENING: 1091 val = RTL8365MB_STP_STATE_BLOCKING; 1092 break; 1093 case BR_STATE_LEARNING: 1094 val = RTL8365MB_STP_STATE_LEARNING; 1095 break; 1096 case BR_STATE_FORWARDING: 1097 val = RTL8365MB_STP_STATE_FORWARDING; 1098 break; 1099 default: 1100 dev_err(priv->dev, "invalid STP state: %u\n", state); 1101 return; 1102 } 1103 1104 regmap_update_bits(priv->map, RTL8365MB_MSTI_CTRL_REG(msti, port), 1105 RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(port), 1106 val << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(port)); 1107 } 1108 1109 static int rtl8365mb_port_set_learning(struct realtek_priv *priv, int port, 1110 bool enable) 1111 { 1112 struct rtl8365mb *mb = priv->chip_data; 1113 1114 /* Enable/disable learning by limiting the number of L2 addresses the 1115 * port can learn. Realtek documentation states that a limit of zero 1116 * disables learning. When enabling learning, set it to the chip's 1117 * maximum. 1118 */ 1119 return regmap_write(priv->map, RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(port), 1120 enable ? mb->learn_limit_max : 0); 1121 } 1122 1123 static int rtl8365mb_port_set_isolation(struct realtek_priv *priv, int port, 1124 u32 mask) 1125 { 1126 return regmap_write(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), mask); 1127 } 1128 1129 static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port, 1130 u32 offset, u32 length, u64 *mibvalue) 1131 { 1132 u64 tmpvalue = 0; 1133 u32 val; 1134 int ret; 1135 int i; 1136 1137 /* The MIB address is an SRAM address. We request a particular address 1138 * and then poll the control register before reading the value from some 1139 * counter registers. 1140 */ 1141 ret = regmap_write(priv->map, RTL8365MB_MIB_ADDRESS_REG, 1142 RTL8365MB_MIB_ADDRESS(port, offset)); 1143 if (ret) 1144 return ret; 1145 1146 /* Poll for completion */ 1147 ret = regmap_read_poll_timeout(priv->map, RTL8365MB_MIB_CTRL0_REG, val, 1148 !(val & RTL8365MB_MIB_CTRL0_BUSY_MASK), 1149 10, 100); 1150 if (ret) 1151 return ret; 1152 1153 /* Presumably this indicates a MIB counter read failure */ 1154 if (val & RTL8365MB_MIB_CTRL0_RESET_MASK) 1155 return -EIO; 1156 1157 /* There are four MIB counter registers each holding a 16 bit word of a 1158 * MIB counter. Depending on the offset, we should read from the upper 1159 * two or lower two registers. In case the MIB counter is 4 words, we 1160 * read from all four registers. 1161 */ 1162 if (length == 4) 1163 offset = 3; 1164 else 1165 offset = (offset + 1) % 4; 1166 1167 /* Read the MIB counter 16 bits at a time */ 1168 for (i = 0; i < length; i++) { 1169 ret = regmap_read(priv->map, 1170 RTL8365MB_MIB_COUNTER_REG(offset - i), &val); 1171 if (ret) 1172 return ret; 1173 1174 tmpvalue = ((tmpvalue) << 16) | (val & 0xFFFF); 1175 } 1176 1177 /* Only commit the result if no error occurred */ 1178 *mibvalue = tmpvalue; 1179 1180 return 0; 1181 } 1182 1183 static void rtl8365mb_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data) 1184 { 1185 struct realtek_priv *priv = ds->priv; 1186 struct rtl8365mb *mb; 1187 int ret; 1188 int i; 1189 1190 mb = priv->chip_data; 1191 1192 mutex_lock(&mb->mib_lock); 1193 for (i = 0; i < RTL8365MB_MIB_END; i++) { 1194 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; 1195 1196 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset, 1197 mib->length, &data[i]); 1198 if (ret) { 1199 dev_err(priv->dev, 1200 "failed to read port %d counters: %d\n", port, 1201 ret); 1202 break; 1203 } 1204 } 1205 mutex_unlock(&mb->mib_lock); 1206 } 1207 1208 static void rtl8365mb_get_strings(struct dsa_switch *ds, int port, u32 stringset, u8 *data) 1209 { 1210 int i; 1211 1212 if (stringset != ETH_SS_STATS) 1213 return; 1214 1215 for (i = 0; i < RTL8365MB_MIB_END; i++) { 1216 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; 1217 1218 strncpy(data + i * ETH_GSTRING_LEN, mib->name, ETH_GSTRING_LEN); 1219 } 1220 } 1221 1222 static int rtl8365mb_get_sset_count(struct dsa_switch *ds, int port, int sset) 1223 { 1224 if (sset != ETH_SS_STATS) 1225 return -EOPNOTSUPP; 1226 1227 return RTL8365MB_MIB_END; 1228 } 1229 1230 static void rtl8365mb_get_phy_stats(struct dsa_switch *ds, int port, 1231 struct ethtool_eth_phy_stats *phy_stats) 1232 { 1233 struct realtek_priv *priv = ds->priv; 1234 struct rtl8365mb_mib_counter *mib; 1235 struct rtl8365mb *mb; 1236 1237 mb = priv->chip_data; 1238 mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3StatsSymbolErrors]; 1239 1240 mutex_lock(&mb->mib_lock); 1241 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, 1242 &phy_stats->SymbolErrorDuringCarrier); 1243 mutex_unlock(&mb->mib_lock); 1244 } 1245 1246 static void rtl8365mb_get_mac_stats(struct dsa_switch *ds, int port, 1247 struct ethtool_eth_mac_stats *mac_stats) 1248 { 1249 u64 cnt[RTL8365MB_MIB_END] = { 1250 [RTL8365MB_MIB_ifOutOctets] = 1, 1251 [RTL8365MB_MIB_ifOutUcastPkts] = 1, 1252 [RTL8365MB_MIB_ifOutMulticastPkts] = 1, 1253 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1, 1254 [RTL8365MB_MIB_dot3OutPauseFrames] = 1, 1255 [RTL8365MB_MIB_ifOutDiscards] = 1, 1256 [RTL8365MB_MIB_ifInOctets] = 1, 1257 [RTL8365MB_MIB_ifInUcastPkts] = 1, 1258 [RTL8365MB_MIB_ifInMulticastPkts] = 1, 1259 [RTL8365MB_MIB_ifInBroadcastPkts] = 1, 1260 [RTL8365MB_MIB_dot3InPauseFrames] = 1, 1261 [RTL8365MB_MIB_dot3StatsSingleCollisionFrames] = 1, 1262 [RTL8365MB_MIB_dot3StatsMultipleCollisionFrames] = 1, 1263 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1, 1264 [RTL8365MB_MIB_dot3StatsDeferredTransmissions] = 1, 1265 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1, 1266 [RTL8365MB_MIB_dot3StatsExcessiveCollisions] = 1, 1267 1268 }; 1269 struct realtek_priv *priv = ds->priv; 1270 struct rtl8365mb *mb; 1271 int ret; 1272 int i; 1273 1274 mb = priv->chip_data; 1275 1276 mutex_lock(&mb->mib_lock); 1277 for (i = 0; i < RTL8365MB_MIB_END; i++) { 1278 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; 1279 1280 /* Only fetch required MIB counters (marked = 1 above) */ 1281 if (!cnt[i]) 1282 continue; 1283 1284 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset, 1285 mib->length, &cnt[i]); 1286 if (ret) 1287 break; 1288 } 1289 mutex_unlock(&mb->mib_lock); 1290 1291 /* The RTL8365MB-VC exposes MIB objects, which we have to translate into 1292 * IEEE 802.3 Managed Objects. This is not always completely faithful, 1293 * but we try out best. See RFC 3635 for a detailed treatment of the 1294 * subject. 1295 */ 1296 1297 mac_stats->FramesTransmittedOK = cnt[RTL8365MB_MIB_ifOutUcastPkts] + 1298 cnt[RTL8365MB_MIB_ifOutMulticastPkts] + 1299 cnt[RTL8365MB_MIB_ifOutBroadcastPkts] + 1300 cnt[RTL8365MB_MIB_dot3OutPauseFrames] - 1301 cnt[RTL8365MB_MIB_ifOutDiscards]; 1302 mac_stats->SingleCollisionFrames = 1303 cnt[RTL8365MB_MIB_dot3StatsSingleCollisionFrames]; 1304 mac_stats->MultipleCollisionFrames = 1305 cnt[RTL8365MB_MIB_dot3StatsMultipleCollisionFrames]; 1306 mac_stats->FramesReceivedOK = cnt[RTL8365MB_MIB_ifInUcastPkts] + 1307 cnt[RTL8365MB_MIB_ifInMulticastPkts] + 1308 cnt[RTL8365MB_MIB_ifInBroadcastPkts] + 1309 cnt[RTL8365MB_MIB_dot3InPauseFrames]; 1310 mac_stats->FrameCheckSequenceErrors = 1311 cnt[RTL8365MB_MIB_dot3StatsFCSErrors]; 1312 mac_stats->OctetsTransmittedOK = cnt[RTL8365MB_MIB_ifOutOctets] - 1313 18 * mac_stats->FramesTransmittedOK; 1314 mac_stats->FramesWithDeferredXmissions = 1315 cnt[RTL8365MB_MIB_dot3StatsDeferredTransmissions]; 1316 mac_stats->LateCollisions = cnt[RTL8365MB_MIB_dot3StatsLateCollisions]; 1317 mac_stats->FramesAbortedDueToXSColls = 1318 cnt[RTL8365MB_MIB_dot3StatsExcessiveCollisions]; 1319 mac_stats->OctetsReceivedOK = cnt[RTL8365MB_MIB_ifInOctets] - 1320 18 * mac_stats->FramesReceivedOK; 1321 mac_stats->MulticastFramesXmittedOK = 1322 cnt[RTL8365MB_MIB_ifOutMulticastPkts]; 1323 mac_stats->BroadcastFramesXmittedOK = 1324 cnt[RTL8365MB_MIB_ifOutBroadcastPkts]; 1325 mac_stats->MulticastFramesReceivedOK = 1326 cnt[RTL8365MB_MIB_ifInMulticastPkts]; 1327 mac_stats->BroadcastFramesReceivedOK = 1328 cnt[RTL8365MB_MIB_ifInBroadcastPkts]; 1329 } 1330 1331 static void rtl8365mb_get_ctrl_stats(struct dsa_switch *ds, int port, 1332 struct ethtool_eth_ctrl_stats *ctrl_stats) 1333 { 1334 struct realtek_priv *priv = ds->priv; 1335 struct rtl8365mb_mib_counter *mib; 1336 struct rtl8365mb *mb; 1337 1338 mb = priv->chip_data; 1339 mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3ControlInUnknownOpcodes]; 1340 1341 mutex_lock(&mb->mib_lock); 1342 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, 1343 &ctrl_stats->UnsupportedOpcodesReceived); 1344 mutex_unlock(&mb->mib_lock); 1345 } 1346 1347 static void rtl8365mb_stats_update(struct realtek_priv *priv, int port) 1348 { 1349 u64 cnt[RTL8365MB_MIB_END] = { 1350 [RTL8365MB_MIB_ifOutOctets] = 1, 1351 [RTL8365MB_MIB_ifOutUcastPkts] = 1, 1352 [RTL8365MB_MIB_ifOutMulticastPkts] = 1, 1353 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1, 1354 [RTL8365MB_MIB_ifOutDiscards] = 1, 1355 [RTL8365MB_MIB_ifInOctets] = 1, 1356 [RTL8365MB_MIB_ifInUcastPkts] = 1, 1357 [RTL8365MB_MIB_ifInMulticastPkts] = 1, 1358 [RTL8365MB_MIB_ifInBroadcastPkts] = 1, 1359 [RTL8365MB_MIB_etherStatsDropEvents] = 1, 1360 [RTL8365MB_MIB_etherStatsCollisions] = 1, 1361 [RTL8365MB_MIB_etherStatsFragments] = 1, 1362 [RTL8365MB_MIB_etherStatsJabbers] = 1, 1363 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1, 1364 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1, 1365 }; 1366 struct rtl8365mb *mb = priv->chip_data; 1367 struct rtnl_link_stats64 *stats; 1368 int ret; 1369 int i; 1370 1371 stats = &mb->ports[port].stats; 1372 1373 mutex_lock(&mb->mib_lock); 1374 for (i = 0; i < RTL8365MB_MIB_END; i++) { 1375 struct rtl8365mb_mib_counter *c = &rtl8365mb_mib_counters[i]; 1376 1377 /* Only fetch required MIB counters (marked = 1 above) */ 1378 if (!cnt[i]) 1379 continue; 1380 1381 ret = rtl8365mb_mib_counter_read(priv, port, c->offset, 1382 c->length, &cnt[i]); 1383 if (ret) 1384 break; 1385 } 1386 mutex_unlock(&mb->mib_lock); 1387 1388 /* Don't update statistics if there was an error reading the counters */ 1389 if (ret) 1390 return; 1391 1392 spin_lock(&mb->ports[port].stats_lock); 1393 1394 stats->rx_packets = cnt[RTL8365MB_MIB_ifInUcastPkts] + 1395 cnt[RTL8365MB_MIB_ifInMulticastPkts] + 1396 cnt[RTL8365MB_MIB_ifInBroadcastPkts] - 1397 cnt[RTL8365MB_MIB_ifOutDiscards]; 1398 1399 stats->tx_packets = cnt[RTL8365MB_MIB_ifOutUcastPkts] + 1400 cnt[RTL8365MB_MIB_ifOutMulticastPkts] + 1401 cnt[RTL8365MB_MIB_ifOutBroadcastPkts]; 1402 1403 /* if{In,Out}Octets includes FCS - remove it */ 1404 stats->rx_bytes = cnt[RTL8365MB_MIB_ifInOctets] - 4 * stats->rx_packets; 1405 stats->tx_bytes = 1406 cnt[RTL8365MB_MIB_ifOutOctets] - 4 * stats->tx_packets; 1407 1408 stats->rx_dropped = cnt[RTL8365MB_MIB_etherStatsDropEvents]; 1409 stats->tx_dropped = cnt[RTL8365MB_MIB_ifOutDiscards]; 1410 1411 stats->multicast = cnt[RTL8365MB_MIB_ifInMulticastPkts]; 1412 stats->collisions = cnt[RTL8365MB_MIB_etherStatsCollisions]; 1413 1414 stats->rx_length_errors = cnt[RTL8365MB_MIB_etherStatsFragments] + 1415 cnt[RTL8365MB_MIB_etherStatsJabbers]; 1416 stats->rx_crc_errors = cnt[RTL8365MB_MIB_dot3StatsFCSErrors]; 1417 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors; 1418 1419 stats->tx_aborted_errors = cnt[RTL8365MB_MIB_ifOutDiscards]; 1420 stats->tx_window_errors = cnt[RTL8365MB_MIB_dot3StatsLateCollisions]; 1421 stats->tx_errors = stats->tx_aborted_errors + stats->tx_window_errors; 1422 1423 spin_unlock(&mb->ports[port].stats_lock); 1424 } 1425 1426 static void rtl8365mb_stats_poll(struct work_struct *work) 1427 { 1428 struct rtl8365mb_port *p = container_of(to_delayed_work(work), 1429 struct rtl8365mb_port, 1430 mib_work); 1431 struct realtek_priv *priv = p->priv; 1432 1433 rtl8365mb_stats_update(priv, p->index); 1434 1435 schedule_delayed_work(&p->mib_work, RTL8365MB_STATS_INTERVAL_JIFFIES); 1436 } 1437 1438 static void rtl8365mb_get_stats64(struct dsa_switch *ds, int port, 1439 struct rtnl_link_stats64 *s) 1440 { 1441 struct realtek_priv *priv = ds->priv; 1442 struct rtl8365mb_port *p; 1443 struct rtl8365mb *mb; 1444 1445 mb = priv->chip_data; 1446 p = &mb->ports[port]; 1447 1448 spin_lock(&p->stats_lock); 1449 memcpy(s, &p->stats, sizeof(*s)); 1450 spin_unlock(&p->stats_lock); 1451 } 1452 1453 static void rtl8365mb_stats_setup(struct realtek_priv *priv) 1454 { 1455 struct rtl8365mb *mb = priv->chip_data; 1456 int i; 1457 1458 /* Per-chip global mutex to protect MIB counter access, since doing 1459 * so requires accessing a series of registers in a particular order. 1460 */ 1461 mutex_init(&mb->mib_lock); 1462 1463 for (i = 0; i < priv->num_ports; i++) { 1464 struct rtl8365mb_port *p = &mb->ports[i]; 1465 1466 if (dsa_is_unused_port(priv->ds, i)) 1467 continue; 1468 1469 /* Per-port spinlock to protect the stats64 data */ 1470 spin_lock_init(&p->stats_lock); 1471 1472 /* This work polls the MIB counters and keeps the stats64 data 1473 * up-to-date. 1474 */ 1475 INIT_DELAYED_WORK(&p->mib_work, rtl8365mb_stats_poll); 1476 } 1477 } 1478 1479 static void rtl8365mb_stats_teardown(struct realtek_priv *priv) 1480 { 1481 struct rtl8365mb *mb = priv->chip_data; 1482 int i; 1483 1484 for (i = 0; i < priv->num_ports; i++) { 1485 struct rtl8365mb_port *p = &mb->ports[i]; 1486 1487 if (dsa_is_unused_port(priv->ds, i)) 1488 continue; 1489 1490 cancel_delayed_work_sync(&p->mib_work); 1491 } 1492 } 1493 1494 static int rtl8365mb_get_and_clear_status_reg(struct realtek_priv *priv, u32 reg, 1495 u32 *val) 1496 { 1497 int ret; 1498 1499 ret = regmap_read(priv->map, reg, val); 1500 if (ret) 1501 return ret; 1502 1503 return regmap_write(priv->map, reg, *val); 1504 } 1505 1506 static irqreturn_t rtl8365mb_irq(int irq, void *data) 1507 { 1508 struct realtek_priv *priv = data; 1509 unsigned long line_changes = 0; 1510 struct rtl8365mb *mb; 1511 u32 stat; 1512 int line; 1513 int ret; 1514 1515 mb = priv->chip_data; 1516 1517 ret = rtl8365mb_get_and_clear_status_reg(priv, RTL8365MB_INTR_STATUS_REG, 1518 &stat); 1519 if (ret) 1520 goto out_error; 1521 1522 if (stat & RTL8365MB_INTR_LINK_CHANGE_MASK) { 1523 u32 linkdown_ind; 1524 u32 linkup_ind; 1525 u32 val; 1526 1527 ret = rtl8365mb_get_and_clear_status_reg( 1528 priv, RTL8365MB_PORT_LINKUP_IND_REG, &val); 1529 if (ret) 1530 goto out_error; 1531 1532 linkup_ind = FIELD_GET(RTL8365MB_PORT_LINKUP_IND_MASK, val); 1533 1534 ret = rtl8365mb_get_and_clear_status_reg( 1535 priv, RTL8365MB_PORT_LINKDOWN_IND_REG, &val); 1536 if (ret) 1537 goto out_error; 1538 1539 linkdown_ind = FIELD_GET(RTL8365MB_PORT_LINKDOWN_IND_MASK, val); 1540 1541 line_changes = (linkup_ind | linkdown_ind) & mb->port_mask; 1542 } 1543 1544 if (!line_changes) 1545 goto out_none; 1546 1547 for_each_set_bit(line, &line_changes, priv->num_ports) { 1548 int child_irq = irq_find_mapping(priv->irqdomain, line); 1549 1550 handle_nested_irq(child_irq); 1551 } 1552 1553 return IRQ_HANDLED; 1554 1555 out_error: 1556 dev_err(priv->dev, "failed to read interrupt status: %d\n", ret); 1557 1558 out_none: 1559 return IRQ_NONE; 1560 } 1561 1562 static struct irq_chip rtl8365mb_irq_chip = { 1563 .name = "rtl8365mb", 1564 /* The hardware doesn't support masking IRQs on a per-port basis */ 1565 }; 1566 1567 static int rtl8365mb_irq_map(struct irq_domain *domain, unsigned int irq, 1568 irq_hw_number_t hwirq) 1569 { 1570 irq_set_chip_data(irq, domain->host_data); 1571 irq_set_chip_and_handler(irq, &rtl8365mb_irq_chip, handle_simple_irq); 1572 irq_set_nested_thread(irq, 1); 1573 irq_set_noprobe(irq); 1574 1575 return 0; 1576 } 1577 1578 static void rtl8365mb_irq_unmap(struct irq_domain *d, unsigned int irq) 1579 { 1580 irq_set_nested_thread(irq, 0); 1581 irq_set_chip_and_handler(irq, NULL, NULL); 1582 irq_set_chip_data(irq, NULL); 1583 } 1584 1585 static const struct irq_domain_ops rtl8365mb_irqdomain_ops = { 1586 .map = rtl8365mb_irq_map, 1587 .unmap = rtl8365mb_irq_unmap, 1588 .xlate = irq_domain_xlate_onecell, 1589 }; 1590 1591 static int rtl8365mb_set_irq_enable(struct realtek_priv *priv, bool enable) 1592 { 1593 return regmap_update_bits(priv->map, RTL8365MB_INTR_CTRL_REG, 1594 RTL8365MB_INTR_LINK_CHANGE_MASK, 1595 FIELD_PREP(RTL8365MB_INTR_LINK_CHANGE_MASK, 1596 enable ? 1 : 0)); 1597 } 1598 1599 static int rtl8365mb_irq_enable(struct realtek_priv *priv) 1600 { 1601 return rtl8365mb_set_irq_enable(priv, true); 1602 } 1603 1604 static int rtl8365mb_irq_disable(struct realtek_priv *priv) 1605 { 1606 return rtl8365mb_set_irq_enable(priv, false); 1607 } 1608 1609 static int rtl8365mb_irq_setup(struct realtek_priv *priv) 1610 { 1611 struct rtl8365mb *mb = priv->chip_data; 1612 struct device_node *intc; 1613 u32 irq_trig; 1614 int virq; 1615 int irq; 1616 u32 val; 1617 int ret; 1618 int i; 1619 1620 intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller"); 1621 if (!intc) { 1622 dev_err(priv->dev, "missing child interrupt-controller node\n"); 1623 return -EINVAL; 1624 } 1625 1626 /* rtl8365mb IRQs cascade off this one */ 1627 irq = of_irq_get(intc, 0); 1628 if (irq <= 0) { 1629 if (irq != -EPROBE_DEFER) 1630 dev_err(priv->dev, "failed to get parent irq: %d\n", 1631 irq); 1632 ret = irq ? irq : -EINVAL; 1633 goto out_put_node; 1634 } 1635 1636 priv->irqdomain = irq_domain_add_linear(intc, priv->num_ports, 1637 &rtl8365mb_irqdomain_ops, priv); 1638 if (!priv->irqdomain) { 1639 dev_err(priv->dev, "failed to add irq domain\n"); 1640 ret = -ENOMEM; 1641 goto out_put_node; 1642 } 1643 1644 for (i = 0; i < priv->num_ports; i++) { 1645 virq = irq_create_mapping(priv->irqdomain, i); 1646 if (!virq) { 1647 dev_err(priv->dev, 1648 "failed to create irq domain mapping\n"); 1649 ret = -EINVAL; 1650 goto out_remove_irqdomain; 1651 } 1652 1653 irq_set_parent(virq, irq); 1654 } 1655 1656 /* Configure chip interrupt signal polarity */ 1657 irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq)); 1658 switch (irq_trig) { 1659 case IRQF_TRIGGER_RISING: 1660 case IRQF_TRIGGER_HIGH: 1661 val = RTL8365MB_INTR_POLARITY_HIGH; 1662 break; 1663 case IRQF_TRIGGER_FALLING: 1664 case IRQF_TRIGGER_LOW: 1665 val = RTL8365MB_INTR_POLARITY_LOW; 1666 break; 1667 default: 1668 dev_err(priv->dev, "unsupported irq trigger type %u\n", 1669 irq_trig); 1670 ret = -EINVAL; 1671 goto out_remove_irqdomain; 1672 } 1673 1674 ret = regmap_update_bits(priv->map, RTL8365MB_INTR_POLARITY_REG, 1675 RTL8365MB_INTR_POLARITY_MASK, 1676 FIELD_PREP(RTL8365MB_INTR_POLARITY_MASK, val)); 1677 if (ret) 1678 goto out_remove_irqdomain; 1679 1680 /* Disable the interrupt in case the chip has it enabled on reset */ 1681 ret = rtl8365mb_irq_disable(priv); 1682 if (ret) 1683 goto out_remove_irqdomain; 1684 1685 /* Clear the interrupt status register */ 1686 ret = regmap_write(priv->map, RTL8365MB_INTR_STATUS_REG, 1687 RTL8365MB_INTR_ALL_MASK); 1688 if (ret) 1689 goto out_remove_irqdomain; 1690 1691 ret = request_threaded_irq(irq, NULL, rtl8365mb_irq, IRQF_ONESHOT, 1692 "rtl8365mb", priv); 1693 if (ret) { 1694 dev_err(priv->dev, "failed to request irq: %d\n", ret); 1695 goto out_remove_irqdomain; 1696 } 1697 1698 /* Store the irq so that we know to free it during teardown */ 1699 mb->irq = irq; 1700 1701 ret = rtl8365mb_irq_enable(priv); 1702 if (ret) 1703 goto out_free_irq; 1704 1705 of_node_put(intc); 1706 1707 return 0; 1708 1709 out_free_irq: 1710 free_irq(mb->irq, priv); 1711 mb->irq = 0; 1712 1713 out_remove_irqdomain: 1714 for (i = 0; i < priv->num_ports; i++) { 1715 virq = irq_find_mapping(priv->irqdomain, i); 1716 irq_dispose_mapping(virq); 1717 } 1718 1719 irq_domain_remove(priv->irqdomain); 1720 priv->irqdomain = NULL; 1721 1722 out_put_node: 1723 of_node_put(intc); 1724 1725 return ret; 1726 } 1727 1728 static void rtl8365mb_irq_teardown(struct realtek_priv *priv) 1729 { 1730 struct rtl8365mb *mb = priv->chip_data; 1731 int virq; 1732 int i; 1733 1734 if (mb->irq) { 1735 free_irq(mb->irq, priv); 1736 mb->irq = 0; 1737 } 1738 1739 if (priv->irqdomain) { 1740 for (i = 0; i < priv->num_ports; i++) { 1741 virq = irq_find_mapping(priv->irqdomain, i); 1742 irq_dispose_mapping(virq); 1743 } 1744 1745 irq_domain_remove(priv->irqdomain); 1746 priv->irqdomain = NULL; 1747 } 1748 } 1749 1750 static int rtl8365mb_cpu_config(struct realtek_priv *priv, const struct rtl8365mb_cpu *cpu) 1751 { 1752 u32 val; 1753 int ret; 1754 1755 ret = regmap_update_bits(priv->map, RTL8365MB_CPU_PORT_MASK_REG, 1756 RTL8365MB_CPU_PORT_MASK_MASK, 1757 FIELD_PREP(RTL8365MB_CPU_PORT_MASK_MASK, 1758 cpu->mask)); 1759 if (ret) 1760 return ret; 1761 1762 val = FIELD_PREP(RTL8365MB_CPU_CTRL_EN_MASK, cpu->enable ? 1 : 0) | 1763 FIELD_PREP(RTL8365MB_CPU_CTRL_INSERTMODE_MASK, cpu->insert) | 1764 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_POSITION_MASK, cpu->position) | 1765 FIELD_PREP(RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK, cpu->rx_length) | 1766 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK, cpu->format) | 1767 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_MASK, cpu->trap_port & 0x7) | 1768 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK, 1769 cpu->trap_port >> 3 & 0x1); 1770 ret = regmap_write(priv->map, RTL8365MB_CPU_CTRL_REG, val); 1771 if (ret) 1772 return ret; 1773 1774 return 0; 1775 } 1776 1777 static int rtl8365mb_switch_init(struct realtek_priv *priv) 1778 { 1779 struct rtl8365mb *mb = priv->chip_data; 1780 int ret; 1781 int i; 1782 1783 /* Do any chip-specific init jam before getting to the common stuff */ 1784 if (mb->jam_table) { 1785 for (i = 0; i < mb->jam_size; i++) { 1786 ret = regmap_write(priv->map, mb->jam_table[i].reg, 1787 mb->jam_table[i].val); 1788 if (ret) 1789 return ret; 1790 } 1791 } 1792 1793 /* Common init jam */ 1794 for (i = 0; i < ARRAY_SIZE(rtl8365mb_init_jam_common); i++) { 1795 ret = regmap_write(priv->map, rtl8365mb_init_jam_common[i].reg, 1796 rtl8365mb_init_jam_common[i].val); 1797 if (ret) 1798 return ret; 1799 } 1800 1801 return 0; 1802 } 1803 1804 static int rtl8365mb_reset_chip(struct realtek_priv *priv) 1805 { 1806 u32 val; 1807 1808 priv->write_reg_noack(priv, RTL8365MB_CHIP_RESET_REG, 1809 FIELD_PREP(RTL8365MB_CHIP_RESET_HW_MASK, 1)); 1810 1811 /* Realtek documentation says the chip needs 1 second to reset. Sleep 1812 * for 100 ms before accessing any registers to prevent ACK timeouts. 1813 */ 1814 msleep(100); 1815 return regmap_read_poll_timeout(priv->map, RTL8365MB_CHIP_RESET_REG, val, 1816 !(val & RTL8365MB_CHIP_RESET_HW_MASK), 1817 20000, 1e6); 1818 } 1819 1820 static int rtl8365mb_setup(struct dsa_switch *ds) 1821 { 1822 struct realtek_priv *priv = ds->priv; 1823 struct rtl8365mb_cpu cpu = {0}; 1824 struct dsa_port *cpu_dp; 1825 struct rtl8365mb *mb; 1826 int ret; 1827 int i; 1828 1829 mb = priv->chip_data; 1830 1831 ret = rtl8365mb_reset_chip(priv); 1832 if (ret) { 1833 dev_err(priv->dev, "failed to reset chip: %d\n", ret); 1834 goto out_error; 1835 } 1836 1837 /* Configure switch to vendor-defined initial state */ 1838 ret = rtl8365mb_switch_init(priv); 1839 if (ret) { 1840 dev_err(priv->dev, "failed to initialize switch: %d\n", ret); 1841 goto out_error; 1842 } 1843 1844 /* Set up cascading IRQs */ 1845 ret = rtl8365mb_irq_setup(priv); 1846 if (ret == -EPROBE_DEFER) 1847 return ret; 1848 else if (ret) 1849 dev_info(priv->dev, "no interrupt support\n"); 1850 1851 /* Configure CPU tagging */ 1852 cpu.trap_port = RTL8365MB_MAX_NUM_PORTS; 1853 dsa_switch_for_each_cpu_port(cpu_dp, priv->ds) { 1854 cpu.mask |= BIT(cpu_dp->index); 1855 1856 if (cpu.trap_port == RTL8365MB_MAX_NUM_PORTS) 1857 cpu.trap_port = cpu_dp->index; 1858 } 1859 1860 cpu.enable = cpu.mask > 0; 1861 cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL; 1862 cpu.position = RTL8365MB_CPU_POS_AFTER_SA; 1863 cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES; 1864 cpu.format = RTL8365MB_CPU_FORMAT_8BYTES; 1865 1866 ret = rtl8365mb_cpu_config(priv, &cpu); 1867 if (ret) 1868 goto out_teardown_irq; 1869 1870 /* Configure ports */ 1871 for (i = 0; i < priv->num_ports; i++) { 1872 struct rtl8365mb_port *p = &mb->ports[i]; 1873 1874 if (dsa_is_unused_port(priv->ds, i)) 1875 continue; 1876 1877 /* Forward only to the CPU */ 1878 ret = rtl8365mb_port_set_isolation(priv, i, cpu.mask); 1879 if (ret) 1880 goto out_teardown_irq; 1881 1882 /* Disable learning */ 1883 ret = rtl8365mb_port_set_learning(priv, i, false); 1884 if (ret) 1885 goto out_teardown_irq; 1886 1887 /* Set the initial STP state of all ports to DISABLED, otherwise 1888 * ports will still forward frames to the CPU despite being 1889 * administratively down by default. 1890 */ 1891 rtl8365mb_port_stp_state_set(priv->ds, i, BR_STATE_DISABLED); 1892 1893 /* Set up per-port private data */ 1894 p->priv = priv; 1895 p->index = i; 1896 } 1897 1898 /* Set maximum packet length to 1536 bytes */ 1899 ret = regmap_update_bits(priv->map, RTL8365MB_CFG0_MAX_LEN_REG, 1900 RTL8365MB_CFG0_MAX_LEN_MASK, 1901 FIELD_PREP(RTL8365MB_CFG0_MAX_LEN_MASK, 1536)); 1902 if (ret) 1903 goto out_teardown_irq; 1904 1905 if (priv->setup_interface) { 1906 ret = priv->setup_interface(ds); 1907 if (ret) { 1908 dev_err(priv->dev, "could not set up MDIO bus\n"); 1909 goto out_teardown_irq; 1910 } 1911 } 1912 1913 /* Start statistics counter polling */ 1914 rtl8365mb_stats_setup(priv); 1915 1916 return 0; 1917 1918 out_teardown_irq: 1919 rtl8365mb_irq_teardown(priv); 1920 1921 out_error: 1922 return ret; 1923 } 1924 1925 static void rtl8365mb_teardown(struct dsa_switch *ds) 1926 { 1927 struct realtek_priv *priv = ds->priv; 1928 1929 rtl8365mb_stats_teardown(priv); 1930 rtl8365mb_irq_teardown(priv); 1931 } 1932 1933 static int rtl8365mb_get_chip_id_and_ver(struct regmap *map, u32 *id, u32 *ver) 1934 { 1935 int ret; 1936 1937 /* For some reason we have to write a magic value to an arbitrary 1938 * register whenever accessing the chip ID/version registers. 1939 */ 1940 ret = regmap_write(map, RTL8365MB_MAGIC_REG, RTL8365MB_MAGIC_VALUE); 1941 if (ret) 1942 return ret; 1943 1944 ret = regmap_read(map, RTL8365MB_CHIP_ID_REG, id); 1945 if (ret) 1946 return ret; 1947 1948 ret = regmap_read(map, RTL8365MB_CHIP_VER_REG, ver); 1949 if (ret) 1950 return ret; 1951 1952 /* Reset magic register */ 1953 ret = regmap_write(map, RTL8365MB_MAGIC_REG, 0); 1954 if (ret) 1955 return ret; 1956 1957 return 0; 1958 } 1959 1960 static int rtl8365mb_detect(struct realtek_priv *priv) 1961 { 1962 struct rtl8365mb *mb = priv->chip_data; 1963 u32 chip_id; 1964 u32 chip_ver; 1965 int ret; 1966 1967 ret = rtl8365mb_get_chip_id_and_ver(priv->map, &chip_id, &chip_ver); 1968 if (ret) { 1969 dev_err(priv->dev, "failed to read chip id and version: %d\n", 1970 ret); 1971 return ret; 1972 } 1973 1974 switch (chip_id) { 1975 case RTL8365MB_CHIP_ID_8365MB_VC: 1976 switch (chip_ver) { 1977 case RTL8365MB_CHIP_VER_8365MB_VC: 1978 dev_info(priv->dev, 1979 "found an RTL8365MB-VC switch (ver=0x%04x)\n", 1980 chip_ver); 1981 break; 1982 case RTL8365MB_CHIP_VER_8367RB: 1983 dev_info(priv->dev, 1984 "found an RTL8367RB-VB switch (ver=0x%04x)\n", 1985 chip_ver); 1986 break; 1987 case RTL8365MB_CHIP_VER_8367S: 1988 dev_info(priv->dev, 1989 "found an RTL8367S switch (ver=0x%04x)\n", 1990 chip_ver); 1991 break; 1992 default: 1993 dev_err(priv->dev, "unrecognized switch version (ver=0x%04x)", 1994 chip_ver); 1995 return -ENODEV; 1996 } 1997 1998 priv->num_ports = RTL8365MB_MAX_NUM_PORTS; 1999 2000 mb->priv = priv; 2001 mb->chip_id = chip_id; 2002 mb->chip_ver = chip_ver; 2003 mb->port_mask = GENMASK(priv->num_ports - 1, 0); 2004 mb->learn_limit_max = RTL8365MB_LEARN_LIMIT_MAX; 2005 mb->jam_table = rtl8365mb_init_jam_8365mb_vc; 2006 mb->jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc); 2007 2008 break; 2009 default: 2010 dev_err(priv->dev, 2011 "found an unknown Realtek switch (id=0x%04x, ver=0x%04x)\n", 2012 chip_id, chip_ver); 2013 return -ENODEV; 2014 } 2015 2016 return 0; 2017 } 2018 2019 static const struct dsa_switch_ops rtl8365mb_switch_ops_smi = { 2020 .get_tag_protocol = rtl8365mb_get_tag_protocol, 2021 .setup = rtl8365mb_setup, 2022 .teardown = rtl8365mb_teardown, 2023 .phylink_validate = rtl8365mb_phylink_validate, 2024 .phylink_mac_config = rtl8365mb_phylink_mac_config, 2025 .phylink_mac_link_down = rtl8365mb_phylink_mac_link_down, 2026 .phylink_mac_link_up = rtl8365mb_phylink_mac_link_up, 2027 .port_stp_state_set = rtl8365mb_port_stp_state_set, 2028 .get_strings = rtl8365mb_get_strings, 2029 .get_ethtool_stats = rtl8365mb_get_ethtool_stats, 2030 .get_sset_count = rtl8365mb_get_sset_count, 2031 .get_eth_phy_stats = rtl8365mb_get_phy_stats, 2032 .get_eth_mac_stats = rtl8365mb_get_mac_stats, 2033 .get_eth_ctrl_stats = rtl8365mb_get_ctrl_stats, 2034 .get_stats64 = rtl8365mb_get_stats64, 2035 }; 2036 2037 static const struct dsa_switch_ops rtl8365mb_switch_ops_mdio = { 2038 .get_tag_protocol = rtl8365mb_get_tag_protocol, 2039 .setup = rtl8365mb_setup, 2040 .teardown = rtl8365mb_teardown, 2041 .phylink_validate = rtl8365mb_phylink_validate, 2042 .phylink_mac_config = rtl8365mb_phylink_mac_config, 2043 .phylink_mac_link_down = rtl8365mb_phylink_mac_link_down, 2044 .phylink_mac_link_up = rtl8365mb_phylink_mac_link_up, 2045 .phy_read = rtl8365mb_dsa_phy_read, 2046 .phy_write = rtl8365mb_dsa_phy_write, 2047 .port_stp_state_set = rtl8365mb_port_stp_state_set, 2048 .get_strings = rtl8365mb_get_strings, 2049 .get_ethtool_stats = rtl8365mb_get_ethtool_stats, 2050 .get_sset_count = rtl8365mb_get_sset_count, 2051 .get_eth_phy_stats = rtl8365mb_get_phy_stats, 2052 .get_eth_mac_stats = rtl8365mb_get_mac_stats, 2053 .get_eth_ctrl_stats = rtl8365mb_get_ctrl_stats, 2054 .get_stats64 = rtl8365mb_get_stats64, 2055 }; 2056 2057 static const struct realtek_ops rtl8365mb_ops = { 2058 .detect = rtl8365mb_detect, 2059 .phy_read = rtl8365mb_phy_read, 2060 .phy_write = rtl8365mb_phy_write, 2061 }; 2062 2063 const struct realtek_variant rtl8365mb_variant = { 2064 .ds_ops_smi = &rtl8365mb_switch_ops_smi, 2065 .ds_ops_mdio = &rtl8365mb_switch_ops_mdio, 2066 .ops = &rtl8365mb_ops, 2067 .clk_delay = 10, 2068 .cmd_read = 0xb9, 2069 .cmd_write = 0xb8, 2070 .chip_data_sz = sizeof(struct rtl8365mb), 2071 }; 2072 EXPORT_SYMBOL_GPL(rtl8365mb_variant); 2073 2074 MODULE_AUTHOR("Alvin Šipraga <alsi@bang-olufsen.dk>"); 2075 MODULE_DESCRIPTION("Driver for RTL8365MB-VC ethernet switch"); 2076 MODULE_LICENSE("GPL"); 2077