1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Realtek Simple Management Interface (SMI) driver 3 * It can be discussed how "simple" this interface is. 4 * 5 * The SMI protocol piggy-backs the MDIO MDC and MDIO signals levels 6 * but the protocol is not MDIO at all. Instead it is a Realtek 7 * pecularity that need to bit-bang the lines in a special way to 8 * communicate with the switch. 9 * 10 * ASICs we intend to support with this driver: 11 * 12 * RTL8366 - The original version, apparently 13 * RTL8369 - Similar enough to have the same datsheet as RTL8366 14 * RTL8366RB - Probably reads out "RTL8366 revision B", has a quite 15 * different register layout from the other two 16 * RTL8366S - Is this "RTL8366 super"? 17 * RTL8367 - Has an OpenWRT driver as well 18 * RTL8368S - Seems to be an alternative name for RTL8366RB 19 * RTL8370 - Also uses SMI 20 * 21 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> 22 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com> 23 * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv> 24 * Copyright (C) 2011 Colin Leitner <colin.leitner@googlemail.com> 25 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org> 26 */ 27 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/device.h> 31 #include <linux/spinlock.h> 32 #include <linux/skbuff.h> 33 #include <linux/of.h> 34 #include <linux/of_device.h> 35 #include <linux/of_mdio.h> 36 #include <linux/delay.h> 37 #include <linux/gpio/consumer.h> 38 #include <linux/platform_device.h> 39 #include <linux/regmap.h> 40 #include <linux/bitops.h> 41 #include <linux/if_bridge.h> 42 43 #include "realtek.h" 44 45 #define REALTEK_SMI_ACK_RETRY_COUNT 5 46 #define REALTEK_SMI_HW_STOP_DELAY 25 /* msecs */ 47 #define REALTEK_SMI_HW_START_DELAY 100 /* msecs */ 48 49 static inline void realtek_smi_clk_delay(struct realtek_priv *priv) 50 { 51 ndelay(priv->clk_delay); 52 } 53 54 static void realtek_smi_start(struct realtek_priv *priv) 55 { 56 /* Set GPIO pins to output mode, with initial state: 57 * SCK = 0, SDA = 1 58 */ 59 gpiod_direction_output(priv->mdc, 0); 60 gpiod_direction_output(priv->mdio, 1); 61 realtek_smi_clk_delay(priv); 62 63 /* CLK 1: 0 -> 1, 1 -> 0 */ 64 gpiod_set_value(priv->mdc, 1); 65 realtek_smi_clk_delay(priv); 66 gpiod_set_value(priv->mdc, 0); 67 realtek_smi_clk_delay(priv); 68 69 /* CLK 2: */ 70 gpiod_set_value(priv->mdc, 1); 71 realtek_smi_clk_delay(priv); 72 gpiod_set_value(priv->mdio, 0); 73 realtek_smi_clk_delay(priv); 74 gpiod_set_value(priv->mdc, 0); 75 realtek_smi_clk_delay(priv); 76 gpiod_set_value(priv->mdio, 1); 77 } 78 79 static void realtek_smi_stop(struct realtek_priv *priv) 80 { 81 realtek_smi_clk_delay(priv); 82 gpiod_set_value(priv->mdio, 0); 83 gpiod_set_value(priv->mdc, 1); 84 realtek_smi_clk_delay(priv); 85 gpiod_set_value(priv->mdio, 1); 86 realtek_smi_clk_delay(priv); 87 gpiod_set_value(priv->mdc, 1); 88 realtek_smi_clk_delay(priv); 89 gpiod_set_value(priv->mdc, 0); 90 realtek_smi_clk_delay(priv); 91 gpiod_set_value(priv->mdc, 1); 92 93 /* Add a click */ 94 realtek_smi_clk_delay(priv); 95 gpiod_set_value(priv->mdc, 0); 96 realtek_smi_clk_delay(priv); 97 gpiod_set_value(priv->mdc, 1); 98 99 /* Set GPIO pins to input mode */ 100 gpiod_direction_input(priv->mdio); 101 gpiod_direction_input(priv->mdc); 102 } 103 104 static void realtek_smi_write_bits(struct realtek_priv *priv, u32 data, u32 len) 105 { 106 for (; len > 0; len--) { 107 realtek_smi_clk_delay(priv); 108 109 /* Prepare data */ 110 gpiod_set_value(priv->mdio, !!(data & (1 << (len - 1)))); 111 realtek_smi_clk_delay(priv); 112 113 /* Clocking */ 114 gpiod_set_value(priv->mdc, 1); 115 realtek_smi_clk_delay(priv); 116 gpiod_set_value(priv->mdc, 0); 117 } 118 } 119 120 static void realtek_smi_read_bits(struct realtek_priv *priv, u32 len, u32 *data) 121 { 122 gpiod_direction_input(priv->mdio); 123 124 for (*data = 0; len > 0; len--) { 125 u32 u; 126 127 realtek_smi_clk_delay(priv); 128 129 /* Clocking */ 130 gpiod_set_value(priv->mdc, 1); 131 realtek_smi_clk_delay(priv); 132 u = !!gpiod_get_value(priv->mdio); 133 gpiod_set_value(priv->mdc, 0); 134 135 *data |= (u << (len - 1)); 136 } 137 138 gpiod_direction_output(priv->mdio, 0); 139 } 140 141 static int realtek_smi_wait_for_ack(struct realtek_priv *priv) 142 { 143 int retry_cnt; 144 145 retry_cnt = 0; 146 do { 147 u32 ack; 148 149 realtek_smi_read_bits(priv, 1, &ack); 150 if (ack == 0) 151 break; 152 153 if (++retry_cnt > REALTEK_SMI_ACK_RETRY_COUNT) { 154 dev_err(priv->dev, "ACK timeout\n"); 155 return -ETIMEDOUT; 156 } 157 } while (1); 158 159 return 0; 160 } 161 162 static int realtek_smi_write_byte(struct realtek_priv *priv, u8 data) 163 { 164 realtek_smi_write_bits(priv, data, 8); 165 return realtek_smi_wait_for_ack(priv); 166 } 167 168 static int realtek_smi_write_byte_noack(struct realtek_priv *priv, u8 data) 169 { 170 realtek_smi_write_bits(priv, data, 8); 171 return 0; 172 } 173 174 static int realtek_smi_read_byte0(struct realtek_priv *priv, u8 *data) 175 { 176 u32 t; 177 178 /* Read data */ 179 realtek_smi_read_bits(priv, 8, &t); 180 *data = (t & 0xff); 181 182 /* Send an ACK */ 183 realtek_smi_write_bits(priv, 0x00, 1); 184 185 return 0; 186 } 187 188 static int realtek_smi_read_byte1(struct realtek_priv *priv, u8 *data) 189 { 190 u32 t; 191 192 /* Read data */ 193 realtek_smi_read_bits(priv, 8, &t); 194 *data = (t & 0xff); 195 196 /* Send an ACK */ 197 realtek_smi_write_bits(priv, 0x01, 1); 198 199 return 0; 200 } 201 202 static int realtek_smi_read_reg(struct realtek_priv *priv, u32 addr, u32 *data) 203 { 204 unsigned long flags; 205 u8 lo = 0; 206 u8 hi = 0; 207 int ret; 208 209 spin_lock_irqsave(&priv->lock, flags); 210 211 realtek_smi_start(priv); 212 213 /* Send READ command */ 214 ret = realtek_smi_write_byte(priv, priv->cmd_read); 215 if (ret) 216 goto out; 217 218 /* Set ADDR[7:0] */ 219 ret = realtek_smi_write_byte(priv, addr & 0xff); 220 if (ret) 221 goto out; 222 223 /* Set ADDR[15:8] */ 224 ret = realtek_smi_write_byte(priv, addr >> 8); 225 if (ret) 226 goto out; 227 228 /* Read DATA[7:0] */ 229 realtek_smi_read_byte0(priv, &lo); 230 /* Read DATA[15:8] */ 231 realtek_smi_read_byte1(priv, &hi); 232 233 *data = ((u32)lo) | (((u32)hi) << 8); 234 235 ret = 0; 236 237 out: 238 realtek_smi_stop(priv); 239 spin_unlock_irqrestore(&priv->lock, flags); 240 241 return ret; 242 } 243 244 static int realtek_smi_write_reg(struct realtek_priv *priv, 245 u32 addr, u32 data, bool ack) 246 { 247 unsigned long flags; 248 int ret; 249 250 spin_lock_irqsave(&priv->lock, flags); 251 252 realtek_smi_start(priv); 253 254 /* Send WRITE command */ 255 ret = realtek_smi_write_byte(priv, priv->cmd_write); 256 if (ret) 257 goto out; 258 259 /* Set ADDR[7:0] */ 260 ret = realtek_smi_write_byte(priv, addr & 0xff); 261 if (ret) 262 goto out; 263 264 /* Set ADDR[15:8] */ 265 ret = realtek_smi_write_byte(priv, addr >> 8); 266 if (ret) 267 goto out; 268 269 /* Write DATA[7:0] */ 270 ret = realtek_smi_write_byte(priv, data & 0xff); 271 if (ret) 272 goto out; 273 274 /* Write DATA[15:8] */ 275 if (ack) 276 ret = realtek_smi_write_byte(priv, data >> 8); 277 else 278 ret = realtek_smi_write_byte_noack(priv, data >> 8); 279 if (ret) 280 goto out; 281 282 ret = 0; 283 284 out: 285 realtek_smi_stop(priv); 286 spin_unlock_irqrestore(&priv->lock, flags); 287 288 return ret; 289 } 290 291 /* There is one single case when we need to use this accessor and that 292 * is when issueing soft reset. Since the device reset as soon as we write 293 * that bit, no ACK will come back for natural reasons. 294 */ 295 static int realtek_smi_write_reg_noack(void *ctx, u32 reg, u32 val) 296 { 297 return realtek_smi_write_reg(ctx, reg, val, false); 298 } 299 300 /* Regmap accessors */ 301 302 static int realtek_smi_write(void *ctx, u32 reg, u32 val) 303 { 304 struct realtek_priv *priv = ctx; 305 306 return realtek_smi_write_reg(priv, reg, val, true); 307 } 308 309 static int realtek_smi_read(void *ctx, u32 reg, u32 *val) 310 { 311 struct realtek_priv *priv = ctx; 312 313 return realtek_smi_read_reg(priv, reg, val); 314 } 315 316 static const struct regmap_config realtek_smi_mdio_regmap_config = { 317 .reg_bits = 10, /* A4..A0 R4..R0 */ 318 .val_bits = 16, 319 .reg_stride = 1, 320 /* PHY regs are at 0x8000 */ 321 .max_register = 0xffff, 322 .reg_format_endian = REGMAP_ENDIAN_BIG, 323 .reg_read = realtek_smi_read, 324 .reg_write = realtek_smi_write, 325 .cache_type = REGCACHE_NONE, 326 }; 327 328 static int realtek_smi_mdio_read(struct mii_bus *bus, int addr, int regnum) 329 { 330 struct realtek_priv *priv = bus->priv; 331 332 return priv->ops->phy_read(priv, addr, regnum); 333 } 334 335 static int realtek_smi_mdio_write(struct mii_bus *bus, int addr, int regnum, 336 u16 val) 337 { 338 struct realtek_priv *priv = bus->priv; 339 340 return priv->ops->phy_write(priv, addr, regnum, val); 341 } 342 343 static int realtek_smi_setup_mdio(struct dsa_switch *ds) 344 { 345 struct realtek_priv *priv = ds->priv; 346 struct device_node *mdio_np; 347 int ret; 348 349 mdio_np = of_get_compatible_child(priv->dev->of_node, "realtek,smi-mdio"); 350 if (!mdio_np) { 351 dev_err(priv->dev, "no MDIO bus node\n"); 352 return -ENODEV; 353 } 354 355 priv->slave_mii_bus = devm_mdiobus_alloc(priv->dev); 356 if (!priv->slave_mii_bus) { 357 ret = -ENOMEM; 358 goto err_put_node; 359 } 360 priv->slave_mii_bus->priv = priv; 361 priv->slave_mii_bus->name = "SMI slave MII"; 362 priv->slave_mii_bus->read = realtek_smi_mdio_read; 363 priv->slave_mii_bus->write = realtek_smi_mdio_write; 364 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "SMI-%d", 365 ds->index); 366 priv->slave_mii_bus->dev.of_node = mdio_np; 367 priv->slave_mii_bus->parent = priv->dev; 368 ds->slave_mii_bus = priv->slave_mii_bus; 369 370 ret = devm_of_mdiobus_register(priv->dev, priv->slave_mii_bus, mdio_np); 371 if (ret) { 372 dev_err(priv->dev, "unable to register MDIO bus %s\n", 373 priv->slave_mii_bus->id); 374 goto err_put_node; 375 } 376 377 return 0; 378 379 err_put_node: 380 of_node_put(mdio_np); 381 382 return ret; 383 } 384 385 static int realtek_smi_probe(struct platform_device *pdev) 386 { 387 const struct realtek_variant *var; 388 struct device *dev = &pdev->dev; 389 struct realtek_priv *priv; 390 struct device_node *np; 391 int ret; 392 393 var = of_device_get_match_data(dev); 394 np = dev->of_node; 395 396 priv = devm_kzalloc(dev, sizeof(*priv) + var->chip_data_sz, GFP_KERNEL); 397 if (!priv) 398 return -ENOMEM; 399 priv->chip_data = (void *)priv + sizeof(*priv); 400 priv->map = devm_regmap_init(dev, NULL, priv, 401 &realtek_smi_mdio_regmap_config); 402 if (IS_ERR(priv->map)) { 403 ret = PTR_ERR(priv->map); 404 dev_err(dev, "regmap init failed: %d\n", ret); 405 return ret; 406 } 407 408 /* Link forward and backward */ 409 priv->dev = dev; 410 priv->clk_delay = var->clk_delay; 411 priv->cmd_read = var->cmd_read; 412 priv->cmd_write = var->cmd_write; 413 priv->ops = var->ops; 414 415 priv->setup_interface = realtek_smi_setup_mdio; 416 priv->write_reg_noack = realtek_smi_write_reg_noack; 417 418 dev_set_drvdata(dev, priv); 419 spin_lock_init(&priv->lock); 420 421 /* TODO: if power is software controlled, set up any regulators here */ 422 423 /* Assert then deassert RESET */ 424 priv->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 425 if (IS_ERR(priv->reset)) { 426 dev_err(dev, "failed to get RESET GPIO\n"); 427 return PTR_ERR(priv->reset); 428 } 429 msleep(REALTEK_SMI_HW_STOP_DELAY); 430 gpiod_set_value(priv->reset, 0); 431 msleep(REALTEK_SMI_HW_START_DELAY); 432 dev_info(dev, "deasserted RESET\n"); 433 434 /* Fetch MDIO pins */ 435 priv->mdc = devm_gpiod_get_optional(dev, "mdc", GPIOD_OUT_LOW); 436 if (IS_ERR(priv->mdc)) 437 return PTR_ERR(priv->mdc); 438 priv->mdio = devm_gpiod_get_optional(dev, "mdio", GPIOD_OUT_LOW); 439 if (IS_ERR(priv->mdio)) 440 return PTR_ERR(priv->mdio); 441 442 priv->leds_disabled = of_property_read_bool(np, "realtek,disable-leds"); 443 444 ret = priv->ops->detect(priv); 445 if (ret) { 446 dev_err(dev, "unable to detect switch\n"); 447 return ret; 448 } 449 450 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 451 if (!priv->ds) 452 return -ENOMEM; 453 454 priv->ds->dev = dev; 455 priv->ds->num_ports = priv->num_ports; 456 priv->ds->priv = priv; 457 458 priv->ds->ops = var->ds_ops_smi; 459 ret = dsa_register_switch(priv->ds); 460 if (ret) { 461 dev_err_probe(dev, ret, "unable to register switch\n"); 462 return ret; 463 } 464 return 0; 465 } 466 467 static int realtek_smi_remove(struct platform_device *pdev) 468 { 469 struct realtek_priv *priv = platform_get_drvdata(pdev); 470 471 if (!priv) 472 return 0; 473 474 dsa_unregister_switch(priv->ds); 475 if (priv->slave_mii_bus) 476 of_node_put(priv->slave_mii_bus->dev.of_node); 477 gpiod_set_value(priv->reset, 1); 478 479 platform_set_drvdata(pdev, NULL); 480 481 return 0; 482 } 483 484 static void realtek_smi_shutdown(struct platform_device *pdev) 485 { 486 struct realtek_priv *priv = platform_get_drvdata(pdev); 487 488 if (!priv) 489 return; 490 491 dsa_switch_shutdown(priv->ds); 492 493 platform_set_drvdata(pdev, NULL); 494 } 495 496 static const struct of_device_id realtek_smi_of_match[] = { 497 #if IS_ENABLED(CONFIG_NET_DSA_REALTEK_RTL8366RB) 498 { 499 .compatible = "realtek,rtl8366rb", 500 .data = &rtl8366rb_variant, 501 }, 502 #endif 503 { 504 /* FIXME: add support for RTL8366S and more */ 505 .compatible = "realtek,rtl8366s", 506 .data = NULL, 507 }, 508 #if IS_ENABLED(CONFIG_NET_DSA_REALTEK_RTL8365MB) 509 { 510 .compatible = "realtek,rtl8365mb", 511 .data = &rtl8365mb_variant, 512 }, 513 { 514 .compatible = "realtek,rtl8367s", 515 .data = &rtl8365mb_variant, 516 }, 517 #endif 518 { /* sentinel */ }, 519 }; 520 MODULE_DEVICE_TABLE(of, realtek_smi_of_match); 521 522 static struct platform_driver realtek_smi_driver = { 523 .driver = { 524 .name = "realtek-smi", 525 .of_match_table = of_match_ptr(realtek_smi_of_match), 526 }, 527 .probe = realtek_smi_probe, 528 .remove = realtek_smi_remove, 529 .shutdown = realtek_smi_shutdown, 530 }; 531 module_platform_driver(realtek_smi_driver); 532 533 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>"); 534 MODULE_DESCRIPTION("Driver for Realtek ethernet switch connected via SMI interface"); 535 MODULE_LICENSE("GPL"); 536