1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2019 Pengutronix, Oleksij Rempel <kernel@pengutronix.de> 3 /* 4 * +----------------------+ 5 * GMAC1----RGMII----|--MAC0 | 6 * \---MDIO1----|--REGs |----MDIO3----\ 7 * | | | +------+ 8 * | | +--| | 9 * | MAC1-|----RMII--M-----| PHY0 |-o P0 10 * | | | | +------+ 11 * | | | +--| | 12 * | MAC2-|----RMII--------| PHY1 |-o P1 13 * | | | | +------+ 14 * | | | +--| | 15 * | MAC3-|----RMII--------| PHY2 |-o P2 16 * | | | | +------+ 17 * | | | +--| | 18 * | MAC4-|----RMII--------| PHY3 |-o P3 19 * | | | | +------+ 20 * | | | +--| | 21 * | MAC5-|--+-RMII--M-----|-PHY4-|-o P4 22 * | | | | +------+ 23 * +----------------------+ | \--CFG_SW_PHY_SWAP 24 * GMAC0---------------RMII--------------------/ \-CFG_SW_PHY_ADDR_SWAP 25 * \---MDIO0--NC 26 * 27 * GMAC0 and MAC5 are connected together and use same PHY. Depending on 28 * configuration it can be PHY4 (default) or PHY0. Only GMAC0 or MAC5 can be 29 * used at same time. If GMAC0 is used (default) then MAC5 should be disabled. 30 * 31 * CFG_SW_PHY_SWAP - swap connections of PHY0 and PHY4. If this bit is not set 32 * PHY4 is connected to GMAC0/MAC5 bundle and PHY0 is connected to MAC1. If this 33 * bit is set, PHY4 is connected to MAC1 and PHY0 is connected to GMAC0/MAC5 34 * bundle. 35 * 36 * CFG_SW_PHY_ADDR_SWAP - swap addresses of PHY0 and PHY4 37 * 38 * CFG_SW_PHY_SWAP and CFG_SW_PHY_ADDR_SWAP are part of SoC specific register 39 * set and not related to switch internal registers. 40 */ 41 42 #include <linux/bitfield.h> 43 #include <linux/module.h> 44 #include <linux/of_irq.h> 45 #include <linux/of_mdio.h> 46 #include <linux/regmap.h> 47 #include <linux/reset.h> 48 #include <net/dsa.h> 49 50 #define AR9331_SW_NAME "ar9331_switch" 51 #define AR9331_SW_PORTS 6 52 53 /* dummy reg to change page */ 54 #define AR9331_SW_REG_PAGE 0x40000 55 56 /* Global Interrupt */ 57 #define AR9331_SW_REG_GINT 0x10 58 #define AR9331_SW_REG_GINT_MASK 0x14 59 #define AR9331_SW_GINT_PHY_INT BIT(2) 60 61 #define AR9331_SW_REG_FLOOD_MASK 0x2c 62 #define AR9331_SW_FLOOD_MASK_BROAD_TO_CPU BIT(26) 63 64 #define AR9331_SW_REG_GLOBAL_CTRL 0x30 65 #define AR9331_SW_GLOBAL_CTRL_MFS_M GENMASK(13, 0) 66 67 #define AR9331_SW_REG_MDIO_CTRL 0x98 68 #define AR9331_SW_MDIO_CTRL_BUSY BIT(31) 69 #define AR9331_SW_MDIO_CTRL_MASTER_EN BIT(30) 70 #define AR9331_SW_MDIO_CTRL_CMD_READ BIT(27) 71 #define AR9331_SW_MDIO_CTRL_PHY_ADDR_M GENMASK(25, 21) 72 #define AR9331_SW_MDIO_CTRL_REG_ADDR_M GENMASK(20, 16) 73 #define AR9331_SW_MDIO_CTRL_DATA_M GENMASK(16, 0) 74 75 #define AR9331_SW_REG_PORT_STATUS(_port) (0x100 + (_port) * 0x100) 76 77 /* FLOW_LINK_EN - enable mac flow control config auto-neg with phy. 78 * If not set, mac can be config by software. 79 */ 80 #define AR9331_SW_PORT_STATUS_FLOW_LINK_EN BIT(12) 81 82 /* LINK_EN - If set, MAC is configured from PHY link status. 83 * If not set, MAC should be configured by software. 84 */ 85 #define AR9331_SW_PORT_STATUS_LINK_EN BIT(9) 86 #define AR9331_SW_PORT_STATUS_DUPLEX_MODE BIT(6) 87 #define AR9331_SW_PORT_STATUS_RX_FLOW_EN BIT(5) 88 #define AR9331_SW_PORT_STATUS_TX_FLOW_EN BIT(4) 89 #define AR9331_SW_PORT_STATUS_RXMAC BIT(3) 90 #define AR9331_SW_PORT_STATUS_TXMAC BIT(2) 91 #define AR9331_SW_PORT_STATUS_SPEED_M GENMASK(1, 0) 92 #define AR9331_SW_PORT_STATUS_SPEED_1000 2 93 #define AR9331_SW_PORT_STATUS_SPEED_100 1 94 #define AR9331_SW_PORT_STATUS_SPEED_10 0 95 96 #define AR9331_SW_PORT_STATUS_MAC_MASK \ 97 (AR9331_SW_PORT_STATUS_TXMAC | AR9331_SW_PORT_STATUS_RXMAC) 98 99 #define AR9331_SW_PORT_STATUS_LINK_MASK \ 100 (AR9331_SW_PORT_STATUS_DUPLEX_MODE | \ 101 AR9331_SW_PORT_STATUS_RX_FLOW_EN | AR9331_SW_PORT_STATUS_TX_FLOW_EN | \ 102 AR9331_SW_PORT_STATUS_SPEED_M) 103 104 #define AR9331_SW_REG_PORT_CTRL(_port) (0x104 + (_port) * 0x100) 105 #define AR9331_SW_PORT_CTRL_HEAD_EN BIT(11) 106 #define AR9331_SW_PORT_CTRL_PORT_STATE GENMASK(2, 0) 107 #define AR9331_SW_PORT_CTRL_PORT_STATE_DISABLED 0 108 #define AR9331_SW_PORT_CTRL_PORT_STATE_BLOCKING 1 109 #define AR9331_SW_PORT_CTRL_PORT_STATE_LISTENING 2 110 #define AR9331_SW_PORT_CTRL_PORT_STATE_LEARNING 3 111 #define AR9331_SW_PORT_CTRL_PORT_STATE_FORWARD 4 112 113 #define AR9331_SW_REG_PORT_VLAN(_port) (0x108 + (_port) * 0x100) 114 #define AR9331_SW_PORT_VLAN_8021Q_MODE GENMASK(31, 30) 115 #define AR9331_SW_8021Q_MODE_SECURE 3 116 #define AR9331_SW_8021Q_MODE_CHECK 2 117 #define AR9331_SW_8021Q_MODE_FALLBACK 1 118 #define AR9331_SW_8021Q_MODE_NONE 0 119 #define AR9331_SW_PORT_VLAN_PORT_VID_MEMBER GENMASK(25, 16) 120 121 /* MIB registers */ 122 #define AR9331_MIB_COUNTER(x) (0x20000 + ((x) * 0x100)) 123 124 /* Phy bypass mode 125 * ------------------------------------------------------------------------ 126 * Bit: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 | 127 * 128 * real | start | OP | PhyAddr | Reg Addr | TA | 129 * atheros| start | OP | 2'b00 |PhyAdd[2:0]| Reg Addr[4:0] | TA | 130 * 131 * 132 * Bit: |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 | 133 * real | Data | 134 * atheros| Data | 135 * 136 * ------------------------------------------------------------------------ 137 * Page address mode 138 * ------------------------------------------------------------------------ 139 * Bit: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 | 140 * real | start | OP | PhyAddr | Reg Addr | TA | 141 * atheros| start | OP | 2'b11 | 8'b0 | TA | 142 * 143 * Bit: |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 | 144 * real | Data | 145 * atheros| | Page [9:0] | 146 */ 147 /* In case of Page Address mode, Bit[18:9] of 32 bit register address should be 148 * written to bits[9:0] of mdio data register. 149 */ 150 #define AR9331_SW_ADDR_PAGE GENMASK(18, 9) 151 152 /* ------------------------------------------------------------------------ 153 * Normal register access mode 154 * ------------------------------------------------------------------------ 155 * Bit: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 | 156 * real | start | OP | PhyAddr | Reg Addr | TA | 157 * atheros| start | OP | 2'b10 | low_addr[7:0] | TA | 158 * 159 * Bit: |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 | 160 * real | Data | 161 * atheros| Data | 162 * ------------------------------------------------------------------------ 163 */ 164 #define AR9331_SW_LOW_ADDR_PHY GENMASK(8, 6) 165 #define AR9331_SW_LOW_ADDR_REG GENMASK(5, 1) 166 167 #define AR9331_SW_MDIO_PHY_MODE_M GENMASK(4, 3) 168 #define AR9331_SW_MDIO_PHY_MODE_PAGE 3 169 #define AR9331_SW_MDIO_PHY_MODE_REG 2 170 #define AR9331_SW_MDIO_PHY_MODE_BYPASS 0 171 #define AR9331_SW_MDIO_PHY_ADDR_M GENMASK(2, 0) 172 173 /* Empirical determined values */ 174 #define AR9331_SW_MDIO_POLL_SLEEP_US 1 175 #define AR9331_SW_MDIO_POLL_TIMEOUT_US 20 176 177 /* The interval should be small enough to avoid overflow of 32bit MIBs */ 178 /* 179 * FIXME: until we can read MIBs from stats64 call directly (i.e. sleep 180 * there), we have to poll stats more frequently then it is actually needed. 181 * For overflow protection, normally, 100 sec interval should have been OK. 182 */ 183 #define STATS_INTERVAL_JIFFIES (3 * HZ) 184 185 struct ar9331_sw_stats_raw { 186 u32 rxbroad; /* 0x00 */ 187 u32 rxpause; /* 0x04 */ 188 u32 rxmulti; /* 0x08 */ 189 u32 rxfcserr; /* 0x0c */ 190 u32 rxalignerr; /* 0x10 */ 191 u32 rxrunt; /* 0x14 */ 192 u32 rxfragment; /* 0x18 */ 193 u32 rx64byte; /* 0x1c */ 194 u32 rx128byte; /* 0x20 */ 195 u32 rx256byte; /* 0x24 */ 196 u32 rx512byte; /* 0x28 */ 197 u32 rx1024byte; /* 0x2c */ 198 u32 rx1518byte; /* 0x30 */ 199 u32 rxmaxbyte; /* 0x34 */ 200 u32 rxtoolong; /* 0x38 */ 201 u32 rxgoodbyte; /* 0x3c */ 202 u32 rxgoodbyte_hi; 203 u32 rxbadbyte; /* 0x44 */ 204 u32 rxbadbyte_hi; 205 u32 rxoverflow; /* 0x4c */ 206 u32 filtered; /* 0x50 */ 207 u32 txbroad; /* 0x54 */ 208 u32 txpause; /* 0x58 */ 209 u32 txmulti; /* 0x5c */ 210 u32 txunderrun; /* 0x60 */ 211 u32 tx64byte; /* 0x64 */ 212 u32 tx128byte; /* 0x68 */ 213 u32 tx256byte; /* 0x6c */ 214 u32 tx512byte; /* 0x70 */ 215 u32 tx1024byte; /* 0x74 */ 216 u32 tx1518byte; /* 0x78 */ 217 u32 txmaxbyte; /* 0x7c */ 218 u32 txoversize; /* 0x80 */ 219 u32 txbyte; /* 0x84 */ 220 u32 txbyte_hi; 221 u32 txcollision; /* 0x8c */ 222 u32 txabortcol; /* 0x90 */ 223 u32 txmulticol; /* 0x94 */ 224 u32 txsinglecol; /* 0x98 */ 225 u32 txexcdefer; /* 0x9c */ 226 u32 txdefer; /* 0xa0 */ 227 u32 txlatecol; /* 0xa4 */ 228 }; 229 230 struct ar9331_sw_port { 231 int idx; 232 struct delayed_work mib_read; 233 struct rtnl_link_stats64 stats; 234 struct ethtool_pause_stats pause_stats; 235 struct spinlock stats_lock; 236 }; 237 238 struct ar9331_sw_priv { 239 struct device *dev; 240 struct dsa_switch ds; 241 struct dsa_switch_ops ops; 242 struct irq_domain *irqdomain; 243 u32 irq_mask; 244 struct mutex lock_irq; 245 struct mii_bus *mbus; /* mdio master */ 246 struct mii_bus *sbus; /* mdio slave */ 247 struct regmap *regmap; 248 struct reset_control *sw_reset; 249 struct ar9331_sw_port port[AR9331_SW_PORTS]; 250 }; 251 252 static struct ar9331_sw_priv *ar9331_sw_port_to_priv(struct ar9331_sw_port *port) 253 { 254 struct ar9331_sw_port *p = port - port->idx; 255 256 return (struct ar9331_sw_priv *)((void *)p - 257 offsetof(struct ar9331_sw_priv, port)); 258 } 259 260 /* Warning: switch reset will reset last AR9331_SW_MDIO_PHY_MODE_PAGE request 261 * If some kind of optimization is used, the request should be repeated. 262 */ 263 static int ar9331_sw_reset(struct ar9331_sw_priv *priv) 264 { 265 int ret; 266 267 ret = reset_control_assert(priv->sw_reset); 268 if (ret) 269 goto error; 270 271 /* AR9331 doc do not provide any information about proper reset 272 * sequence. The AR8136 (the closes switch to the AR9331) doc says: 273 * reset duration should be greater than 10ms. So, let's use this value 274 * for now. 275 */ 276 usleep_range(10000, 15000); 277 ret = reset_control_deassert(priv->sw_reset); 278 if (ret) 279 goto error; 280 /* There is no information on how long should we wait after reset. 281 * AR8136 has an EEPROM and there is an Interrupt for EEPROM load 282 * status. AR9331 has no EEPROM support. 283 * For now, do not wait. In case AR8136 will be needed, the after 284 * reset delay can be added as well. 285 */ 286 287 return 0; 288 error: 289 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); 290 return ret; 291 } 292 293 static int ar9331_sw_mbus_write(struct mii_bus *mbus, int port, int regnum, 294 u16 data) 295 { 296 struct ar9331_sw_priv *priv = mbus->priv; 297 struct regmap *regmap = priv->regmap; 298 u32 val; 299 int ret; 300 301 ret = regmap_write(regmap, AR9331_SW_REG_MDIO_CTRL, 302 AR9331_SW_MDIO_CTRL_BUSY | 303 AR9331_SW_MDIO_CTRL_MASTER_EN | 304 FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) | 305 FIELD_PREP(AR9331_SW_MDIO_CTRL_REG_ADDR_M, regnum) | 306 FIELD_PREP(AR9331_SW_MDIO_CTRL_DATA_M, data)); 307 if (ret) 308 goto error; 309 310 ret = regmap_read_poll_timeout(regmap, AR9331_SW_REG_MDIO_CTRL, val, 311 !(val & AR9331_SW_MDIO_CTRL_BUSY), 312 AR9331_SW_MDIO_POLL_SLEEP_US, 313 AR9331_SW_MDIO_POLL_TIMEOUT_US); 314 if (ret) 315 goto error; 316 317 return 0; 318 error: 319 dev_err_ratelimited(priv->dev, "PHY write error: %i\n", ret); 320 return ret; 321 } 322 323 static int ar9331_sw_mbus_read(struct mii_bus *mbus, int port, int regnum) 324 { 325 struct ar9331_sw_priv *priv = mbus->priv; 326 struct regmap *regmap = priv->regmap; 327 u32 val; 328 int ret; 329 330 ret = regmap_write(regmap, AR9331_SW_REG_MDIO_CTRL, 331 AR9331_SW_MDIO_CTRL_BUSY | 332 AR9331_SW_MDIO_CTRL_MASTER_EN | 333 AR9331_SW_MDIO_CTRL_CMD_READ | 334 FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) | 335 FIELD_PREP(AR9331_SW_MDIO_CTRL_REG_ADDR_M, regnum)); 336 if (ret) 337 goto error; 338 339 ret = regmap_read_poll_timeout(regmap, AR9331_SW_REG_MDIO_CTRL, val, 340 !(val & AR9331_SW_MDIO_CTRL_BUSY), 341 AR9331_SW_MDIO_POLL_SLEEP_US, 342 AR9331_SW_MDIO_POLL_TIMEOUT_US); 343 if (ret) 344 goto error; 345 346 ret = regmap_read(regmap, AR9331_SW_REG_MDIO_CTRL, &val); 347 if (ret) 348 goto error; 349 350 return FIELD_GET(AR9331_SW_MDIO_CTRL_DATA_M, val); 351 352 error: 353 dev_err_ratelimited(priv->dev, "PHY read error: %i\n", ret); 354 return ret; 355 } 356 357 static int ar9331_sw_mbus_init(struct ar9331_sw_priv *priv) 358 { 359 struct device *dev = priv->dev; 360 struct mii_bus *mbus; 361 struct device_node *np, *mnp; 362 int ret; 363 364 np = dev->of_node; 365 366 mbus = devm_mdiobus_alloc(dev); 367 if (!mbus) 368 return -ENOMEM; 369 370 mbus->name = np->full_name; 371 snprintf(mbus->id, MII_BUS_ID_SIZE, "%pOF", np); 372 373 mbus->read = ar9331_sw_mbus_read; 374 mbus->write = ar9331_sw_mbus_write; 375 mbus->priv = priv; 376 mbus->parent = dev; 377 378 mnp = of_get_child_by_name(np, "mdio"); 379 if (!mnp) 380 return -ENODEV; 381 382 ret = devm_of_mdiobus_register(dev, mbus, mnp); 383 of_node_put(mnp); 384 if (ret) 385 return ret; 386 387 priv->mbus = mbus; 388 389 return 0; 390 } 391 392 static int ar9331_sw_setup_port(struct dsa_switch *ds, int port) 393 { 394 struct ar9331_sw_priv *priv = ds->priv; 395 struct regmap *regmap = priv->regmap; 396 u32 port_mask, port_ctrl, val; 397 int ret; 398 399 /* Generate default port settings */ 400 port_ctrl = FIELD_PREP(AR9331_SW_PORT_CTRL_PORT_STATE, 401 AR9331_SW_PORT_CTRL_PORT_STATE_FORWARD); 402 403 if (dsa_is_cpu_port(ds, port)) { 404 /* CPU port should be allowed to communicate with all user 405 * ports. 406 */ 407 port_mask = dsa_user_ports(ds); 408 /* Enable Atheros header on CPU port. This will allow us 409 * communicate with each port separately 410 */ 411 port_ctrl |= AR9331_SW_PORT_CTRL_HEAD_EN; 412 } else if (dsa_is_user_port(ds, port)) { 413 /* User ports should communicate only with the CPU port. 414 */ 415 port_mask = BIT(dsa_upstream_port(ds, port)); 416 } else { 417 /* Other ports do not need to communicate at all */ 418 port_mask = 0; 419 } 420 421 val = FIELD_PREP(AR9331_SW_PORT_VLAN_8021Q_MODE, 422 AR9331_SW_8021Q_MODE_NONE) | 423 FIELD_PREP(AR9331_SW_PORT_VLAN_PORT_VID_MEMBER, port_mask); 424 425 ret = regmap_write(regmap, AR9331_SW_REG_PORT_VLAN(port), val); 426 if (ret) 427 goto error; 428 429 ret = regmap_write(regmap, AR9331_SW_REG_PORT_CTRL(port), port_ctrl); 430 if (ret) 431 goto error; 432 433 return 0; 434 error: 435 dev_err(priv->dev, "%s: error: %i\n", __func__, ret); 436 437 return ret; 438 } 439 440 static int ar9331_sw_setup(struct dsa_switch *ds) 441 { 442 struct ar9331_sw_priv *priv = ds->priv; 443 struct regmap *regmap = priv->regmap; 444 int ret, i; 445 446 ret = ar9331_sw_reset(priv); 447 if (ret) 448 return ret; 449 450 /* Reset will set proper defaults. CPU - Port0 will be enabled and 451 * configured. All other ports (ports 1 - 5) are disabled 452 */ 453 ret = ar9331_sw_mbus_init(priv); 454 if (ret) 455 return ret; 456 457 /* Do not drop broadcast frames */ 458 ret = regmap_write_bits(regmap, AR9331_SW_REG_FLOOD_MASK, 459 AR9331_SW_FLOOD_MASK_BROAD_TO_CPU, 460 AR9331_SW_FLOOD_MASK_BROAD_TO_CPU); 461 if (ret) 462 goto error; 463 464 /* Set max frame size to the maximum supported value */ 465 ret = regmap_write_bits(regmap, AR9331_SW_REG_GLOBAL_CTRL, 466 AR9331_SW_GLOBAL_CTRL_MFS_M, 467 AR9331_SW_GLOBAL_CTRL_MFS_M); 468 if (ret) 469 goto error; 470 471 for (i = 0; i < ds->num_ports; i++) { 472 ret = ar9331_sw_setup_port(ds, i); 473 if (ret) 474 goto error; 475 } 476 477 ds->configure_vlan_while_not_filtering = false; 478 479 return 0; 480 error: 481 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); 482 return ret; 483 } 484 485 static void ar9331_sw_port_disable(struct dsa_switch *ds, int port) 486 { 487 struct ar9331_sw_priv *priv = ds->priv; 488 struct regmap *regmap = priv->regmap; 489 int ret; 490 491 ret = regmap_write(regmap, AR9331_SW_REG_PORT_STATUS(port), 0); 492 if (ret) 493 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); 494 } 495 496 static enum dsa_tag_protocol ar9331_sw_get_tag_protocol(struct dsa_switch *ds, 497 int port, 498 enum dsa_tag_protocol m) 499 { 500 return DSA_TAG_PROTO_AR9331; 501 } 502 503 static void ar9331_sw_phylink_get_caps(struct dsa_switch *ds, int port, 504 struct phylink_config *config) 505 { 506 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 507 MAC_10 | MAC_100; 508 509 switch (port) { 510 case 0: 511 __set_bit(PHY_INTERFACE_MODE_GMII, 512 config->supported_interfaces); 513 config->mac_capabilities |= MAC_1000; 514 break; 515 case 1: 516 case 2: 517 case 3: 518 case 4: 519 case 5: 520 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 521 config->supported_interfaces); 522 break; 523 } 524 } 525 526 static void ar9331_sw_phylink_mac_config(struct phylink_config *config, 527 unsigned int mode, 528 const struct phylink_link_state *state) 529 { 530 struct dsa_port *dp = dsa_phylink_to_port(config); 531 struct ar9331_sw_priv *priv = dp->ds->priv; 532 struct regmap *regmap = priv->regmap; 533 int ret; 534 535 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(dp->index), 536 AR9331_SW_PORT_STATUS_LINK_EN | 537 AR9331_SW_PORT_STATUS_FLOW_LINK_EN, 0); 538 if (ret) 539 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); 540 } 541 542 static void ar9331_sw_phylink_mac_link_down(struct phylink_config *config, 543 unsigned int mode, 544 phy_interface_t interface) 545 { 546 struct dsa_port *dp = dsa_phylink_to_port(config); 547 struct ar9331_sw_priv *priv = dp->ds->priv; 548 struct regmap *regmap = priv->regmap; 549 int port = dp->index; 550 int ret; 551 552 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port), 553 AR9331_SW_PORT_STATUS_MAC_MASK, 0); 554 if (ret) 555 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); 556 557 cancel_delayed_work_sync(&priv->port[port].mib_read); 558 } 559 560 static void ar9331_sw_phylink_mac_link_up(struct phylink_config *config, 561 struct phy_device *phydev, 562 unsigned int mode, 563 phy_interface_t interface, 564 int speed, int duplex, 565 bool tx_pause, bool rx_pause) 566 { 567 struct dsa_port *dp = dsa_phylink_to_port(config); 568 struct ar9331_sw_priv *priv = dp->ds->priv; 569 struct regmap *regmap = priv->regmap; 570 int port = dp->index; 571 u32 val; 572 int ret; 573 574 schedule_delayed_work(&priv->port[port].mib_read, 0); 575 576 val = AR9331_SW_PORT_STATUS_MAC_MASK; 577 switch (speed) { 578 case SPEED_1000: 579 val |= AR9331_SW_PORT_STATUS_SPEED_1000; 580 break; 581 case SPEED_100: 582 val |= AR9331_SW_PORT_STATUS_SPEED_100; 583 break; 584 case SPEED_10: 585 val |= AR9331_SW_PORT_STATUS_SPEED_10; 586 break; 587 default: 588 return; 589 } 590 591 if (duplex) 592 val |= AR9331_SW_PORT_STATUS_DUPLEX_MODE; 593 594 if (tx_pause) 595 val |= AR9331_SW_PORT_STATUS_TX_FLOW_EN; 596 597 if (rx_pause) 598 val |= AR9331_SW_PORT_STATUS_RX_FLOW_EN; 599 600 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port), 601 AR9331_SW_PORT_STATUS_MAC_MASK | 602 AR9331_SW_PORT_STATUS_LINK_MASK, 603 val); 604 if (ret) 605 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); 606 } 607 608 static void ar9331_read_stats(struct ar9331_sw_port *port) 609 { 610 struct ar9331_sw_priv *priv = ar9331_sw_port_to_priv(port); 611 struct ethtool_pause_stats *pstats = &port->pause_stats; 612 struct rtnl_link_stats64 *stats = &port->stats; 613 struct ar9331_sw_stats_raw raw; 614 int ret; 615 616 /* Do the slowest part first, to avoid needless locking for long time */ 617 ret = regmap_bulk_read(priv->regmap, AR9331_MIB_COUNTER(port->idx), 618 &raw, sizeof(raw) / sizeof(u32)); 619 if (ret) { 620 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); 621 return; 622 } 623 /* All MIB counters are cleared automatically on read */ 624 625 spin_lock(&port->stats_lock); 626 627 stats->rx_bytes += raw.rxgoodbyte; 628 stats->tx_bytes += raw.txbyte; 629 630 stats->rx_packets += raw.rx64byte + raw.rx128byte + raw.rx256byte + 631 raw.rx512byte + raw.rx1024byte + raw.rx1518byte + raw.rxmaxbyte; 632 stats->tx_packets += raw.tx64byte + raw.tx128byte + raw.tx256byte + 633 raw.tx512byte + raw.tx1024byte + raw.tx1518byte + raw.txmaxbyte; 634 635 stats->rx_length_errors += raw.rxrunt + raw.rxfragment + raw.rxtoolong; 636 stats->rx_crc_errors += raw.rxfcserr; 637 stats->rx_frame_errors += raw.rxalignerr; 638 stats->rx_missed_errors += raw.rxoverflow; 639 stats->rx_dropped += raw.filtered; 640 stats->rx_errors += raw.rxfcserr + raw.rxalignerr + raw.rxrunt + 641 raw.rxfragment + raw.rxoverflow + raw.rxtoolong; 642 643 stats->tx_window_errors += raw.txlatecol; 644 stats->tx_fifo_errors += raw.txunderrun; 645 stats->tx_aborted_errors += raw.txabortcol; 646 stats->tx_errors += raw.txoversize + raw.txabortcol + raw.txunderrun + 647 raw.txlatecol; 648 649 stats->multicast += raw.rxmulti; 650 stats->collisions += raw.txcollision; 651 652 pstats->tx_pause_frames += raw.txpause; 653 pstats->rx_pause_frames += raw.rxpause; 654 655 spin_unlock(&port->stats_lock); 656 } 657 658 static void ar9331_do_stats_poll(struct work_struct *work) 659 { 660 struct ar9331_sw_port *port = container_of(work, struct ar9331_sw_port, 661 mib_read.work); 662 663 ar9331_read_stats(port); 664 665 schedule_delayed_work(&port->mib_read, STATS_INTERVAL_JIFFIES); 666 } 667 668 static void ar9331_get_stats64(struct dsa_switch *ds, int port, 669 struct rtnl_link_stats64 *s) 670 { 671 struct ar9331_sw_priv *priv = ds->priv; 672 struct ar9331_sw_port *p = &priv->port[port]; 673 674 spin_lock(&p->stats_lock); 675 memcpy(s, &p->stats, sizeof(*s)); 676 spin_unlock(&p->stats_lock); 677 } 678 679 static void ar9331_get_pause_stats(struct dsa_switch *ds, int port, 680 struct ethtool_pause_stats *pause_stats) 681 { 682 struct ar9331_sw_priv *priv = ds->priv; 683 struct ar9331_sw_port *p = &priv->port[port]; 684 685 spin_lock(&p->stats_lock); 686 memcpy(pause_stats, &p->pause_stats, sizeof(*pause_stats)); 687 spin_unlock(&p->stats_lock); 688 } 689 690 static const struct phylink_mac_ops ar9331_phylink_mac_ops = { 691 .mac_config = ar9331_sw_phylink_mac_config, 692 .mac_link_down = ar9331_sw_phylink_mac_link_down, 693 .mac_link_up = ar9331_sw_phylink_mac_link_up, 694 }; 695 696 static const struct dsa_switch_ops ar9331_sw_ops = { 697 .get_tag_protocol = ar9331_sw_get_tag_protocol, 698 .setup = ar9331_sw_setup, 699 .port_disable = ar9331_sw_port_disable, 700 .phylink_get_caps = ar9331_sw_phylink_get_caps, 701 .get_stats64 = ar9331_get_stats64, 702 .get_pause_stats = ar9331_get_pause_stats, 703 }; 704 705 static irqreturn_t ar9331_sw_irq(int irq, void *data) 706 { 707 struct ar9331_sw_priv *priv = data; 708 struct regmap *regmap = priv->regmap; 709 u32 stat; 710 int ret; 711 712 ret = regmap_read(regmap, AR9331_SW_REG_GINT, &stat); 713 if (ret) { 714 dev_err(priv->dev, "can't read interrupt status\n"); 715 return IRQ_NONE; 716 } 717 718 if (!stat) 719 return IRQ_NONE; 720 721 if (stat & AR9331_SW_GINT_PHY_INT) { 722 int child_irq; 723 724 child_irq = irq_find_mapping(priv->irqdomain, 0); 725 handle_nested_irq(child_irq); 726 } 727 728 ret = regmap_write(regmap, AR9331_SW_REG_GINT, stat); 729 if (ret) { 730 dev_err(priv->dev, "can't write interrupt status\n"); 731 return IRQ_NONE; 732 } 733 734 return IRQ_HANDLED; 735 } 736 737 static void ar9331_sw_mask_irq(struct irq_data *d) 738 { 739 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d); 740 741 priv->irq_mask = 0; 742 } 743 744 static void ar9331_sw_unmask_irq(struct irq_data *d) 745 { 746 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d); 747 748 priv->irq_mask = AR9331_SW_GINT_PHY_INT; 749 } 750 751 static void ar9331_sw_irq_bus_lock(struct irq_data *d) 752 { 753 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d); 754 755 mutex_lock(&priv->lock_irq); 756 } 757 758 static void ar9331_sw_irq_bus_sync_unlock(struct irq_data *d) 759 { 760 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d); 761 struct regmap *regmap = priv->regmap; 762 int ret; 763 764 ret = regmap_update_bits(regmap, AR9331_SW_REG_GINT_MASK, 765 AR9331_SW_GINT_PHY_INT, priv->irq_mask); 766 if (ret) 767 dev_err(priv->dev, "failed to change IRQ mask\n"); 768 769 mutex_unlock(&priv->lock_irq); 770 } 771 772 static struct irq_chip ar9331_sw_irq_chip = { 773 .name = AR9331_SW_NAME, 774 .irq_mask = ar9331_sw_mask_irq, 775 .irq_unmask = ar9331_sw_unmask_irq, 776 .irq_bus_lock = ar9331_sw_irq_bus_lock, 777 .irq_bus_sync_unlock = ar9331_sw_irq_bus_sync_unlock, 778 }; 779 780 static int ar9331_sw_irq_map(struct irq_domain *domain, unsigned int irq, 781 irq_hw_number_t hwirq) 782 { 783 irq_set_chip_data(irq, domain->host_data); 784 irq_set_chip_and_handler(irq, &ar9331_sw_irq_chip, handle_simple_irq); 785 irq_set_nested_thread(irq, 1); 786 irq_set_noprobe(irq); 787 788 return 0; 789 } 790 791 static void ar9331_sw_irq_unmap(struct irq_domain *d, unsigned int irq) 792 { 793 irq_set_nested_thread(irq, 0); 794 irq_set_chip_and_handler(irq, NULL, NULL); 795 irq_set_chip_data(irq, NULL); 796 } 797 798 static const struct irq_domain_ops ar9331_sw_irqdomain_ops = { 799 .map = ar9331_sw_irq_map, 800 .unmap = ar9331_sw_irq_unmap, 801 .xlate = irq_domain_xlate_onecell, 802 }; 803 804 static int ar9331_sw_irq_init(struct ar9331_sw_priv *priv) 805 { 806 struct device_node *np = priv->dev->of_node; 807 struct device *dev = priv->dev; 808 int ret, irq; 809 810 irq = of_irq_get(np, 0); 811 if (irq <= 0) { 812 dev_err(dev, "failed to get parent IRQ\n"); 813 return irq ? irq : -EINVAL; 814 } 815 816 mutex_init(&priv->lock_irq); 817 ret = devm_request_threaded_irq(dev, irq, NULL, ar9331_sw_irq, 818 IRQF_ONESHOT, AR9331_SW_NAME, priv); 819 if (ret) { 820 dev_err(dev, "unable to request irq: %d\n", ret); 821 return ret; 822 } 823 824 priv->irqdomain = irq_domain_add_linear(np, 1, &ar9331_sw_irqdomain_ops, 825 priv); 826 if (!priv->irqdomain) { 827 dev_err(dev, "failed to create IRQ domain\n"); 828 return -EINVAL; 829 } 830 831 irq_set_parent(irq_create_mapping(priv->irqdomain, 0), irq); 832 833 return 0; 834 } 835 836 static int __ar9331_mdio_write(struct mii_bus *sbus, u8 mode, u16 reg, u16 val) 837 { 838 u8 r, p; 839 840 p = FIELD_PREP(AR9331_SW_MDIO_PHY_MODE_M, mode) | 841 FIELD_GET(AR9331_SW_LOW_ADDR_PHY, reg); 842 r = FIELD_GET(AR9331_SW_LOW_ADDR_REG, reg); 843 844 return __mdiobus_write(sbus, p, r, val); 845 } 846 847 static int __ar9331_mdio_read(struct mii_bus *sbus, u16 reg) 848 { 849 u8 r, p; 850 851 p = FIELD_PREP(AR9331_SW_MDIO_PHY_MODE_M, AR9331_SW_MDIO_PHY_MODE_REG) | 852 FIELD_GET(AR9331_SW_LOW_ADDR_PHY, reg); 853 r = FIELD_GET(AR9331_SW_LOW_ADDR_REG, reg); 854 855 return __mdiobus_read(sbus, p, r); 856 } 857 858 static int ar9331_mdio_read(void *ctx, const void *reg_buf, size_t reg_len, 859 void *val_buf, size_t val_len) 860 { 861 struct ar9331_sw_priv *priv = ctx; 862 struct mii_bus *sbus = priv->sbus; 863 u32 reg = *(u32 *)reg_buf; 864 int ret; 865 866 if (reg == AR9331_SW_REG_PAGE) { 867 /* We cannot read the page selector register from hardware and 868 * we cache its value in regmap. Return all bits set here, 869 * that regmap will always write the page on first use. 870 */ 871 *(u32 *)val_buf = GENMASK(9, 0); 872 return 0; 873 } 874 875 mutex_lock_nested(&sbus->mdio_lock, MDIO_MUTEX_NESTED); 876 877 ret = __ar9331_mdio_read(sbus, reg); 878 if (ret < 0) 879 goto error; 880 881 *(u32 *)val_buf = ret; 882 ret = __ar9331_mdio_read(sbus, reg + 2); 883 if (ret < 0) 884 goto error; 885 886 *(u32 *)val_buf |= ret << 16; 887 888 mutex_unlock(&sbus->mdio_lock); 889 890 return 0; 891 error: 892 mutex_unlock(&sbus->mdio_lock); 893 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to read register.\n"); 894 895 return ret; 896 } 897 898 static int ar9331_mdio_write(void *ctx, u32 reg, u32 val) 899 { 900 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ctx; 901 struct mii_bus *sbus = priv->sbus; 902 int ret; 903 904 mutex_lock_nested(&sbus->mdio_lock, MDIO_MUTEX_NESTED); 905 if (reg == AR9331_SW_REG_PAGE) { 906 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_PAGE, 907 0, val); 908 if (ret < 0) 909 goto error; 910 911 mutex_unlock(&sbus->mdio_lock); 912 913 return 0; 914 } 915 916 /* In case of this switch we work with 32bit registers on top of 16bit 917 * bus. Some registers (for example access to forwarding database) have 918 * trigger bit on the first 16bit half of request, the result and 919 * configuration of request in the second half. 920 * To make it work properly, we should do the second part of transfer 921 * before the first one is done. 922 */ 923 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg + 2, 924 val >> 16); 925 if (ret < 0) 926 goto error; 927 928 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg, val); 929 if (ret < 0) 930 goto error; 931 932 mutex_unlock(&sbus->mdio_lock); 933 934 return 0; 935 936 error: 937 mutex_unlock(&sbus->mdio_lock); 938 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to write register.\n"); 939 940 return ret; 941 } 942 943 static int ar9331_sw_bus_write(void *context, const void *data, size_t count) 944 { 945 u32 reg = *(u32 *)data; 946 u32 val = *((u32 *)data + 1); 947 948 return ar9331_mdio_write(context, reg, val); 949 } 950 951 static const struct regmap_range ar9331_valid_regs[] = { 952 regmap_reg_range(0x0, 0x0), 953 regmap_reg_range(0x10, 0x14), 954 regmap_reg_range(0x20, 0x24), 955 regmap_reg_range(0x2c, 0x30), 956 regmap_reg_range(0x40, 0x44), 957 regmap_reg_range(0x50, 0x78), 958 regmap_reg_range(0x80, 0x98), 959 960 regmap_reg_range(0x100, 0x120), 961 regmap_reg_range(0x200, 0x220), 962 regmap_reg_range(0x300, 0x320), 963 regmap_reg_range(0x400, 0x420), 964 regmap_reg_range(0x500, 0x520), 965 regmap_reg_range(0x600, 0x620), 966 967 regmap_reg_range(0x20000, 0x200a4), 968 regmap_reg_range(0x20100, 0x201a4), 969 regmap_reg_range(0x20200, 0x202a4), 970 regmap_reg_range(0x20300, 0x203a4), 971 regmap_reg_range(0x20400, 0x204a4), 972 regmap_reg_range(0x20500, 0x205a4), 973 974 /* dummy page selector reg */ 975 regmap_reg_range(AR9331_SW_REG_PAGE, AR9331_SW_REG_PAGE), 976 }; 977 978 static const struct regmap_range ar9331_nonvolatile_regs[] = { 979 regmap_reg_range(AR9331_SW_REG_PAGE, AR9331_SW_REG_PAGE), 980 }; 981 982 static const struct regmap_range_cfg ar9331_regmap_range[] = { 983 { 984 .selector_reg = AR9331_SW_REG_PAGE, 985 .selector_mask = GENMASK(9, 0), 986 .selector_shift = 0, 987 988 .window_start = 0, 989 .window_len = 512, 990 991 .range_min = 0, 992 .range_max = AR9331_SW_REG_PAGE - 4, 993 }, 994 }; 995 996 static const struct regmap_access_table ar9331_register_set = { 997 .yes_ranges = ar9331_valid_regs, 998 .n_yes_ranges = ARRAY_SIZE(ar9331_valid_regs), 999 }; 1000 1001 static const struct regmap_access_table ar9331_volatile_set = { 1002 .no_ranges = ar9331_nonvolatile_regs, 1003 .n_no_ranges = ARRAY_SIZE(ar9331_nonvolatile_regs), 1004 }; 1005 1006 static const struct regmap_config ar9331_mdio_regmap_config = { 1007 .reg_bits = 32, 1008 .val_bits = 32, 1009 .reg_stride = 4, 1010 .max_register = AR9331_SW_REG_PAGE, 1011 .use_single_read = true, 1012 .use_single_write = true, 1013 1014 .ranges = ar9331_regmap_range, 1015 .num_ranges = ARRAY_SIZE(ar9331_regmap_range), 1016 1017 .volatile_table = &ar9331_volatile_set, 1018 .wr_table = &ar9331_register_set, 1019 .rd_table = &ar9331_register_set, 1020 1021 .cache_type = REGCACHE_MAPLE, 1022 }; 1023 1024 static struct regmap_bus ar9331_sw_bus = { 1025 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE, 1026 .val_format_endian_default = REGMAP_ENDIAN_NATIVE, 1027 .read = ar9331_mdio_read, 1028 .write = ar9331_sw_bus_write, 1029 }; 1030 1031 static int ar9331_sw_probe(struct mdio_device *mdiodev) 1032 { 1033 struct ar9331_sw_priv *priv; 1034 struct dsa_switch *ds; 1035 int ret, i; 1036 1037 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 1038 if (!priv) 1039 return -ENOMEM; 1040 1041 priv->regmap = devm_regmap_init(&mdiodev->dev, &ar9331_sw_bus, priv, 1042 &ar9331_mdio_regmap_config); 1043 if (IS_ERR(priv->regmap)) { 1044 ret = PTR_ERR(priv->regmap); 1045 dev_err(&mdiodev->dev, "regmap init failed: %d\n", ret); 1046 return ret; 1047 } 1048 1049 priv->sw_reset = devm_reset_control_get(&mdiodev->dev, "switch"); 1050 if (IS_ERR(priv->sw_reset)) { 1051 dev_err(&mdiodev->dev, "missing switch reset\n"); 1052 return PTR_ERR(priv->sw_reset); 1053 } 1054 1055 priv->sbus = mdiodev->bus; 1056 priv->dev = &mdiodev->dev; 1057 1058 ret = ar9331_sw_irq_init(priv); 1059 if (ret) 1060 return ret; 1061 1062 ds = &priv->ds; 1063 ds->dev = &mdiodev->dev; 1064 ds->num_ports = AR9331_SW_PORTS; 1065 ds->priv = priv; 1066 priv->ops = ar9331_sw_ops; 1067 ds->ops = &priv->ops; 1068 ds->phylink_mac_ops = &ar9331_phylink_mac_ops; 1069 dev_set_drvdata(&mdiodev->dev, priv); 1070 1071 for (i = 0; i < ARRAY_SIZE(priv->port); i++) { 1072 struct ar9331_sw_port *port = &priv->port[i]; 1073 1074 port->idx = i; 1075 spin_lock_init(&port->stats_lock); 1076 INIT_DELAYED_WORK(&port->mib_read, ar9331_do_stats_poll); 1077 } 1078 1079 ret = dsa_register_switch(ds); 1080 if (ret) 1081 goto err_remove_irq; 1082 1083 return 0; 1084 1085 err_remove_irq: 1086 irq_domain_remove(priv->irqdomain); 1087 1088 return ret; 1089 } 1090 1091 static void ar9331_sw_remove(struct mdio_device *mdiodev) 1092 { 1093 struct ar9331_sw_priv *priv = dev_get_drvdata(&mdiodev->dev); 1094 unsigned int i; 1095 1096 if (!priv) 1097 return; 1098 1099 for (i = 0; i < ARRAY_SIZE(priv->port); i++) { 1100 struct ar9331_sw_port *port = &priv->port[i]; 1101 1102 cancel_delayed_work_sync(&port->mib_read); 1103 } 1104 1105 irq_domain_remove(priv->irqdomain); 1106 dsa_unregister_switch(&priv->ds); 1107 1108 reset_control_assert(priv->sw_reset); 1109 } 1110 1111 static void ar9331_sw_shutdown(struct mdio_device *mdiodev) 1112 { 1113 struct ar9331_sw_priv *priv = dev_get_drvdata(&mdiodev->dev); 1114 1115 if (!priv) 1116 return; 1117 1118 dsa_switch_shutdown(&priv->ds); 1119 1120 dev_set_drvdata(&mdiodev->dev, NULL); 1121 } 1122 1123 static const struct of_device_id ar9331_sw_of_match[] = { 1124 { .compatible = "qca,ar9331-switch" }, 1125 { }, 1126 }; 1127 1128 static struct mdio_driver ar9331_sw_mdio_driver = { 1129 .probe = ar9331_sw_probe, 1130 .remove = ar9331_sw_remove, 1131 .shutdown = ar9331_sw_shutdown, 1132 .mdiodrv.driver = { 1133 .name = AR9331_SW_NAME, 1134 .of_match_table = ar9331_sw_of_match, 1135 }, 1136 }; 1137 1138 mdio_module_driver(ar9331_sw_mdio_driver); 1139 1140 MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>"); 1141 MODULE_DESCRIPTION("Driver for Atheros AR9331 switch"); 1142 MODULE_LICENSE("GPL v2"); 1143