1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright 2017 Microsemi Corporation 3 * Copyright 2018-2019 NXP Semiconductors 4 */ 5 #include <linux/fsl/enetc_mdio.h> 6 #include <soc/mscc/ocelot_qsys.h> 7 #include <soc/mscc/ocelot_vcap.h> 8 #include <soc/mscc/ocelot_ptp.h> 9 #include <soc/mscc/ocelot_sys.h> 10 #include <soc/mscc/ocelot.h> 11 #include <linux/packing.h> 12 #include <net/pkt_sched.h> 13 #include <linux/iopoll.h> 14 #include <linux/pci.h> 15 #include "felix.h" 16 17 #define VSC9959_VCAP_IS2_CNT 1024 18 #define VSC9959_VCAP_IS2_ENTRY_WIDTH 376 19 #define VSC9959_VCAP_PORT_CNT 6 20 21 /* TODO: should find a better place for these */ 22 #define USXGMII_BMCR_RESET BIT(15) 23 #define USXGMII_BMCR_AN_EN BIT(12) 24 #define USXGMII_BMCR_RST_AN BIT(9) 25 #define USXGMII_BMSR_LNKS(status) (((status) & GENMASK(2, 2)) >> 2) 26 #define USXGMII_BMSR_AN_CMPL(status) (((status) & GENMASK(5, 5)) >> 5) 27 #define USXGMII_ADVERTISE_LNKS(x) (((x) << 15) & BIT(15)) 28 #define USXGMII_ADVERTISE_FDX BIT(12) 29 #define USXGMII_ADVERTISE_SPEED(x) (((x) << 9) & GENMASK(11, 9)) 30 #define USXGMII_LPA_LNKS(lpa) ((lpa) >> 15) 31 #define USXGMII_LPA_DUPLEX(lpa) (((lpa) & GENMASK(12, 12)) >> 12) 32 #define USXGMII_LPA_SPEED(lpa) (((lpa) & GENMASK(11, 9)) >> 9) 33 34 #define VSC9959_TAS_GCL_ENTRY_MAX 63 35 36 enum usxgmii_speed { 37 USXGMII_SPEED_10 = 0, 38 USXGMII_SPEED_100 = 1, 39 USXGMII_SPEED_1000 = 2, 40 USXGMII_SPEED_2500 = 4, 41 }; 42 43 static const u32 vsc9959_ana_regmap[] = { 44 REG(ANA_ADVLEARN, 0x0089a0), 45 REG(ANA_VLANMASK, 0x0089a4), 46 REG_RESERVED(ANA_PORT_B_DOMAIN), 47 REG(ANA_ANAGEFIL, 0x0089ac), 48 REG(ANA_ANEVENTS, 0x0089b0), 49 REG(ANA_STORMLIMIT_BURST, 0x0089b4), 50 REG(ANA_STORMLIMIT_CFG, 0x0089b8), 51 REG(ANA_ISOLATED_PORTS, 0x0089c8), 52 REG(ANA_COMMUNITY_PORTS, 0x0089cc), 53 REG(ANA_AUTOAGE, 0x0089d0), 54 REG(ANA_MACTOPTIONS, 0x0089d4), 55 REG(ANA_LEARNDISC, 0x0089d8), 56 REG(ANA_AGENCTRL, 0x0089dc), 57 REG(ANA_MIRRORPORTS, 0x0089e0), 58 REG(ANA_EMIRRORPORTS, 0x0089e4), 59 REG(ANA_FLOODING, 0x0089e8), 60 REG(ANA_FLOODING_IPMC, 0x008a08), 61 REG(ANA_SFLOW_CFG, 0x008a0c), 62 REG(ANA_PORT_MODE, 0x008a28), 63 REG(ANA_CUT_THRU_CFG, 0x008a48), 64 REG(ANA_PGID_PGID, 0x008400), 65 REG(ANA_TABLES_ANMOVED, 0x007f1c), 66 REG(ANA_TABLES_MACHDATA, 0x007f20), 67 REG(ANA_TABLES_MACLDATA, 0x007f24), 68 REG(ANA_TABLES_STREAMDATA, 0x007f28), 69 REG(ANA_TABLES_MACACCESS, 0x007f2c), 70 REG(ANA_TABLES_MACTINDX, 0x007f30), 71 REG(ANA_TABLES_VLANACCESS, 0x007f34), 72 REG(ANA_TABLES_VLANTIDX, 0x007f38), 73 REG(ANA_TABLES_ISDXACCESS, 0x007f3c), 74 REG(ANA_TABLES_ISDXTIDX, 0x007f40), 75 REG(ANA_TABLES_ENTRYLIM, 0x007f00), 76 REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44), 77 REG(ANA_TABLES_PTP_ID_LOW, 0x007f48), 78 REG(ANA_TABLES_STREAMACCESS, 0x007f4c), 79 REG(ANA_TABLES_STREAMTIDX, 0x007f50), 80 REG(ANA_TABLES_SEQ_HISTORY, 0x007f54), 81 REG(ANA_TABLES_SEQ_MASK, 0x007f58), 82 REG(ANA_TABLES_SFID_MASK, 0x007f5c), 83 REG(ANA_TABLES_SFIDACCESS, 0x007f60), 84 REG(ANA_TABLES_SFIDTIDX, 0x007f64), 85 REG(ANA_MSTI_STATE, 0x008600), 86 REG(ANA_OAM_UPM_LM_CNT, 0x008000), 87 REG(ANA_SG_ACCESS_CTRL, 0x008a64), 88 REG(ANA_SG_CONFIG_REG_1, 0x007fb0), 89 REG(ANA_SG_CONFIG_REG_2, 0x007fb4), 90 REG(ANA_SG_CONFIG_REG_3, 0x007fb8), 91 REG(ANA_SG_CONFIG_REG_4, 0x007fbc), 92 REG(ANA_SG_CONFIG_REG_5, 0x007fc0), 93 REG(ANA_SG_GCL_GS_CONFIG, 0x007f80), 94 REG(ANA_SG_GCL_TI_CONFIG, 0x007f90), 95 REG(ANA_SG_STATUS_REG_1, 0x008980), 96 REG(ANA_SG_STATUS_REG_2, 0x008984), 97 REG(ANA_SG_STATUS_REG_3, 0x008988), 98 REG(ANA_PORT_VLAN_CFG, 0x007800), 99 REG(ANA_PORT_DROP_CFG, 0x007804), 100 REG(ANA_PORT_QOS_CFG, 0x007808), 101 REG(ANA_PORT_VCAP_CFG, 0x00780c), 102 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810), 103 REG(ANA_PORT_VCAP_S2_CFG, 0x00781c), 104 REG(ANA_PORT_PCP_DEI_MAP, 0x007820), 105 REG(ANA_PORT_CPU_FWD_CFG, 0x007860), 106 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864), 107 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868), 108 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c), 109 REG(ANA_PORT_PORT_CFG, 0x007870), 110 REG(ANA_PORT_POL_CFG, 0x007874), 111 REG(ANA_PORT_PTP_CFG, 0x007878), 112 REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c), 113 REG(ANA_PORT_PTP_DLY2_CFG, 0x007880), 114 REG(ANA_PORT_SFID_CFG, 0x007884), 115 REG(ANA_PFC_PFC_CFG, 0x008800), 116 REG_RESERVED(ANA_PFC_PFC_TIMER), 117 REG_RESERVED(ANA_IPT_OAM_MEP_CFG), 118 REG_RESERVED(ANA_IPT_IPT), 119 REG_RESERVED(ANA_PPT_PPT), 120 REG_RESERVED(ANA_FID_MAP_FID_MAP), 121 REG(ANA_AGGR_CFG, 0x008a68), 122 REG(ANA_CPUQ_CFG, 0x008a6c), 123 REG_RESERVED(ANA_CPUQ_CFG2), 124 REG(ANA_CPUQ_8021_CFG, 0x008a74), 125 REG(ANA_DSCP_CFG, 0x008ab4), 126 REG(ANA_DSCP_REWR_CFG, 0x008bb4), 127 REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4), 128 REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14), 129 REG_RESERVED(ANA_VRAP_CFG), 130 REG_RESERVED(ANA_VRAP_HDR_DATA), 131 REG_RESERVED(ANA_VRAP_HDR_MASK), 132 REG(ANA_DISCARD_CFG, 0x008c40), 133 REG(ANA_FID_CFG, 0x008c44), 134 REG(ANA_POL_PIR_CFG, 0x004000), 135 REG(ANA_POL_CIR_CFG, 0x004004), 136 REG(ANA_POL_MODE_CFG, 0x004008), 137 REG(ANA_POL_PIR_STATE, 0x00400c), 138 REG(ANA_POL_CIR_STATE, 0x004010), 139 REG_RESERVED(ANA_POL_STATE), 140 REG(ANA_POL_FLOWC, 0x008c48), 141 REG(ANA_POL_HYST, 0x008cb4), 142 REG_RESERVED(ANA_POL_MISC_CFG), 143 }; 144 145 static const u32 vsc9959_qs_regmap[] = { 146 REG(QS_XTR_GRP_CFG, 0x000000), 147 REG(QS_XTR_RD, 0x000008), 148 REG(QS_XTR_FRM_PRUNING, 0x000010), 149 REG(QS_XTR_FLUSH, 0x000018), 150 REG(QS_XTR_DATA_PRESENT, 0x00001c), 151 REG(QS_XTR_CFG, 0x000020), 152 REG(QS_INJ_GRP_CFG, 0x000024), 153 REG(QS_INJ_WR, 0x00002c), 154 REG(QS_INJ_CTRL, 0x000034), 155 REG(QS_INJ_STATUS, 0x00003c), 156 REG(QS_INJ_ERR, 0x000040), 157 REG_RESERVED(QS_INH_DBG), 158 }; 159 160 static const u32 vsc9959_s2_regmap[] = { 161 REG(S2_CORE_UPDATE_CTRL, 0x000000), 162 REG(S2_CORE_MV_CFG, 0x000004), 163 REG(S2_CACHE_ENTRY_DAT, 0x000008), 164 REG(S2_CACHE_MASK_DAT, 0x000108), 165 REG(S2_CACHE_ACTION_DAT, 0x000208), 166 REG(S2_CACHE_CNT_DAT, 0x000308), 167 REG(S2_CACHE_TG_DAT, 0x000388), 168 }; 169 170 static const u32 vsc9959_qsys_regmap[] = { 171 REG(QSYS_PORT_MODE, 0x00f460), 172 REG(QSYS_SWITCH_PORT_MODE, 0x00f480), 173 REG(QSYS_STAT_CNT_CFG, 0x00f49c), 174 REG(QSYS_EEE_CFG, 0x00f4a0), 175 REG(QSYS_EEE_THRES, 0x00f4b8), 176 REG(QSYS_IGR_NO_SHARING, 0x00f4bc), 177 REG(QSYS_EGR_NO_SHARING, 0x00f4c0), 178 REG(QSYS_SW_STATUS, 0x00f4c4), 179 REG(QSYS_EXT_CPU_CFG, 0x00f4e0), 180 REG_RESERVED(QSYS_PAD_CFG), 181 REG(QSYS_CPU_GROUP_MAP, 0x00f4e8), 182 REG_RESERVED(QSYS_QMAP), 183 REG_RESERVED(QSYS_ISDX_SGRP), 184 REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), 185 REG(QSYS_TFRM_MISC, 0x00f50c), 186 REG(QSYS_TFRM_PORT_DLY, 0x00f510), 187 REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514), 188 REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518), 189 REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c), 190 REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520), 191 REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524), 192 REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528), 193 REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c), 194 REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530), 195 REG(QSYS_RED_PROFILE, 0x00f534), 196 REG(QSYS_RES_QOS_MODE, 0x00f574), 197 REG(QSYS_RES_CFG, 0x00c000), 198 REG(QSYS_RES_STAT, 0x00c004), 199 REG(QSYS_EGR_DROP_MODE, 0x00f578), 200 REG(QSYS_EQ_CTRL, 0x00f57c), 201 REG_RESERVED(QSYS_EVENTS_CORE), 202 REG(QSYS_QMAXSDU_CFG_0, 0x00f584), 203 REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0), 204 REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc), 205 REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8), 206 REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4), 207 REG(QSYS_QMAXSDU_CFG_5, 0x00f610), 208 REG(QSYS_QMAXSDU_CFG_6, 0x00f62c), 209 REG(QSYS_QMAXSDU_CFG_7, 0x00f648), 210 REG(QSYS_PREEMPTION_CFG, 0x00f664), 211 REG(QSYS_CIR_CFG, 0x000000), 212 REG(QSYS_EIR_CFG, 0x000004), 213 REG(QSYS_SE_CFG, 0x000008), 214 REG(QSYS_SE_DWRR_CFG, 0x00000c), 215 REG_RESERVED(QSYS_SE_CONNECT), 216 REG(QSYS_SE_DLB_SENSE, 0x000040), 217 REG(QSYS_CIR_STATE, 0x000044), 218 REG(QSYS_EIR_STATE, 0x000048), 219 REG_RESERVED(QSYS_SE_STATE), 220 REG(QSYS_HSCH_MISC_CFG, 0x00f67c), 221 REG(QSYS_TAG_CONFIG, 0x00f680), 222 REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698), 223 REG(QSYS_PORT_MAX_SDU, 0x00f69c), 224 REG(QSYS_PARAM_CFG_REG_1, 0x00f440), 225 REG(QSYS_PARAM_CFG_REG_2, 0x00f444), 226 REG(QSYS_PARAM_CFG_REG_3, 0x00f448), 227 REG(QSYS_PARAM_CFG_REG_4, 0x00f44c), 228 REG(QSYS_PARAM_CFG_REG_5, 0x00f450), 229 REG(QSYS_GCL_CFG_REG_1, 0x00f454), 230 REG(QSYS_GCL_CFG_REG_2, 0x00f458), 231 REG(QSYS_PARAM_STATUS_REG_1, 0x00f400), 232 REG(QSYS_PARAM_STATUS_REG_2, 0x00f404), 233 REG(QSYS_PARAM_STATUS_REG_3, 0x00f408), 234 REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c), 235 REG(QSYS_PARAM_STATUS_REG_5, 0x00f410), 236 REG(QSYS_PARAM_STATUS_REG_6, 0x00f414), 237 REG(QSYS_PARAM_STATUS_REG_7, 0x00f418), 238 REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c), 239 REG(QSYS_PARAM_STATUS_REG_9, 0x00f420), 240 REG(QSYS_GCL_STATUS_REG_1, 0x00f424), 241 REG(QSYS_GCL_STATUS_REG_2, 0x00f428), 242 }; 243 244 static const u32 vsc9959_rew_regmap[] = { 245 REG(REW_PORT_VLAN_CFG, 0x000000), 246 REG(REW_TAG_CFG, 0x000004), 247 REG(REW_PORT_CFG, 0x000008), 248 REG(REW_DSCP_CFG, 0x00000c), 249 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 250 REG(REW_PTP_CFG, 0x000050), 251 REG(REW_PTP_DLY1_CFG, 0x000054), 252 REG(REW_RED_TAG_CFG, 0x000058), 253 REG(REW_DSCP_REMAP_DP1_CFG, 0x000410), 254 REG(REW_DSCP_REMAP_CFG, 0x000510), 255 REG_RESERVED(REW_STAT_CFG), 256 REG_RESERVED(REW_REW_STICKY), 257 REG_RESERVED(REW_PPT), 258 }; 259 260 static const u32 vsc9959_sys_regmap[] = { 261 REG(SYS_COUNT_RX_OCTETS, 0x000000), 262 REG(SYS_COUNT_RX_MULTICAST, 0x000008), 263 REG(SYS_COUNT_RX_SHORTS, 0x000010), 264 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 265 REG(SYS_COUNT_RX_JABBERS, 0x000018), 266 REG(SYS_COUNT_RX_64, 0x000024), 267 REG(SYS_COUNT_RX_65_127, 0x000028), 268 REG(SYS_COUNT_RX_128_255, 0x00002c), 269 REG(SYS_COUNT_RX_256_1023, 0x000030), 270 REG(SYS_COUNT_RX_1024_1526, 0x000034), 271 REG(SYS_COUNT_RX_1527_MAX, 0x000038), 272 REG(SYS_COUNT_RX_LONGS, 0x000044), 273 REG(SYS_COUNT_TX_OCTETS, 0x000200), 274 REG(SYS_COUNT_TX_COLLISION, 0x000210), 275 REG(SYS_COUNT_TX_DROPS, 0x000214), 276 REG(SYS_COUNT_TX_64, 0x00021c), 277 REG(SYS_COUNT_TX_65_127, 0x000220), 278 REG(SYS_COUNT_TX_128_511, 0x000224), 279 REG(SYS_COUNT_TX_512_1023, 0x000228), 280 REG(SYS_COUNT_TX_1024_1526, 0x00022c), 281 REG(SYS_COUNT_TX_1527_MAX, 0x000230), 282 REG(SYS_COUNT_TX_AGING, 0x000278), 283 REG(SYS_RESET_CFG, 0x000e00), 284 REG(SYS_SR_ETYPE_CFG, 0x000e04), 285 REG(SYS_VLAN_ETYPE_CFG, 0x000e08), 286 REG(SYS_PORT_MODE, 0x000e0c), 287 REG(SYS_FRONT_PORT_MODE, 0x000e2c), 288 REG(SYS_FRM_AGING, 0x000e44), 289 REG(SYS_STAT_CFG, 0x000e48), 290 REG(SYS_SW_STATUS, 0x000e4c), 291 REG_RESERVED(SYS_MISC_CFG), 292 REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c), 293 REG(SYS_REW_MAC_LOW_CFG, 0x000e84), 294 REG(SYS_TIMESTAMP_OFFSET, 0x000e9c), 295 REG(SYS_PAUSE_CFG, 0x000ea0), 296 REG(SYS_PAUSE_TOT_CFG, 0x000ebc), 297 REG(SYS_ATOP, 0x000ec0), 298 REG(SYS_ATOP_TOT_CFG, 0x000edc), 299 REG(SYS_MAC_FC_CFG, 0x000ee0), 300 REG(SYS_MMGT, 0x000ef8), 301 REG_RESERVED(SYS_MMGT_FAST), 302 REG_RESERVED(SYS_EVENTS_DIF), 303 REG_RESERVED(SYS_EVENTS_CORE), 304 REG_RESERVED(SYS_CNT), 305 REG(SYS_PTP_STATUS, 0x000f14), 306 REG(SYS_PTP_TXSTAMP, 0x000f18), 307 REG(SYS_PTP_NXT, 0x000f1c), 308 REG(SYS_PTP_CFG, 0x000f20), 309 REG(SYS_RAM_INIT, 0x000f24), 310 REG_RESERVED(SYS_CM_ADDR), 311 REG_RESERVED(SYS_CM_DATA_WR), 312 REG_RESERVED(SYS_CM_DATA_RD), 313 REG_RESERVED(SYS_CM_OP), 314 REG_RESERVED(SYS_CM_DATA), 315 }; 316 317 static const u32 vsc9959_ptp_regmap[] = { 318 REG(PTP_PIN_CFG, 0x000000), 319 REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 320 REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 321 REG(PTP_PIN_TOD_NSEC, 0x00000c), 322 REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 323 REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 324 REG(PTP_CFG_MISC, 0x0000a0), 325 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 326 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 327 }; 328 329 static const u32 vsc9959_gcb_regmap[] = { 330 REG(GCB_SOFT_RST, 0x000004), 331 }; 332 333 static const u32 vsc9959_dev_gmii_regmap[] = { 334 REG(DEV_CLOCK_CFG, 0x0), 335 REG(DEV_PORT_MISC, 0x4), 336 REG(DEV_EVENTS, 0x8), 337 REG(DEV_EEE_CFG, 0xc), 338 REG(DEV_RX_PATH_DELAY, 0x10), 339 REG(DEV_TX_PATH_DELAY, 0x14), 340 REG(DEV_PTP_PREDICT_CFG, 0x18), 341 REG(DEV_MAC_ENA_CFG, 0x1c), 342 REG(DEV_MAC_MODE_CFG, 0x20), 343 REG(DEV_MAC_MAXLEN_CFG, 0x24), 344 REG(DEV_MAC_TAGS_CFG, 0x28), 345 REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 346 REG(DEV_MAC_IFG_CFG, 0x30), 347 REG(DEV_MAC_HDX_CFG, 0x34), 348 REG(DEV_MAC_DBG_CFG, 0x38), 349 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 350 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 351 REG(DEV_MAC_STICKY, 0x44), 352 REG_RESERVED(PCS1G_CFG), 353 REG_RESERVED(PCS1G_MODE_CFG), 354 REG_RESERVED(PCS1G_SD_CFG), 355 REG_RESERVED(PCS1G_ANEG_CFG), 356 REG_RESERVED(PCS1G_ANEG_NP_CFG), 357 REG_RESERVED(PCS1G_LB_CFG), 358 REG_RESERVED(PCS1G_DBG_CFG), 359 REG_RESERVED(PCS1G_CDET_CFG), 360 REG_RESERVED(PCS1G_ANEG_STATUS), 361 REG_RESERVED(PCS1G_ANEG_NP_STATUS), 362 REG_RESERVED(PCS1G_LINK_STATUS), 363 REG_RESERVED(PCS1G_LINK_DOWN_CNT), 364 REG_RESERVED(PCS1G_STICKY), 365 REG_RESERVED(PCS1G_DEBUG_STATUS), 366 REG_RESERVED(PCS1G_LPI_CFG), 367 REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT), 368 REG_RESERVED(PCS1G_LPI_STATUS), 369 REG_RESERVED(PCS1G_TSTPAT_MODE_CFG), 370 REG_RESERVED(PCS1G_TSTPAT_STATUS), 371 REG_RESERVED(DEV_PCS_FX100_CFG), 372 REG_RESERVED(DEV_PCS_FX100_STATUS), 373 }; 374 375 static const u32 *vsc9959_regmap[TARGET_MAX] = { 376 [ANA] = vsc9959_ana_regmap, 377 [QS] = vsc9959_qs_regmap, 378 [QSYS] = vsc9959_qsys_regmap, 379 [REW] = vsc9959_rew_regmap, 380 [SYS] = vsc9959_sys_regmap, 381 [S2] = vsc9959_s2_regmap, 382 [PTP] = vsc9959_ptp_regmap, 383 [GCB] = vsc9959_gcb_regmap, 384 [DEV_GMII] = vsc9959_dev_gmii_regmap, 385 }; 386 387 /* Addresses are relative to the PCI device's base address */ 388 static const struct resource vsc9959_target_io_res[TARGET_MAX] = { 389 [ANA] = { 390 .start = 0x0280000, 391 .end = 0x028ffff, 392 .name = "ana", 393 }, 394 [QS] = { 395 .start = 0x0080000, 396 .end = 0x00800ff, 397 .name = "qs", 398 }, 399 [QSYS] = { 400 .start = 0x0200000, 401 .end = 0x021ffff, 402 .name = "qsys", 403 }, 404 [REW] = { 405 .start = 0x0030000, 406 .end = 0x003ffff, 407 .name = "rew", 408 }, 409 [SYS] = { 410 .start = 0x0010000, 411 .end = 0x001ffff, 412 .name = "sys", 413 }, 414 [S2] = { 415 .start = 0x0060000, 416 .end = 0x00603ff, 417 .name = "s2", 418 }, 419 [PTP] = { 420 .start = 0x0090000, 421 .end = 0x00900cb, 422 .name = "ptp", 423 }, 424 [GCB] = { 425 .start = 0x0070000, 426 .end = 0x00701ff, 427 .name = "devcpu_gcb", 428 }, 429 }; 430 431 static const struct resource vsc9959_port_io_res[] = { 432 { 433 .start = 0x0100000, 434 .end = 0x010ffff, 435 .name = "port0", 436 }, 437 { 438 .start = 0x0110000, 439 .end = 0x011ffff, 440 .name = "port1", 441 }, 442 { 443 .start = 0x0120000, 444 .end = 0x012ffff, 445 .name = "port2", 446 }, 447 { 448 .start = 0x0130000, 449 .end = 0x013ffff, 450 .name = "port3", 451 }, 452 { 453 .start = 0x0140000, 454 .end = 0x014ffff, 455 .name = "port4", 456 }, 457 { 458 .start = 0x0150000, 459 .end = 0x015ffff, 460 .name = "port5", 461 }, 462 }; 463 464 /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an 465 * SGMII/QSGMII MAC PCS can be found. 466 */ 467 static const struct resource vsc9959_imdio_res = { 468 .start = 0x8030, 469 .end = 0x8040, 470 .name = "imdio", 471 }; 472 473 static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = { 474 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), 475 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5), 476 [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30), 477 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26), 478 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24), 479 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23), 480 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22), 481 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21), 482 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20), 483 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19), 484 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 485 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17), 486 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15), 487 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14), 488 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13), 489 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12), 490 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 491 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 492 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9), 493 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8), 494 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7), 495 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 496 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 497 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4), 498 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3), 499 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2), 500 [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1), 501 [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0), 502 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), 503 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), 504 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), 505 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0), 506 [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), 507 /* Replicated per number of ports (7), register size 4 per port */ 508 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4), 509 [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4), 510 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4), 511 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4), 512 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4), 513 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4), 514 [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4), 515 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4), 516 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4), 517 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4), 518 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4), 519 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4), 520 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4), 521 }; 522 523 static const struct ocelot_stat_layout vsc9959_stats_layout[] = { 524 { .offset = 0x00, .name = "rx_octets", }, 525 { .offset = 0x01, .name = "rx_unicast", }, 526 { .offset = 0x02, .name = "rx_multicast", }, 527 { .offset = 0x03, .name = "rx_broadcast", }, 528 { .offset = 0x04, .name = "rx_shorts", }, 529 { .offset = 0x05, .name = "rx_fragments", }, 530 { .offset = 0x06, .name = "rx_jabbers", }, 531 { .offset = 0x07, .name = "rx_crc_align_errs", }, 532 { .offset = 0x08, .name = "rx_sym_errs", }, 533 { .offset = 0x09, .name = "rx_frames_below_65_octets", }, 534 { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", }, 535 { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", }, 536 { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", }, 537 { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", }, 538 { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", }, 539 { .offset = 0x0F, .name = "rx_frames_over_1526_octets", }, 540 { .offset = 0x10, .name = "rx_pause", }, 541 { .offset = 0x11, .name = "rx_control", }, 542 { .offset = 0x12, .name = "rx_longs", }, 543 { .offset = 0x13, .name = "rx_classified_drops", }, 544 { .offset = 0x14, .name = "rx_red_prio_0", }, 545 { .offset = 0x15, .name = "rx_red_prio_1", }, 546 { .offset = 0x16, .name = "rx_red_prio_2", }, 547 { .offset = 0x17, .name = "rx_red_prio_3", }, 548 { .offset = 0x18, .name = "rx_red_prio_4", }, 549 { .offset = 0x19, .name = "rx_red_prio_5", }, 550 { .offset = 0x1A, .name = "rx_red_prio_6", }, 551 { .offset = 0x1B, .name = "rx_red_prio_7", }, 552 { .offset = 0x1C, .name = "rx_yellow_prio_0", }, 553 { .offset = 0x1D, .name = "rx_yellow_prio_1", }, 554 { .offset = 0x1E, .name = "rx_yellow_prio_2", }, 555 { .offset = 0x1F, .name = "rx_yellow_prio_3", }, 556 { .offset = 0x20, .name = "rx_yellow_prio_4", }, 557 { .offset = 0x21, .name = "rx_yellow_prio_5", }, 558 { .offset = 0x22, .name = "rx_yellow_prio_6", }, 559 { .offset = 0x23, .name = "rx_yellow_prio_7", }, 560 { .offset = 0x24, .name = "rx_green_prio_0", }, 561 { .offset = 0x25, .name = "rx_green_prio_1", }, 562 { .offset = 0x26, .name = "rx_green_prio_2", }, 563 { .offset = 0x27, .name = "rx_green_prio_3", }, 564 { .offset = 0x28, .name = "rx_green_prio_4", }, 565 { .offset = 0x29, .name = "rx_green_prio_5", }, 566 { .offset = 0x2A, .name = "rx_green_prio_6", }, 567 { .offset = 0x2B, .name = "rx_green_prio_7", }, 568 { .offset = 0x80, .name = "tx_octets", }, 569 { .offset = 0x81, .name = "tx_unicast", }, 570 { .offset = 0x82, .name = "tx_multicast", }, 571 { .offset = 0x83, .name = "tx_broadcast", }, 572 { .offset = 0x84, .name = "tx_collision", }, 573 { .offset = 0x85, .name = "tx_drops", }, 574 { .offset = 0x86, .name = "tx_pause", }, 575 { .offset = 0x87, .name = "tx_frames_below_65_octets", }, 576 { .offset = 0x88, .name = "tx_frames_65_to_127_octets", }, 577 { .offset = 0x89, .name = "tx_frames_128_255_octets", }, 578 { .offset = 0x8B, .name = "tx_frames_256_511_octets", }, 579 { .offset = 0x8C, .name = "tx_frames_1024_1526_octets", }, 580 { .offset = 0x8D, .name = "tx_frames_over_1526_octets", }, 581 { .offset = 0x8E, .name = "tx_yellow_prio_0", }, 582 { .offset = 0x8F, .name = "tx_yellow_prio_1", }, 583 { .offset = 0x90, .name = "tx_yellow_prio_2", }, 584 { .offset = 0x91, .name = "tx_yellow_prio_3", }, 585 { .offset = 0x92, .name = "tx_yellow_prio_4", }, 586 { .offset = 0x93, .name = "tx_yellow_prio_5", }, 587 { .offset = 0x94, .name = "tx_yellow_prio_6", }, 588 { .offset = 0x95, .name = "tx_yellow_prio_7", }, 589 { .offset = 0x96, .name = "tx_green_prio_0", }, 590 { .offset = 0x97, .name = "tx_green_prio_1", }, 591 { .offset = 0x98, .name = "tx_green_prio_2", }, 592 { .offset = 0x99, .name = "tx_green_prio_3", }, 593 { .offset = 0x9A, .name = "tx_green_prio_4", }, 594 { .offset = 0x9B, .name = "tx_green_prio_5", }, 595 { .offset = 0x9C, .name = "tx_green_prio_6", }, 596 { .offset = 0x9D, .name = "tx_green_prio_7", }, 597 { .offset = 0x9E, .name = "tx_aged", }, 598 { .offset = 0x100, .name = "drop_local", }, 599 { .offset = 0x101, .name = "drop_tail", }, 600 { .offset = 0x102, .name = "drop_yellow_prio_0", }, 601 { .offset = 0x103, .name = "drop_yellow_prio_1", }, 602 { .offset = 0x104, .name = "drop_yellow_prio_2", }, 603 { .offset = 0x105, .name = "drop_yellow_prio_3", }, 604 { .offset = 0x106, .name = "drop_yellow_prio_4", }, 605 { .offset = 0x107, .name = "drop_yellow_prio_5", }, 606 { .offset = 0x108, .name = "drop_yellow_prio_6", }, 607 { .offset = 0x109, .name = "drop_yellow_prio_7", }, 608 { .offset = 0x10A, .name = "drop_green_prio_0", }, 609 { .offset = 0x10B, .name = "drop_green_prio_1", }, 610 { .offset = 0x10C, .name = "drop_green_prio_2", }, 611 { .offset = 0x10D, .name = "drop_green_prio_3", }, 612 { .offset = 0x10E, .name = "drop_green_prio_4", }, 613 { .offset = 0x10F, .name = "drop_green_prio_5", }, 614 { .offset = 0x110, .name = "drop_green_prio_6", }, 615 { .offset = 0x111, .name = "drop_green_prio_7", }, 616 }; 617 618 static struct vcap_field vsc9959_vcap_is2_keys[] = { 619 /* Common: 41 bits */ 620 [VCAP_IS2_TYPE] = { 0, 4}, 621 [VCAP_IS2_HK_FIRST] = { 4, 1}, 622 [VCAP_IS2_HK_PAG] = { 5, 8}, 623 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 7}, 624 [VCAP_IS2_HK_RSV2] = { 20, 1}, 625 [VCAP_IS2_HK_HOST_MATCH] = { 21, 1}, 626 [VCAP_IS2_HK_L2_MC] = { 22, 1}, 627 [VCAP_IS2_HK_L2_BC] = { 23, 1}, 628 [VCAP_IS2_HK_VLAN_TAGGED] = { 24, 1}, 629 [VCAP_IS2_HK_VID] = { 25, 12}, 630 [VCAP_IS2_HK_DEI] = { 37, 1}, 631 [VCAP_IS2_HK_PCP] = { 38, 3}, 632 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 633 [VCAP_IS2_HK_L2_DMAC] = { 41, 48}, 634 [VCAP_IS2_HK_L2_SMAC] = { 89, 48}, 635 /* MAC_ETYPE (TYPE=000) */ 636 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {137, 16}, 637 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {153, 16}, 638 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {169, 8}, 639 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {177, 3}, 640 /* MAC_LLC (TYPE=001) */ 641 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {137, 40}, 642 /* MAC_SNAP (TYPE=010) */ 643 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {137, 40}, 644 /* MAC_ARP (TYPE=011) */ 645 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 41, 48}, 646 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 89, 1}, 647 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 90, 1}, 648 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 91, 1}, 649 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 92, 1}, 650 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 93, 1}, 651 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 94, 1}, 652 [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 95, 2}, 653 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 97, 32}, 654 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {129, 32}, 655 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {161, 1}, 656 /* IP4_TCP_UDP / IP4_OTHER common */ 657 [VCAP_IS2_HK_IP4] = { 41, 1}, 658 [VCAP_IS2_HK_L3_FRAGMENT] = { 42, 1}, 659 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 43, 1}, 660 [VCAP_IS2_HK_L3_OPTIONS] = { 44, 1}, 661 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 45, 1}, 662 [VCAP_IS2_HK_L3_TOS] = { 46, 8}, 663 [VCAP_IS2_HK_L3_IP4_DIP] = { 54, 32}, 664 [VCAP_IS2_HK_L3_IP4_SIP] = { 86, 32}, 665 [VCAP_IS2_HK_DIP_EQ_SIP] = {118, 1}, 666 /* IP4_TCP_UDP (TYPE=100) */ 667 [VCAP_IS2_HK_TCP] = {119, 1}, 668 [VCAP_IS2_HK_L4_SPORT] = {120, 16}, 669 [VCAP_IS2_HK_L4_DPORT] = {136, 16}, 670 [VCAP_IS2_HK_L4_RNG] = {152, 8}, 671 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {160, 1}, 672 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {161, 1}, 673 [VCAP_IS2_HK_L4_URG] = {162, 1}, 674 [VCAP_IS2_HK_L4_ACK] = {163, 1}, 675 [VCAP_IS2_HK_L4_PSH] = {164, 1}, 676 [VCAP_IS2_HK_L4_RST] = {165, 1}, 677 [VCAP_IS2_HK_L4_SYN] = {166, 1}, 678 [VCAP_IS2_HK_L4_FIN] = {167, 1}, 679 [VCAP_IS2_HK_L4_1588_DOM] = {168, 8}, 680 [VCAP_IS2_HK_L4_1588_VER] = {176, 4}, 681 /* IP4_OTHER (TYPE=101) */ 682 [VCAP_IS2_HK_IP4_L3_PROTO] = {119, 8}, 683 [VCAP_IS2_HK_L3_PAYLOAD] = {127, 56}, 684 /* IP6_STD (TYPE=110) */ 685 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 41, 1}, 686 [VCAP_IS2_HK_L3_IP6_SIP] = { 42, 128}, 687 [VCAP_IS2_HK_IP6_L3_PROTO] = {170, 8}, 688 /* OAM (TYPE=111) */ 689 [VCAP_IS2_HK_OAM_MEL_FLAGS] = {137, 7}, 690 [VCAP_IS2_HK_OAM_VER] = {144, 5}, 691 [VCAP_IS2_HK_OAM_OPCODE] = {149, 8}, 692 [VCAP_IS2_HK_OAM_FLAGS] = {157, 8}, 693 [VCAP_IS2_HK_OAM_MEPID] = {165, 16}, 694 [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {181, 1}, 695 [VCAP_IS2_HK_OAM_IS_Y1731] = {182, 1}, 696 }; 697 698 static struct vcap_field vsc9959_vcap_is2_actions[] = { 699 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 700 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 701 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 702 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 703 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 704 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 705 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 706 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 707 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 708 [VCAP_IS2_ACT_PORT_MASK] = { 20, 11}, 709 [VCAP_IS2_ACT_REW_OP] = { 31, 9}, 710 [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 40, 1}, 711 [VCAP_IS2_ACT_RSV] = { 41, 2}, 712 [VCAP_IS2_ACT_ACL_ID] = { 43, 6}, 713 [VCAP_IS2_ACT_HIT_CNT] = { 49, 32}, 714 }; 715 716 static const struct vcap_props vsc9959_vcap_props[] = { 717 [VCAP_IS2] = { 718 .tg_width = 2, 719 .sw_count = 4, 720 .entry_count = VSC9959_VCAP_IS2_CNT, 721 .entry_width = VSC9959_VCAP_IS2_ENTRY_WIDTH, 722 .action_count = VSC9959_VCAP_IS2_CNT + 723 VSC9959_VCAP_PORT_CNT + 2, 724 .action_width = 89, 725 .action_type_width = 1, 726 .action_table = { 727 [IS2_ACTION_TYPE_NORMAL] = { 728 .width = 44, 729 .count = 2 730 }, 731 [IS2_ACTION_TYPE_SMAC_SIP] = { 732 .width = 6, 733 .count = 4 734 }, 735 }, 736 .counter_words = 4, 737 .counter_width = 32, 738 }, 739 }; 740 741 #define VSC9959_INIT_TIMEOUT 50000 742 #define VSC9959_GCB_RST_SLEEP 100 743 #define VSC9959_SYS_RAMINIT_SLEEP 80 744 745 static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot) 746 { 747 int val; 748 749 regmap_field_read(ocelot->regfields[GCB_SOFT_RST_SWC_RST], &val); 750 751 return val; 752 } 753 754 static int vsc9959_sys_ram_init_status(struct ocelot *ocelot) 755 { 756 return ocelot_read(ocelot, SYS_RAM_INIT); 757 } 758 759 static int vsc9959_reset(struct ocelot *ocelot) 760 { 761 int val, err; 762 763 /* soft-reset the switch core */ 764 regmap_field_write(ocelot->regfields[GCB_SOFT_RST_SWC_RST], 1); 765 766 err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val, 767 VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT); 768 if (err) { 769 dev_err(ocelot->dev, "timeout: switch core reset\n"); 770 return err; 771 } 772 773 /* initialize switch mem ~40us */ 774 ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT); 775 err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val, 776 VSC9959_SYS_RAMINIT_SLEEP, 777 VSC9959_INIT_TIMEOUT); 778 if (err) { 779 dev_err(ocelot->dev, "timeout: switch sram init\n"); 780 return err; 781 } 782 783 /* enable switch core */ 784 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1); 785 786 return 0; 787 } 788 789 /* We enable SGMII AN only when the PHY has managed = "in-band-status" in the 790 * device tree. If we are in MLO_AN_PHY mode, we program directly state->speed 791 * into the PCS, which is retrieved out-of-band over MDIO. This also has the 792 * benefit of working with SGMII fixed-links, like downstream switches, where 793 * both link partners attempt to operate as AN slaves and therefore AN never 794 * completes. But it also has the disadvantage that some PHY chips don't pass 795 * traffic if SGMII AN is enabled but not completed (acknowledged by us), so 796 * setting MLO_AN_INBAND is actually required for those. 797 */ 798 static void vsc9959_pcs_config_sgmii(struct phy_device *pcs, 799 unsigned int link_an_mode, 800 const struct phylink_link_state *state) 801 { 802 int bmsr, bmcr; 803 804 /* Some PHYs like VSC8234 don't like it when AN restarts on 805 * their system side and they restart line side AN too, going 806 * into an endless link up/down loop. Don't restart PCS AN if 807 * link is up already. 808 * We do check that AN is enabled just in case this is the 1st 809 * call, PCS detects a carrier but AN is disabled from power on 810 * or by boot loader. 811 */ 812 bmcr = phy_read(pcs, MII_BMCR); 813 if (bmcr < 0) 814 return; 815 816 bmsr = phy_read(pcs, MII_BMSR); 817 if (bmsr < 0) 818 return; 819 820 if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_LSTATUS)) 821 return; 822 823 /* SGMII spec requires tx_config_Reg[15:0] to be exactly 0x4001 824 * for the MAC PCS in order to acknowledge the AN. 825 */ 826 phy_write(pcs, MII_ADVERTISE, ADVERTISE_SGMII | 827 ADVERTISE_LPACK); 828 829 phy_write(pcs, ENETC_PCS_IF_MODE, 830 ENETC_PCS_IF_MODE_SGMII_EN | 831 ENETC_PCS_IF_MODE_USE_SGMII_AN); 832 833 /* Adjust link timer for SGMII */ 834 phy_write(pcs, ENETC_PCS_LINK_TIMER1, 835 ENETC_PCS_LINK_TIMER1_VAL); 836 phy_write(pcs, ENETC_PCS_LINK_TIMER2, 837 ENETC_PCS_LINK_TIMER2_VAL); 838 839 phy_set_bits(pcs, MII_BMCR, BMCR_ANENABLE); 840 } 841 842 static void vsc9959_pcs_config_usxgmii(struct phy_device *pcs, 843 unsigned int link_an_mode, 844 const struct phylink_link_state *state) 845 { 846 /* Configure device ability for the USXGMII Replicator */ 847 phy_write_mmd(pcs, MDIO_MMD_VEND2, MII_ADVERTISE, 848 USXGMII_ADVERTISE_SPEED(USXGMII_SPEED_2500) | 849 USXGMII_ADVERTISE_LNKS(1) | 850 ADVERTISE_SGMII | 851 ADVERTISE_LPACK | 852 USXGMII_ADVERTISE_FDX); 853 } 854 855 void vsc9959_pcs_config(struct ocelot *ocelot, int port, 856 unsigned int link_an_mode, 857 const struct phylink_link_state *state) 858 { 859 struct felix *felix = ocelot_to_felix(ocelot); 860 struct phy_device *pcs = felix->pcs[port]; 861 862 if (!pcs) 863 return; 864 865 /* The PCS does not implement the BMSR register fully, so capability 866 * detection via genphy_read_abilities does not work. Since we can get 867 * the PHY config word from the LPA register though, there is still 868 * value in using the generic phy_resolve_aneg_linkmode function. So 869 * populate the supported and advertising link modes manually here. 870 */ 871 linkmode_set_bit_array(phy_basic_ports_array, 872 ARRAY_SIZE(phy_basic_ports_array), 873 pcs->supported); 874 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, pcs->supported); 875 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, pcs->supported); 876 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, pcs->supported); 877 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, pcs->supported); 878 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, pcs->supported); 879 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, pcs->supported); 880 if (pcs->interface == PHY_INTERFACE_MODE_2500BASEX || 881 pcs->interface == PHY_INTERFACE_MODE_USXGMII) 882 linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, 883 pcs->supported); 884 if (pcs->interface != PHY_INTERFACE_MODE_2500BASEX) 885 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 886 pcs->supported); 887 phy_advertise_supported(pcs); 888 889 if (!phylink_autoneg_inband(link_an_mode)) 890 return; 891 892 switch (pcs->interface) { 893 case PHY_INTERFACE_MODE_SGMII: 894 case PHY_INTERFACE_MODE_QSGMII: 895 vsc9959_pcs_config_sgmii(pcs, link_an_mode, state); 896 break; 897 case PHY_INTERFACE_MODE_2500BASEX: 898 phydev_err(pcs, "AN not supported on 3.125GHz SerDes lane\n"); 899 break; 900 case PHY_INTERFACE_MODE_USXGMII: 901 vsc9959_pcs_config_usxgmii(pcs, link_an_mode, state); 902 break; 903 default: 904 dev_err(ocelot->dev, "Unsupported link mode %s\n", 905 phy_modes(pcs->interface)); 906 } 907 } 908 909 static void vsc9959_pcs_link_up_sgmii(struct phy_device *pcs, 910 unsigned int link_an_mode, 911 int speed, int duplex) 912 { 913 u16 if_mode = ENETC_PCS_IF_MODE_SGMII_EN; 914 915 switch (speed) { 916 case SPEED_1000: 917 if_mode |= ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_1000); 918 break; 919 case SPEED_100: 920 if_mode |= ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_100); 921 break; 922 case SPEED_10: 923 if_mode |= ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_10); 924 break; 925 default: 926 phydev_err(pcs, "Invalid PCS speed %d\n", speed); 927 return; 928 } 929 930 if (duplex == DUPLEX_HALF) 931 if_mode |= ENETC_PCS_IF_MODE_DUPLEX_HALF; 932 933 phy_write(pcs, ENETC_PCS_IF_MODE, if_mode); 934 phy_clear_bits(pcs, MII_BMCR, BMCR_ANENABLE); 935 } 936 937 /* 2500Base-X is SerDes protocol 7 on Felix and 6 on ENETC. It is a SerDes lane 938 * clocked at 3.125 GHz which encodes symbols with 8b/10b and does not have 939 * auto-negotiation of any link parameters. Electrically it is compatible with 940 * a single lane of XAUI. 941 * The hardware reference manual wants to call this mode SGMII, but it isn't 942 * really, since the fundamental features of SGMII: 943 * - Downgrading the link speed by duplicating symbols 944 * - Auto-negotiation 945 * are not there. 946 * The speed is configured at 1000 in the IF_MODE and BMCR MDIO registers 947 * because the clock frequency is actually given by a PLL configured in the 948 * Reset Configuration Word (RCW). 949 * Since there is no difference between fixed speed SGMII w/o AN and 802.3z w/o 950 * AN, we call this PHY interface type 2500Base-X. In case a PHY negotiates a 951 * lower link speed on line side, the system-side interface remains fixed at 952 * 2500 Mbps and we do rate adaptation through pause frames. 953 */ 954 static void vsc9959_pcs_link_up_2500basex(struct phy_device *pcs, 955 unsigned int link_an_mode, 956 int speed, int duplex) 957 { 958 u16 if_mode = ENETC_PCS_IF_MODE_SGMII_SPEED(ENETC_PCS_SPEED_2500) | 959 ENETC_PCS_IF_MODE_SGMII_EN; 960 961 if (duplex == DUPLEX_HALF) 962 if_mode |= ENETC_PCS_IF_MODE_DUPLEX_HALF; 963 964 phy_write(pcs, ENETC_PCS_IF_MODE, if_mode); 965 phy_clear_bits(pcs, MII_BMCR, BMCR_ANENABLE); 966 } 967 968 void vsc9959_pcs_link_up(struct ocelot *ocelot, int port, 969 unsigned int link_an_mode, 970 phy_interface_t interface, 971 int speed, int duplex) 972 { 973 struct felix *felix = ocelot_to_felix(ocelot); 974 struct phy_device *pcs = felix->pcs[port]; 975 976 if (!pcs) 977 return; 978 979 if (phylink_autoneg_inband(link_an_mode)) 980 return; 981 982 switch (interface) { 983 case PHY_INTERFACE_MODE_SGMII: 984 case PHY_INTERFACE_MODE_QSGMII: 985 vsc9959_pcs_link_up_sgmii(pcs, link_an_mode, speed, duplex); 986 break; 987 case PHY_INTERFACE_MODE_2500BASEX: 988 vsc9959_pcs_link_up_2500basex(pcs, link_an_mode, speed, 989 duplex); 990 break; 991 case PHY_INTERFACE_MODE_USXGMII: 992 phydev_err(pcs, "USXGMII only supports in-band AN for now\n"); 993 break; 994 default: 995 dev_err(ocelot->dev, "Unsupported link mode %s\n", 996 phy_modes(pcs->interface)); 997 } 998 } 999 1000 static void vsc9959_pcs_link_state_resolve(struct phy_device *pcs, 1001 struct phylink_link_state *state) 1002 { 1003 state->an_complete = pcs->autoneg_complete; 1004 state->an_enabled = pcs->autoneg; 1005 state->link = pcs->link; 1006 state->duplex = pcs->duplex; 1007 state->speed = pcs->speed; 1008 /* SGMII AN does not negotiate flow control, but that's ok, 1009 * since phylink already knows that, and does: 1010 * link_state.pause |= pl->phy_state.pause; 1011 */ 1012 state->pause = MLO_PAUSE_NONE; 1013 1014 phydev_dbg(pcs, 1015 "mode=%s/%s/%s adv=%*pb lpa=%*pb link=%u an_enabled=%u an_complete=%u\n", 1016 phy_modes(pcs->interface), 1017 phy_speed_to_str(pcs->speed), 1018 phy_duplex_to_str(pcs->duplex), 1019 __ETHTOOL_LINK_MODE_MASK_NBITS, pcs->advertising, 1020 __ETHTOOL_LINK_MODE_MASK_NBITS, pcs->lp_advertising, 1021 pcs->link, pcs->autoneg, pcs->autoneg_complete); 1022 } 1023 1024 static void vsc9959_pcs_link_state_sgmii(struct phy_device *pcs, 1025 struct phylink_link_state *state) 1026 { 1027 int err; 1028 1029 err = genphy_update_link(pcs); 1030 if (err < 0) 1031 return; 1032 1033 if (pcs->autoneg_complete) { 1034 u16 lpa = phy_read(pcs, MII_LPA); 1035 1036 mii_lpa_to_linkmode_lpa_sgmii(pcs->lp_advertising, lpa); 1037 1038 phy_resolve_aneg_linkmode(pcs); 1039 } 1040 } 1041 1042 static void vsc9959_pcs_link_state_2500basex(struct phy_device *pcs, 1043 struct phylink_link_state *state) 1044 { 1045 int err; 1046 1047 err = genphy_update_link(pcs); 1048 if (err < 0) 1049 return; 1050 1051 pcs->speed = SPEED_2500; 1052 pcs->asym_pause = true; 1053 pcs->pause = true; 1054 } 1055 1056 static void vsc9959_pcs_link_state_usxgmii(struct phy_device *pcs, 1057 struct phylink_link_state *state) 1058 { 1059 int status, lpa; 1060 1061 status = phy_read_mmd(pcs, MDIO_MMD_VEND2, MII_BMSR); 1062 if (status < 0) 1063 return; 1064 1065 pcs->autoneg = true; 1066 pcs->autoneg_complete = USXGMII_BMSR_AN_CMPL(status); 1067 pcs->link = USXGMII_BMSR_LNKS(status); 1068 1069 if (!pcs->link || !pcs->autoneg_complete) 1070 return; 1071 1072 lpa = phy_read_mmd(pcs, MDIO_MMD_VEND2, MII_LPA); 1073 if (lpa < 0) 1074 return; 1075 1076 switch (USXGMII_LPA_SPEED(lpa)) { 1077 case USXGMII_SPEED_10: 1078 pcs->speed = SPEED_10; 1079 break; 1080 case USXGMII_SPEED_100: 1081 pcs->speed = SPEED_100; 1082 break; 1083 case USXGMII_SPEED_1000: 1084 pcs->speed = SPEED_1000; 1085 break; 1086 case USXGMII_SPEED_2500: 1087 pcs->speed = SPEED_2500; 1088 break; 1089 default: 1090 break; 1091 } 1092 1093 if (USXGMII_LPA_DUPLEX(lpa)) 1094 pcs->duplex = DUPLEX_FULL; 1095 else 1096 pcs->duplex = DUPLEX_HALF; 1097 } 1098 1099 void vsc9959_pcs_link_state(struct ocelot *ocelot, int port, 1100 struct phylink_link_state *state) 1101 { 1102 struct felix *felix = ocelot_to_felix(ocelot); 1103 struct phy_device *pcs = felix->pcs[port]; 1104 1105 if (!pcs) 1106 return; 1107 1108 pcs->speed = SPEED_UNKNOWN; 1109 pcs->duplex = DUPLEX_UNKNOWN; 1110 pcs->pause = 0; 1111 pcs->asym_pause = 0; 1112 1113 switch (pcs->interface) { 1114 case PHY_INTERFACE_MODE_SGMII: 1115 case PHY_INTERFACE_MODE_QSGMII: 1116 vsc9959_pcs_link_state_sgmii(pcs, state); 1117 break; 1118 case PHY_INTERFACE_MODE_2500BASEX: 1119 vsc9959_pcs_link_state_2500basex(pcs, state); 1120 break; 1121 case PHY_INTERFACE_MODE_USXGMII: 1122 vsc9959_pcs_link_state_usxgmii(pcs, state); 1123 break; 1124 default: 1125 return; 1126 } 1127 1128 vsc9959_pcs_link_state_resolve(pcs, state); 1129 } 1130 1131 static void vsc9959_phylink_validate(struct ocelot *ocelot, int port, 1132 unsigned long *supported, 1133 struct phylink_link_state *state) 1134 { 1135 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1136 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1137 1138 if (state->interface != PHY_INTERFACE_MODE_NA && 1139 state->interface != ocelot_port->phy_mode) { 1140 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 1141 return; 1142 } 1143 1144 phylink_set_port_modes(mask); 1145 phylink_set(mask, Autoneg); 1146 phylink_set(mask, Pause); 1147 phylink_set(mask, Asym_Pause); 1148 phylink_set(mask, 10baseT_Half); 1149 phylink_set(mask, 10baseT_Full); 1150 phylink_set(mask, 100baseT_Half); 1151 phylink_set(mask, 100baseT_Full); 1152 phylink_set(mask, 1000baseT_Half); 1153 phylink_set(mask, 1000baseT_Full); 1154 1155 if (state->interface == PHY_INTERFACE_MODE_INTERNAL || 1156 state->interface == PHY_INTERFACE_MODE_2500BASEX || 1157 state->interface == PHY_INTERFACE_MODE_USXGMII) { 1158 phylink_set(mask, 2500baseT_Full); 1159 phylink_set(mask, 2500baseX_Full); 1160 } 1161 1162 bitmap_and(supported, supported, mask, 1163 __ETHTOOL_LINK_MODE_MASK_NBITS); 1164 bitmap_and(state->advertising, state->advertising, mask, 1165 __ETHTOOL_LINK_MODE_MASK_NBITS); 1166 } 1167 1168 static int vsc9959_prevalidate_phy_mode(struct ocelot *ocelot, int port, 1169 phy_interface_t phy_mode) 1170 { 1171 switch (phy_mode) { 1172 case PHY_INTERFACE_MODE_INTERNAL: 1173 if (port != 4 && port != 5) 1174 return -ENOTSUPP; 1175 return 0; 1176 case PHY_INTERFACE_MODE_SGMII: 1177 case PHY_INTERFACE_MODE_QSGMII: 1178 case PHY_INTERFACE_MODE_USXGMII: 1179 case PHY_INTERFACE_MODE_2500BASEX: 1180 /* Not supported on internal to-CPU ports */ 1181 if (port == 4 || port == 5) 1182 return -ENOTSUPP; 1183 return 0; 1184 default: 1185 return -ENOTSUPP; 1186 } 1187 } 1188 1189 /* Watermark encode 1190 * Bit 8: Unit; 0:1, 1:16 1191 * Bit 7-0: Value to be multiplied with unit 1192 */ 1193 static u16 vsc9959_wm_enc(u16 value) 1194 { 1195 if (value >= BIT(8)) 1196 return BIT(8) | (value / 16); 1197 1198 return value; 1199 } 1200 1201 static const struct ocelot_ops vsc9959_ops = { 1202 .reset = vsc9959_reset, 1203 .wm_enc = vsc9959_wm_enc, 1204 }; 1205 1206 static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot) 1207 { 1208 struct felix *felix = ocelot_to_felix(ocelot); 1209 struct enetc_mdio_priv *mdio_priv; 1210 struct device *dev = ocelot->dev; 1211 void __iomem *imdio_regs; 1212 struct resource res; 1213 struct enetc_hw *hw; 1214 struct mii_bus *bus; 1215 int port; 1216 int rc; 1217 1218 felix->pcs = devm_kcalloc(dev, felix->info->num_ports, 1219 sizeof(struct phy_device *), 1220 GFP_KERNEL); 1221 if (!felix->pcs) { 1222 dev_err(dev, "failed to allocate array for PCS PHYs\n"); 1223 return -ENOMEM; 1224 } 1225 1226 memcpy(&res, felix->info->imdio_res, sizeof(res)); 1227 res.flags = IORESOURCE_MEM; 1228 res.start += felix->imdio_base; 1229 res.end += felix->imdio_base; 1230 1231 imdio_regs = devm_ioremap_resource(dev, &res); 1232 if (IS_ERR(imdio_regs)) { 1233 dev_err(dev, "failed to map internal MDIO registers\n"); 1234 return PTR_ERR(imdio_regs); 1235 } 1236 1237 hw = enetc_hw_alloc(dev, imdio_regs); 1238 if (IS_ERR(hw)) { 1239 dev_err(dev, "failed to allocate ENETC HW structure\n"); 1240 return PTR_ERR(hw); 1241 } 1242 1243 bus = devm_mdiobus_alloc_size(dev, sizeof(*mdio_priv)); 1244 if (!bus) 1245 return -ENOMEM; 1246 1247 bus->name = "VSC9959 internal MDIO bus"; 1248 bus->read = enetc_mdio_read; 1249 bus->write = enetc_mdio_write; 1250 bus->parent = dev; 1251 mdio_priv = bus->priv; 1252 mdio_priv->hw = hw; 1253 /* This gets added to imdio_regs, which already maps addresses 1254 * starting with the proper offset. 1255 */ 1256 mdio_priv->mdio_base = 0; 1257 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); 1258 1259 /* Needed in order to initialize the bus mutex lock */ 1260 rc = mdiobus_register(bus); 1261 if (rc < 0) { 1262 dev_err(dev, "failed to register MDIO bus\n"); 1263 return rc; 1264 } 1265 1266 felix->imdio = bus; 1267 1268 for (port = 0; port < felix->info->num_ports; port++) { 1269 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1270 struct phy_device *pcs; 1271 bool is_c45 = false; 1272 1273 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_USXGMII) 1274 is_c45 = true; 1275 1276 pcs = get_phy_device(felix->imdio, port, is_c45); 1277 if (IS_ERR(pcs)) 1278 continue; 1279 1280 pcs->interface = ocelot_port->phy_mode; 1281 felix->pcs[port] = pcs; 1282 1283 dev_info(dev, "Found PCS at internal MDIO address %d\n", port); 1284 } 1285 1286 return 0; 1287 } 1288 1289 void vsc9959_mdio_bus_free(struct ocelot *ocelot) 1290 { 1291 struct felix *felix = ocelot_to_felix(ocelot); 1292 int port; 1293 1294 for (port = 0; port < ocelot->num_phys_ports; port++) { 1295 struct phy_device *pcs = felix->pcs[port]; 1296 1297 if (!pcs) 1298 continue; 1299 1300 put_device(&pcs->mdio.dev); 1301 } 1302 mdiobus_unregister(felix->imdio); 1303 } 1304 1305 static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port, 1306 u32 speed) 1307 { 1308 ocelot_rmw_rix(ocelot, 1309 QSYS_TAG_CONFIG_LINK_SPEED(speed), 1310 QSYS_TAG_CONFIG_LINK_SPEED_M, 1311 QSYS_TAG_CONFIG, port); 1312 } 1313 1314 static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time, 1315 u64 cycle_time, 1316 struct timespec64 *new_base_ts) 1317 { 1318 struct timespec64 ts; 1319 ktime_t new_base_time; 1320 ktime_t current_time; 1321 1322 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1323 current_time = timespec64_to_ktime(ts); 1324 new_base_time = base_time; 1325 1326 if (base_time < current_time) { 1327 u64 nr_of_cycles = current_time - base_time; 1328 1329 do_div(nr_of_cycles, cycle_time); 1330 new_base_time += cycle_time * (nr_of_cycles + 1); 1331 } 1332 1333 *new_base_ts = ktime_to_timespec64(new_base_time); 1334 } 1335 1336 static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot) 1337 { 1338 return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL); 1339 } 1340 1341 static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix, 1342 struct tc_taprio_sched_entry *entry) 1343 { 1344 ocelot_write(ocelot, 1345 QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) | 1346 QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask), 1347 QSYS_GCL_CFG_REG_1); 1348 ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2); 1349 } 1350 1351 static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port, 1352 struct tc_taprio_qopt_offload *taprio) 1353 { 1354 struct timespec64 base_ts; 1355 int ret, i; 1356 u32 val; 1357 1358 if (!taprio->enable) { 1359 ocelot_rmw_rix(ocelot, 1360 QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF), 1361 QSYS_TAG_CONFIG_ENABLE | 1362 QSYS_TAG_CONFIG_INIT_GATE_STATE_M, 1363 QSYS_TAG_CONFIG, port); 1364 1365 return 0; 1366 } 1367 1368 if (taprio->cycle_time > NSEC_PER_SEC || 1369 taprio->cycle_time_extension >= NSEC_PER_SEC) 1370 return -EINVAL; 1371 1372 if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX) 1373 return -ERANGE; 1374 1375 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) | 1376 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1377 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M | 1378 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1379 QSYS_TAS_PARAM_CFG_CTRL); 1380 1381 /* Hardware errata - Admin config could not be overwritten if 1382 * config is pending, need reset the TAS module 1383 */ 1384 val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8); 1385 if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) 1386 return -EBUSY; 1387 1388 ocelot_rmw_rix(ocelot, 1389 QSYS_TAG_CONFIG_ENABLE | 1390 QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) | 1391 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF), 1392 QSYS_TAG_CONFIG_ENABLE | 1393 QSYS_TAG_CONFIG_INIT_GATE_STATE_M | 1394 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M, 1395 QSYS_TAG_CONFIG, port); 1396 1397 vsc9959_new_base_time(ocelot, taprio->base_time, 1398 taprio->cycle_time, &base_ts); 1399 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1400 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2); 1401 val = upper_32_bits(base_ts.tv_sec); 1402 ocelot_write(ocelot, 1403 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) | 1404 QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries), 1405 QSYS_PARAM_CFG_REG_3); 1406 ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4); 1407 ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5); 1408 1409 for (i = 0; i < taprio->num_entries; i++) 1410 vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]); 1411 1412 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1413 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1414 QSYS_TAS_PARAM_CFG_CTRL); 1415 1416 ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val, 1417 !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE), 1418 10, 100000); 1419 1420 return ret; 1421 } 1422 1423 static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port, 1424 struct tc_cbs_qopt_offload *cbs_qopt) 1425 { 1426 struct ocelot *ocelot = ds->priv; 1427 int port_ix = port * 8 + cbs_qopt->queue; 1428 u32 rate, burst; 1429 1430 if (cbs_qopt->queue >= ds->num_tx_queues) 1431 return -EINVAL; 1432 1433 if (!cbs_qopt->enable) { 1434 ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) | 1435 QSYS_CIR_CFG_CIR_BURST(0), 1436 QSYS_CIR_CFG, port_ix); 1437 1438 ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA, 1439 QSYS_SE_CFG, port_ix); 1440 1441 return 0; 1442 } 1443 1444 /* Rate unit is 100 kbps */ 1445 rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100); 1446 /* Avoid using zero rate */ 1447 rate = clamp_t(u32, rate, 1, GENMASK(14, 0)); 1448 /* Burst unit is 4kB */ 1449 burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096); 1450 /* Avoid using zero burst size */ 1451 burst = clamp_t(u32, burst, 1, GENMASK(5, 0)); 1452 ocelot_write_gix(ocelot, 1453 QSYS_CIR_CFG_CIR_RATE(rate) | 1454 QSYS_CIR_CFG_CIR_BURST(burst), 1455 QSYS_CIR_CFG, 1456 port_ix); 1457 1458 ocelot_rmw_gix(ocelot, 1459 QSYS_SE_CFG_SE_FRM_MODE(0) | 1460 QSYS_SE_CFG_SE_AVB_ENA, 1461 QSYS_SE_CFG_SE_AVB_ENA | 1462 QSYS_SE_CFG_SE_FRM_MODE_M, 1463 QSYS_SE_CFG, 1464 port_ix); 1465 1466 return 0; 1467 } 1468 1469 static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port, 1470 enum tc_setup_type type, 1471 void *type_data) 1472 { 1473 struct ocelot *ocelot = ds->priv; 1474 1475 switch (type) { 1476 case TC_SETUP_QDISC_TAPRIO: 1477 return vsc9959_qos_port_tas_set(ocelot, port, type_data); 1478 case TC_SETUP_QDISC_CBS: 1479 return vsc9959_qos_port_cbs_set(ds, port, type_data); 1480 default: 1481 return -EOPNOTSUPP; 1482 } 1483 } 1484 1485 static void vsc9959_xmit_template_populate(struct ocelot *ocelot, int port) 1486 { 1487 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1488 u8 *template = ocelot_port->xmit_template; 1489 u64 bypass, dest, src; 1490 1491 /* Set the source port as the CPU port module and not the 1492 * NPI port 1493 */ 1494 src = ocelot->num_phys_ports; 1495 dest = BIT(port); 1496 bypass = true; 1497 1498 packing(template, &bypass, 127, 127, OCELOT_TAG_LEN, PACK, 0); 1499 packing(template, &dest, 68, 56, OCELOT_TAG_LEN, PACK, 0); 1500 packing(template, &src, 46, 43, OCELOT_TAG_LEN, PACK, 0); 1501 } 1502 1503 static const struct felix_info felix_info_vsc9959 = { 1504 .target_io_res = vsc9959_target_io_res, 1505 .port_io_res = vsc9959_port_io_res, 1506 .imdio_res = &vsc9959_imdio_res, 1507 .regfields = vsc9959_regfields, 1508 .map = vsc9959_regmap, 1509 .ops = &vsc9959_ops, 1510 .stats_layout = vsc9959_stats_layout, 1511 .num_stats = ARRAY_SIZE(vsc9959_stats_layout), 1512 .vcap_is2_keys = vsc9959_vcap_is2_keys, 1513 .vcap_is2_actions = vsc9959_vcap_is2_actions, 1514 .vcap = vsc9959_vcap_props, 1515 .shared_queue_sz = 128 * 1024, 1516 .num_mact_rows = 2048, 1517 .num_ports = 6, 1518 .num_tx_queues = FELIX_NUM_TC, 1519 .switch_pci_bar = 4, 1520 .imdio_pci_bar = 0, 1521 .mdio_bus_alloc = vsc9959_mdio_bus_alloc, 1522 .mdio_bus_free = vsc9959_mdio_bus_free, 1523 .pcs_config = vsc9959_pcs_config, 1524 .pcs_link_up = vsc9959_pcs_link_up, 1525 .pcs_link_state = vsc9959_pcs_link_state, 1526 .phylink_validate = vsc9959_phylink_validate, 1527 .prevalidate_phy_mode = vsc9959_prevalidate_phy_mode, 1528 .port_setup_tc = vsc9959_port_setup_tc, 1529 .port_sched_speed_set = vsc9959_sched_speed_set, 1530 .xmit_template_populate = vsc9959_xmit_template_populate, 1531 }; 1532 1533 static irqreturn_t felix_irq_handler(int irq, void *data) 1534 { 1535 struct ocelot *ocelot = (struct ocelot *)data; 1536 1537 /* The INTB interrupt is used for both PTP TX timestamp interrupt 1538 * and preemption status change interrupt on each port. 1539 * 1540 * - Get txtstamp if have 1541 * - TODO: handle preemption. Without handling it, driver may get 1542 * interrupt storm. 1543 */ 1544 1545 ocelot_get_txtstamp(ocelot); 1546 1547 return IRQ_HANDLED; 1548 } 1549 1550 static int felix_pci_probe(struct pci_dev *pdev, 1551 const struct pci_device_id *id) 1552 { 1553 struct dsa_switch *ds; 1554 struct ocelot *ocelot; 1555 struct felix *felix; 1556 int err; 1557 1558 if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) { 1559 dev_info(&pdev->dev, "device is disabled, skipping\n"); 1560 return -ENODEV; 1561 } 1562 1563 err = pci_enable_device(pdev); 1564 if (err) { 1565 dev_err(&pdev->dev, "device enable failed\n"); 1566 goto err_pci_enable; 1567 } 1568 1569 /* set up for high or low dma */ 1570 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1571 if (err) { 1572 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1573 if (err) { 1574 dev_err(&pdev->dev, 1575 "DMA configuration failed: 0x%x\n", err); 1576 goto err_dma; 1577 } 1578 } 1579 1580 felix = kzalloc(sizeof(struct felix), GFP_KERNEL); 1581 if (!felix) { 1582 err = -ENOMEM; 1583 dev_err(&pdev->dev, "Failed to allocate driver memory\n"); 1584 goto err_alloc_felix; 1585 } 1586 1587 pci_set_drvdata(pdev, felix); 1588 ocelot = &felix->ocelot; 1589 ocelot->dev = &pdev->dev; 1590 felix->info = &felix_info_vsc9959; 1591 felix->switch_base = pci_resource_start(pdev, 1592 felix->info->switch_pci_bar); 1593 felix->imdio_base = pci_resource_start(pdev, 1594 felix->info->imdio_pci_bar); 1595 1596 pci_set_master(pdev); 1597 1598 err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL, 1599 &felix_irq_handler, IRQF_ONESHOT, 1600 "felix-intb", ocelot); 1601 if (err) { 1602 dev_err(&pdev->dev, "Failed to request irq\n"); 1603 goto err_alloc_irq; 1604 } 1605 1606 ocelot->ptp = 1; 1607 1608 ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL); 1609 if (!ds) { 1610 err = -ENOMEM; 1611 dev_err(&pdev->dev, "Failed to allocate DSA switch\n"); 1612 goto err_alloc_ds; 1613 } 1614 1615 ds->dev = &pdev->dev; 1616 ds->num_ports = felix->info->num_ports; 1617 ds->num_tx_queues = felix->info->num_tx_queues; 1618 ds->ops = &felix_switch_ops; 1619 ds->priv = ocelot; 1620 felix->ds = ds; 1621 1622 err = dsa_register_switch(ds); 1623 if (err) { 1624 dev_err(&pdev->dev, "Failed to register DSA switch: %d\n", err); 1625 goto err_register_ds; 1626 } 1627 1628 return 0; 1629 1630 err_register_ds: 1631 kfree(ds); 1632 err_alloc_ds: 1633 err_alloc_irq: 1634 err_alloc_felix: 1635 kfree(felix); 1636 err_dma: 1637 pci_disable_device(pdev); 1638 err_pci_enable: 1639 return err; 1640 } 1641 1642 static void felix_pci_remove(struct pci_dev *pdev) 1643 { 1644 struct felix *felix; 1645 1646 felix = pci_get_drvdata(pdev); 1647 1648 dsa_unregister_switch(felix->ds); 1649 1650 kfree(felix->ds); 1651 kfree(felix); 1652 1653 pci_disable_device(pdev); 1654 } 1655 1656 static struct pci_device_id felix_ids[] = { 1657 { 1658 /* NXP LS1028A */ 1659 PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0), 1660 }, 1661 { 0, } 1662 }; 1663 MODULE_DEVICE_TABLE(pci, felix_ids); 1664 1665 struct pci_driver felix_vsc9959_pci_driver = { 1666 .name = "mscc_felix", 1667 .id_table = felix_ids, 1668 .probe = felix_pci_probe, 1669 .remove = felix_pci_remove, 1670 }; 1671