1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright 2017 Microsemi Corporation 3 * Copyright 2018-2019 NXP Semiconductors 4 */ 5 #include <soc/mscc/ocelot_sys.h> 6 #include <soc/mscc/ocelot.h> 7 #include <linux/iopoll.h> 8 #include <linux/pci.h> 9 #include "felix.h" 10 11 static const u32 vsc9959_ana_regmap[] = { 12 REG(ANA_ADVLEARN, 0x0089a0), 13 REG(ANA_VLANMASK, 0x0089a4), 14 REG_RESERVED(ANA_PORT_B_DOMAIN), 15 REG(ANA_ANAGEFIL, 0x0089ac), 16 REG(ANA_ANEVENTS, 0x0089b0), 17 REG(ANA_STORMLIMIT_BURST, 0x0089b4), 18 REG(ANA_STORMLIMIT_CFG, 0x0089b8), 19 REG(ANA_ISOLATED_PORTS, 0x0089c8), 20 REG(ANA_COMMUNITY_PORTS, 0x0089cc), 21 REG(ANA_AUTOAGE, 0x0089d0), 22 REG(ANA_MACTOPTIONS, 0x0089d4), 23 REG(ANA_LEARNDISC, 0x0089d8), 24 REG(ANA_AGENCTRL, 0x0089dc), 25 REG(ANA_MIRRORPORTS, 0x0089e0), 26 REG(ANA_EMIRRORPORTS, 0x0089e4), 27 REG(ANA_FLOODING, 0x0089e8), 28 REG(ANA_FLOODING_IPMC, 0x008a08), 29 REG(ANA_SFLOW_CFG, 0x008a0c), 30 REG(ANA_PORT_MODE, 0x008a28), 31 REG(ANA_CUT_THRU_CFG, 0x008a48), 32 REG(ANA_PGID_PGID, 0x008400), 33 REG(ANA_TABLES_ANMOVED, 0x007f1c), 34 REG(ANA_TABLES_MACHDATA, 0x007f20), 35 REG(ANA_TABLES_MACLDATA, 0x007f24), 36 REG(ANA_TABLES_STREAMDATA, 0x007f28), 37 REG(ANA_TABLES_MACACCESS, 0x007f2c), 38 REG(ANA_TABLES_MACTINDX, 0x007f30), 39 REG(ANA_TABLES_VLANACCESS, 0x007f34), 40 REG(ANA_TABLES_VLANTIDX, 0x007f38), 41 REG(ANA_TABLES_ISDXACCESS, 0x007f3c), 42 REG(ANA_TABLES_ISDXTIDX, 0x007f40), 43 REG(ANA_TABLES_ENTRYLIM, 0x007f00), 44 REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44), 45 REG(ANA_TABLES_PTP_ID_LOW, 0x007f48), 46 REG(ANA_TABLES_STREAMACCESS, 0x007f4c), 47 REG(ANA_TABLES_STREAMTIDX, 0x007f50), 48 REG(ANA_TABLES_SEQ_HISTORY, 0x007f54), 49 REG(ANA_TABLES_SEQ_MASK, 0x007f58), 50 REG(ANA_TABLES_SFID_MASK, 0x007f5c), 51 REG(ANA_TABLES_SFIDACCESS, 0x007f60), 52 REG(ANA_TABLES_SFIDTIDX, 0x007f64), 53 REG(ANA_MSTI_STATE, 0x008600), 54 REG(ANA_OAM_UPM_LM_CNT, 0x008000), 55 REG(ANA_SG_ACCESS_CTRL, 0x008a64), 56 REG(ANA_SG_CONFIG_REG_1, 0x007fb0), 57 REG(ANA_SG_CONFIG_REG_2, 0x007fb4), 58 REG(ANA_SG_CONFIG_REG_3, 0x007fb8), 59 REG(ANA_SG_CONFIG_REG_4, 0x007fbc), 60 REG(ANA_SG_CONFIG_REG_5, 0x007fc0), 61 REG(ANA_SG_GCL_GS_CONFIG, 0x007f80), 62 REG(ANA_SG_GCL_TI_CONFIG, 0x007f90), 63 REG(ANA_SG_STATUS_REG_1, 0x008980), 64 REG(ANA_SG_STATUS_REG_2, 0x008984), 65 REG(ANA_SG_STATUS_REG_3, 0x008988), 66 REG(ANA_PORT_VLAN_CFG, 0x007800), 67 REG(ANA_PORT_DROP_CFG, 0x007804), 68 REG(ANA_PORT_QOS_CFG, 0x007808), 69 REG(ANA_PORT_VCAP_CFG, 0x00780c), 70 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810), 71 REG(ANA_PORT_VCAP_S2_CFG, 0x00781c), 72 REG(ANA_PORT_PCP_DEI_MAP, 0x007820), 73 REG(ANA_PORT_CPU_FWD_CFG, 0x007860), 74 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864), 75 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868), 76 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c), 77 REG(ANA_PORT_PORT_CFG, 0x007870), 78 REG(ANA_PORT_POL_CFG, 0x007874), 79 REG(ANA_PORT_PTP_CFG, 0x007878), 80 REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c), 81 REG(ANA_PORT_PTP_DLY2_CFG, 0x007880), 82 REG(ANA_PORT_SFID_CFG, 0x007884), 83 REG(ANA_PFC_PFC_CFG, 0x008800), 84 REG_RESERVED(ANA_PFC_PFC_TIMER), 85 REG_RESERVED(ANA_IPT_OAM_MEP_CFG), 86 REG_RESERVED(ANA_IPT_IPT), 87 REG_RESERVED(ANA_PPT_PPT), 88 REG_RESERVED(ANA_FID_MAP_FID_MAP), 89 REG(ANA_AGGR_CFG, 0x008a68), 90 REG(ANA_CPUQ_CFG, 0x008a6c), 91 REG_RESERVED(ANA_CPUQ_CFG2), 92 REG(ANA_CPUQ_8021_CFG, 0x008a74), 93 REG(ANA_DSCP_CFG, 0x008ab4), 94 REG(ANA_DSCP_REWR_CFG, 0x008bb4), 95 REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4), 96 REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14), 97 REG_RESERVED(ANA_VRAP_CFG), 98 REG_RESERVED(ANA_VRAP_HDR_DATA), 99 REG_RESERVED(ANA_VRAP_HDR_MASK), 100 REG(ANA_DISCARD_CFG, 0x008c40), 101 REG(ANA_FID_CFG, 0x008c44), 102 REG(ANA_POL_PIR_CFG, 0x004000), 103 REG(ANA_POL_CIR_CFG, 0x004004), 104 REG(ANA_POL_MODE_CFG, 0x004008), 105 REG(ANA_POL_PIR_STATE, 0x00400c), 106 REG(ANA_POL_CIR_STATE, 0x004010), 107 REG_RESERVED(ANA_POL_STATE), 108 REG(ANA_POL_FLOWC, 0x008c48), 109 REG(ANA_POL_HYST, 0x008cb4), 110 REG_RESERVED(ANA_POL_MISC_CFG), 111 }; 112 113 static const u32 vsc9959_qs_regmap[] = { 114 REG(QS_XTR_GRP_CFG, 0x000000), 115 REG(QS_XTR_RD, 0x000008), 116 REG(QS_XTR_FRM_PRUNING, 0x000010), 117 REG(QS_XTR_FLUSH, 0x000018), 118 REG(QS_XTR_DATA_PRESENT, 0x00001c), 119 REG(QS_XTR_CFG, 0x000020), 120 REG(QS_INJ_GRP_CFG, 0x000024), 121 REG(QS_INJ_WR, 0x00002c), 122 REG(QS_INJ_CTRL, 0x000034), 123 REG(QS_INJ_STATUS, 0x00003c), 124 REG(QS_INJ_ERR, 0x000040), 125 REG_RESERVED(QS_INH_DBG), 126 }; 127 128 static const u32 vsc9959_s2_regmap[] = { 129 REG(S2_CORE_UPDATE_CTRL, 0x000000), 130 REG(S2_CORE_MV_CFG, 0x000004), 131 REG(S2_CACHE_ENTRY_DAT, 0x000008), 132 REG(S2_CACHE_MASK_DAT, 0x000108), 133 REG(S2_CACHE_ACTION_DAT, 0x000208), 134 REG(S2_CACHE_CNT_DAT, 0x000308), 135 REG(S2_CACHE_TG_DAT, 0x000388), 136 }; 137 138 static const u32 vsc9959_qsys_regmap[] = { 139 REG(QSYS_PORT_MODE, 0x00f460), 140 REG(QSYS_SWITCH_PORT_MODE, 0x00f480), 141 REG(QSYS_STAT_CNT_CFG, 0x00f49c), 142 REG(QSYS_EEE_CFG, 0x00f4a0), 143 REG(QSYS_EEE_THRES, 0x00f4b8), 144 REG(QSYS_IGR_NO_SHARING, 0x00f4bc), 145 REG(QSYS_EGR_NO_SHARING, 0x00f4c0), 146 REG(QSYS_SW_STATUS, 0x00f4c4), 147 REG(QSYS_EXT_CPU_CFG, 0x00f4e0), 148 REG_RESERVED(QSYS_PAD_CFG), 149 REG(QSYS_CPU_GROUP_MAP, 0x00f4e8), 150 REG_RESERVED(QSYS_QMAP), 151 REG_RESERVED(QSYS_ISDX_SGRP), 152 REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), 153 REG(QSYS_TFRM_MISC, 0x00f50c), 154 REG(QSYS_TFRM_PORT_DLY, 0x00f510), 155 REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514), 156 REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518), 157 REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c), 158 REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520), 159 REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524), 160 REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528), 161 REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c), 162 REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530), 163 REG(QSYS_RED_PROFILE, 0x00f534), 164 REG(QSYS_RES_QOS_MODE, 0x00f574), 165 REG(QSYS_RES_CFG, 0x00c000), 166 REG(QSYS_RES_STAT, 0x00c004), 167 REG(QSYS_EGR_DROP_MODE, 0x00f578), 168 REG(QSYS_EQ_CTRL, 0x00f57c), 169 REG_RESERVED(QSYS_EVENTS_CORE), 170 REG(QSYS_QMAXSDU_CFG_0, 0x00f584), 171 REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0), 172 REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc), 173 REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8), 174 REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4), 175 REG(QSYS_QMAXSDU_CFG_5, 0x00f610), 176 REG(QSYS_QMAXSDU_CFG_6, 0x00f62c), 177 REG(QSYS_QMAXSDU_CFG_7, 0x00f648), 178 REG(QSYS_PREEMPTION_CFG, 0x00f664), 179 REG_RESERVED(QSYS_CIR_CFG), 180 REG(QSYS_EIR_CFG, 0x000004), 181 REG(QSYS_SE_CFG, 0x000008), 182 REG(QSYS_SE_DWRR_CFG, 0x00000c), 183 REG_RESERVED(QSYS_SE_CONNECT), 184 REG(QSYS_SE_DLB_SENSE, 0x000040), 185 REG(QSYS_CIR_STATE, 0x000044), 186 REG(QSYS_EIR_STATE, 0x000048), 187 REG_RESERVED(QSYS_SE_STATE), 188 REG(QSYS_HSCH_MISC_CFG, 0x00f67c), 189 REG(QSYS_TAG_CONFIG, 0x00f680), 190 REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698), 191 REG(QSYS_PORT_MAX_SDU, 0x00f69c), 192 REG(QSYS_PARAM_CFG_REG_1, 0x00f440), 193 REG(QSYS_PARAM_CFG_REG_2, 0x00f444), 194 REG(QSYS_PARAM_CFG_REG_3, 0x00f448), 195 REG(QSYS_PARAM_CFG_REG_4, 0x00f44c), 196 REG(QSYS_PARAM_CFG_REG_5, 0x00f450), 197 REG(QSYS_GCL_CFG_REG_1, 0x00f454), 198 REG(QSYS_GCL_CFG_REG_2, 0x00f458), 199 REG(QSYS_PARAM_STATUS_REG_1, 0x00f400), 200 REG(QSYS_PARAM_STATUS_REG_2, 0x00f404), 201 REG(QSYS_PARAM_STATUS_REG_3, 0x00f408), 202 REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c), 203 REG(QSYS_PARAM_STATUS_REG_5, 0x00f410), 204 REG(QSYS_PARAM_STATUS_REG_6, 0x00f414), 205 REG(QSYS_PARAM_STATUS_REG_7, 0x00f418), 206 REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c), 207 REG(QSYS_PARAM_STATUS_REG_9, 0x00f420), 208 REG(QSYS_GCL_STATUS_REG_1, 0x00f424), 209 REG(QSYS_GCL_STATUS_REG_2, 0x00f428), 210 }; 211 212 static const u32 vsc9959_rew_regmap[] = { 213 REG(REW_PORT_VLAN_CFG, 0x000000), 214 REG(REW_TAG_CFG, 0x000004), 215 REG(REW_PORT_CFG, 0x000008), 216 REG(REW_DSCP_CFG, 0x00000c), 217 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 218 REG(REW_PTP_CFG, 0x000050), 219 REG(REW_PTP_DLY1_CFG, 0x000054), 220 REG(REW_RED_TAG_CFG, 0x000058), 221 REG(REW_DSCP_REMAP_DP1_CFG, 0x000410), 222 REG(REW_DSCP_REMAP_CFG, 0x000510), 223 REG_RESERVED(REW_STAT_CFG), 224 REG_RESERVED(REW_REW_STICKY), 225 REG_RESERVED(REW_PPT), 226 }; 227 228 static const u32 vsc9959_sys_regmap[] = { 229 REG(SYS_COUNT_RX_OCTETS, 0x000000), 230 REG(SYS_COUNT_RX_MULTICAST, 0x000008), 231 REG(SYS_COUNT_RX_SHORTS, 0x000010), 232 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 233 REG(SYS_COUNT_RX_JABBERS, 0x000018), 234 REG(SYS_COUNT_RX_64, 0x000024), 235 REG(SYS_COUNT_RX_65_127, 0x000028), 236 REG(SYS_COUNT_RX_128_255, 0x00002c), 237 REG(SYS_COUNT_RX_256_1023, 0x000030), 238 REG(SYS_COUNT_RX_1024_1526, 0x000034), 239 REG(SYS_COUNT_RX_1527_MAX, 0x000038), 240 REG(SYS_COUNT_RX_LONGS, 0x000044), 241 REG(SYS_COUNT_TX_OCTETS, 0x000200), 242 REG(SYS_COUNT_TX_COLLISION, 0x000210), 243 REG(SYS_COUNT_TX_DROPS, 0x000214), 244 REG(SYS_COUNT_TX_64, 0x00021c), 245 REG(SYS_COUNT_TX_65_127, 0x000220), 246 REG(SYS_COUNT_TX_128_511, 0x000224), 247 REG(SYS_COUNT_TX_512_1023, 0x000228), 248 REG(SYS_COUNT_TX_1024_1526, 0x00022c), 249 REG(SYS_COUNT_TX_1527_MAX, 0x000230), 250 REG(SYS_COUNT_TX_AGING, 0x000278), 251 REG(SYS_RESET_CFG, 0x000e00), 252 REG(SYS_SR_ETYPE_CFG, 0x000e04), 253 REG(SYS_VLAN_ETYPE_CFG, 0x000e08), 254 REG(SYS_PORT_MODE, 0x000e0c), 255 REG(SYS_FRONT_PORT_MODE, 0x000e2c), 256 REG(SYS_FRM_AGING, 0x000e44), 257 REG(SYS_STAT_CFG, 0x000e48), 258 REG(SYS_SW_STATUS, 0x000e4c), 259 REG_RESERVED(SYS_MISC_CFG), 260 REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c), 261 REG(SYS_REW_MAC_LOW_CFG, 0x000e84), 262 REG(SYS_TIMESTAMP_OFFSET, 0x000e9c), 263 REG(SYS_PAUSE_CFG, 0x000ea0), 264 REG(SYS_PAUSE_TOT_CFG, 0x000ebc), 265 REG(SYS_ATOP, 0x000ec0), 266 REG(SYS_ATOP_TOT_CFG, 0x000edc), 267 REG(SYS_MAC_FC_CFG, 0x000ee0), 268 REG(SYS_MMGT, 0x000ef8), 269 REG_RESERVED(SYS_MMGT_FAST), 270 REG_RESERVED(SYS_EVENTS_DIF), 271 REG_RESERVED(SYS_EVENTS_CORE), 272 REG_RESERVED(SYS_CNT), 273 REG(SYS_PTP_STATUS, 0x000f14), 274 REG(SYS_PTP_TXSTAMP, 0x000f18), 275 REG(SYS_PTP_NXT, 0x000f1c), 276 REG(SYS_PTP_CFG, 0x000f20), 277 REG(SYS_RAM_INIT, 0x000f24), 278 REG_RESERVED(SYS_CM_ADDR), 279 REG_RESERVED(SYS_CM_DATA_WR), 280 REG_RESERVED(SYS_CM_DATA_RD), 281 REG_RESERVED(SYS_CM_OP), 282 REG_RESERVED(SYS_CM_DATA), 283 }; 284 285 static const u32 vsc9959_ptp_regmap[] = { 286 REG(PTP_PIN_CFG, 0x000000), 287 REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 288 REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 289 REG(PTP_PIN_TOD_NSEC, 0x00000c), 290 REG(PTP_CFG_MISC, 0x0000a0), 291 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 292 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 293 }; 294 295 static const u32 vsc9959_gcb_regmap[] = { 296 REG(GCB_SOFT_RST, 0x000004), 297 }; 298 299 static const u32 *vsc9959_regmap[] = { 300 [ANA] = vsc9959_ana_regmap, 301 [QS] = vsc9959_qs_regmap, 302 [QSYS] = vsc9959_qsys_regmap, 303 [REW] = vsc9959_rew_regmap, 304 [SYS] = vsc9959_sys_regmap, 305 [S2] = vsc9959_s2_regmap, 306 [PTP] = vsc9959_ptp_regmap, 307 [GCB] = vsc9959_gcb_regmap, 308 }; 309 310 /* Addresses are relative to the PCI device's base address and 311 * will be fixed up at ioremap time. 312 */ 313 static struct resource vsc9959_target_io_res[] = { 314 [ANA] = { 315 .start = 0x0280000, 316 .end = 0x028ffff, 317 .name = "ana", 318 }, 319 [QS] = { 320 .start = 0x0080000, 321 .end = 0x00800ff, 322 .name = "qs", 323 }, 324 [QSYS] = { 325 .start = 0x0200000, 326 .end = 0x021ffff, 327 .name = "qsys", 328 }, 329 [REW] = { 330 .start = 0x0030000, 331 .end = 0x003ffff, 332 .name = "rew", 333 }, 334 [SYS] = { 335 .start = 0x0010000, 336 .end = 0x001ffff, 337 .name = "sys", 338 }, 339 [S2] = { 340 .start = 0x0060000, 341 .end = 0x00603ff, 342 .name = "s2", 343 }, 344 [PTP] = { 345 .start = 0x0090000, 346 .end = 0x00900cb, 347 .name = "ptp", 348 }, 349 [GCB] = { 350 .start = 0x0070000, 351 .end = 0x00701ff, 352 .name = "devcpu_gcb", 353 }, 354 }; 355 356 static struct resource vsc9959_port_io_res[] = { 357 { 358 .start = 0x0100000, 359 .end = 0x010ffff, 360 .name = "port0", 361 }, 362 { 363 .start = 0x0110000, 364 .end = 0x011ffff, 365 .name = "port1", 366 }, 367 { 368 .start = 0x0120000, 369 .end = 0x012ffff, 370 .name = "port2", 371 }, 372 { 373 .start = 0x0130000, 374 .end = 0x013ffff, 375 .name = "port3", 376 }, 377 { 378 .start = 0x0140000, 379 .end = 0x014ffff, 380 .name = "port4", 381 }, 382 { 383 .start = 0x0150000, 384 .end = 0x015ffff, 385 .name = "port5", 386 }, 387 }; 388 389 static const struct reg_field vsc9959_regfields[] = { 390 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), 391 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5), 392 [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30), 393 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26), 394 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24), 395 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23), 396 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22), 397 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21), 398 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20), 399 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19), 400 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 401 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17), 402 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15), 403 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14), 404 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13), 405 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12), 406 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 407 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 408 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9), 409 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8), 410 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7), 411 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 412 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 413 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4), 414 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3), 415 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2), 416 [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1), 417 [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0), 418 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), 419 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), 420 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), 421 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0), 422 [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), 423 }; 424 425 static const struct ocelot_stat_layout vsc9959_stats_layout[] = { 426 { .offset = 0x00, .name = "rx_octets", }, 427 { .offset = 0x01, .name = "rx_unicast", }, 428 { .offset = 0x02, .name = "rx_multicast", }, 429 { .offset = 0x03, .name = "rx_broadcast", }, 430 { .offset = 0x04, .name = "rx_shorts", }, 431 { .offset = 0x05, .name = "rx_fragments", }, 432 { .offset = 0x06, .name = "rx_jabbers", }, 433 { .offset = 0x07, .name = "rx_crc_align_errs", }, 434 { .offset = 0x08, .name = "rx_sym_errs", }, 435 { .offset = 0x09, .name = "rx_frames_below_65_octets", }, 436 { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", }, 437 { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", }, 438 { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", }, 439 { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", }, 440 { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", }, 441 { .offset = 0x0F, .name = "rx_frames_over_1526_octets", }, 442 { .offset = 0x10, .name = "rx_pause", }, 443 { .offset = 0x11, .name = "rx_control", }, 444 { .offset = 0x12, .name = "rx_longs", }, 445 { .offset = 0x13, .name = "rx_classified_drops", }, 446 { .offset = 0x14, .name = "rx_red_prio_0", }, 447 { .offset = 0x15, .name = "rx_red_prio_1", }, 448 { .offset = 0x16, .name = "rx_red_prio_2", }, 449 { .offset = 0x17, .name = "rx_red_prio_3", }, 450 { .offset = 0x18, .name = "rx_red_prio_4", }, 451 { .offset = 0x19, .name = "rx_red_prio_5", }, 452 { .offset = 0x1A, .name = "rx_red_prio_6", }, 453 { .offset = 0x1B, .name = "rx_red_prio_7", }, 454 { .offset = 0x1C, .name = "rx_yellow_prio_0", }, 455 { .offset = 0x1D, .name = "rx_yellow_prio_1", }, 456 { .offset = 0x1E, .name = "rx_yellow_prio_2", }, 457 { .offset = 0x1F, .name = "rx_yellow_prio_3", }, 458 { .offset = 0x20, .name = "rx_yellow_prio_4", }, 459 { .offset = 0x21, .name = "rx_yellow_prio_5", }, 460 { .offset = 0x22, .name = "rx_yellow_prio_6", }, 461 { .offset = 0x23, .name = "rx_yellow_prio_7", }, 462 { .offset = 0x24, .name = "rx_green_prio_0", }, 463 { .offset = 0x25, .name = "rx_green_prio_1", }, 464 { .offset = 0x26, .name = "rx_green_prio_2", }, 465 { .offset = 0x27, .name = "rx_green_prio_3", }, 466 { .offset = 0x28, .name = "rx_green_prio_4", }, 467 { .offset = 0x29, .name = "rx_green_prio_5", }, 468 { .offset = 0x2A, .name = "rx_green_prio_6", }, 469 { .offset = 0x2B, .name = "rx_green_prio_7", }, 470 { .offset = 0x80, .name = "tx_octets", }, 471 { .offset = 0x81, .name = "tx_unicast", }, 472 { .offset = 0x82, .name = "tx_multicast", }, 473 { .offset = 0x83, .name = "tx_broadcast", }, 474 { .offset = 0x84, .name = "tx_collision", }, 475 { .offset = 0x85, .name = "tx_drops", }, 476 { .offset = 0x86, .name = "tx_pause", }, 477 { .offset = 0x87, .name = "tx_frames_below_65_octets", }, 478 { .offset = 0x88, .name = "tx_frames_65_to_127_octets", }, 479 { .offset = 0x89, .name = "tx_frames_128_255_octets", }, 480 { .offset = 0x8B, .name = "tx_frames_256_511_octets", }, 481 { .offset = 0x8C, .name = "tx_frames_1024_1526_octets", }, 482 { .offset = 0x8D, .name = "tx_frames_over_1526_octets", }, 483 { .offset = 0x8E, .name = "tx_yellow_prio_0", }, 484 { .offset = 0x8F, .name = "tx_yellow_prio_1", }, 485 { .offset = 0x90, .name = "tx_yellow_prio_2", }, 486 { .offset = 0x91, .name = "tx_yellow_prio_3", }, 487 { .offset = 0x92, .name = "tx_yellow_prio_4", }, 488 { .offset = 0x93, .name = "tx_yellow_prio_5", }, 489 { .offset = 0x94, .name = "tx_yellow_prio_6", }, 490 { .offset = 0x95, .name = "tx_yellow_prio_7", }, 491 { .offset = 0x96, .name = "tx_green_prio_0", }, 492 { .offset = 0x97, .name = "tx_green_prio_1", }, 493 { .offset = 0x98, .name = "tx_green_prio_2", }, 494 { .offset = 0x99, .name = "tx_green_prio_3", }, 495 { .offset = 0x9A, .name = "tx_green_prio_4", }, 496 { .offset = 0x9B, .name = "tx_green_prio_5", }, 497 { .offset = 0x9C, .name = "tx_green_prio_6", }, 498 { .offset = 0x9D, .name = "tx_green_prio_7", }, 499 { .offset = 0x9E, .name = "tx_aged", }, 500 { .offset = 0x100, .name = "drop_local", }, 501 { .offset = 0x101, .name = "drop_tail", }, 502 { .offset = 0x102, .name = "drop_yellow_prio_0", }, 503 { .offset = 0x103, .name = "drop_yellow_prio_1", }, 504 { .offset = 0x104, .name = "drop_yellow_prio_2", }, 505 { .offset = 0x105, .name = "drop_yellow_prio_3", }, 506 { .offset = 0x106, .name = "drop_yellow_prio_4", }, 507 { .offset = 0x107, .name = "drop_yellow_prio_5", }, 508 { .offset = 0x108, .name = "drop_yellow_prio_6", }, 509 { .offset = 0x109, .name = "drop_yellow_prio_7", }, 510 { .offset = 0x10A, .name = "drop_green_prio_0", }, 511 { .offset = 0x10B, .name = "drop_green_prio_1", }, 512 { .offset = 0x10C, .name = "drop_green_prio_2", }, 513 { .offset = 0x10D, .name = "drop_green_prio_3", }, 514 { .offset = 0x10E, .name = "drop_green_prio_4", }, 515 { .offset = 0x10F, .name = "drop_green_prio_5", }, 516 { .offset = 0x110, .name = "drop_green_prio_6", }, 517 { .offset = 0x111, .name = "drop_green_prio_7", }, 518 }; 519 520 #define VSC9959_INIT_TIMEOUT 50000 521 #define VSC9959_GCB_RST_SLEEP 100 522 #define VSC9959_SYS_RAMINIT_SLEEP 80 523 524 static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot) 525 { 526 int val; 527 528 regmap_field_read(ocelot->regfields[GCB_SOFT_RST_SWC_RST], &val); 529 530 return val; 531 } 532 533 static int vsc9959_sys_ram_init_status(struct ocelot *ocelot) 534 { 535 return ocelot_read(ocelot, SYS_RAM_INIT); 536 } 537 538 static int vsc9959_reset(struct ocelot *ocelot) 539 { 540 int val, err; 541 542 /* soft-reset the switch core */ 543 regmap_field_write(ocelot->regfields[GCB_SOFT_RST_SWC_RST], 1); 544 545 err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val, 546 VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT); 547 if (err) { 548 dev_err(ocelot->dev, "timeout: switch core reset\n"); 549 return err; 550 } 551 552 /* initialize switch mem ~40us */ 553 ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT); 554 err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val, 555 VSC9959_SYS_RAMINIT_SLEEP, 556 VSC9959_INIT_TIMEOUT); 557 if (err) { 558 dev_err(ocelot->dev, "timeout: switch sram init\n"); 559 return err; 560 } 561 562 /* enable switch core */ 563 regmap_field_write(ocelot->regfields[SYS_RESET_CFG_CORE_ENA], 1); 564 565 return 0; 566 } 567 568 static const struct ocelot_ops vsc9959_ops = { 569 .reset = vsc9959_reset, 570 }; 571 572 struct felix_info felix_info_vsc9959 = { 573 .target_io_res = vsc9959_target_io_res, 574 .port_io_res = vsc9959_port_io_res, 575 .regfields = vsc9959_regfields, 576 .map = vsc9959_regmap, 577 .ops = &vsc9959_ops, 578 .stats_layout = vsc9959_stats_layout, 579 .num_stats = ARRAY_SIZE(vsc9959_stats_layout), 580 .shared_queue_sz = 128 * 1024, 581 .num_ports = 6, 582 .pci_bar = 4, 583 }; 584