1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright 2017 Microsemi Corporation 3 * Copyright 2018-2019 NXP 4 */ 5 #include <linux/fsl/enetc_mdio.h> 6 #include <soc/mscc/ocelot_qsys.h> 7 #include <soc/mscc/ocelot_vcap.h> 8 #include <soc/mscc/ocelot_ana.h> 9 #include <soc/mscc/ocelot_ptp.h> 10 #include <soc/mscc/ocelot_sys.h> 11 #include <net/tc_act/tc_gate.h> 12 #include <soc/mscc/ocelot.h> 13 #include <linux/dsa/ocelot.h> 14 #include <linux/pcs-lynx.h> 15 #include <net/pkt_sched.h> 16 #include <linux/iopoll.h> 17 #include <linux/mdio.h> 18 #include <linux/pci.h> 19 #include <linux/time.h> 20 #include "felix.h" 21 22 #define VSC9959_NUM_PORTS 6 23 24 #define VSC9959_TAS_GCL_ENTRY_MAX 63 25 #define VSC9959_TAS_MIN_GATE_LEN_NS 33 26 #define VSC9959_VCAP_POLICER_BASE 63 27 #define VSC9959_VCAP_POLICER_MAX 383 28 #define VSC9959_SWITCH_PCI_BAR 4 29 #define VSC9959_IMDIO_PCI_BAR 0 30 31 #define VSC9959_PORT_MODE_SERDES (OCELOT_PORT_MODE_SGMII | \ 32 OCELOT_PORT_MODE_QSGMII | \ 33 OCELOT_PORT_MODE_1000BASEX | \ 34 OCELOT_PORT_MODE_2500BASEX | \ 35 OCELOT_PORT_MODE_USXGMII) 36 37 static const u32 vsc9959_port_modes[VSC9959_NUM_PORTS] = { 38 VSC9959_PORT_MODE_SERDES, 39 VSC9959_PORT_MODE_SERDES, 40 VSC9959_PORT_MODE_SERDES, 41 VSC9959_PORT_MODE_SERDES, 42 OCELOT_PORT_MODE_INTERNAL, 43 OCELOT_PORT_MODE_INTERNAL, 44 }; 45 46 static const u32 vsc9959_ana_regmap[] = { 47 REG(ANA_ADVLEARN, 0x0089a0), 48 REG(ANA_VLANMASK, 0x0089a4), 49 REG_RESERVED(ANA_PORT_B_DOMAIN), 50 REG(ANA_ANAGEFIL, 0x0089ac), 51 REG(ANA_ANEVENTS, 0x0089b0), 52 REG(ANA_STORMLIMIT_BURST, 0x0089b4), 53 REG(ANA_STORMLIMIT_CFG, 0x0089b8), 54 REG(ANA_ISOLATED_PORTS, 0x0089c8), 55 REG(ANA_COMMUNITY_PORTS, 0x0089cc), 56 REG(ANA_AUTOAGE, 0x0089d0), 57 REG(ANA_MACTOPTIONS, 0x0089d4), 58 REG(ANA_LEARNDISC, 0x0089d8), 59 REG(ANA_AGENCTRL, 0x0089dc), 60 REG(ANA_MIRRORPORTS, 0x0089e0), 61 REG(ANA_EMIRRORPORTS, 0x0089e4), 62 REG(ANA_FLOODING, 0x0089e8), 63 REG(ANA_FLOODING_IPMC, 0x008a08), 64 REG(ANA_SFLOW_CFG, 0x008a0c), 65 REG(ANA_PORT_MODE, 0x008a28), 66 REG(ANA_CUT_THRU_CFG, 0x008a48), 67 REG(ANA_PGID_PGID, 0x008400), 68 REG(ANA_TABLES_ANMOVED, 0x007f1c), 69 REG(ANA_TABLES_MACHDATA, 0x007f20), 70 REG(ANA_TABLES_MACLDATA, 0x007f24), 71 REG(ANA_TABLES_STREAMDATA, 0x007f28), 72 REG(ANA_TABLES_MACACCESS, 0x007f2c), 73 REG(ANA_TABLES_MACTINDX, 0x007f30), 74 REG(ANA_TABLES_VLANACCESS, 0x007f34), 75 REG(ANA_TABLES_VLANTIDX, 0x007f38), 76 REG(ANA_TABLES_ISDXACCESS, 0x007f3c), 77 REG(ANA_TABLES_ISDXTIDX, 0x007f40), 78 REG(ANA_TABLES_ENTRYLIM, 0x007f00), 79 REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44), 80 REG(ANA_TABLES_PTP_ID_LOW, 0x007f48), 81 REG(ANA_TABLES_STREAMACCESS, 0x007f4c), 82 REG(ANA_TABLES_STREAMTIDX, 0x007f50), 83 REG(ANA_TABLES_SEQ_HISTORY, 0x007f54), 84 REG(ANA_TABLES_SEQ_MASK, 0x007f58), 85 REG(ANA_TABLES_SFID_MASK, 0x007f5c), 86 REG(ANA_TABLES_SFIDACCESS, 0x007f60), 87 REG(ANA_TABLES_SFIDTIDX, 0x007f64), 88 REG(ANA_MSTI_STATE, 0x008600), 89 REG(ANA_OAM_UPM_LM_CNT, 0x008000), 90 REG(ANA_SG_ACCESS_CTRL, 0x008a64), 91 REG(ANA_SG_CONFIG_REG_1, 0x007fb0), 92 REG(ANA_SG_CONFIG_REG_2, 0x007fb4), 93 REG(ANA_SG_CONFIG_REG_3, 0x007fb8), 94 REG(ANA_SG_CONFIG_REG_4, 0x007fbc), 95 REG(ANA_SG_CONFIG_REG_5, 0x007fc0), 96 REG(ANA_SG_GCL_GS_CONFIG, 0x007f80), 97 REG(ANA_SG_GCL_TI_CONFIG, 0x007f90), 98 REG(ANA_SG_STATUS_REG_1, 0x008980), 99 REG(ANA_SG_STATUS_REG_2, 0x008984), 100 REG(ANA_SG_STATUS_REG_3, 0x008988), 101 REG(ANA_PORT_VLAN_CFG, 0x007800), 102 REG(ANA_PORT_DROP_CFG, 0x007804), 103 REG(ANA_PORT_QOS_CFG, 0x007808), 104 REG(ANA_PORT_VCAP_CFG, 0x00780c), 105 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810), 106 REG(ANA_PORT_VCAP_S2_CFG, 0x00781c), 107 REG(ANA_PORT_PCP_DEI_MAP, 0x007820), 108 REG(ANA_PORT_CPU_FWD_CFG, 0x007860), 109 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864), 110 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868), 111 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c), 112 REG(ANA_PORT_PORT_CFG, 0x007870), 113 REG(ANA_PORT_POL_CFG, 0x007874), 114 REG(ANA_PORT_PTP_CFG, 0x007878), 115 REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c), 116 REG(ANA_PORT_PTP_DLY2_CFG, 0x007880), 117 REG(ANA_PORT_SFID_CFG, 0x007884), 118 REG(ANA_PFC_PFC_CFG, 0x008800), 119 REG_RESERVED(ANA_PFC_PFC_TIMER), 120 REG_RESERVED(ANA_IPT_OAM_MEP_CFG), 121 REG_RESERVED(ANA_IPT_IPT), 122 REG_RESERVED(ANA_PPT_PPT), 123 REG_RESERVED(ANA_FID_MAP_FID_MAP), 124 REG(ANA_AGGR_CFG, 0x008a68), 125 REG(ANA_CPUQ_CFG, 0x008a6c), 126 REG_RESERVED(ANA_CPUQ_CFG2), 127 REG(ANA_CPUQ_8021_CFG, 0x008a74), 128 REG(ANA_DSCP_CFG, 0x008ab4), 129 REG(ANA_DSCP_REWR_CFG, 0x008bb4), 130 REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4), 131 REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14), 132 REG_RESERVED(ANA_VRAP_CFG), 133 REG_RESERVED(ANA_VRAP_HDR_DATA), 134 REG_RESERVED(ANA_VRAP_HDR_MASK), 135 REG(ANA_DISCARD_CFG, 0x008c40), 136 REG(ANA_FID_CFG, 0x008c44), 137 REG(ANA_POL_PIR_CFG, 0x004000), 138 REG(ANA_POL_CIR_CFG, 0x004004), 139 REG(ANA_POL_MODE_CFG, 0x004008), 140 REG(ANA_POL_PIR_STATE, 0x00400c), 141 REG(ANA_POL_CIR_STATE, 0x004010), 142 REG_RESERVED(ANA_POL_STATE), 143 REG(ANA_POL_FLOWC, 0x008c48), 144 REG(ANA_POL_HYST, 0x008cb4), 145 REG_RESERVED(ANA_POL_MISC_CFG), 146 }; 147 148 static const u32 vsc9959_qs_regmap[] = { 149 REG(QS_XTR_GRP_CFG, 0x000000), 150 REG(QS_XTR_RD, 0x000008), 151 REG(QS_XTR_FRM_PRUNING, 0x000010), 152 REG(QS_XTR_FLUSH, 0x000018), 153 REG(QS_XTR_DATA_PRESENT, 0x00001c), 154 REG(QS_XTR_CFG, 0x000020), 155 REG(QS_INJ_GRP_CFG, 0x000024), 156 REG(QS_INJ_WR, 0x00002c), 157 REG(QS_INJ_CTRL, 0x000034), 158 REG(QS_INJ_STATUS, 0x00003c), 159 REG(QS_INJ_ERR, 0x000040), 160 REG_RESERVED(QS_INH_DBG), 161 }; 162 163 static const u32 vsc9959_vcap_regmap[] = { 164 /* VCAP_CORE_CFG */ 165 REG(VCAP_CORE_UPDATE_CTRL, 0x000000), 166 REG(VCAP_CORE_MV_CFG, 0x000004), 167 /* VCAP_CORE_CACHE */ 168 REG(VCAP_CACHE_ENTRY_DAT, 0x000008), 169 REG(VCAP_CACHE_MASK_DAT, 0x000108), 170 REG(VCAP_CACHE_ACTION_DAT, 0x000208), 171 REG(VCAP_CACHE_CNT_DAT, 0x000308), 172 REG(VCAP_CACHE_TG_DAT, 0x000388), 173 /* VCAP_CONST */ 174 REG(VCAP_CONST_VCAP_VER, 0x000398), 175 REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c), 176 REG(VCAP_CONST_ENTRY_CNT, 0x0003a0), 177 REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4), 178 REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8), 179 REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac), 180 REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0), 181 REG(VCAP_CONST_CNT_WIDTH, 0x0003b4), 182 REG(VCAP_CONST_CORE_CNT, 0x0003b8), 183 REG(VCAP_CONST_IF_CNT, 0x0003bc), 184 }; 185 186 static const u32 vsc9959_qsys_regmap[] = { 187 REG(QSYS_PORT_MODE, 0x00f460), 188 REG(QSYS_SWITCH_PORT_MODE, 0x00f480), 189 REG(QSYS_STAT_CNT_CFG, 0x00f49c), 190 REG(QSYS_EEE_CFG, 0x00f4a0), 191 REG(QSYS_EEE_THRES, 0x00f4b8), 192 REG(QSYS_IGR_NO_SHARING, 0x00f4bc), 193 REG(QSYS_EGR_NO_SHARING, 0x00f4c0), 194 REG(QSYS_SW_STATUS, 0x00f4c4), 195 REG(QSYS_EXT_CPU_CFG, 0x00f4e0), 196 REG_RESERVED(QSYS_PAD_CFG), 197 REG(QSYS_CPU_GROUP_MAP, 0x00f4e8), 198 REG_RESERVED(QSYS_QMAP), 199 REG_RESERVED(QSYS_ISDX_SGRP), 200 REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), 201 REG(QSYS_TFRM_MISC, 0x00f50c), 202 REG(QSYS_TFRM_PORT_DLY, 0x00f510), 203 REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514), 204 REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518), 205 REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c), 206 REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520), 207 REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524), 208 REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528), 209 REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c), 210 REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530), 211 REG(QSYS_RED_PROFILE, 0x00f534), 212 REG(QSYS_RES_QOS_MODE, 0x00f574), 213 REG(QSYS_RES_CFG, 0x00c000), 214 REG(QSYS_RES_STAT, 0x00c004), 215 REG(QSYS_EGR_DROP_MODE, 0x00f578), 216 REG(QSYS_EQ_CTRL, 0x00f57c), 217 REG_RESERVED(QSYS_EVENTS_CORE), 218 REG(QSYS_QMAXSDU_CFG_0, 0x00f584), 219 REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0), 220 REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc), 221 REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8), 222 REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4), 223 REG(QSYS_QMAXSDU_CFG_5, 0x00f610), 224 REG(QSYS_QMAXSDU_CFG_6, 0x00f62c), 225 REG(QSYS_QMAXSDU_CFG_7, 0x00f648), 226 REG(QSYS_PREEMPTION_CFG, 0x00f664), 227 REG(QSYS_CIR_CFG, 0x000000), 228 REG(QSYS_EIR_CFG, 0x000004), 229 REG(QSYS_SE_CFG, 0x000008), 230 REG(QSYS_SE_DWRR_CFG, 0x00000c), 231 REG_RESERVED(QSYS_SE_CONNECT), 232 REG(QSYS_SE_DLB_SENSE, 0x000040), 233 REG(QSYS_CIR_STATE, 0x000044), 234 REG(QSYS_EIR_STATE, 0x000048), 235 REG_RESERVED(QSYS_SE_STATE), 236 REG(QSYS_HSCH_MISC_CFG, 0x00f67c), 237 REG(QSYS_TAG_CONFIG, 0x00f680), 238 REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698), 239 REG(QSYS_PORT_MAX_SDU, 0x00f69c), 240 REG(QSYS_PARAM_CFG_REG_1, 0x00f440), 241 REG(QSYS_PARAM_CFG_REG_2, 0x00f444), 242 REG(QSYS_PARAM_CFG_REG_3, 0x00f448), 243 REG(QSYS_PARAM_CFG_REG_4, 0x00f44c), 244 REG(QSYS_PARAM_CFG_REG_5, 0x00f450), 245 REG(QSYS_GCL_CFG_REG_1, 0x00f454), 246 REG(QSYS_GCL_CFG_REG_2, 0x00f458), 247 REG(QSYS_PARAM_STATUS_REG_1, 0x00f400), 248 REG(QSYS_PARAM_STATUS_REG_2, 0x00f404), 249 REG(QSYS_PARAM_STATUS_REG_3, 0x00f408), 250 REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c), 251 REG(QSYS_PARAM_STATUS_REG_5, 0x00f410), 252 REG(QSYS_PARAM_STATUS_REG_6, 0x00f414), 253 REG(QSYS_PARAM_STATUS_REG_7, 0x00f418), 254 REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c), 255 REG(QSYS_PARAM_STATUS_REG_9, 0x00f420), 256 REG(QSYS_GCL_STATUS_REG_1, 0x00f424), 257 REG(QSYS_GCL_STATUS_REG_2, 0x00f428), 258 }; 259 260 static const u32 vsc9959_rew_regmap[] = { 261 REG(REW_PORT_VLAN_CFG, 0x000000), 262 REG(REW_TAG_CFG, 0x000004), 263 REG(REW_PORT_CFG, 0x000008), 264 REG(REW_DSCP_CFG, 0x00000c), 265 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 266 REG(REW_PTP_CFG, 0x000050), 267 REG(REW_PTP_DLY1_CFG, 0x000054), 268 REG(REW_RED_TAG_CFG, 0x000058), 269 REG(REW_DSCP_REMAP_DP1_CFG, 0x000410), 270 REG(REW_DSCP_REMAP_CFG, 0x000510), 271 REG_RESERVED(REW_STAT_CFG), 272 REG_RESERVED(REW_REW_STICKY), 273 REG_RESERVED(REW_PPT), 274 }; 275 276 static const u32 vsc9959_sys_regmap[] = { 277 REG(SYS_COUNT_RX_OCTETS, 0x000000), 278 REG(SYS_COUNT_RX_UNICAST, 0x000004), 279 REG(SYS_COUNT_RX_MULTICAST, 0x000008), 280 REG(SYS_COUNT_RX_BROADCAST, 0x00000c), 281 REG(SYS_COUNT_RX_SHORTS, 0x000010), 282 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 283 REG(SYS_COUNT_RX_JABBERS, 0x000018), 284 REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c), 285 REG(SYS_COUNT_RX_SYM_ERRS, 0x000020), 286 REG(SYS_COUNT_RX_64, 0x000024), 287 REG(SYS_COUNT_RX_65_127, 0x000028), 288 REG(SYS_COUNT_RX_128_255, 0x00002c), 289 REG(SYS_COUNT_RX_256_511, 0x000030), 290 REG(SYS_COUNT_RX_512_1023, 0x000034), 291 REG(SYS_COUNT_RX_1024_1526, 0x000038), 292 REG(SYS_COUNT_RX_1527_MAX, 0x00003c), 293 REG(SYS_COUNT_RX_PAUSE, 0x000040), 294 REG(SYS_COUNT_RX_CONTROL, 0x000044), 295 REG(SYS_COUNT_RX_LONGS, 0x000048), 296 REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x00004c), 297 REG(SYS_COUNT_RX_RED_PRIO_0, 0x000050), 298 REG(SYS_COUNT_RX_RED_PRIO_1, 0x000054), 299 REG(SYS_COUNT_RX_RED_PRIO_2, 0x000058), 300 REG(SYS_COUNT_RX_RED_PRIO_3, 0x00005c), 301 REG(SYS_COUNT_RX_RED_PRIO_4, 0x000060), 302 REG(SYS_COUNT_RX_RED_PRIO_5, 0x000064), 303 REG(SYS_COUNT_RX_RED_PRIO_6, 0x000068), 304 REG(SYS_COUNT_RX_RED_PRIO_7, 0x00006c), 305 REG(SYS_COUNT_RX_YELLOW_PRIO_0, 0x000070), 306 REG(SYS_COUNT_RX_YELLOW_PRIO_1, 0x000074), 307 REG(SYS_COUNT_RX_YELLOW_PRIO_2, 0x000078), 308 REG(SYS_COUNT_RX_YELLOW_PRIO_3, 0x00007c), 309 REG(SYS_COUNT_RX_YELLOW_PRIO_4, 0x000080), 310 REG(SYS_COUNT_RX_YELLOW_PRIO_5, 0x000084), 311 REG(SYS_COUNT_RX_YELLOW_PRIO_6, 0x000088), 312 REG(SYS_COUNT_RX_YELLOW_PRIO_7, 0x00008c), 313 REG(SYS_COUNT_RX_GREEN_PRIO_0, 0x000090), 314 REG(SYS_COUNT_RX_GREEN_PRIO_1, 0x000094), 315 REG(SYS_COUNT_RX_GREEN_PRIO_2, 0x000098), 316 REG(SYS_COUNT_RX_GREEN_PRIO_3, 0x00009c), 317 REG(SYS_COUNT_RX_GREEN_PRIO_4, 0x0000a0), 318 REG(SYS_COUNT_RX_GREEN_PRIO_5, 0x0000a4), 319 REG(SYS_COUNT_RX_GREEN_PRIO_6, 0x0000a8), 320 REG(SYS_COUNT_RX_GREEN_PRIO_7, 0x0000ac), 321 REG(SYS_COUNT_TX_OCTETS, 0x000200), 322 REG(SYS_COUNT_TX_UNICAST, 0x000204), 323 REG(SYS_COUNT_TX_MULTICAST, 0x000208), 324 REG(SYS_COUNT_TX_BROADCAST, 0x00020c), 325 REG(SYS_COUNT_TX_COLLISION, 0x000210), 326 REG(SYS_COUNT_TX_DROPS, 0x000214), 327 REG(SYS_COUNT_TX_PAUSE, 0x000218), 328 REG(SYS_COUNT_TX_64, 0x00021c), 329 REG(SYS_COUNT_TX_65_127, 0x000220), 330 REG(SYS_COUNT_TX_128_255, 0x000224), 331 REG(SYS_COUNT_TX_256_511, 0x000228), 332 REG(SYS_COUNT_TX_512_1023, 0x00022c), 333 REG(SYS_COUNT_TX_1024_1526, 0x000230), 334 REG(SYS_COUNT_TX_1527_MAX, 0x000234), 335 REG(SYS_COUNT_TX_YELLOW_PRIO_0, 0x000238), 336 REG(SYS_COUNT_TX_YELLOW_PRIO_1, 0x00023c), 337 REG(SYS_COUNT_TX_YELLOW_PRIO_2, 0x000240), 338 REG(SYS_COUNT_TX_YELLOW_PRIO_3, 0x000244), 339 REG(SYS_COUNT_TX_YELLOW_PRIO_4, 0x000248), 340 REG(SYS_COUNT_TX_YELLOW_PRIO_5, 0x00024c), 341 REG(SYS_COUNT_TX_YELLOW_PRIO_6, 0x000250), 342 REG(SYS_COUNT_TX_YELLOW_PRIO_7, 0x000254), 343 REG(SYS_COUNT_TX_GREEN_PRIO_0, 0x000258), 344 REG(SYS_COUNT_TX_GREEN_PRIO_1, 0x00025c), 345 REG(SYS_COUNT_TX_GREEN_PRIO_2, 0x000260), 346 REG(SYS_COUNT_TX_GREEN_PRIO_3, 0x000264), 347 REG(SYS_COUNT_TX_GREEN_PRIO_4, 0x000268), 348 REG(SYS_COUNT_TX_GREEN_PRIO_5, 0x00026c), 349 REG(SYS_COUNT_TX_GREEN_PRIO_6, 0x000270), 350 REG(SYS_COUNT_TX_GREEN_PRIO_7, 0x000274), 351 REG(SYS_COUNT_TX_AGED, 0x000278), 352 REG(SYS_COUNT_DROP_LOCAL, 0x000400), 353 REG(SYS_COUNT_DROP_TAIL, 0x000404), 354 REG(SYS_COUNT_DROP_YELLOW_PRIO_0, 0x000408), 355 REG(SYS_COUNT_DROP_YELLOW_PRIO_1, 0x00040c), 356 REG(SYS_COUNT_DROP_YELLOW_PRIO_2, 0x000410), 357 REG(SYS_COUNT_DROP_YELLOW_PRIO_3, 0x000414), 358 REG(SYS_COUNT_DROP_YELLOW_PRIO_4, 0x000418), 359 REG(SYS_COUNT_DROP_YELLOW_PRIO_5, 0x00041c), 360 REG(SYS_COUNT_DROP_YELLOW_PRIO_6, 0x000420), 361 REG(SYS_COUNT_DROP_YELLOW_PRIO_7, 0x000424), 362 REG(SYS_COUNT_DROP_GREEN_PRIO_0, 0x000428), 363 REG(SYS_COUNT_DROP_GREEN_PRIO_1, 0x00042c), 364 REG(SYS_COUNT_DROP_GREEN_PRIO_2, 0x000430), 365 REG(SYS_COUNT_DROP_GREEN_PRIO_3, 0x000434), 366 REG(SYS_COUNT_DROP_GREEN_PRIO_4, 0x000438), 367 REG(SYS_COUNT_DROP_GREEN_PRIO_5, 0x00043c), 368 REG(SYS_COUNT_DROP_GREEN_PRIO_6, 0x000440), 369 REG(SYS_COUNT_DROP_GREEN_PRIO_7, 0x000444), 370 REG(SYS_COUNT_SF_MATCHING_FRAMES, 0x000800), 371 REG(SYS_COUNT_SF_NOT_PASSING_FRAMES, 0x000804), 372 REG(SYS_COUNT_SF_NOT_PASSING_SDU, 0x000808), 373 REG(SYS_COUNT_SF_RED_FRAMES, 0x00080c), 374 REG(SYS_RESET_CFG, 0x000e00), 375 REG(SYS_SR_ETYPE_CFG, 0x000e04), 376 REG(SYS_VLAN_ETYPE_CFG, 0x000e08), 377 REG(SYS_PORT_MODE, 0x000e0c), 378 REG(SYS_FRONT_PORT_MODE, 0x000e2c), 379 REG(SYS_FRM_AGING, 0x000e44), 380 REG(SYS_STAT_CFG, 0x000e48), 381 REG(SYS_SW_STATUS, 0x000e4c), 382 REG_RESERVED(SYS_MISC_CFG), 383 REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c), 384 REG(SYS_REW_MAC_LOW_CFG, 0x000e84), 385 REG(SYS_TIMESTAMP_OFFSET, 0x000e9c), 386 REG(SYS_PAUSE_CFG, 0x000ea0), 387 REG(SYS_PAUSE_TOT_CFG, 0x000ebc), 388 REG(SYS_ATOP, 0x000ec0), 389 REG(SYS_ATOP_TOT_CFG, 0x000edc), 390 REG(SYS_MAC_FC_CFG, 0x000ee0), 391 REG(SYS_MMGT, 0x000ef8), 392 REG_RESERVED(SYS_MMGT_FAST), 393 REG_RESERVED(SYS_EVENTS_DIF), 394 REG_RESERVED(SYS_EVENTS_CORE), 395 REG(SYS_PTP_STATUS, 0x000f14), 396 REG(SYS_PTP_TXSTAMP, 0x000f18), 397 REG(SYS_PTP_NXT, 0x000f1c), 398 REG(SYS_PTP_CFG, 0x000f20), 399 REG(SYS_RAM_INIT, 0x000f24), 400 REG_RESERVED(SYS_CM_ADDR), 401 REG_RESERVED(SYS_CM_DATA_WR), 402 REG_RESERVED(SYS_CM_DATA_RD), 403 REG_RESERVED(SYS_CM_OP), 404 REG_RESERVED(SYS_CM_DATA), 405 }; 406 407 static const u32 vsc9959_ptp_regmap[] = { 408 REG(PTP_PIN_CFG, 0x000000), 409 REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 410 REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 411 REG(PTP_PIN_TOD_NSEC, 0x00000c), 412 REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 413 REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 414 REG(PTP_CFG_MISC, 0x0000a0), 415 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 416 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 417 }; 418 419 static const u32 vsc9959_gcb_regmap[] = { 420 REG(GCB_SOFT_RST, 0x000004), 421 }; 422 423 static const u32 vsc9959_dev_gmii_regmap[] = { 424 REG(DEV_CLOCK_CFG, 0x0), 425 REG(DEV_PORT_MISC, 0x4), 426 REG(DEV_EVENTS, 0x8), 427 REG(DEV_EEE_CFG, 0xc), 428 REG(DEV_RX_PATH_DELAY, 0x10), 429 REG(DEV_TX_PATH_DELAY, 0x14), 430 REG(DEV_PTP_PREDICT_CFG, 0x18), 431 REG(DEV_MAC_ENA_CFG, 0x1c), 432 REG(DEV_MAC_MODE_CFG, 0x20), 433 REG(DEV_MAC_MAXLEN_CFG, 0x24), 434 REG(DEV_MAC_TAGS_CFG, 0x28), 435 REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 436 REG(DEV_MAC_IFG_CFG, 0x30), 437 REG(DEV_MAC_HDX_CFG, 0x34), 438 REG(DEV_MAC_DBG_CFG, 0x38), 439 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 440 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 441 REG(DEV_MAC_STICKY, 0x44), 442 REG_RESERVED(PCS1G_CFG), 443 REG_RESERVED(PCS1G_MODE_CFG), 444 REG_RESERVED(PCS1G_SD_CFG), 445 REG_RESERVED(PCS1G_ANEG_CFG), 446 REG_RESERVED(PCS1G_ANEG_NP_CFG), 447 REG_RESERVED(PCS1G_LB_CFG), 448 REG_RESERVED(PCS1G_DBG_CFG), 449 REG_RESERVED(PCS1G_CDET_CFG), 450 REG_RESERVED(PCS1G_ANEG_STATUS), 451 REG_RESERVED(PCS1G_ANEG_NP_STATUS), 452 REG_RESERVED(PCS1G_LINK_STATUS), 453 REG_RESERVED(PCS1G_LINK_DOWN_CNT), 454 REG_RESERVED(PCS1G_STICKY), 455 REG_RESERVED(PCS1G_DEBUG_STATUS), 456 REG_RESERVED(PCS1G_LPI_CFG), 457 REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT), 458 REG_RESERVED(PCS1G_LPI_STATUS), 459 REG_RESERVED(PCS1G_TSTPAT_MODE_CFG), 460 REG_RESERVED(PCS1G_TSTPAT_STATUS), 461 REG_RESERVED(DEV_PCS_FX100_CFG), 462 REG_RESERVED(DEV_PCS_FX100_STATUS), 463 }; 464 465 static const u32 *vsc9959_regmap[TARGET_MAX] = { 466 [ANA] = vsc9959_ana_regmap, 467 [QS] = vsc9959_qs_regmap, 468 [QSYS] = vsc9959_qsys_regmap, 469 [REW] = vsc9959_rew_regmap, 470 [SYS] = vsc9959_sys_regmap, 471 [S0] = vsc9959_vcap_regmap, 472 [S1] = vsc9959_vcap_regmap, 473 [S2] = vsc9959_vcap_regmap, 474 [PTP] = vsc9959_ptp_regmap, 475 [GCB] = vsc9959_gcb_regmap, 476 [DEV_GMII] = vsc9959_dev_gmii_regmap, 477 }; 478 479 /* Addresses are relative to the PCI device's base address */ 480 static const struct resource vsc9959_target_io_res[TARGET_MAX] = { 481 [ANA] = { 482 .start = 0x0280000, 483 .end = 0x028ffff, 484 .name = "ana", 485 }, 486 [QS] = { 487 .start = 0x0080000, 488 .end = 0x00800ff, 489 .name = "qs", 490 }, 491 [QSYS] = { 492 .start = 0x0200000, 493 .end = 0x021ffff, 494 .name = "qsys", 495 }, 496 [REW] = { 497 .start = 0x0030000, 498 .end = 0x003ffff, 499 .name = "rew", 500 }, 501 [SYS] = { 502 .start = 0x0010000, 503 .end = 0x001ffff, 504 .name = "sys", 505 }, 506 [S0] = { 507 .start = 0x0040000, 508 .end = 0x00403ff, 509 .name = "s0", 510 }, 511 [S1] = { 512 .start = 0x0050000, 513 .end = 0x00503ff, 514 .name = "s1", 515 }, 516 [S2] = { 517 .start = 0x0060000, 518 .end = 0x00603ff, 519 .name = "s2", 520 }, 521 [PTP] = { 522 .start = 0x0090000, 523 .end = 0x00900cb, 524 .name = "ptp", 525 }, 526 [GCB] = { 527 .start = 0x0070000, 528 .end = 0x00701ff, 529 .name = "devcpu_gcb", 530 }, 531 }; 532 533 static const struct resource vsc9959_port_io_res[] = { 534 { 535 .start = 0x0100000, 536 .end = 0x010ffff, 537 .name = "port0", 538 }, 539 { 540 .start = 0x0110000, 541 .end = 0x011ffff, 542 .name = "port1", 543 }, 544 { 545 .start = 0x0120000, 546 .end = 0x012ffff, 547 .name = "port2", 548 }, 549 { 550 .start = 0x0130000, 551 .end = 0x013ffff, 552 .name = "port3", 553 }, 554 { 555 .start = 0x0140000, 556 .end = 0x014ffff, 557 .name = "port4", 558 }, 559 { 560 .start = 0x0150000, 561 .end = 0x015ffff, 562 .name = "port5", 563 }, 564 }; 565 566 /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an 567 * SGMII/QSGMII MAC PCS can be found. 568 */ 569 static const struct resource vsc9959_imdio_res = { 570 .start = 0x8030, 571 .end = 0x8040, 572 .name = "imdio", 573 }; 574 575 static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = { 576 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), 577 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5), 578 [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30), 579 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26), 580 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24), 581 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23), 582 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22), 583 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21), 584 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20), 585 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19), 586 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 587 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17), 588 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15), 589 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14), 590 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13), 591 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12), 592 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 593 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 594 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9), 595 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8), 596 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7), 597 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 598 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 599 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4), 600 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3), 601 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2), 602 [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1), 603 [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0), 604 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), 605 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), 606 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), 607 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0), 608 [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), 609 /* Replicated per number of ports (7), register size 4 per port */ 610 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4), 611 [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4), 612 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4), 613 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4), 614 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4), 615 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4), 616 [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4), 617 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4), 618 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4), 619 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4), 620 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4), 621 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4), 622 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4), 623 }; 624 625 static const struct ocelot_stat_layout vsc9959_stats_layout[OCELOT_NUM_STATS] = { 626 OCELOT_COMMON_STATS, 627 }; 628 629 static const struct vcap_field vsc9959_vcap_es0_keys[] = { 630 [VCAP_ES0_EGR_PORT] = { 0, 3}, 631 [VCAP_ES0_IGR_PORT] = { 3, 3}, 632 [VCAP_ES0_RSV] = { 6, 2}, 633 [VCAP_ES0_L2_MC] = { 8, 1}, 634 [VCAP_ES0_L2_BC] = { 9, 1}, 635 [VCAP_ES0_VID] = { 10, 12}, 636 [VCAP_ES0_DP] = { 22, 1}, 637 [VCAP_ES0_PCP] = { 23, 3}, 638 }; 639 640 static const struct vcap_field vsc9959_vcap_es0_actions[] = { 641 [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2}, 642 [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1}, 643 [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2}, 644 [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1}, 645 [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2}, 646 [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2}, 647 [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2}, 648 [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1}, 649 [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2}, 650 [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2}, 651 [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12}, 652 [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3}, 653 [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1}, 654 [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12}, 655 [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3}, 656 [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1}, 657 [VCAP_ES0_ACT_RSV] = { 49, 23}, 658 [VCAP_ES0_ACT_HIT_STICKY] = { 72, 1}, 659 }; 660 661 static const struct vcap_field vsc9959_vcap_is1_keys[] = { 662 [VCAP_IS1_HK_TYPE] = { 0, 1}, 663 [VCAP_IS1_HK_LOOKUP] = { 1, 2}, 664 [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 7}, 665 [VCAP_IS1_HK_RSV] = { 10, 9}, 666 [VCAP_IS1_HK_OAM_Y1731] = { 19, 1}, 667 [VCAP_IS1_HK_L2_MC] = { 20, 1}, 668 [VCAP_IS1_HK_L2_BC] = { 21, 1}, 669 [VCAP_IS1_HK_IP_MC] = { 22, 1}, 670 [VCAP_IS1_HK_VLAN_TAGGED] = { 23, 1}, 671 [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 24, 1}, 672 [VCAP_IS1_HK_TPID] = { 25, 1}, 673 [VCAP_IS1_HK_VID] = { 26, 12}, 674 [VCAP_IS1_HK_DEI] = { 38, 1}, 675 [VCAP_IS1_HK_PCP] = { 39, 3}, 676 /* Specific Fields for IS1 Half Key S1_NORMAL */ 677 [VCAP_IS1_HK_L2_SMAC] = { 42, 48}, 678 [VCAP_IS1_HK_ETYPE_LEN] = { 90, 1}, 679 [VCAP_IS1_HK_ETYPE] = { 91, 16}, 680 [VCAP_IS1_HK_IP_SNAP] = {107, 1}, 681 [VCAP_IS1_HK_IP4] = {108, 1}, 682 /* Layer-3 Information */ 683 [VCAP_IS1_HK_L3_FRAGMENT] = {109, 1}, 684 [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {110, 1}, 685 [VCAP_IS1_HK_L3_OPTIONS] = {111, 1}, 686 [VCAP_IS1_HK_L3_DSCP] = {112, 6}, 687 [VCAP_IS1_HK_L3_IP4_SIP] = {118, 32}, 688 /* Layer-4 Information */ 689 [VCAP_IS1_HK_TCP_UDP] = {150, 1}, 690 [VCAP_IS1_HK_TCP] = {151, 1}, 691 [VCAP_IS1_HK_L4_SPORT] = {152, 16}, 692 [VCAP_IS1_HK_L4_RNG] = {168, 8}, 693 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 694 [VCAP_IS1_HK_IP4_INNER_TPID] = { 42, 1}, 695 [VCAP_IS1_HK_IP4_INNER_VID] = { 43, 12}, 696 [VCAP_IS1_HK_IP4_INNER_DEI] = { 55, 1}, 697 [VCAP_IS1_HK_IP4_INNER_PCP] = { 56, 3}, 698 [VCAP_IS1_HK_IP4_IP4] = { 59, 1}, 699 [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 60, 1}, 700 [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 61, 1}, 701 [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 62, 1}, 702 [VCAP_IS1_HK_IP4_L3_DSCP] = { 63, 6}, 703 [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 69, 32}, 704 [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {101, 32}, 705 [VCAP_IS1_HK_IP4_L3_PROTO] = {133, 8}, 706 [VCAP_IS1_HK_IP4_TCP_UDP] = {141, 1}, 707 [VCAP_IS1_HK_IP4_TCP] = {142, 1}, 708 [VCAP_IS1_HK_IP4_L4_RNG] = {143, 8}, 709 [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {151, 32}, 710 }; 711 712 static const struct vcap_field vsc9959_vcap_is1_actions[] = { 713 [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1}, 714 [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6}, 715 [VCAP_IS1_ACT_QOS_ENA] = { 7, 1}, 716 [VCAP_IS1_ACT_QOS_VAL] = { 8, 3}, 717 [VCAP_IS1_ACT_DP_ENA] = { 11, 1}, 718 [VCAP_IS1_ACT_DP_VAL] = { 12, 1}, 719 [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8}, 720 [VCAP_IS1_ACT_PAG_VAL] = { 21, 8}, 721 [VCAP_IS1_ACT_RSV] = { 29, 9}, 722 /* The fields below are incorrectly shifted by 2 in the manual */ 723 [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1}, 724 [VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12}, 725 [VCAP_IS1_ACT_FID_SEL] = { 51, 2}, 726 [VCAP_IS1_ACT_FID_VAL] = { 53, 13}, 727 [VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1}, 728 [VCAP_IS1_ACT_PCP_VAL] = { 67, 3}, 729 [VCAP_IS1_ACT_DEI_VAL] = { 70, 1}, 730 [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1}, 731 [VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2}, 732 [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4}, 733 [VCAP_IS1_ACT_HIT_STICKY] = { 78, 1}, 734 }; 735 736 static struct vcap_field vsc9959_vcap_is2_keys[] = { 737 /* Common: 41 bits */ 738 [VCAP_IS2_TYPE] = { 0, 4}, 739 [VCAP_IS2_HK_FIRST] = { 4, 1}, 740 [VCAP_IS2_HK_PAG] = { 5, 8}, 741 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 7}, 742 [VCAP_IS2_HK_RSV2] = { 20, 1}, 743 [VCAP_IS2_HK_HOST_MATCH] = { 21, 1}, 744 [VCAP_IS2_HK_L2_MC] = { 22, 1}, 745 [VCAP_IS2_HK_L2_BC] = { 23, 1}, 746 [VCAP_IS2_HK_VLAN_TAGGED] = { 24, 1}, 747 [VCAP_IS2_HK_VID] = { 25, 12}, 748 [VCAP_IS2_HK_DEI] = { 37, 1}, 749 [VCAP_IS2_HK_PCP] = { 38, 3}, 750 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 751 [VCAP_IS2_HK_L2_DMAC] = { 41, 48}, 752 [VCAP_IS2_HK_L2_SMAC] = { 89, 48}, 753 /* MAC_ETYPE (TYPE=000) */ 754 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {137, 16}, 755 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {153, 16}, 756 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {169, 8}, 757 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {177, 3}, 758 /* MAC_LLC (TYPE=001) */ 759 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {137, 40}, 760 /* MAC_SNAP (TYPE=010) */ 761 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {137, 40}, 762 /* MAC_ARP (TYPE=011) */ 763 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 41, 48}, 764 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 89, 1}, 765 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 90, 1}, 766 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 91, 1}, 767 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 92, 1}, 768 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 93, 1}, 769 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 94, 1}, 770 [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 95, 2}, 771 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 97, 32}, 772 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {129, 32}, 773 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {161, 1}, 774 /* IP4_TCP_UDP / IP4_OTHER common */ 775 [VCAP_IS2_HK_IP4] = { 41, 1}, 776 [VCAP_IS2_HK_L3_FRAGMENT] = { 42, 1}, 777 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 43, 1}, 778 [VCAP_IS2_HK_L3_OPTIONS] = { 44, 1}, 779 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 45, 1}, 780 [VCAP_IS2_HK_L3_TOS] = { 46, 8}, 781 [VCAP_IS2_HK_L3_IP4_DIP] = { 54, 32}, 782 [VCAP_IS2_HK_L3_IP4_SIP] = { 86, 32}, 783 [VCAP_IS2_HK_DIP_EQ_SIP] = {118, 1}, 784 /* IP4_TCP_UDP (TYPE=100) */ 785 [VCAP_IS2_HK_TCP] = {119, 1}, 786 [VCAP_IS2_HK_L4_DPORT] = {120, 16}, 787 [VCAP_IS2_HK_L4_SPORT] = {136, 16}, 788 [VCAP_IS2_HK_L4_RNG] = {152, 8}, 789 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {160, 1}, 790 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {161, 1}, 791 [VCAP_IS2_HK_L4_FIN] = {162, 1}, 792 [VCAP_IS2_HK_L4_SYN] = {163, 1}, 793 [VCAP_IS2_HK_L4_RST] = {164, 1}, 794 [VCAP_IS2_HK_L4_PSH] = {165, 1}, 795 [VCAP_IS2_HK_L4_ACK] = {166, 1}, 796 [VCAP_IS2_HK_L4_URG] = {167, 1}, 797 [VCAP_IS2_HK_L4_1588_DOM] = {168, 8}, 798 [VCAP_IS2_HK_L4_1588_VER] = {176, 4}, 799 /* IP4_OTHER (TYPE=101) */ 800 [VCAP_IS2_HK_IP4_L3_PROTO] = {119, 8}, 801 [VCAP_IS2_HK_L3_PAYLOAD] = {127, 56}, 802 /* IP6_STD (TYPE=110) */ 803 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 41, 1}, 804 [VCAP_IS2_HK_L3_IP6_SIP] = { 42, 128}, 805 [VCAP_IS2_HK_IP6_L3_PROTO] = {170, 8}, 806 /* OAM (TYPE=111) */ 807 [VCAP_IS2_HK_OAM_MEL_FLAGS] = {137, 7}, 808 [VCAP_IS2_HK_OAM_VER] = {144, 5}, 809 [VCAP_IS2_HK_OAM_OPCODE] = {149, 8}, 810 [VCAP_IS2_HK_OAM_FLAGS] = {157, 8}, 811 [VCAP_IS2_HK_OAM_MEPID] = {165, 16}, 812 [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {181, 1}, 813 [VCAP_IS2_HK_OAM_IS_Y1731] = {182, 1}, 814 }; 815 816 static struct vcap_field vsc9959_vcap_is2_actions[] = { 817 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 818 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 819 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 820 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 821 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 822 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 823 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 824 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 825 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 826 [VCAP_IS2_ACT_PORT_MASK] = { 20, 6}, 827 [VCAP_IS2_ACT_REW_OP] = { 26, 9}, 828 [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 35, 1}, 829 [VCAP_IS2_ACT_RSV] = { 36, 2}, 830 [VCAP_IS2_ACT_ACL_ID] = { 38, 6}, 831 [VCAP_IS2_ACT_HIT_CNT] = { 44, 32}, 832 }; 833 834 static struct vcap_props vsc9959_vcap_props[] = { 835 [VCAP_ES0] = { 836 .action_type_width = 0, 837 .action_table = { 838 [ES0_ACTION_TYPE_NORMAL] = { 839 .width = 72, /* HIT_STICKY not included */ 840 .count = 1, 841 }, 842 }, 843 .target = S0, 844 .keys = vsc9959_vcap_es0_keys, 845 .actions = vsc9959_vcap_es0_actions, 846 }, 847 [VCAP_IS1] = { 848 .action_type_width = 0, 849 .action_table = { 850 [IS1_ACTION_TYPE_NORMAL] = { 851 .width = 78, /* HIT_STICKY not included */ 852 .count = 4, 853 }, 854 }, 855 .target = S1, 856 .keys = vsc9959_vcap_is1_keys, 857 .actions = vsc9959_vcap_is1_actions, 858 }, 859 [VCAP_IS2] = { 860 .action_type_width = 1, 861 .action_table = { 862 [IS2_ACTION_TYPE_NORMAL] = { 863 .width = 44, 864 .count = 2 865 }, 866 [IS2_ACTION_TYPE_SMAC_SIP] = { 867 .width = 6, 868 .count = 4 869 }, 870 }, 871 .target = S2, 872 .keys = vsc9959_vcap_is2_keys, 873 .actions = vsc9959_vcap_is2_actions, 874 }, 875 }; 876 877 static const struct ptp_clock_info vsc9959_ptp_caps = { 878 .owner = THIS_MODULE, 879 .name = "felix ptp", 880 .max_adj = 0x7fffffff, 881 .n_alarm = 0, 882 .n_ext_ts = 0, 883 .n_per_out = OCELOT_PTP_PINS_NUM, 884 .n_pins = OCELOT_PTP_PINS_NUM, 885 .pps = 0, 886 .gettime64 = ocelot_ptp_gettime64, 887 .settime64 = ocelot_ptp_settime64, 888 .adjtime = ocelot_ptp_adjtime, 889 .adjfine = ocelot_ptp_adjfine, 890 .verify = ocelot_ptp_verify, 891 .enable = ocelot_ptp_enable, 892 }; 893 894 #define VSC9959_INIT_TIMEOUT 50000 895 #define VSC9959_GCB_RST_SLEEP 100 896 #define VSC9959_SYS_RAMINIT_SLEEP 80 897 898 static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot) 899 { 900 int val; 901 902 ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val); 903 904 return val; 905 } 906 907 static int vsc9959_sys_ram_init_status(struct ocelot *ocelot) 908 { 909 return ocelot_read(ocelot, SYS_RAM_INIT); 910 } 911 912 /* CORE_ENA is in SYS:SYSTEM:RESET_CFG 913 * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT 914 */ 915 static int vsc9959_reset(struct ocelot *ocelot) 916 { 917 int val, err; 918 919 /* soft-reset the switch core */ 920 ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1); 921 922 err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val, 923 VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT); 924 if (err) { 925 dev_err(ocelot->dev, "timeout: switch core reset\n"); 926 return err; 927 } 928 929 /* initialize switch mem ~40us */ 930 ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT); 931 err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val, 932 VSC9959_SYS_RAMINIT_SLEEP, 933 VSC9959_INIT_TIMEOUT); 934 if (err) { 935 dev_err(ocelot->dev, "timeout: switch sram init\n"); 936 return err; 937 } 938 939 /* enable switch core */ 940 ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1); 941 942 return 0; 943 } 944 945 static void vsc9959_phylink_validate(struct ocelot *ocelot, int port, 946 unsigned long *supported, 947 struct phylink_link_state *state) 948 { 949 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 950 951 phylink_set_port_modes(mask); 952 phylink_set(mask, Autoneg); 953 phylink_set(mask, Pause); 954 phylink_set(mask, Asym_Pause); 955 phylink_set(mask, 10baseT_Half); 956 phylink_set(mask, 10baseT_Full); 957 phylink_set(mask, 100baseT_Half); 958 phylink_set(mask, 100baseT_Full); 959 phylink_set(mask, 1000baseT_Half); 960 phylink_set(mask, 1000baseT_Full); 961 phylink_set(mask, 1000baseX_Full); 962 963 if (state->interface == PHY_INTERFACE_MODE_INTERNAL || 964 state->interface == PHY_INTERFACE_MODE_2500BASEX || 965 state->interface == PHY_INTERFACE_MODE_USXGMII) { 966 phylink_set(mask, 2500baseT_Full); 967 phylink_set(mask, 2500baseX_Full); 968 } 969 970 linkmode_and(supported, supported, mask); 971 linkmode_and(state->advertising, state->advertising, mask); 972 } 973 974 /* Watermark encode 975 * Bit 8: Unit; 0:1, 1:16 976 * Bit 7-0: Value to be multiplied with unit 977 */ 978 static u16 vsc9959_wm_enc(u16 value) 979 { 980 WARN_ON(value >= 16 * BIT(8)); 981 982 if (value >= BIT(8)) 983 return BIT(8) | (value / 16); 984 985 return value; 986 } 987 988 static u16 vsc9959_wm_dec(u16 wm) 989 { 990 WARN_ON(wm & ~GENMASK(8, 0)); 991 992 if (wm & BIT(8)) 993 return (wm & GENMASK(7, 0)) * 16; 994 995 return wm; 996 } 997 998 static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse) 999 { 1000 *inuse = (val & GENMASK(23, 12)) >> 12; 1001 *maxuse = val & GENMASK(11, 0); 1002 } 1003 1004 static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot) 1005 { 1006 struct felix *felix = ocelot_to_felix(ocelot); 1007 struct enetc_mdio_priv *mdio_priv; 1008 struct device *dev = ocelot->dev; 1009 void __iomem *imdio_regs; 1010 struct resource res; 1011 struct enetc_hw *hw; 1012 struct mii_bus *bus; 1013 int port; 1014 int rc; 1015 1016 felix->pcs = devm_kcalloc(dev, felix->info->num_ports, 1017 sizeof(struct phylink_pcs *), 1018 GFP_KERNEL); 1019 if (!felix->pcs) { 1020 dev_err(dev, "failed to allocate array for PCS PHYs\n"); 1021 return -ENOMEM; 1022 } 1023 1024 memcpy(&res, felix->info->imdio_res, sizeof(res)); 1025 res.flags = IORESOURCE_MEM; 1026 res.start += felix->imdio_base; 1027 res.end += felix->imdio_base; 1028 1029 imdio_regs = devm_ioremap_resource(dev, &res); 1030 if (IS_ERR(imdio_regs)) 1031 return PTR_ERR(imdio_regs); 1032 1033 hw = enetc_hw_alloc(dev, imdio_regs); 1034 if (IS_ERR(hw)) { 1035 dev_err(dev, "failed to allocate ENETC HW structure\n"); 1036 return PTR_ERR(hw); 1037 } 1038 1039 bus = mdiobus_alloc_size(sizeof(*mdio_priv)); 1040 if (!bus) 1041 return -ENOMEM; 1042 1043 bus->name = "VSC9959 internal MDIO bus"; 1044 bus->read = enetc_mdio_read; 1045 bus->write = enetc_mdio_write; 1046 bus->parent = dev; 1047 mdio_priv = bus->priv; 1048 mdio_priv->hw = hw; 1049 /* This gets added to imdio_regs, which already maps addresses 1050 * starting with the proper offset. 1051 */ 1052 mdio_priv->mdio_base = 0; 1053 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); 1054 1055 /* Needed in order to initialize the bus mutex lock */ 1056 rc = mdiobus_register(bus); 1057 if (rc < 0) { 1058 dev_err(dev, "failed to register MDIO bus\n"); 1059 mdiobus_free(bus); 1060 return rc; 1061 } 1062 1063 felix->imdio = bus; 1064 1065 for (port = 0; port < felix->info->num_ports; port++) { 1066 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1067 struct phylink_pcs *phylink_pcs; 1068 struct mdio_device *mdio_device; 1069 1070 if (dsa_is_unused_port(felix->ds, port)) 1071 continue; 1072 1073 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL) 1074 continue; 1075 1076 mdio_device = mdio_device_create(felix->imdio, port); 1077 if (IS_ERR(mdio_device)) 1078 continue; 1079 1080 phylink_pcs = lynx_pcs_create(mdio_device); 1081 if (!phylink_pcs) { 1082 mdio_device_free(mdio_device); 1083 continue; 1084 } 1085 1086 felix->pcs[port] = phylink_pcs; 1087 1088 dev_info(dev, "Found PCS at internal MDIO address %d\n", port); 1089 } 1090 1091 return 0; 1092 } 1093 1094 static void vsc9959_mdio_bus_free(struct ocelot *ocelot) 1095 { 1096 struct felix *felix = ocelot_to_felix(ocelot); 1097 int port; 1098 1099 for (port = 0; port < ocelot->num_phys_ports; port++) { 1100 struct phylink_pcs *phylink_pcs = felix->pcs[port]; 1101 struct mdio_device *mdio_device; 1102 1103 if (!phylink_pcs) 1104 continue; 1105 1106 mdio_device = lynx_get_mdio_device(phylink_pcs); 1107 mdio_device_free(mdio_device); 1108 lynx_pcs_destroy(phylink_pcs); 1109 } 1110 mdiobus_unregister(felix->imdio); 1111 mdiobus_free(felix->imdio); 1112 } 1113 1114 /* The switch considers any frame (regardless of size) as eligible for 1115 * transmission if the traffic class gate is open for at least 33 ns. 1116 * Overruns are prevented by cropping an interval at the end of the gate time 1117 * slot for which egress scheduling is blocked, but we need to still keep 33 ns 1118 * available for one packet to be transmitted, otherwise the port tc will hang. 1119 * This function returns the size of a gate interval that remains available for 1120 * setting the guard band, after reserving the space for one egress frame. 1121 */ 1122 static u64 vsc9959_tas_remaining_gate_len_ps(u64 gate_len_ns) 1123 { 1124 /* Gate always open */ 1125 if (gate_len_ns == U64_MAX) 1126 return U64_MAX; 1127 1128 return (gate_len_ns - VSC9959_TAS_MIN_GATE_LEN_NS) * PSEC_PER_NSEC; 1129 } 1130 1131 /* Extract shortest continuous gate open intervals in ns for each traffic class 1132 * of a cyclic tc-taprio schedule. If a gate is always open, the duration is 1133 * considered U64_MAX. If the gate is always closed, it is considered 0. 1134 */ 1135 static void vsc9959_tas_min_gate_lengths(struct tc_taprio_qopt_offload *taprio, 1136 u64 min_gate_len[OCELOT_NUM_TC]) 1137 { 1138 struct tc_taprio_sched_entry *entry; 1139 u64 gate_len[OCELOT_NUM_TC]; 1140 u8 gates_ever_opened = 0; 1141 int tc, i, n; 1142 1143 /* Initialize arrays */ 1144 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1145 min_gate_len[tc] = U64_MAX; 1146 gate_len[tc] = 0; 1147 } 1148 1149 /* If we don't have taprio, consider all gates as permanently open */ 1150 if (!taprio) 1151 return; 1152 1153 n = taprio->num_entries; 1154 1155 /* Walk through the gate list twice to determine the length 1156 * of consecutively open gates for a traffic class, including 1157 * open gates that wrap around. We are just interested in the 1158 * minimum window size, and this doesn't change what the 1159 * minimum is (if the gate never closes, min_gate_len will 1160 * remain U64_MAX). 1161 */ 1162 for (i = 0; i < 2 * n; i++) { 1163 entry = &taprio->entries[i % n]; 1164 1165 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1166 if (entry->gate_mask & BIT(tc)) { 1167 gate_len[tc] += entry->interval; 1168 gates_ever_opened |= BIT(tc); 1169 } else { 1170 /* Gate closes now, record a potential new 1171 * minimum and reinitialize length 1172 */ 1173 if (min_gate_len[tc] > gate_len[tc] && 1174 gate_len[tc]) 1175 min_gate_len[tc] = gate_len[tc]; 1176 gate_len[tc] = 0; 1177 } 1178 } 1179 } 1180 1181 /* min_gate_len[tc] actually tracks minimum *open* gate time, so for 1182 * permanently closed gates, min_gate_len[tc] will still be U64_MAX. 1183 * Therefore they are currently indistinguishable from permanently 1184 * open gates. Overwrite the gate len with 0 when we know they're 1185 * actually permanently closed, i.e. after the loop above. 1186 */ 1187 for (tc = 0; tc < OCELOT_NUM_TC; tc++) 1188 if (!(gates_ever_opened & BIT(tc))) 1189 min_gate_len[tc] = 0; 1190 } 1191 1192 /* ocelot_write_rix is a macro that concatenates QSYS_MAXSDU_CFG_* with _RSZ, 1193 * so we need to spell out the register access to each traffic class in helper 1194 * functions, to simplify callers 1195 */ 1196 static void vsc9959_port_qmaxsdu_set(struct ocelot *ocelot, int port, int tc, 1197 u32 max_sdu) 1198 { 1199 switch (tc) { 1200 case 0: 1201 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_0, 1202 port); 1203 break; 1204 case 1: 1205 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_1, 1206 port); 1207 break; 1208 case 2: 1209 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_2, 1210 port); 1211 break; 1212 case 3: 1213 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_3, 1214 port); 1215 break; 1216 case 4: 1217 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_4, 1218 port); 1219 break; 1220 case 5: 1221 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_5, 1222 port); 1223 break; 1224 case 6: 1225 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_6, 1226 port); 1227 break; 1228 case 7: 1229 ocelot_write_rix(ocelot, max_sdu, QSYS_QMAXSDU_CFG_7, 1230 port); 1231 break; 1232 } 1233 } 1234 1235 static u32 vsc9959_port_qmaxsdu_get(struct ocelot *ocelot, int port, int tc) 1236 { 1237 switch (tc) { 1238 case 0: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_0, port); 1239 case 1: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_1, port); 1240 case 2: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_2, port); 1241 case 3: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_3, port); 1242 case 4: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_4, port); 1243 case 5: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_5, port); 1244 case 6: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_6, port); 1245 case 7: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_7, port); 1246 default: 1247 return 0; 1248 } 1249 } 1250 1251 /* Update QSYS_PORT_MAX_SDU to make sure the static guard bands added by the 1252 * switch (see the ALWAYS_GUARD_BAND_SCH_Q comment) are correct at all MTU 1253 * values (the default value is 1518). Also, for traffic class windows smaller 1254 * than one MTU sized frame, update QSYS_QMAXSDU_CFG to enable oversized frame 1255 * dropping, such that these won't hang the port, as they will never be sent. 1256 */ 1257 static void vsc9959_tas_guard_bands_update(struct ocelot *ocelot, int port) 1258 { 1259 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1260 u64 min_gate_len[OCELOT_NUM_TC]; 1261 int speed, picos_per_byte; 1262 u64 needed_bit_time_ps; 1263 u32 val, maxlen; 1264 u8 tas_speed; 1265 int tc; 1266 1267 lockdep_assert_held(&ocelot->tas_lock); 1268 1269 val = ocelot_read_rix(ocelot, QSYS_TAG_CONFIG, port); 1270 tas_speed = QSYS_TAG_CONFIG_LINK_SPEED_X(val); 1271 1272 switch (tas_speed) { 1273 case OCELOT_SPEED_10: 1274 speed = SPEED_10; 1275 break; 1276 case OCELOT_SPEED_100: 1277 speed = SPEED_100; 1278 break; 1279 case OCELOT_SPEED_1000: 1280 speed = SPEED_1000; 1281 break; 1282 case OCELOT_SPEED_2500: 1283 speed = SPEED_2500; 1284 break; 1285 default: 1286 return; 1287 } 1288 1289 picos_per_byte = (USEC_PER_SEC * 8) / speed; 1290 1291 val = ocelot_port_readl(ocelot_port, DEV_MAC_MAXLEN_CFG); 1292 /* MAXLEN_CFG accounts automatically for VLAN. We need to include it 1293 * manually in the bit time calculation, plus the preamble and SFD. 1294 */ 1295 maxlen = val + 2 * VLAN_HLEN; 1296 /* Consider the standard Ethernet overhead of 8 octets preamble+SFD, 1297 * 4 octets FCS, 12 octets IFG. 1298 */ 1299 needed_bit_time_ps = (maxlen + 24) * picos_per_byte; 1300 1301 dev_dbg(ocelot->dev, 1302 "port %d: max frame size %d needs %llu ps at speed %d\n", 1303 port, maxlen, needed_bit_time_ps, speed); 1304 1305 vsc9959_tas_min_gate_lengths(ocelot_port->taprio, min_gate_len); 1306 1307 mutex_lock(&ocelot->fwd_domain_lock); 1308 1309 for (tc = 0; tc < OCELOT_NUM_TC; tc++) { 1310 u64 remaining_gate_len_ps; 1311 u32 max_sdu; 1312 1313 remaining_gate_len_ps = 1314 vsc9959_tas_remaining_gate_len_ps(min_gate_len[tc]); 1315 1316 if (remaining_gate_len_ps > needed_bit_time_ps) { 1317 /* Setting QMAXSDU_CFG to 0 disables oversized frame 1318 * dropping. 1319 */ 1320 max_sdu = 0; 1321 dev_dbg(ocelot->dev, 1322 "port %d tc %d min gate len %llu" 1323 ", sending all frames\n", 1324 port, tc, min_gate_len[tc]); 1325 } else { 1326 /* If traffic class doesn't support a full MTU sized 1327 * frame, make sure to enable oversize frame dropping 1328 * for frames larger than the smallest that would fit. 1329 * 1330 * However, the exact same register, QSYS_QMAXSDU_CFG_*, 1331 * controls not only oversized frame dropping, but also 1332 * per-tc static guard band lengths, so it reduces the 1333 * useful gate interval length. Therefore, be careful 1334 * to calculate a guard band (and therefore max_sdu) 1335 * that still leaves 33 ns available in the time slot. 1336 */ 1337 max_sdu = div_u64(remaining_gate_len_ps, picos_per_byte); 1338 /* A TC gate may be completely closed, which is a 1339 * special case where all packets are oversized. 1340 * Any limit smaller than 64 octets accomplishes this 1341 */ 1342 if (!max_sdu) 1343 max_sdu = 1; 1344 /* Take L1 overhead into account, but just don't allow 1345 * max_sdu to go negative or to 0. Here we use 20 1346 * because QSYS_MAXSDU_CFG_* already counts the 4 FCS 1347 * octets as part of packet size. 1348 */ 1349 if (max_sdu > 20) 1350 max_sdu -= 20; 1351 dev_info(ocelot->dev, 1352 "port %d tc %d min gate length %llu" 1353 " ns not enough for max frame size %d at %d" 1354 " Mbps, dropping frames over %d" 1355 " octets including FCS\n", 1356 port, tc, min_gate_len[tc], maxlen, speed, 1357 max_sdu); 1358 } 1359 1360 vsc9959_port_qmaxsdu_set(ocelot, port, tc, max_sdu); 1361 } 1362 1363 ocelot_write_rix(ocelot, maxlen, QSYS_PORT_MAX_SDU, port); 1364 1365 ocelot->ops->cut_through_fwd(ocelot); 1366 1367 mutex_unlock(&ocelot->fwd_domain_lock); 1368 } 1369 1370 static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port, 1371 u32 speed) 1372 { 1373 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1374 u8 tas_speed; 1375 1376 switch (speed) { 1377 case SPEED_10: 1378 tas_speed = OCELOT_SPEED_10; 1379 break; 1380 case SPEED_100: 1381 tas_speed = OCELOT_SPEED_100; 1382 break; 1383 case SPEED_1000: 1384 tas_speed = OCELOT_SPEED_1000; 1385 break; 1386 case SPEED_2500: 1387 tas_speed = OCELOT_SPEED_2500; 1388 break; 1389 default: 1390 tas_speed = OCELOT_SPEED_1000; 1391 break; 1392 } 1393 1394 mutex_lock(&ocelot->tas_lock); 1395 1396 ocelot_rmw_rix(ocelot, 1397 QSYS_TAG_CONFIG_LINK_SPEED(tas_speed), 1398 QSYS_TAG_CONFIG_LINK_SPEED_M, 1399 QSYS_TAG_CONFIG, port); 1400 1401 if (ocelot_port->taprio) 1402 vsc9959_tas_guard_bands_update(ocelot, port); 1403 1404 mutex_unlock(&ocelot->tas_lock); 1405 } 1406 1407 static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time, 1408 u64 cycle_time, 1409 struct timespec64 *new_base_ts) 1410 { 1411 struct timespec64 ts; 1412 ktime_t new_base_time; 1413 ktime_t current_time; 1414 1415 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1416 current_time = timespec64_to_ktime(ts); 1417 new_base_time = base_time; 1418 1419 if (base_time < current_time) { 1420 u64 nr_of_cycles = current_time - base_time; 1421 1422 do_div(nr_of_cycles, cycle_time); 1423 new_base_time += cycle_time * (nr_of_cycles + 1); 1424 } 1425 1426 *new_base_ts = ktime_to_timespec64(new_base_time); 1427 } 1428 1429 static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot) 1430 { 1431 return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL); 1432 } 1433 1434 static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix, 1435 struct tc_taprio_sched_entry *entry) 1436 { 1437 ocelot_write(ocelot, 1438 QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) | 1439 QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask), 1440 QSYS_GCL_CFG_REG_1); 1441 ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2); 1442 } 1443 1444 static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port, 1445 struct tc_taprio_qopt_offload *taprio) 1446 { 1447 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1448 struct timespec64 base_ts; 1449 int ret, i; 1450 u32 val; 1451 1452 mutex_lock(&ocelot->tas_lock); 1453 1454 if (!taprio->enable) { 1455 ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE, 1456 QSYS_TAG_CONFIG, port); 1457 1458 taprio_offload_free(ocelot_port->taprio); 1459 ocelot_port->taprio = NULL; 1460 1461 vsc9959_tas_guard_bands_update(ocelot, port); 1462 1463 mutex_unlock(&ocelot->tas_lock); 1464 return 0; 1465 } 1466 1467 if (taprio->cycle_time > NSEC_PER_SEC || 1468 taprio->cycle_time_extension >= NSEC_PER_SEC) { 1469 ret = -EINVAL; 1470 goto err; 1471 } 1472 1473 if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX) { 1474 ret = -ERANGE; 1475 goto err; 1476 } 1477 1478 /* Enable guard band. The switch will schedule frames without taking 1479 * their length into account. Thus we'll always need to enable the 1480 * guard band which reserves the time of a maximum sized frame at the 1481 * end of the time window. 1482 * 1483 * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we 1484 * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n 1485 * operate on the port number. 1486 */ 1487 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) | 1488 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1489 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M | 1490 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1491 QSYS_TAS_PARAM_CFG_CTRL); 1492 1493 /* Hardware errata - Admin config could not be overwritten if 1494 * config is pending, need reset the TAS module 1495 */ 1496 val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8); 1497 if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) { 1498 ret = -EBUSY; 1499 goto err; 1500 } 1501 1502 ocelot_rmw_rix(ocelot, 1503 QSYS_TAG_CONFIG_ENABLE | 1504 QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) | 1505 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF), 1506 QSYS_TAG_CONFIG_ENABLE | 1507 QSYS_TAG_CONFIG_INIT_GATE_STATE_M | 1508 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M, 1509 QSYS_TAG_CONFIG, port); 1510 1511 vsc9959_new_base_time(ocelot, taprio->base_time, 1512 taprio->cycle_time, &base_ts); 1513 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1514 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2); 1515 val = upper_32_bits(base_ts.tv_sec); 1516 ocelot_write(ocelot, 1517 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) | 1518 QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries), 1519 QSYS_PARAM_CFG_REG_3); 1520 ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4); 1521 ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5); 1522 1523 for (i = 0; i < taprio->num_entries; i++) 1524 vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]); 1525 1526 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1527 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1528 QSYS_TAS_PARAM_CFG_CTRL); 1529 1530 ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val, 1531 !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE), 1532 10, 100000); 1533 if (ret) 1534 goto err; 1535 1536 ocelot_port->taprio = taprio_offload_get(taprio); 1537 vsc9959_tas_guard_bands_update(ocelot, port); 1538 1539 err: 1540 mutex_unlock(&ocelot->tas_lock); 1541 1542 return ret; 1543 } 1544 1545 static void vsc9959_tas_clock_adjust(struct ocelot *ocelot) 1546 { 1547 struct tc_taprio_qopt_offload *taprio; 1548 struct ocelot_port *ocelot_port; 1549 struct timespec64 base_ts; 1550 int port; 1551 u32 val; 1552 1553 mutex_lock(&ocelot->tas_lock); 1554 1555 for (port = 0; port < ocelot->num_phys_ports; port++) { 1556 ocelot_port = ocelot->ports[port]; 1557 taprio = ocelot_port->taprio; 1558 if (!taprio) 1559 continue; 1560 1561 ocelot_rmw(ocelot, 1562 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port), 1563 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M, 1564 QSYS_TAS_PARAM_CFG_CTRL); 1565 1566 /* Disable time-aware shaper */ 1567 ocelot_rmw_rix(ocelot, 0, QSYS_TAG_CONFIG_ENABLE, 1568 QSYS_TAG_CONFIG, port); 1569 1570 vsc9959_new_base_time(ocelot, taprio->base_time, 1571 taprio->cycle_time, &base_ts); 1572 1573 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1574 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), 1575 QSYS_PARAM_CFG_REG_2); 1576 val = upper_32_bits(base_ts.tv_sec); 1577 ocelot_rmw(ocelot, 1578 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val), 1579 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M, 1580 QSYS_PARAM_CFG_REG_3); 1581 1582 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1583 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1584 QSYS_TAS_PARAM_CFG_CTRL); 1585 1586 /* Re-enable time-aware shaper */ 1587 ocelot_rmw_rix(ocelot, QSYS_TAG_CONFIG_ENABLE, 1588 QSYS_TAG_CONFIG_ENABLE, 1589 QSYS_TAG_CONFIG, port); 1590 } 1591 mutex_unlock(&ocelot->tas_lock); 1592 } 1593 1594 static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port, 1595 struct tc_cbs_qopt_offload *cbs_qopt) 1596 { 1597 struct ocelot *ocelot = ds->priv; 1598 int port_ix = port * 8 + cbs_qopt->queue; 1599 u32 rate, burst; 1600 1601 if (cbs_qopt->queue >= ds->num_tx_queues) 1602 return -EINVAL; 1603 1604 if (!cbs_qopt->enable) { 1605 ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) | 1606 QSYS_CIR_CFG_CIR_BURST(0), 1607 QSYS_CIR_CFG, port_ix); 1608 1609 ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA, 1610 QSYS_SE_CFG, port_ix); 1611 1612 return 0; 1613 } 1614 1615 /* Rate unit is 100 kbps */ 1616 rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100); 1617 /* Avoid using zero rate */ 1618 rate = clamp_t(u32, rate, 1, GENMASK(14, 0)); 1619 /* Burst unit is 4kB */ 1620 burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096); 1621 /* Avoid using zero burst size */ 1622 burst = clamp_t(u32, burst, 1, GENMASK(5, 0)); 1623 ocelot_write_gix(ocelot, 1624 QSYS_CIR_CFG_CIR_RATE(rate) | 1625 QSYS_CIR_CFG_CIR_BURST(burst), 1626 QSYS_CIR_CFG, 1627 port_ix); 1628 1629 ocelot_rmw_gix(ocelot, 1630 QSYS_SE_CFG_SE_FRM_MODE(0) | 1631 QSYS_SE_CFG_SE_AVB_ENA, 1632 QSYS_SE_CFG_SE_AVB_ENA | 1633 QSYS_SE_CFG_SE_FRM_MODE_M, 1634 QSYS_SE_CFG, 1635 port_ix); 1636 1637 return 0; 1638 } 1639 1640 static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port, 1641 enum tc_setup_type type, 1642 void *type_data) 1643 { 1644 struct ocelot *ocelot = ds->priv; 1645 1646 switch (type) { 1647 case TC_SETUP_QDISC_TAPRIO: 1648 return vsc9959_qos_port_tas_set(ocelot, port, type_data); 1649 case TC_SETUP_QDISC_CBS: 1650 return vsc9959_qos_port_cbs_set(ds, port, type_data); 1651 default: 1652 return -EOPNOTSUPP; 1653 } 1654 } 1655 1656 #define VSC9959_PSFP_SFID_MAX 175 1657 #define VSC9959_PSFP_GATE_ID_MAX 183 1658 #define VSC9959_PSFP_POLICER_BASE 63 1659 #define VSC9959_PSFP_POLICER_MAX 383 1660 #define VSC9959_PSFP_GATE_LIST_NUM 4 1661 #define VSC9959_PSFP_GATE_CYCLETIME_MIN 5000 1662 1663 struct felix_stream { 1664 struct list_head list; 1665 unsigned long id; 1666 bool dummy; 1667 int ports; 1668 int port; 1669 u8 dmac[ETH_ALEN]; 1670 u16 vid; 1671 s8 prio; 1672 u8 sfid_valid; 1673 u8 ssid_valid; 1674 u32 sfid; 1675 u32 ssid; 1676 }; 1677 1678 struct felix_stream_filter_counters { 1679 u64 match; 1680 u64 not_pass_gate; 1681 u64 not_pass_sdu; 1682 u64 red; 1683 }; 1684 1685 struct felix_stream_filter { 1686 struct felix_stream_filter_counters stats; 1687 struct list_head list; 1688 refcount_t refcount; 1689 u32 index; 1690 u8 enable; 1691 int portmask; 1692 u8 sg_valid; 1693 u32 sgid; 1694 u8 fm_valid; 1695 u32 fmid; 1696 u8 prio_valid; 1697 u8 prio; 1698 u32 maxsdu; 1699 }; 1700 1701 struct felix_stream_gate { 1702 u32 index; 1703 u8 enable; 1704 u8 ipv_valid; 1705 u8 init_ipv; 1706 u64 basetime; 1707 u64 cycletime; 1708 u64 cycletime_ext; 1709 u32 num_entries; 1710 struct action_gate_entry entries[]; 1711 }; 1712 1713 struct felix_stream_gate_entry { 1714 struct list_head list; 1715 refcount_t refcount; 1716 u32 index; 1717 }; 1718 1719 static int vsc9959_stream_identify(struct flow_cls_offload *f, 1720 struct felix_stream *stream) 1721 { 1722 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 1723 struct flow_dissector *dissector = rule->match.dissector; 1724 1725 if (dissector->used_keys & 1726 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | 1727 BIT(FLOW_DISSECTOR_KEY_BASIC) | 1728 BIT(FLOW_DISSECTOR_KEY_VLAN) | 1729 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS))) 1730 return -EOPNOTSUPP; 1731 1732 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 1733 struct flow_match_eth_addrs match; 1734 1735 flow_rule_match_eth_addrs(rule, &match); 1736 ether_addr_copy(stream->dmac, match.key->dst); 1737 if (!is_zero_ether_addr(match.mask->src)) 1738 return -EOPNOTSUPP; 1739 } else { 1740 return -EOPNOTSUPP; 1741 } 1742 1743 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 1744 struct flow_match_vlan match; 1745 1746 flow_rule_match_vlan(rule, &match); 1747 if (match.mask->vlan_priority) 1748 stream->prio = match.key->vlan_priority; 1749 else 1750 stream->prio = -1; 1751 1752 if (!match.mask->vlan_id) 1753 return -EOPNOTSUPP; 1754 stream->vid = match.key->vlan_id; 1755 } else { 1756 return -EOPNOTSUPP; 1757 } 1758 1759 stream->id = f->cookie; 1760 1761 return 0; 1762 } 1763 1764 static int vsc9959_mact_stream_set(struct ocelot *ocelot, 1765 struct felix_stream *stream, 1766 struct netlink_ext_ack *extack) 1767 { 1768 enum macaccess_entry_type type; 1769 int ret, sfid, ssid; 1770 u32 vid, dst_idx; 1771 u8 mac[ETH_ALEN]; 1772 1773 ether_addr_copy(mac, stream->dmac); 1774 vid = stream->vid; 1775 1776 /* Stream identification desn't support to add a stream with non 1777 * existent MAC (The MAC entry has not been learned in MAC table). 1778 */ 1779 ret = ocelot_mact_lookup(ocelot, &dst_idx, mac, vid, &type); 1780 if (ret) { 1781 if (extack) 1782 NL_SET_ERR_MSG_MOD(extack, "Stream is not learned in MAC table"); 1783 return -EOPNOTSUPP; 1784 } 1785 1786 if ((stream->sfid_valid || stream->ssid_valid) && 1787 type == ENTRYTYPE_NORMAL) 1788 type = ENTRYTYPE_LOCKED; 1789 1790 sfid = stream->sfid_valid ? stream->sfid : -1; 1791 ssid = stream->ssid_valid ? stream->ssid : -1; 1792 1793 ret = ocelot_mact_learn_streamdata(ocelot, dst_idx, mac, vid, type, 1794 sfid, ssid); 1795 1796 return ret; 1797 } 1798 1799 static struct felix_stream * 1800 vsc9959_stream_table_lookup(struct list_head *stream_list, 1801 struct felix_stream *stream) 1802 { 1803 struct felix_stream *tmp; 1804 1805 list_for_each_entry(tmp, stream_list, list) 1806 if (ether_addr_equal(tmp->dmac, stream->dmac) && 1807 tmp->vid == stream->vid) 1808 return tmp; 1809 1810 return NULL; 1811 } 1812 1813 static int vsc9959_stream_table_add(struct ocelot *ocelot, 1814 struct list_head *stream_list, 1815 struct felix_stream *stream, 1816 struct netlink_ext_ack *extack) 1817 { 1818 struct felix_stream *stream_entry; 1819 int ret; 1820 1821 stream_entry = kmemdup(stream, sizeof(*stream_entry), GFP_KERNEL); 1822 if (!stream_entry) 1823 return -ENOMEM; 1824 1825 if (!stream->dummy) { 1826 ret = vsc9959_mact_stream_set(ocelot, stream_entry, extack); 1827 if (ret) { 1828 kfree(stream_entry); 1829 return ret; 1830 } 1831 } 1832 1833 list_add_tail(&stream_entry->list, stream_list); 1834 1835 return 0; 1836 } 1837 1838 static struct felix_stream * 1839 vsc9959_stream_table_get(struct list_head *stream_list, unsigned long id) 1840 { 1841 struct felix_stream *tmp; 1842 1843 list_for_each_entry(tmp, stream_list, list) 1844 if (tmp->id == id) 1845 return tmp; 1846 1847 return NULL; 1848 } 1849 1850 static void vsc9959_stream_table_del(struct ocelot *ocelot, 1851 struct felix_stream *stream) 1852 { 1853 if (!stream->dummy) 1854 vsc9959_mact_stream_set(ocelot, stream, NULL); 1855 1856 list_del(&stream->list); 1857 kfree(stream); 1858 } 1859 1860 static u32 vsc9959_sfi_access_status(struct ocelot *ocelot) 1861 { 1862 return ocelot_read(ocelot, ANA_TABLES_SFIDACCESS); 1863 } 1864 1865 static int vsc9959_psfp_sfi_set(struct ocelot *ocelot, 1866 struct felix_stream_filter *sfi) 1867 { 1868 u32 val; 1869 1870 if (sfi->index > VSC9959_PSFP_SFID_MAX) 1871 return -EINVAL; 1872 1873 if (!sfi->enable) { 1874 ocelot_write(ocelot, ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 1875 ANA_TABLES_SFIDTIDX); 1876 1877 val = ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE); 1878 ocelot_write(ocelot, val, ANA_TABLES_SFIDACCESS); 1879 1880 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1881 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1882 10, 100000); 1883 } 1884 1885 if (sfi->sgid > VSC9959_PSFP_GATE_ID_MAX || 1886 sfi->fmid > VSC9959_PSFP_POLICER_MAX) 1887 return -EINVAL; 1888 1889 ocelot_write(ocelot, 1890 (sfi->sg_valid ? ANA_TABLES_SFIDTIDX_SGID_VALID : 0) | 1891 ANA_TABLES_SFIDTIDX_SGID(sfi->sgid) | 1892 (sfi->fm_valid ? ANA_TABLES_SFIDTIDX_POL_ENA : 0) | 1893 ANA_TABLES_SFIDTIDX_POL_IDX(sfi->fmid) | 1894 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 1895 ANA_TABLES_SFIDTIDX); 1896 1897 ocelot_write(ocelot, 1898 (sfi->prio_valid ? ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA : 0) | 1899 ANA_TABLES_SFIDACCESS_IGR_PRIO(sfi->prio) | 1900 ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(sfi->maxsdu) | 1901 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 1902 ANA_TABLES_SFIDACCESS); 1903 1904 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1905 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1906 10, 100000); 1907 } 1908 1909 static int vsc9959_psfp_sfidmask_set(struct ocelot *ocelot, u32 sfid, int ports) 1910 { 1911 u32 val; 1912 1913 ocelot_rmw(ocelot, 1914 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfid), 1915 ANA_TABLES_SFIDTIDX_SFID_INDEX_M, 1916 ANA_TABLES_SFIDTIDX); 1917 1918 ocelot_write(ocelot, 1919 ANA_TABLES_SFID_MASK_IGR_PORT_MASK(ports) | 1920 ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA, 1921 ANA_TABLES_SFID_MASK); 1922 1923 ocelot_rmw(ocelot, 1924 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 1925 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M, 1926 ANA_TABLES_SFIDACCESS); 1927 1928 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1929 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1930 10, 100000); 1931 } 1932 1933 static int vsc9959_psfp_sfi_list_add(struct ocelot *ocelot, 1934 struct felix_stream_filter *sfi, 1935 struct list_head *pos) 1936 { 1937 struct felix_stream_filter *sfi_entry; 1938 int ret; 1939 1940 sfi_entry = kmemdup(sfi, sizeof(*sfi_entry), GFP_KERNEL); 1941 if (!sfi_entry) 1942 return -ENOMEM; 1943 1944 refcount_set(&sfi_entry->refcount, 1); 1945 1946 ret = vsc9959_psfp_sfi_set(ocelot, sfi_entry); 1947 if (ret) { 1948 kfree(sfi_entry); 1949 return ret; 1950 } 1951 1952 vsc9959_psfp_sfidmask_set(ocelot, sfi->index, sfi->portmask); 1953 1954 list_add(&sfi_entry->list, pos); 1955 1956 return 0; 1957 } 1958 1959 static int vsc9959_psfp_sfi_table_add(struct ocelot *ocelot, 1960 struct felix_stream_filter *sfi) 1961 { 1962 struct list_head *pos, *q, *last; 1963 struct felix_stream_filter *tmp; 1964 struct ocelot_psfp_list *psfp; 1965 u32 insert = 0; 1966 1967 psfp = &ocelot->psfp; 1968 last = &psfp->sfi_list; 1969 1970 list_for_each_safe(pos, q, &psfp->sfi_list) { 1971 tmp = list_entry(pos, struct felix_stream_filter, list); 1972 if (sfi->sg_valid == tmp->sg_valid && 1973 sfi->fm_valid == tmp->fm_valid && 1974 sfi->portmask == tmp->portmask && 1975 tmp->sgid == sfi->sgid && 1976 tmp->fmid == sfi->fmid) { 1977 sfi->index = tmp->index; 1978 refcount_inc(&tmp->refcount); 1979 return 0; 1980 } 1981 /* Make sure that the index is increasing in order. */ 1982 if (tmp->index == insert) { 1983 last = pos; 1984 insert++; 1985 } 1986 } 1987 sfi->index = insert; 1988 1989 return vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 1990 } 1991 1992 static int vsc9959_psfp_sfi_table_add2(struct ocelot *ocelot, 1993 struct felix_stream_filter *sfi, 1994 struct felix_stream_filter *sfi2) 1995 { 1996 struct felix_stream_filter *tmp; 1997 struct list_head *pos, *q, *last; 1998 struct ocelot_psfp_list *psfp; 1999 u32 insert = 0; 2000 int ret; 2001 2002 psfp = &ocelot->psfp; 2003 last = &psfp->sfi_list; 2004 2005 list_for_each_safe(pos, q, &psfp->sfi_list) { 2006 tmp = list_entry(pos, struct felix_stream_filter, list); 2007 /* Make sure that the index is increasing in order. */ 2008 if (tmp->index >= insert + 2) 2009 break; 2010 2011 insert = tmp->index + 1; 2012 last = pos; 2013 } 2014 sfi->index = insert; 2015 2016 ret = vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 2017 if (ret) 2018 return ret; 2019 2020 sfi2->index = insert + 1; 2021 2022 return vsc9959_psfp_sfi_list_add(ocelot, sfi2, last->next); 2023 } 2024 2025 static struct felix_stream_filter * 2026 vsc9959_psfp_sfi_table_get(struct list_head *sfi_list, u32 index) 2027 { 2028 struct felix_stream_filter *tmp; 2029 2030 list_for_each_entry(tmp, sfi_list, list) 2031 if (tmp->index == index) 2032 return tmp; 2033 2034 return NULL; 2035 } 2036 2037 static void vsc9959_psfp_sfi_table_del(struct ocelot *ocelot, u32 index) 2038 { 2039 struct felix_stream_filter *tmp, *n; 2040 struct ocelot_psfp_list *psfp; 2041 u8 z; 2042 2043 psfp = &ocelot->psfp; 2044 2045 list_for_each_entry_safe(tmp, n, &psfp->sfi_list, list) 2046 if (tmp->index == index) { 2047 z = refcount_dec_and_test(&tmp->refcount); 2048 if (z) { 2049 tmp->enable = 0; 2050 vsc9959_psfp_sfi_set(ocelot, tmp); 2051 list_del(&tmp->list); 2052 kfree(tmp); 2053 } 2054 break; 2055 } 2056 } 2057 2058 static void vsc9959_psfp_parse_gate(const struct flow_action_entry *entry, 2059 struct felix_stream_gate *sgi) 2060 { 2061 sgi->index = entry->hw_index; 2062 sgi->ipv_valid = (entry->gate.prio < 0) ? 0 : 1; 2063 sgi->init_ipv = (sgi->ipv_valid) ? entry->gate.prio : 0; 2064 sgi->basetime = entry->gate.basetime; 2065 sgi->cycletime = entry->gate.cycletime; 2066 sgi->num_entries = entry->gate.num_entries; 2067 sgi->enable = 1; 2068 2069 memcpy(sgi->entries, entry->gate.entries, 2070 entry->gate.num_entries * sizeof(struct action_gate_entry)); 2071 } 2072 2073 static u32 vsc9959_sgi_cfg_status(struct ocelot *ocelot) 2074 { 2075 return ocelot_read(ocelot, ANA_SG_ACCESS_CTRL); 2076 } 2077 2078 static int vsc9959_psfp_sgi_set(struct ocelot *ocelot, 2079 struct felix_stream_gate *sgi) 2080 { 2081 struct action_gate_entry *e; 2082 struct timespec64 base_ts; 2083 u32 interval_sum = 0; 2084 u32 val; 2085 int i; 2086 2087 if (sgi->index > VSC9959_PSFP_GATE_ID_MAX) 2088 return -EINVAL; 2089 2090 ocelot_write(ocelot, ANA_SG_ACCESS_CTRL_SGID(sgi->index), 2091 ANA_SG_ACCESS_CTRL); 2092 2093 if (!sgi->enable) { 2094 ocelot_rmw(ocelot, ANA_SG_CONFIG_REG_3_INIT_GATE_STATE, 2095 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 2096 ANA_SG_CONFIG_REG_3_GATE_ENABLE, 2097 ANA_SG_CONFIG_REG_3); 2098 2099 return 0; 2100 } 2101 2102 if (sgi->cycletime < VSC9959_PSFP_GATE_CYCLETIME_MIN || 2103 sgi->cycletime > NSEC_PER_SEC) 2104 return -EINVAL; 2105 2106 if (sgi->num_entries > VSC9959_PSFP_GATE_LIST_NUM) 2107 return -EINVAL; 2108 2109 vsc9959_new_base_time(ocelot, sgi->basetime, sgi->cycletime, &base_ts); 2110 ocelot_write(ocelot, base_ts.tv_nsec, ANA_SG_CONFIG_REG_1); 2111 val = lower_32_bits(base_ts.tv_sec); 2112 ocelot_write(ocelot, val, ANA_SG_CONFIG_REG_2); 2113 2114 val = upper_32_bits(base_ts.tv_sec); 2115 ocelot_write(ocelot, 2116 (sgi->ipv_valid ? ANA_SG_CONFIG_REG_3_IPV_VALID : 0) | 2117 ANA_SG_CONFIG_REG_3_INIT_IPV(sgi->init_ipv) | 2118 ANA_SG_CONFIG_REG_3_GATE_ENABLE | 2119 ANA_SG_CONFIG_REG_3_LIST_LENGTH(sgi->num_entries) | 2120 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 2121 ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(val), 2122 ANA_SG_CONFIG_REG_3); 2123 2124 ocelot_write(ocelot, sgi->cycletime, ANA_SG_CONFIG_REG_4); 2125 2126 e = sgi->entries; 2127 for (i = 0; i < sgi->num_entries; i++) { 2128 u32 ips = (e[i].ipv < 0) ? 0 : (e[i].ipv + 8); 2129 2130 ocelot_write_rix(ocelot, ANA_SG_GCL_GS_CONFIG_IPS(ips) | 2131 (e[i].gate_state ? 2132 ANA_SG_GCL_GS_CONFIG_GATE_STATE : 0), 2133 ANA_SG_GCL_GS_CONFIG, i); 2134 2135 interval_sum += e[i].interval; 2136 ocelot_write_rix(ocelot, interval_sum, ANA_SG_GCL_TI_CONFIG, i); 2137 } 2138 2139 ocelot_rmw(ocelot, ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 2140 ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 2141 ANA_SG_ACCESS_CTRL); 2142 2143 return readx_poll_timeout(vsc9959_sgi_cfg_status, ocelot, val, 2144 (!(ANA_SG_ACCESS_CTRL_CONFIG_CHANGE & val)), 2145 10, 100000); 2146 } 2147 2148 static int vsc9959_psfp_sgi_table_add(struct ocelot *ocelot, 2149 struct felix_stream_gate *sgi) 2150 { 2151 struct felix_stream_gate_entry *tmp; 2152 struct ocelot_psfp_list *psfp; 2153 int ret; 2154 2155 psfp = &ocelot->psfp; 2156 2157 list_for_each_entry(tmp, &psfp->sgi_list, list) 2158 if (tmp->index == sgi->index) { 2159 refcount_inc(&tmp->refcount); 2160 return 0; 2161 } 2162 2163 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 2164 if (!tmp) 2165 return -ENOMEM; 2166 2167 ret = vsc9959_psfp_sgi_set(ocelot, sgi); 2168 if (ret) { 2169 kfree(tmp); 2170 return ret; 2171 } 2172 2173 tmp->index = sgi->index; 2174 refcount_set(&tmp->refcount, 1); 2175 list_add_tail(&tmp->list, &psfp->sgi_list); 2176 2177 return 0; 2178 } 2179 2180 static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot, 2181 u32 index) 2182 { 2183 struct felix_stream_gate_entry *tmp, *n; 2184 struct felix_stream_gate sgi = {0}; 2185 struct ocelot_psfp_list *psfp; 2186 u8 z; 2187 2188 psfp = &ocelot->psfp; 2189 2190 list_for_each_entry_safe(tmp, n, &psfp->sgi_list, list) 2191 if (tmp->index == index) { 2192 z = refcount_dec_and_test(&tmp->refcount); 2193 if (z) { 2194 sgi.index = index; 2195 sgi.enable = 0; 2196 vsc9959_psfp_sgi_set(ocelot, &sgi); 2197 list_del(&tmp->list); 2198 kfree(tmp); 2199 } 2200 break; 2201 } 2202 } 2203 2204 static int vsc9959_psfp_filter_add(struct ocelot *ocelot, int port, 2205 struct flow_cls_offload *f) 2206 { 2207 struct netlink_ext_ack *extack = f->common.extack; 2208 struct felix_stream_filter old_sfi, *sfi_entry; 2209 struct felix_stream_filter sfi = {0}; 2210 const struct flow_action_entry *a; 2211 struct felix_stream *stream_entry; 2212 struct felix_stream stream = {0}; 2213 struct felix_stream_gate *sgi; 2214 struct ocelot_psfp_list *psfp; 2215 struct ocelot_policer pol; 2216 int ret, i, size; 2217 u64 rate, burst; 2218 u32 index; 2219 2220 psfp = &ocelot->psfp; 2221 2222 ret = vsc9959_stream_identify(f, &stream); 2223 if (ret) { 2224 NL_SET_ERR_MSG_MOD(extack, "Only can match on VID, PCP, and dest MAC"); 2225 return ret; 2226 } 2227 2228 mutex_lock(&psfp->lock); 2229 2230 flow_action_for_each(i, a, &f->rule->action) { 2231 switch (a->id) { 2232 case FLOW_ACTION_GATE: 2233 size = struct_size(sgi, entries, a->gate.num_entries); 2234 sgi = kzalloc(size, GFP_KERNEL); 2235 if (!sgi) { 2236 ret = -ENOMEM; 2237 goto err; 2238 } 2239 vsc9959_psfp_parse_gate(a, sgi); 2240 ret = vsc9959_psfp_sgi_table_add(ocelot, sgi); 2241 if (ret) { 2242 kfree(sgi); 2243 goto err; 2244 } 2245 sfi.sg_valid = 1; 2246 sfi.sgid = sgi->index; 2247 kfree(sgi); 2248 break; 2249 case FLOW_ACTION_POLICE: 2250 index = a->hw_index + VSC9959_PSFP_POLICER_BASE; 2251 if (index > VSC9959_PSFP_POLICER_MAX) { 2252 ret = -EINVAL; 2253 goto err; 2254 } 2255 2256 rate = a->police.rate_bytes_ps; 2257 burst = rate * PSCHED_NS2TICKS(a->police.burst); 2258 pol = (struct ocelot_policer) { 2259 .burst = div_u64(burst, PSCHED_TICKS_PER_SEC), 2260 .rate = div_u64(rate, 1000) * 8, 2261 }; 2262 ret = ocelot_vcap_policer_add(ocelot, index, &pol); 2263 if (ret) 2264 goto err; 2265 2266 sfi.fm_valid = 1; 2267 sfi.fmid = index; 2268 sfi.maxsdu = a->police.mtu; 2269 break; 2270 default: 2271 mutex_unlock(&psfp->lock); 2272 return -EOPNOTSUPP; 2273 } 2274 } 2275 2276 stream.ports = BIT(port); 2277 stream.port = port; 2278 2279 sfi.portmask = stream.ports; 2280 sfi.prio_valid = (stream.prio < 0 ? 0 : 1); 2281 sfi.prio = (sfi.prio_valid ? stream.prio : 0); 2282 sfi.enable = 1; 2283 2284 /* Check if stream is set. */ 2285 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &stream); 2286 if (stream_entry) { 2287 if (stream_entry->ports & BIT(port)) { 2288 NL_SET_ERR_MSG_MOD(extack, 2289 "The stream is added on this port"); 2290 ret = -EEXIST; 2291 goto err; 2292 } 2293 2294 if (stream_entry->ports != BIT(stream_entry->port)) { 2295 NL_SET_ERR_MSG_MOD(extack, 2296 "The stream is added on two ports"); 2297 ret = -EEXIST; 2298 goto err; 2299 } 2300 2301 stream_entry->ports |= BIT(port); 2302 stream.ports = stream_entry->ports; 2303 2304 sfi_entry = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, 2305 stream_entry->sfid); 2306 memcpy(&old_sfi, sfi_entry, sizeof(old_sfi)); 2307 2308 vsc9959_psfp_sfi_table_del(ocelot, stream_entry->sfid); 2309 2310 old_sfi.portmask = stream_entry->ports; 2311 sfi.portmask = stream.ports; 2312 2313 if (stream_entry->port > port) { 2314 ret = vsc9959_psfp_sfi_table_add2(ocelot, &sfi, 2315 &old_sfi); 2316 stream_entry->dummy = true; 2317 } else { 2318 ret = vsc9959_psfp_sfi_table_add2(ocelot, &old_sfi, 2319 &sfi); 2320 stream.dummy = true; 2321 } 2322 if (ret) 2323 goto err; 2324 2325 stream_entry->sfid = old_sfi.index; 2326 } else { 2327 ret = vsc9959_psfp_sfi_table_add(ocelot, &sfi); 2328 if (ret) 2329 goto err; 2330 } 2331 2332 stream.sfid = sfi.index; 2333 stream.sfid_valid = 1; 2334 ret = vsc9959_stream_table_add(ocelot, &psfp->stream_list, 2335 &stream, extack); 2336 if (ret) { 2337 vsc9959_psfp_sfi_table_del(ocelot, stream.sfid); 2338 goto err; 2339 } 2340 2341 mutex_unlock(&psfp->lock); 2342 2343 return 0; 2344 2345 err: 2346 if (sfi.sg_valid) 2347 vsc9959_psfp_sgi_table_del(ocelot, sfi.sgid); 2348 2349 if (sfi.fm_valid) 2350 ocelot_vcap_policer_del(ocelot, sfi.fmid); 2351 2352 mutex_unlock(&psfp->lock); 2353 2354 return ret; 2355 } 2356 2357 static int vsc9959_psfp_filter_del(struct ocelot *ocelot, 2358 struct flow_cls_offload *f) 2359 { 2360 struct felix_stream *stream, tmp, *stream_entry; 2361 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2362 static struct felix_stream_filter *sfi; 2363 2364 mutex_lock(&psfp->lock); 2365 2366 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 2367 if (!stream) { 2368 mutex_unlock(&psfp->lock); 2369 return -ENOMEM; 2370 } 2371 2372 sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid); 2373 if (!sfi) { 2374 mutex_unlock(&psfp->lock); 2375 return -ENOMEM; 2376 } 2377 2378 if (sfi->sg_valid) 2379 vsc9959_psfp_sgi_table_del(ocelot, sfi->sgid); 2380 2381 if (sfi->fm_valid) 2382 ocelot_vcap_policer_del(ocelot, sfi->fmid); 2383 2384 vsc9959_psfp_sfi_table_del(ocelot, stream->sfid); 2385 2386 memcpy(&tmp, stream, sizeof(tmp)); 2387 2388 stream->sfid_valid = 0; 2389 vsc9959_stream_table_del(ocelot, stream); 2390 2391 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &tmp); 2392 if (stream_entry) { 2393 stream_entry->ports = BIT(stream_entry->port); 2394 if (stream_entry->dummy) { 2395 stream_entry->dummy = false; 2396 vsc9959_mact_stream_set(ocelot, stream_entry, NULL); 2397 } 2398 vsc9959_psfp_sfidmask_set(ocelot, stream_entry->sfid, 2399 stream_entry->ports); 2400 } 2401 2402 mutex_unlock(&psfp->lock); 2403 2404 return 0; 2405 } 2406 2407 static void vsc9959_update_sfid_stats(struct ocelot *ocelot, 2408 struct felix_stream_filter *sfi) 2409 { 2410 struct felix_stream_filter_counters *s = &sfi->stats; 2411 u32 match, not_pass_gate, not_pass_sdu, red; 2412 u32 sfid = sfi->index; 2413 2414 lockdep_assert_held(&ocelot->stat_view_lock); 2415 2416 ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(sfid), 2417 SYS_STAT_CFG_STAT_VIEW_M, 2418 SYS_STAT_CFG); 2419 2420 match = ocelot_read(ocelot, SYS_COUNT_SF_MATCHING_FRAMES); 2421 not_pass_gate = ocelot_read(ocelot, SYS_COUNT_SF_NOT_PASSING_FRAMES); 2422 not_pass_sdu = ocelot_read(ocelot, SYS_COUNT_SF_NOT_PASSING_SDU); 2423 red = ocelot_read(ocelot, SYS_COUNT_SF_RED_FRAMES); 2424 2425 /* Clear the PSFP counter. */ 2426 ocelot_write(ocelot, 2427 SYS_STAT_CFG_STAT_VIEW(sfid) | 2428 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10), 2429 SYS_STAT_CFG); 2430 2431 s->match += match; 2432 s->not_pass_gate += not_pass_gate; 2433 s->not_pass_sdu += not_pass_sdu; 2434 s->red += red; 2435 } 2436 2437 /* Caller must hold &ocelot->stat_view_lock */ 2438 static void vsc9959_update_stats(struct ocelot *ocelot) 2439 { 2440 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2441 struct felix_stream_filter *sfi; 2442 2443 mutex_lock(&psfp->lock); 2444 2445 list_for_each_entry(sfi, &psfp->sfi_list, list) 2446 vsc9959_update_sfid_stats(ocelot, sfi); 2447 2448 mutex_unlock(&psfp->lock); 2449 } 2450 2451 static int vsc9959_psfp_stats_get(struct ocelot *ocelot, 2452 struct flow_cls_offload *f, 2453 struct flow_stats *stats) 2454 { 2455 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2456 struct felix_stream_filter_counters *s; 2457 static struct felix_stream_filter *sfi; 2458 struct felix_stream *stream; 2459 2460 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 2461 if (!stream) 2462 return -ENOMEM; 2463 2464 sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid); 2465 if (!sfi) 2466 return -EINVAL; 2467 2468 mutex_lock(&ocelot->stat_view_lock); 2469 2470 vsc9959_update_sfid_stats(ocelot, sfi); 2471 2472 s = &sfi->stats; 2473 stats->pkts = s->match; 2474 stats->drops = s->not_pass_gate + s->not_pass_sdu + s->red; 2475 2476 memset(s, 0, sizeof(*s)); 2477 2478 mutex_unlock(&ocelot->stat_view_lock); 2479 2480 return 0; 2481 } 2482 2483 static void vsc9959_psfp_init(struct ocelot *ocelot) 2484 { 2485 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2486 2487 INIT_LIST_HEAD(&psfp->stream_list); 2488 INIT_LIST_HEAD(&psfp->sfi_list); 2489 INIT_LIST_HEAD(&psfp->sgi_list); 2490 mutex_init(&psfp->lock); 2491 } 2492 2493 /* When using cut-through forwarding and the egress port runs at a higher data 2494 * rate than the ingress port, the packet currently under transmission would 2495 * suffer an underrun since it would be transmitted faster than it is received. 2496 * The Felix switch implementation of cut-through forwarding does not check in 2497 * hardware whether this condition is satisfied or not, so we must restrict the 2498 * list of ports that have cut-through forwarding enabled on egress to only be 2499 * the ports operating at the lowest link speed within their respective 2500 * forwarding domain. 2501 */ 2502 static void vsc9959_cut_through_fwd(struct ocelot *ocelot) 2503 { 2504 struct felix *felix = ocelot_to_felix(ocelot); 2505 struct dsa_switch *ds = felix->ds; 2506 int tc, port, other_port; 2507 2508 lockdep_assert_held(&ocelot->fwd_domain_lock); 2509 2510 for (port = 0; port < ocelot->num_phys_ports; port++) { 2511 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2512 int min_speed = ocelot_port->speed; 2513 unsigned long mask = 0; 2514 u32 tmp, val = 0; 2515 2516 /* Disable cut-through on ports that are down */ 2517 if (ocelot_port->speed <= 0) 2518 goto set; 2519 2520 if (dsa_is_cpu_port(ds, port)) { 2521 /* Ocelot switches forward from the NPI port towards 2522 * any port, regardless of it being in the NPI port's 2523 * forwarding domain or not. 2524 */ 2525 mask = dsa_user_ports(ds); 2526 } else { 2527 mask = ocelot_get_bridge_fwd_mask(ocelot, port); 2528 mask &= ~BIT(port); 2529 if (ocelot->npi >= 0) 2530 mask |= BIT(ocelot->npi); 2531 else 2532 mask |= ocelot_port_assigned_dsa_8021q_cpu_mask(ocelot, 2533 port); 2534 } 2535 2536 /* Calculate the minimum link speed, among the ports that are 2537 * up, of this source port's forwarding domain. 2538 */ 2539 for_each_set_bit(other_port, &mask, ocelot->num_phys_ports) { 2540 struct ocelot_port *other_ocelot_port; 2541 2542 other_ocelot_port = ocelot->ports[other_port]; 2543 if (other_ocelot_port->speed <= 0) 2544 continue; 2545 2546 if (min_speed > other_ocelot_port->speed) 2547 min_speed = other_ocelot_port->speed; 2548 } 2549 2550 /* Enable cut-through forwarding for all traffic classes that 2551 * don't have oversized dropping enabled, since this check is 2552 * bypassed in cut-through mode. 2553 */ 2554 if (ocelot_port->speed == min_speed) { 2555 val = GENMASK(7, 0); 2556 2557 for (tc = 0; tc < OCELOT_NUM_TC; tc++) 2558 if (vsc9959_port_qmaxsdu_get(ocelot, port, tc)) 2559 val &= ~BIT(tc); 2560 } 2561 2562 set: 2563 tmp = ocelot_read_rix(ocelot, ANA_CUT_THRU_CFG, port); 2564 if (tmp == val) 2565 continue; 2566 2567 dev_dbg(ocelot->dev, 2568 "port %d fwd mask 0x%lx speed %d min_speed %d, %s cut-through forwarding on TC mask 0x%x\n", 2569 port, mask, ocelot_port->speed, min_speed, 2570 val ? "enabling" : "disabling", val); 2571 2572 ocelot_write_rix(ocelot, val, ANA_CUT_THRU_CFG, port); 2573 } 2574 } 2575 2576 static const struct ocelot_ops vsc9959_ops = { 2577 .reset = vsc9959_reset, 2578 .wm_enc = vsc9959_wm_enc, 2579 .wm_dec = vsc9959_wm_dec, 2580 .wm_stat = vsc9959_wm_stat, 2581 .port_to_netdev = felix_port_to_netdev, 2582 .netdev_to_port = felix_netdev_to_port, 2583 .psfp_init = vsc9959_psfp_init, 2584 .psfp_filter_add = vsc9959_psfp_filter_add, 2585 .psfp_filter_del = vsc9959_psfp_filter_del, 2586 .psfp_stats_get = vsc9959_psfp_stats_get, 2587 .cut_through_fwd = vsc9959_cut_through_fwd, 2588 .tas_clock_adjust = vsc9959_tas_clock_adjust, 2589 .update_stats = vsc9959_update_stats, 2590 }; 2591 2592 static const struct felix_info felix_info_vsc9959 = { 2593 .target_io_res = vsc9959_target_io_res, 2594 .port_io_res = vsc9959_port_io_res, 2595 .imdio_res = &vsc9959_imdio_res, 2596 .regfields = vsc9959_regfields, 2597 .map = vsc9959_regmap, 2598 .ops = &vsc9959_ops, 2599 .stats_layout = vsc9959_stats_layout, 2600 .vcap = vsc9959_vcap_props, 2601 .vcap_pol_base = VSC9959_VCAP_POLICER_BASE, 2602 .vcap_pol_max = VSC9959_VCAP_POLICER_MAX, 2603 .vcap_pol_base2 = 0, 2604 .vcap_pol_max2 = 0, 2605 .num_mact_rows = 2048, 2606 .num_ports = VSC9959_NUM_PORTS, 2607 .num_tx_queues = OCELOT_NUM_TC, 2608 .quirk_no_xtr_irq = true, 2609 .ptp_caps = &vsc9959_ptp_caps, 2610 .mdio_bus_alloc = vsc9959_mdio_bus_alloc, 2611 .mdio_bus_free = vsc9959_mdio_bus_free, 2612 .phylink_validate = vsc9959_phylink_validate, 2613 .port_modes = vsc9959_port_modes, 2614 .port_setup_tc = vsc9959_port_setup_tc, 2615 .port_sched_speed_set = vsc9959_sched_speed_set, 2616 .tas_guard_bands_update = vsc9959_tas_guard_bands_update, 2617 .init_regmap = ocelot_regmap_init, 2618 }; 2619 2620 static irqreturn_t felix_irq_handler(int irq, void *data) 2621 { 2622 struct ocelot *ocelot = (struct ocelot *)data; 2623 2624 /* The INTB interrupt is used for both PTP TX timestamp interrupt 2625 * and preemption status change interrupt on each port. 2626 * 2627 * - Get txtstamp if have 2628 * - TODO: handle preemption. Without handling it, driver may get 2629 * interrupt storm. 2630 */ 2631 2632 ocelot_get_txtstamp(ocelot); 2633 2634 return IRQ_HANDLED; 2635 } 2636 2637 static int felix_pci_probe(struct pci_dev *pdev, 2638 const struct pci_device_id *id) 2639 { 2640 struct dsa_switch *ds; 2641 struct ocelot *ocelot; 2642 struct felix *felix; 2643 int err; 2644 2645 if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) { 2646 dev_info(&pdev->dev, "device is disabled, skipping\n"); 2647 return -ENODEV; 2648 } 2649 2650 err = pci_enable_device(pdev); 2651 if (err) { 2652 dev_err(&pdev->dev, "device enable failed\n"); 2653 goto err_pci_enable; 2654 } 2655 2656 felix = kzalloc(sizeof(struct felix), GFP_KERNEL); 2657 if (!felix) { 2658 err = -ENOMEM; 2659 dev_err(&pdev->dev, "Failed to allocate driver memory\n"); 2660 goto err_alloc_felix; 2661 } 2662 2663 pci_set_drvdata(pdev, felix); 2664 ocelot = &felix->ocelot; 2665 ocelot->dev = &pdev->dev; 2666 ocelot->num_flooding_pgids = OCELOT_NUM_TC; 2667 felix->info = &felix_info_vsc9959; 2668 felix->switch_base = pci_resource_start(pdev, VSC9959_SWITCH_PCI_BAR); 2669 felix->imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR); 2670 2671 pci_set_master(pdev); 2672 2673 err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL, 2674 &felix_irq_handler, IRQF_ONESHOT, 2675 "felix-intb", ocelot); 2676 if (err) { 2677 dev_err(&pdev->dev, "Failed to request irq\n"); 2678 goto err_alloc_irq; 2679 } 2680 2681 ocelot->ptp = 1; 2682 2683 ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL); 2684 if (!ds) { 2685 err = -ENOMEM; 2686 dev_err(&pdev->dev, "Failed to allocate DSA switch\n"); 2687 goto err_alloc_ds; 2688 } 2689 2690 ds->dev = &pdev->dev; 2691 ds->num_ports = felix->info->num_ports; 2692 ds->num_tx_queues = felix->info->num_tx_queues; 2693 ds->ops = &felix_switch_ops; 2694 ds->priv = ocelot; 2695 felix->ds = ds; 2696 felix->tag_proto = DSA_TAG_PROTO_OCELOT; 2697 2698 err = dsa_register_switch(ds); 2699 if (err) { 2700 dev_err_probe(&pdev->dev, err, "Failed to register DSA switch\n"); 2701 goto err_register_ds; 2702 } 2703 2704 return 0; 2705 2706 err_register_ds: 2707 kfree(ds); 2708 err_alloc_ds: 2709 err_alloc_irq: 2710 kfree(felix); 2711 err_alloc_felix: 2712 pci_disable_device(pdev); 2713 err_pci_enable: 2714 return err; 2715 } 2716 2717 static void felix_pci_remove(struct pci_dev *pdev) 2718 { 2719 struct felix *felix = pci_get_drvdata(pdev); 2720 2721 if (!felix) 2722 return; 2723 2724 dsa_unregister_switch(felix->ds); 2725 2726 kfree(felix->ds); 2727 kfree(felix); 2728 2729 pci_disable_device(pdev); 2730 2731 pci_set_drvdata(pdev, NULL); 2732 } 2733 2734 static void felix_pci_shutdown(struct pci_dev *pdev) 2735 { 2736 struct felix *felix = pci_get_drvdata(pdev); 2737 2738 if (!felix) 2739 return; 2740 2741 dsa_switch_shutdown(felix->ds); 2742 2743 pci_set_drvdata(pdev, NULL); 2744 } 2745 2746 static struct pci_device_id felix_ids[] = { 2747 { 2748 /* NXP LS1028A */ 2749 PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0), 2750 }, 2751 { 0, } 2752 }; 2753 MODULE_DEVICE_TABLE(pci, felix_ids); 2754 2755 static struct pci_driver felix_vsc9959_pci_driver = { 2756 .name = "mscc_felix", 2757 .id_table = felix_ids, 2758 .probe = felix_pci_probe, 2759 .remove = felix_pci_remove, 2760 .shutdown = felix_pci_shutdown, 2761 }; 2762 module_pci_driver(felix_vsc9959_pci_driver); 2763 2764 MODULE_DESCRIPTION("Felix Switch driver"); 2765 MODULE_LICENSE("GPL v2"); 2766