1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright 2017 Microsemi Corporation 3 * Copyright 2018-2019 NXP 4 */ 5 #include <linux/fsl/enetc_mdio.h> 6 #include <soc/mscc/ocelot_qsys.h> 7 #include <soc/mscc/ocelot_vcap.h> 8 #include <soc/mscc/ocelot_ana.h> 9 #include <soc/mscc/ocelot_ptp.h> 10 #include <soc/mscc/ocelot_sys.h> 11 #include <net/tc_act/tc_gate.h> 12 #include <soc/mscc/ocelot.h> 13 #include <linux/dsa/ocelot.h> 14 #include <linux/pcs-lynx.h> 15 #include <net/pkt_sched.h> 16 #include <linux/iopoll.h> 17 #include <linux/mdio.h> 18 #include <linux/pci.h> 19 #include "felix.h" 20 21 #define VSC9959_TAS_GCL_ENTRY_MAX 63 22 #define VSC9959_VCAP_POLICER_BASE 63 23 #define VSC9959_VCAP_POLICER_MAX 383 24 #define VSC9959_SWITCH_PCI_BAR 4 25 #define VSC9959_IMDIO_PCI_BAR 0 26 27 static const u32 vsc9959_ana_regmap[] = { 28 REG(ANA_ADVLEARN, 0x0089a0), 29 REG(ANA_VLANMASK, 0x0089a4), 30 REG_RESERVED(ANA_PORT_B_DOMAIN), 31 REG(ANA_ANAGEFIL, 0x0089ac), 32 REG(ANA_ANEVENTS, 0x0089b0), 33 REG(ANA_STORMLIMIT_BURST, 0x0089b4), 34 REG(ANA_STORMLIMIT_CFG, 0x0089b8), 35 REG(ANA_ISOLATED_PORTS, 0x0089c8), 36 REG(ANA_COMMUNITY_PORTS, 0x0089cc), 37 REG(ANA_AUTOAGE, 0x0089d0), 38 REG(ANA_MACTOPTIONS, 0x0089d4), 39 REG(ANA_LEARNDISC, 0x0089d8), 40 REG(ANA_AGENCTRL, 0x0089dc), 41 REG(ANA_MIRRORPORTS, 0x0089e0), 42 REG(ANA_EMIRRORPORTS, 0x0089e4), 43 REG(ANA_FLOODING, 0x0089e8), 44 REG(ANA_FLOODING_IPMC, 0x008a08), 45 REG(ANA_SFLOW_CFG, 0x008a0c), 46 REG(ANA_PORT_MODE, 0x008a28), 47 REG(ANA_CUT_THRU_CFG, 0x008a48), 48 REG(ANA_PGID_PGID, 0x008400), 49 REG(ANA_TABLES_ANMOVED, 0x007f1c), 50 REG(ANA_TABLES_MACHDATA, 0x007f20), 51 REG(ANA_TABLES_MACLDATA, 0x007f24), 52 REG(ANA_TABLES_STREAMDATA, 0x007f28), 53 REG(ANA_TABLES_MACACCESS, 0x007f2c), 54 REG(ANA_TABLES_MACTINDX, 0x007f30), 55 REG(ANA_TABLES_VLANACCESS, 0x007f34), 56 REG(ANA_TABLES_VLANTIDX, 0x007f38), 57 REG(ANA_TABLES_ISDXACCESS, 0x007f3c), 58 REG(ANA_TABLES_ISDXTIDX, 0x007f40), 59 REG(ANA_TABLES_ENTRYLIM, 0x007f00), 60 REG(ANA_TABLES_PTP_ID_HIGH, 0x007f44), 61 REG(ANA_TABLES_PTP_ID_LOW, 0x007f48), 62 REG(ANA_TABLES_STREAMACCESS, 0x007f4c), 63 REG(ANA_TABLES_STREAMTIDX, 0x007f50), 64 REG(ANA_TABLES_SEQ_HISTORY, 0x007f54), 65 REG(ANA_TABLES_SEQ_MASK, 0x007f58), 66 REG(ANA_TABLES_SFID_MASK, 0x007f5c), 67 REG(ANA_TABLES_SFIDACCESS, 0x007f60), 68 REG(ANA_TABLES_SFIDTIDX, 0x007f64), 69 REG(ANA_MSTI_STATE, 0x008600), 70 REG(ANA_OAM_UPM_LM_CNT, 0x008000), 71 REG(ANA_SG_ACCESS_CTRL, 0x008a64), 72 REG(ANA_SG_CONFIG_REG_1, 0x007fb0), 73 REG(ANA_SG_CONFIG_REG_2, 0x007fb4), 74 REG(ANA_SG_CONFIG_REG_3, 0x007fb8), 75 REG(ANA_SG_CONFIG_REG_4, 0x007fbc), 76 REG(ANA_SG_CONFIG_REG_5, 0x007fc0), 77 REG(ANA_SG_GCL_GS_CONFIG, 0x007f80), 78 REG(ANA_SG_GCL_TI_CONFIG, 0x007f90), 79 REG(ANA_SG_STATUS_REG_1, 0x008980), 80 REG(ANA_SG_STATUS_REG_2, 0x008984), 81 REG(ANA_SG_STATUS_REG_3, 0x008988), 82 REG(ANA_PORT_VLAN_CFG, 0x007800), 83 REG(ANA_PORT_DROP_CFG, 0x007804), 84 REG(ANA_PORT_QOS_CFG, 0x007808), 85 REG(ANA_PORT_VCAP_CFG, 0x00780c), 86 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007810), 87 REG(ANA_PORT_VCAP_S2_CFG, 0x00781c), 88 REG(ANA_PORT_PCP_DEI_MAP, 0x007820), 89 REG(ANA_PORT_CPU_FWD_CFG, 0x007860), 90 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007864), 91 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007868), 92 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00786c), 93 REG(ANA_PORT_PORT_CFG, 0x007870), 94 REG(ANA_PORT_POL_CFG, 0x007874), 95 REG(ANA_PORT_PTP_CFG, 0x007878), 96 REG(ANA_PORT_PTP_DLY1_CFG, 0x00787c), 97 REG(ANA_PORT_PTP_DLY2_CFG, 0x007880), 98 REG(ANA_PORT_SFID_CFG, 0x007884), 99 REG(ANA_PFC_PFC_CFG, 0x008800), 100 REG_RESERVED(ANA_PFC_PFC_TIMER), 101 REG_RESERVED(ANA_IPT_OAM_MEP_CFG), 102 REG_RESERVED(ANA_IPT_IPT), 103 REG_RESERVED(ANA_PPT_PPT), 104 REG_RESERVED(ANA_FID_MAP_FID_MAP), 105 REG(ANA_AGGR_CFG, 0x008a68), 106 REG(ANA_CPUQ_CFG, 0x008a6c), 107 REG_RESERVED(ANA_CPUQ_CFG2), 108 REG(ANA_CPUQ_8021_CFG, 0x008a74), 109 REG(ANA_DSCP_CFG, 0x008ab4), 110 REG(ANA_DSCP_REWR_CFG, 0x008bb4), 111 REG(ANA_VCAP_RNG_TYPE_CFG, 0x008bf4), 112 REG(ANA_VCAP_RNG_VAL_CFG, 0x008c14), 113 REG_RESERVED(ANA_VRAP_CFG), 114 REG_RESERVED(ANA_VRAP_HDR_DATA), 115 REG_RESERVED(ANA_VRAP_HDR_MASK), 116 REG(ANA_DISCARD_CFG, 0x008c40), 117 REG(ANA_FID_CFG, 0x008c44), 118 REG(ANA_POL_PIR_CFG, 0x004000), 119 REG(ANA_POL_CIR_CFG, 0x004004), 120 REG(ANA_POL_MODE_CFG, 0x004008), 121 REG(ANA_POL_PIR_STATE, 0x00400c), 122 REG(ANA_POL_CIR_STATE, 0x004010), 123 REG_RESERVED(ANA_POL_STATE), 124 REG(ANA_POL_FLOWC, 0x008c48), 125 REG(ANA_POL_HYST, 0x008cb4), 126 REG_RESERVED(ANA_POL_MISC_CFG), 127 }; 128 129 static const u32 vsc9959_qs_regmap[] = { 130 REG(QS_XTR_GRP_CFG, 0x000000), 131 REG(QS_XTR_RD, 0x000008), 132 REG(QS_XTR_FRM_PRUNING, 0x000010), 133 REG(QS_XTR_FLUSH, 0x000018), 134 REG(QS_XTR_DATA_PRESENT, 0x00001c), 135 REG(QS_XTR_CFG, 0x000020), 136 REG(QS_INJ_GRP_CFG, 0x000024), 137 REG(QS_INJ_WR, 0x00002c), 138 REG(QS_INJ_CTRL, 0x000034), 139 REG(QS_INJ_STATUS, 0x00003c), 140 REG(QS_INJ_ERR, 0x000040), 141 REG_RESERVED(QS_INH_DBG), 142 }; 143 144 static const u32 vsc9959_vcap_regmap[] = { 145 /* VCAP_CORE_CFG */ 146 REG(VCAP_CORE_UPDATE_CTRL, 0x000000), 147 REG(VCAP_CORE_MV_CFG, 0x000004), 148 /* VCAP_CORE_CACHE */ 149 REG(VCAP_CACHE_ENTRY_DAT, 0x000008), 150 REG(VCAP_CACHE_MASK_DAT, 0x000108), 151 REG(VCAP_CACHE_ACTION_DAT, 0x000208), 152 REG(VCAP_CACHE_CNT_DAT, 0x000308), 153 REG(VCAP_CACHE_TG_DAT, 0x000388), 154 /* VCAP_CONST */ 155 REG(VCAP_CONST_VCAP_VER, 0x000398), 156 REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c), 157 REG(VCAP_CONST_ENTRY_CNT, 0x0003a0), 158 REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4), 159 REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8), 160 REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac), 161 REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0), 162 REG(VCAP_CONST_CNT_WIDTH, 0x0003b4), 163 REG(VCAP_CONST_CORE_CNT, 0x0003b8), 164 REG(VCAP_CONST_IF_CNT, 0x0003bc), 165 }; 166 167 static const u32 vsc9959_qsys_regmap[] = { 168 REG(QSYS_PORT_MODE, 0x00f460), 169 REG(QSYS_SWITCH_PORT_MODE, 0x00f480), 170 REG(QSYS_STAT_CNT_CFG, 0x00f49c), 171 REG(QSYS_EEE_CFG, 0x00f4a0), 172 REG(QSYS_EEE_THRES, 0x00f4b8), 173 REG(QSYS_IGR_NO_SHARING, 0x00f4bc), 174 REG(QSYS_EGR_NO_SHARING, 0x00f4c0), 175 REG(QSYS_SW_STATUS, 0x00f4c4), 176 REG(QSYS_EXT_CPU_CFG, 0x00f4e0), 177 REG_RESERVED(QSYS_PAD_CFG), 178 REG(QSYS_CPU_GROUP_MAP, 0x00f4e8), 179 REG_RESERVED(QSYS_QMAP), 180 REG_RESERVED(QSYS_ISDX_SGRP), 181 REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), 182 REG(QSYS_TFRM_MISC, 0x00f50c), 183 REG(QSYS_TFRM_PORT_DLY, 0x00f510), 184 REG(QSYS_TFRM_TIMER_CFG_1, 0x00f514), 185 REG(QSYS_TFRM_TIMER_CFG_2, 0x00f518), 186 REG(QSYS_TFRM_TIMER_CFG_3, 0x00f51c), 187 REG(QSYS_TFRM_TIMER_CFG_4, 0x00f520), 188 REG(QSYS_TFRM_TIMER_CFG_5, 0x00f524), 189 REG(QSYS_TFRM_TIMER_CFG_6, 0x00f528), 190 REG(QSYS_TFRM_TIMER_CFG_7, 0x00f52c), 191 REG(QSYS_TFRM_TIMER_CFG_8, 0x00f530), 192 REG(QSYS_RED_PROFILE, 0x00f534), 193 REG(QSYS_RES_QOS_MODE, 0x00f574), 194 REG(QSYS_RES_CFG, 0x00c000), 195 REG(QSYS_RES_STAT, 0x00c004), 196 REG(QSYS_EGR_DROP_MODE, 0x00f578), 197 REG(QSYS_EQ_CTRL, 0x00f57c), 198 REG_RESERVED(QSYS_EVENTS_CORE), 199 REG(QSYS_QMAXSDU_CFG_0, 0x00f584), 200 REG(QSYS_QMAXSDU_CFG_1, 0x00f5a0), 201 REG(QSYS_QMAXSDU_CFG_2, 0x00f5bc), 202 REG(QSYS_QMAXSDU_CFG_3, 0x00f5d8), 203 REG(QSYS_QMAXSDU_CFG_4, 0x00f5f4), 204 REG(QSYS_QMAXSDU_CFG_5, 0x00f610), 205 REG(QSYS_QMAXSDU_CFG_6, 0x00f62c), 206 REG(QSYS_QMAXSDU_CFG_7, 0x00f648), 207 REG(QSYS_PREEMPTION_CFG, 0x00f664), 208 REG(QSYS_CIR_CFG, 0x000000), 209 REG(QSYS_EIR_CFG, 0x000004), 210 REG(QSYS_SE_CFG, 0x000008), 211 REG(QSYS_SE_DWRR_CFG, 0x00000c), 212 REG_RESERVED(QSYS_SE_CONNECT), 213 REG(QSYS_SE_DLB_SENSE, 0x000040), 214 REG(QSYS_CIR_STATE, 0x000044), 215 REG(QSYS_EIR_STATE, 0x000048), 216 REG_RESERVED(QSYS_SE_STATE), 217 REG(QSYS_HSCH_MISC_CFG, 0x00f67c), 218 REG(QSYS_TAG_CONFIG, 0x00f680), 219 REG(QSYS_TAS_PARAM_CFG_CTRL, 0x00f698), 220 REG(QSYS_PORT_MAX_SDU, 0x00f69c), 221 REG(QSYS_PARAM_CFG_REG_1, 0x00f440), 222 REG(QSYS_PARAM_CFG_REG_2, 0x00f444), 223 REG(QSYS_PARAM_CFG_REG_3, 0x00f448), 224 REG(QSYS_PARAM_CFG_REG_4, 0x00f44c), 225 REG(QSYS_PARAM_CFG_REG_5, 0x00f450), 226 REG(QSYS_GCL_CFG_REG_1, 0x00f454), 227 REG(QSYS_GCL_CFG_REG_2, 0x00f458), 228 REG(QSYS_PARAM_STATUS_REG_1, 0x00f400), 229 REG(QSYS_PARAM_STATUS_REG_2, 0x00f404), 230 REG(QSYS_PARAM_STATUS_REG_3, 0x00f408), 231 REG(QSYS_PARAM_STATUS_REG_4, 0x00f40c), 232 REG(QSYS_PARAM_STATUS_REG_5, 0x00f410), 233 REG(QSYS_PARAM_STATUS_REG_6, 0x00f414), 234 REG(QSYS_PARAM_STATUS_REG_7, 0x00f418), 235 REG(QSYS_PARAM_STATUS_REG_8, 0x00f41c), 236 REG(QSYS_PARAM_STATUS_REG_9, 0x00f420), 237 REG(QSYS_GCL_STATUS_REG_1, 0x00f424), 238 REG(QSYS_GCL_STATUS_REG_2, 0x00f428), 239 }; 240 241 static const u32 vsc9959_rew_regmap[] = { 242 REG(REW_PORT_VLAN_CFG, 0x000000), 243 REG(REW_TAG_CFG, 0x000004), 244 REG(REW_PORT_CFG, 0x000008), 245 REG(REW_DSCP_CFG, 0x00000c), 246 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 247 REG(REW_PTP_CFG, 0x000050), 248 REG(REW_PTP_DLY1_CFG, 0x000054), 249 REG(REW_RED_TAG_CFG, 0x000058), 250 REG(REW_DSCP_REMAP_DP1_CFG, 0x000410), 251 REG(REW_DSCP_REMAP_CFG, 0x000510), 252 REG_RESERVED(REW_STAT_CFG), 253 REG_RESERVED(REW_REW_STICKY), 254 REG_RESERVED(REW_PPT), 255 }; 256 257 static const u32 vsc9959_sys_regmap[] = { 258 REG(SYS_COUNT_RX_OCTETS, 0x000000), 259 REG(SYS_COUNT_RX_MULTICAST, 0x000008), 260 REG(SYS_COUNT_RX_SHORTS, 0x000010), 261 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 262 REG(SYS_COUNT_RX_JABBERS, 0x000018), 263 REG(SYS_COUNT_RX_64, 0x000024), 264 REG(SYS_COUNT_RX_65_127, 0x000028), 265 REG(SYS_COUNT_RX_128_255, 0x00002c), 266 REG(SYS_COUNT_RX_256_1023, 0x000030), 267 REG(SYS_COUNT_RX_1024_1526, 0x000034), 268 REG(SYS_COUNT_RX_1527_MAX, 0x000038), 269 REG(SYS_COUNT_RX_LONGS, 0x000044), 270 REG(SYS_COUNT_TX_OCTETS, 0x000200), 271 REG(SYS_COUNT_TX_COLLISION, 0x000210), 272 REG(SYS_COUNT_TX_DROPS, 0x000214), 273 REG(SYS_COUNT_TX_64, 0x00021c), 274 REG(SYS_COUNT_TX_65_127, 0x000220), 275 REG(SYS_COUNT_TX_128_511, 0x000224), 276 REG(SYS_COUNT_TX_512_1023, 0x000228), 277 REG(SYS_COUNT_TX_1024_1526, 0x00022c), 278 REG(SYS_COUNT_TX_1527_MAX, 0x000230), 279 REG(SYS_COUNT_TX_AGING, 0x000278), 280 REG(SYS_RESET_CFG, 0x000e00), 281 REG(SYS_SR_ETYPE_CFG, 0x000e04), 282 REG(SYS_VLAN_ETYPE_CFG, 0x000e08), 283 REG(SYS_PORT_MODE, 0x000e0c), 284 REG(SYS_FRONT_PORT_MODE, 0x000e2c), 285 REG(SYS_FRM_AGING, 0x000e44), 286 REG(SYS_STAT_CFG, 0x000e48), 287 REG(SYS_SW_STATUS, 0x000e4c), 288 REG_RESERVED(SYS_MISC_CFG), 289 REG(SYS_REW_MAC_HIGH_CFG, 0x000e6c), 290 REG(SYS_REW_MAC_LOW_CFG, 0x000e84), 291 REG(SYS_TIMESTAMP_OFFSET, 0x000e9c), 292 REG(SYS_PAUSE_CFG, 0x000ea0), 293 REG(SYS_PAUSE_TOT_CFG, 0x000ebc), 294 REG(SYS_ATOP, 0x000ec0), 295 REG(SYS_ATOP_TOT_CFG, 0x000edc), 296 REG(SYS_MAC_FC_CFG, 0x000ee0), 297 REG(SYS_MMGT, 0x000ef8), 298 REG_RESERVED(SYS_MMGT_FAST), 299 REG_RESERVED(SYS_EVENTS_DIF), 300 REG_RESERVED(SYS_EVENTS_CORE), 301 REG(SYS_CNT, 0x000000), 302 REG(SYS_PTP_STATUS, 0x000f14), 303 REG(SYS_PTP_TXSTAMP, 0x000f18), 304 REG(SYS_PTP_NXT, 0x000f1c), 305 REG(SYS_PTP_CFG, 0x000f20), 306 REG(SYS_RAM_INIT, 0x000f24), 307 REG_RESERVED(SYS_CM_ADDR), 308 REG_RESERVED(SYS_CM_DATA_WR), 309 REG_RESERVED(SYS_CM_DATA_RD), 310 REG_RESERVED(SYS_CM_OP), 311 REG_RESERVED(SYS_CM_DATA), 312 }; 313 314 static const u32 vsc9959_ptp_regmap[] = { 315 REG(PTP_PIN_CFG, 0x000000), 316 REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 317 REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 318 REG(PTP_PIN_TOD_NSEC, 0x00000c), 319 REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 320 REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 321 REG(PTP_CFG_MISC, 0x0000a0), 322 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 323 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 324 }; 325 326 static const u32 vsc9959_gcb_regmap[] = { 327 REG(GCB_SOFT_RST, 0x000004), 328 }; 329 330 static const u32 vsc9959_dev_gmii_regmap[] = { 331 REG(DEV_CLOCK_CFG, 0x0), 332 REG(DEV_PORT_MISC, 0x4), 333 REG(DEV_EVENTS, 0x8), 334 REG(DEV_EEE_CFG, 0xc), 335 REG(DEV_RX_PATH_DELAY, 0x10), 336 REG(DEV_TX_PATH_DELAY, 0x14), 337 REG(DEV_PTP_PREDICT_CFG, 0x18), 338 REG(DEV_MAC_ENA_CFG, 0x1c), 339 REG(DEV_MAC_MODE_CFG, 0x20), 340 REG(DEV_MAC_MAXLEN_CFG, 0x24), 341 REG(DEV_MAC_TAGS_CFG, 0x28), 342 REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 343 REG(DEV_MAC_IFG_CFG, 0x30), 344 REG(DEV_MAC_HDX_CFG, 0x34), 345 REG(DEV_MAC_DBG_CFG, 0x38), 346 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 347 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 348 REG(DEV_MAC_STICKY, 0x44), 349 REG_RESERVED(PCS1G_CFG), 350 REG_RESERVED(PCS1G_MODE_CFG), 351 REG_RESERVED(PCS1G_SD_CFG), 352 REG_RESERVED(PCS1G_ANEG_CFG), 353 REG_RESERVED(PCS1G_ANEG_NP_CFG), 354 REG_RESERVED(PCS1G_LB_CFG), 355 REG_RESERVED(PCS1G_DBG_CFG), 356 REG_RESERVED(PCS1G_CDET_CFG), 357 REG_RESERVED(PCS1G_ANEG_STATUS), 358 REG_RESERVED(PCS1G_ANEG_NP_STATUS), 359 REG_RESERVED(PCS1G_LINK_STATUS), 360 REG_RESERVED(PCS1G_LINK_DOWN_CNT), 361 REG_RESERVED(PCS1G_STICKY), 362 REG_RESERVED(PCS1G_DEBUG_STATUS), 363 REG_RESERVED(PCS1G_LPI_CFG), 364 REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT), 365 REG_RESERVED(PCS1G_LPI_STATUS), 366 REG_RESERVED(PCS1G_TSTPAT_MODE_CFG), 367 REG_RESERVED(PCS1G_TSTPAT_STATUS), 368 REG_RESERVED(DEV_PCS_FX100_CFG), 369 REG_RESERVED(DEV_PCS_FX100_STATUS), 370 }; 371 372 static const u32 *vsc9959_regmap[TARGET_MAX] = { 373 [ANA] = vsc9959_ana_regmap, 374 [QS] = vsc9959_qs_regmap, 375 [QSYS] = vsc9959_qsys_regmap, 376 [REW] = vsc9959_rew_regmap, 377 [SYS] = vsc9959_sys_regmap, 378 [S0] = vsc9959_vcap_regmap, 379 [S1] = vsc9959_vcap_regmap, 380 [S2] = vsc9959_vcap_regmap, 381 [PTP] = vsc9959_ptp_regmap, 382 [GCB] = vsc9959_gcb_regmap, 383 [DEV_GMII] = vsc9959_dev_gmii_regmap, 384 }; 385 386 /* Addresses are relative to the PCI device's base address */ 387 static const struct resource vsc9959_target_io_res[TARGET_MAX] = { 388 [ANA] = { 389 .start = 0x0280000, 390 .end = 0x028ffff, 391 .name = "ana", 392 }, 393 [QS] = { 394 .start = 0x0080000, 395 .end = 0x00800ff, 396 .name = "qs", 397 }, 398 [QSYS] = { 399 .start = 0x0200000, 400 .end = 0x021ffff, 401 .name = "qsys", 402 }, 403 [REW] = { 404 .start = 0x0030000, 405 .end = 0x003ffff, 406 .name = "rew", 407 }, 408 [SYS] = { 409 .start = 0x0010000, 410 .end = 0x001ffff, 411 .name = "sys", 412 }, 413 [S0] = { 414 .start = 0x0040000, 415 .end = 0x00403ff, 416 .name = "s0", 417 }, 418 [S1] = { 419 .start = 0x0050000, 420 .end = 0x00503ff, 421 .name = "s1", 422 }, 423 [S2] = { 424 .start = 0x0060000, 425 .end = 0x00603ff, 426 .name = "s2", 427 }, 428 [PTP] = { 429 .start = 0x0090000, 430 .end = 0x00900cb, 431 .name = "ptp", 432 }, 433 [GCB] = { 434 .start = 0x0070000, 435 .end = 0x00701ff, 436 .name = "devcpu_gcb", 437 }, 438 }; 439 440 static const struct resource vsc9959_port_io_res[] = { 441 { 442 .start = 0x0100000, 443 .end = 0x010ffff, 444 .name = "port0", 445 }, 446 { 447 .start = 0x0110000, 448 .end = 0x011ffff, 449 .name = "port1", 450 }, 451 { 452 .start = 0x0120000, 453 .end = 0x012ffff, 454 .name = "port2", 455 }, 456 { 457 .start = 0x0130000, 458 .end = 0x013ffff, 459 .name = "port3", 460 }, 461 { 462 .start = 0x0140000, 463 .end = 0x014ffff, 464 .name = "port4", 465 }, 466 { 467 .start = 0x0150000, 468 .end = 0x015ffff, 469 .name = "port5", 470 }, 471 }; 472 473 /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an 474 * SGMII/QSGMII MAC PCS can be found. 475 */ 476 static const struct resource vsc9959_imdio_res = { 477 .start = 0x8030, 478 .end = 0x8040, 479 .name = "imdio", 480 }; 481 482 static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = { 483 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), 484 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5), 485 [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30), 486 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26), 487 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24), 488 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23), 489 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22), 490 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21), 491 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20), 492 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19), 493 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 494 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17), 495 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15), 496 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14), 497 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13), 498 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12), 499 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 500 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 501 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9), 502 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8), 503 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7), 504 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 505 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 506 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4), 507 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3), 508 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2), 509 [ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1), 510 [ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0), 511 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), 512 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), 513 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), 514 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0), 515 [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), 516 /* Replicated per number of ports (7), register size 4 per port */ 517 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4), 518 [QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4), 519 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4), 520 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4), 521 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4), 522 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4), 523 [SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4), 524 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4), 525 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4), 526 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4), 527 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4), 528 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4), 529 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4), 530 }; 531 532 static const struct ocelot_stat_layout vsc9959_stats_layout[] = { 533 { .offset = 0x00, .name = "rx_octets", }, 534 { .offset = 0x01, .name = "rx_unicast", }, 535 { .offset = 0x02, .name = "rx_multicast", }, 536 { .offset = 0x03, .name = "rx_broadcast", }, 537 { .offset = 0x04, .name = "rx_shorts", }, 538 { .offset = 0x05, .name = "rx_fragments", }, 539 { .offset = 0x06, .name = "rx_jabbers", }, 540 { .offset = 0x07, .name = "rx_crc_align_errs", }, 541 { .offset = 0x08, .name = "rx_sym_errs", }, 542 { .offset = 0x09, .name = "rx_frames_below_65_octets", }, 543 { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", }, 544 { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", }, 545 { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", }, 546 { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", }, 547 { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", }, 548 { .offset = 0x0F, .name = "rx_frames_over_1526_octets", }, 549 { .offset = 0x10, .name = "rx_pause", }, 550 { .offset = 0x11, .name = "rx_control", }, 551 { .offset = 0x12, .name = "rx_longs", }, 552 { .offset = 0x13, .name = "rx_classified_drops", }, 553 { .offset = 0x14, .name = "rx_red_prio_0", }, 554 { .offset = 0x15, .name = "rx_red_prio_1", }, 555 { .offset = 0x16, .name = "rx_red_prio_2", }, 556 { .offset = 0x17, .name = "rx_red_prio_3", }, 557 { .offset = 0x18, .name = "rx_red_prio_4", }, 558 { .offset = 0x19, .name = "rx_red_prio_5", }, 559 { .offset = 0x1A, .name = "rx_red_prio_6", }, 560 { .offset = 0x1B, .name = "rx_red_prio_7", }, 561 { .offset = 0x1C, .name = "rx_yellow_prio_0", }, 562 { .offset = 0x1D, .name = "rx_yellow_prio_1", }, 563 { .offset = 0x1E, .name = "rx_yellow_prio_2", }, 564 { .offset = 0x1F, .name = "rx_yellow_prio_3", }, 565 { .offset = 0x20, .name = "rx_yellow_prio_4", }, 566 { .offset = 0x21, .name = "rx_yellow_prio_5", }, 567 { .offset = 0x22, .name = "rx_yellow_prio_6", }, 568 { .offset = 0x23, .name = "rx_yellow_prio_7", }, 569 { .offset = 0x24, .name = "rx_green_prio_0", }, 570 { .offset = 0x25, .name = "rx_green_prio_1", }, 571 { .offset = 0x26, .name = "rx_green_prio_2", }, 572 { .offset = 0x27, .name = "rx_green_prio_3", }, 573 { .offset = 0x28, .name = "rx_green_prio_4", }, 574 { .offset = 0x29, .name = "rx_green_prio_5", }, 575 { .offset = 0x2A, .name = "rx_green_prio_6", }, 576 { .offset = 0x2B, .name = "rx_green_prio_7", }, 577 { .offset = 0x80, .name = "tx_octets", }, 578 { .offset = 0x81, .name = "tx_unicast", }, 579 { .offset = 0x82, .name = "tx_multicast", }, 580 { .offset = 0x83, .name = "tx_broadcast", }, 581 { .offset = 0x84, .name = "tx_collision", }, 582 { .offset = 0x85, .name = "tx_drops", }, 583 { .offset = 0x86, .name = "tx_pause", }, 584 { .offset = 0x87, .name = "tx_frames_below_65_octets", }, 585 { .offset = 0x88, .name = "tx_frames_65_to_127_octets", }, 586 { .offset = 0x89, .name = "tx_frames_128_255_octets", }, 587 { .offset = 0x8B, .name = "tx_frames_256_511_octets", }, 588 { .offset = 0x8C, .name = "tx_frames_1024_1526_octets", }, 589 { .offset = 0x8D, .name = "tx_frames_over_1526_octets", }, 590 { .offset = 0x8E, .name = "tx_yellow_prio_0", }, 591 { .offset = 0x8F, .name = "tx_yellow_prio_1", }, 592 { .offset = 0x90, .name = "tx_yellow_prio_2", }, 593 { .offset = 0x91, .name = "tx_yellow_prio_3", }, 594 { .offset = 0x92, .name = "tx_yellow_prio_4", }, 595 { .offset = 0x93, .name = "tx_yellow_prio_5", }, 596 { .offset = 0x94, .name = "tx_yellow_prio_6", }, 597 { .offset = 0x95, .name = "tx_yellow_prio_7", }, 598 { .offset = 0x96, .name = "tx_green_prio_0", }, 599 { .offset = 0x97, .name = "tx_green_prio_1", }, 600 { .offset = 0x98, .name = "tx_green_prio_2", }, 601 { .offset = 0x99, .name = "tx_green_prio_3", }, 602 { .offset = 0x9A, .name = "tx_green_prio_4", }, 603 { .offset = 0x9B, .name = "tx_green_prio_5", }, 604 { .offset = 0x9C, .name = "tx_green_prio_6", }, 605 { .offset = 0x9D, .name = "tx_green_prio_7", }, 606 { .offset = 0x9E, .name = "tx_aged", }, 607 { .offset = 0x100, .name = "drop_local", }, 608 { .offset = 0x101, .name = "drop_tail", }, 609 { .offset = 0x102, .name = "drop_yellow_prio_0", }, 610 { .offset = 0x103, .name = "drop_yellow_prio_1", }, 611 { .offset = 0x104, .name = "drop_yellow_prio_2", }, 612 { .offset = 0x105, .name = "drop_yellow_prio_3", }, 613 { .offset = 0x106, .name = "drop_yellow_prio_4", }, 614 { .offset = 0x107, .name = "drop_yellow_prio_5", }, 615 { .offset = 0x108, .name = "drop_yellow_prio_6", }, 616 { .offset = 0x109, .name = "drop_yellow_prio_7", }, 617 { .offset = 0x10A, .name = "drop_green_prio_0", }, 618 { .offset = 0x10B, .name = "drop_green_prio_1", }, 619 { .offset = 0x10C, .name = "drop_green_prio_2", }, 620 { .offset = 0x10D, .name = "drop_green_prio_3", }, 621 { .offset = 0x10E, .name = "drop_green_prio_4", }, 622 { .offset = 0x10F, .name = "drop_green_prio_5", }, 623 { .offset = 0x110, .name = "drop_green_prio_6", }, 624 { .offset = 0x111, .name = "drop_green_prio_7", }, 625 }; 626 627 static const struct vcap_field vsc9959_vcap_es0_keys[] = { 628 [VCAP_ES0_EGR_PORT] = { 0, 3}, 629 [VCAP_ES0_IGR_PORT] = { 3, 3}, 630 [VCAP_ES0_RSV] = { 6, 2}, 631 [VCAP_ES0_L2_MC] = { 8, 1}, 632 [VCAP_ES0_L2_BC] = { 9, 1}, 633 [VCAP_ES0_VID] = { 10, 12}, 634 [VCAP_ES0_DP] = { 22, 1}, 635 [VCAP_ES0_PCP] = { 23, 3}, 636 }; 637 638 static const struct vcap_field vsc9959_vcap_es0_actions[] = { 639 [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2}, 640 [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1}, 641 [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2}, 642 [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1}, 643 [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2}, 644 [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2}, 645 [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2}, 646 [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1}, 647 [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2}, 648 [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2}, 649 [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12}, 650 [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3}, 651 [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1}, 652 [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12}, 653 [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3}, 654 [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1}, 655 [VCAP_ES0_ACT_RSV] = { 49, 23}, 656 [VCAP_ES0_ACT_HIT_STICKY] = { 72, 1}, 657 }; 658 659 static const struct vcap_field vsc9959_vcap_is1_keys[] = { 660 [VCAP_IS1_HK_TYPE] = { 0, 1}, 661 [VCAP_IS1_HK_LOOKUP] = { 1, 2}, 662 [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 7}, 663 [VCAP_IS1_HK_RSV] = { 10, 9}, 664 [VCAP_IS1_HK_OAM_Y1731] = { 19, 1}, 665 [VCAP_IS1_HK_L2_MC] = { 20, 1}, 666 [VCAP_IS1_HK_L2_BC] = { 21, 1}, 667 [VCAP_IS1_HK_IP_MC] = { 22, 1}, 668 [VCAP_IS1_HK_VLAN_TAGGED] = { 23, 1}, 669 [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 24, 1}, 670 [VCAP_IS1_HK_TPID] = { 25, 1}, 671 [VCAP_IS1_HK_VID] = { 26, 12}, 672 [VCAP_IS1_HK_DEI] = { 38, 1}, 673 [VCAP_IS1_HK_PCP] = { 39, 3}, 674 /* Specific Fields for IS1 Half Key S1_NORMAL */ 675 [VCAP_IS1_HK_L2_SMAC] = { 42, 48}, 676 [VCAP_IS1_HK_ETYPE_LEN] = { 90, 1}, 677 [VCAP_IS1_HK_ETYPE] = { 91, 16}, 678 [VCAP_IS1_HK_IP_SNAP] = {107, 1}, 679 [VCAP_IS1_HK_IP4] = {108, 1}, 680 /* Layer-3 Information */ 681 [VCAP_IS1_HK_L3_FRAGMENT] = {109, 1}, 682 [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {110, 1}, 683 [VCAP_IS1_HK_L3_OPTIONS] = {111, 1}, 684 [VCAP_IS1_HK_L3_DSCP] = {112, 6}, 685 [VCAP_IS1_HK_L3_IP4_SIP] = {118, 32}, 686 /* Layer-4 Information */ 687 [VCAP_IS1_HK_TCP_UDP] = {150, 1}, 688 [VCAP_IS1_HK_TCP] = {151, 1}, 689 [VCAP_IS1_HK_L4_SPORT] = {152, 16}, 690 [VCAP_IS1_HK_L4_RNG] = {168, 8}, 691 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 692 [VCAP_IS1_HK_IP4_INNER_TPID] = { 42, 1}, 693 [VCAP_IS1_HK_IP4_INNER_VID] = { 43, 12}, 694 [VCAP_IS1_HK_IP4_INNER_DEI] = { 55, 1}, 695 [VCAP_IS1_HK_IP4_INNER_PCP] = { 56, 3}, 696 [VCAP_IS1_HK_IP4_IP4] = { 59, 1}, 697 [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 60, 1}, 698 [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 61, 1}, 699 [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 62, 1}, 700 [VCAP_IS1_HK_IP4_L3_DSCP] = { 63, 6}, 701 [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 69, 32}, 702 [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {101, 32}, 703 [VCAP_IS1_HK_IP4_L3_PROTO] = {133, 8}, 704 [VCAP_IS1_HK_IP4_TCP_UDP] = {141, 1}, 705 [VCAP_IS1_HK_IP4_TCP] = {142, 1}, 706 [VCAP_IS1_HK_IP4_L4_RNG] = {143, 8}, 707 [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {151, 32}, 708 }; 709 710 static const struct vcap_field vsc9959_vcap_is1_actions[] = { 711 [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1}, 712 [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6}, 713 [VCAP_IS1_ACT_QOS_ENA] = { 7, 1}, 714 [VCAP_IS1_ACT_QOS_VAL] = { 8, 3}, 715 [VCAP_IS1_ACT_DP_ENA] = { 11, 1}, 716 [VCAP_IS1_ACT_DP_VAL] = { 12, 1}, 717 [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8}, 718 [VCAP_IS1_ACT_PAG_VAL] = { 21, 8}, 719 [VCAP_IS1_ACT_RSV] = { 29, 9}, 720 /* The fields below are incorrectly shifted by 2 in the manual */ 721 [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1}, 722 [VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12}, 723 [VCAP_IS1_ACT_FID_SEL] = { 51, 2}, 724 [VCAP_IS1_ACT_FID_VAL] = { 53, 13}, 725 [VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1}, 726 [VCAP_IS1_ACT_PCP_VAL] = { 67, 3}, 727 [VCAP_IS1_ACT_DEI_VAL] = { 70, 1}, 728 [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1}, 729 [VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2}, 730 [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4}, 731 [VCAP_IS1_ACT_HIT_STICKY] = { 78, 1}, 732 }; 733 734 static struct vcap_field vsc9959_vcap_is2_keys[] = { 735 /* Common: 41 bits */ 736 [VCAP_IS2_TYPE] = { 0, 4}, 737 [VCAP_IS2_HK_FIRST] = { 4, 1}, 738 [VCAP_IS2_HK_PAG] = { 5, 8}, 739 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 7}, 740 [VCAP_IS2_HK_RSV2] = { 20, 1}, 741 [VCAP_IS2_HK_HOST_MATCH] = { 21, 1}, 742 [VCAP_IS2_HK_L2_MC] = { 22, 1}, 743 [VCAP_IS2_HK_L2_BC] = { 23, 1}, 744 [VCAP_IS2_HK_VLAN_TAGGED] = { 24, 1}, 745 [VCAP_IS2_HK_VID] = { 25, 12}, 746 [VCAP_IS2_HK_DEI] = { 37, 1}, 747 [VCAP_IS2_HK_PCP] = { 38, 3}, 748 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 749 [VCAP_IS2_HK_L2_DMAC] = { 41, 48}, 750 [VCAP_IS2_HK_L2_SMAC] = { 89, 48}, 751 /* MAC_ETYPE (TYPE=000) */ 752 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {137, 16}, 753 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {153, 16}, 754 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {169, 8}, 755 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {177, 3}, 756 /* MAC_LLC (TYPE=001) */ 757 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {137, 40}, 758 /* MAC_SNAP (TYPE=010) */ 759 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {137, 40}, 760 /* MAC_ARP (TYPE=011) */ 761 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 41, 48}, 762 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 89, 1}, 763 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 90, 1}, 764 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 91, 1}, 765 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 92, 1}, 766 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 93, 1}, 767 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 94, 1}, 768 [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 95, 2}, 769 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 97, 32}, 770 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {129, 32}, 771 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {161, 1}, 772 /* IP4_TCP_UDP / IP4_OTHER common */ 773 [VCAP_IS2_HK_IP4] = { 41, 1}, 774 [VCAP_IS2_HK_L3_FRAGMENT] = { 42, 1}, 775 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 43, 1}, 776 [VCAP_IS2_HK_L3_OPTIONS] = { 44, 1}, 777 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 45, 1}, 778 [VCAP_IS2_HK_L3_TOS] = { 46, 8}, 779 [VCAP_IS2_HK_L3_IP4_DIP] = { 54, 32}, 780 [VCAP_IS2_HK_L3_IP4_SIP] = { 86, 32}, 781 [VCAP_IS2_HK_DIP_EQ_SIP] = {118, 1}, 782 /* IP4_TCP_UDP (TYPE=100) */ 783 [VCAP_IS2_HK_TCP] = {119, 1}, 784 [VCAP_IS2_HK_L4_DPORT] = {120, 16}, 785 [VCAP_IS2_HK_L4_SPORT] = {136, 16}, 786 [VCAP_IS2_HK_L4_RNG] = {152, 8}, 787 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {160, 1}, 788 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {161, 1}, 789 [VCAP_IS2_HK_L4_FIN] = {162, 1}, 790 [VCAP_IS2_HK_L4_SYN] = {163, 1}, 791 [VCAP_IS2_HK_L4_RST] = {164, 1}, 792 [VCAP_IS2_HK_L4_PSH] = {165, 1}, 793 [VCAP_IS2_HK_L4_ACK] = {166, 1}, 794 [VCAP_IS2_HK_L4_URG] = {167, 1}, 795 [VCAP_IS2_HK_L4_1588_DOM] = {168, 8}, 796 [VCAP_IS2_HK_L4_1588_VER] = {176, 4}, 797 /* IP4_OTHER (TYPE=101) */ 798 [VCAP_IS2_HK_IP4_L3_PROTO] = {119, 8}, 799 [VCAP_IS2_HK_L3_PAYLOAD] = {127, 56}, 800 /* IP6_STD (TYPE=110) */ 801 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 41, 1}, 802 [VCAP_IS2_HK_L3_IP6_SIP] = { 42, 128}, 803 [VCAP_IS2_HK_IP6_L3_PROTO] = {170, 8}, 804 /* OAM (TYPE=111) */ 805 [VCAP_IS2_HK_OAM_MEL_FLAGS] = {137, 7}, 806 [VCAP_IS2_HK_OAM_VER] = {144, 5}, 807 [VCAP_IS2_HK_OAM_OPCODE] = {149, 8}, 808 [VCAP_IS2_HK_OAM_FLAGS] = {157, 8}, 809 [VCAP_IS2_HK_OAM_MEPID] = {165, 16}, 810 [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = {181, 1}, 811 [VCAP_IS2_HK_OAM_IS_Y1731] = {182, 1}, 812 }; 813 814 static struct vcap_field vsc9959_vcap_is2_actions[] = { 815 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 816 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 817 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 818 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 819 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 820 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 821 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 822 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9}, 823 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1}, 824 [VCAP_IS2_ACT_PORT_MASK] = { 20, 6}, 825 [VCAP_IS2_ACT_REW_OP] = { 26, 9}, 826 [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 35, 1}, 827 [VCAP_IS2_ACT_RSV] = { 36, 2}, 828 [VCAP_IS2_ACT_ACL_ID] = { 38, 6}, 829 [VCAP_IS2_ACT_HIT_CNT] = { 44, 32}, 830 }; 831 832 static struct vcap_props vsc9959_vcap_props[] = { 833 [VCAP_ES0] = { 834 .action_type_width = 0, 835 .action_table = { 836 [ES0_ACTION_TYPE_NORMAL] = { 837 .width = 72, /* HIT_STICKY not included */ 838 .count = 1, 839 }, 840 }, 841 .target = S0, 842 .keys = vsc9959_vcap_es0_keys, 843 .actions = vsc9959_vcap_es0_actions, 844 }, 845 [VCAP_IS1] = { 846 .action_type_width = 0, 847 .action_table = { 848 [IS1_ACTION_TYPE_NORMAL] = { 849 .width = 78, /* HIT_STICKY not included */ 850 .count = 4, 851 }, 852 }, 853 .target = S1, 854 .keys = vsc9959_vcap_is1_keys, 855 .actions = vsc9959_vcap_is1_actions, 856 }, 857 [VCAP_IS2] = { 858 .action_type_width = 1, 859 .action_table = { 860 [IS2_ACTION_TYPE_NORMAL] = { 861 .width = 44, 862 .count = 2 863 }, 864 [IS2_ACTION_TYPE_SMAC_SIP] = { 865 .width = 6, 866 .count = 4 867 }, 868 }, 869 .target = S2, 870 .keys = vsc9959_vcap_is2_keys, 871 .actions = vsc9959_vcap_is2_actions, 872 }, 873 }; 874 875 static const struct ptp_clock_info vsc9959_ptp_caps = { 876 .owner = THIS_MODULE, 877 .name = "felix ptp", 878 .max_adj = 0x7fffffff, 879 .n_alarm = 0, 880 .n_ext_ts = 0, 881 .n_per_out = OCELOT_PTP_PINS_NUM, 882 .n_pins = OCELOT_PTP_PINS_NUM, 883 .pps = 0, 884 .gettime64 = ocelot_ptp_gettime64, 885 .settime64 = ocelot_ptp_settime64, 886 .adjtime = ocelot_ptp_adjtime, 887 .adjfine = ocelot_ptp_adjfine, 888 .verify = ocelot_ptp_verify, 889 .enable = ocelot_ptp_enable, 890 }; 891 892 #define VSC9959_INIT_TIMEOUT 50000 893 #define VSC9959_GCB_RST_SLEEP 100 894 #define VSC9959_SYS_RAMINIT_SLEEP 80 895 896 static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot) 897 { 898 int val; 899 900 ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val); 901 902 return val; 903 } 904 905 static int vsc9959_sys_ram_init_status(struct ocelot *ocelot) 906 { 907 return ocelot_read(ocelot, SYS_RAM_INIT); 908 } 909 910 /* CORE_ENA is in SYS:SYSTEM:RESET_CFG 911 * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT 912 */ 913 static int vsc9959_reset(struct ocelot *ocelot) 914 { 915 int val, err; 916 917 /* soft-reset the switch core */ 918 ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1); 919 920 err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val, 921 VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT); 922 if (err) { 923 dev_err(ocelot->dev, "timeout: switch core reset\n"); 924 return err; 925 } 926 927 /* initialize switch mem ~40us */ 928 ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT); 929 err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val, 930 VSC9959_SYS_RAMINIT_SLEEP, 931 VSC9959_INIT_TIMEOUT); 932 if (err) { 933 dev_err(ocelot->dev, "timeout: switch sram init\n"); 934 return err; 935 } 936 937 /* enable switch core */ 938 ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1); 939 940 return 0; 941 } 942 943 static void vsc9959_phylink_validate(struct ocelot *ocelot, int port, 944 unsigned long *supported, 945 struct phylink_link_state *state) 946 { 947 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 948 949 phylink_set_port_modes(mask); 950 phylink_set(mask, Autoneg); 951 phylink_set(mask, Pause); 952 phylink_set(mask, Asym_Pause); 953 phylink_set(mask, 10baseT_Half); 954 phylink_set(mask, 10baseT_Full); 955 phylink_set(mask, 100baseT_Half); 956 phylink_set(mask, 100baseT_Full); 957 phylink_set(mask, 1000baseT_Half); 958 phylink_set(mask, 1000baseT_Full); 959 960 if (state->interface == PHY_INTERFACE_MODE_INTERNAL || 961 state->interface == PHY_INTERFACE_MODE_2500BASEX || 962 state->interface == PHY_INTERFACE_MODE_USXGMII) { 963 phylink_set(mask, 2500baseT_Full); 964 phylink_set(mask, 2500baseX_Full); 965 } 966 967 linkmode_and(supported, supported, mask); 968 linkmode_and(state->advertising, state->advertising, mask); 969 } 970 971 static int vsc9959_prevalidate_phy_mode(struct ocelot *ocelot, int port, 972 phy_interface_t phy_mode) 973 { 974 switch (phy_mode) { 975 case PHY_INTERFACE_MODE_INTERNAL: 976 if (port != 4 && port != 5) 977 return -ENOTSUPP; 978 return 0; 979 case PHY_INTERFACE_MODE_SGMII: 980 case PHY_INTERFACE_MODE_QSGMII: 981 case PHY_INTERFACE_MODE_USXGMII: 982 case PHY_INTERFACE_MODE_2500BASEX: 983 /* Not supported on internal to-CPU ports */ 984 if (port == 4 || port == 5) 985 return -ENOTSUPP; 986 return 0; 987 default: 988 return -ENOTSUPP; 989 } 990 } 991 992 /* Watermark encode 993 * Bit 8: Unit; 0:1, 1:16 994 * Bit 7-0: Value to be multiplied with unit 995 */ 996 static u16 vsc9959_wm_enc(u16 value) 997 { 998 WARN_ON(value >= 16 * BIT(8)); 999 1000 if (value >= BIT(8)) 1001 return BIT(8) | (value / 16); 1002 1003 return value; 1004 } 1005 1006 static u16 vsc9959_wm_dec(u16 wm) 1007 { 1008 WARN_ON(wm & ~GENMASK(8, 0)); 1009 1010 if (wm & BIT(8)) 1011 return (wm & GENMASK(7, 0)) * 16; 1012 1013 return wm; 1014 } 1015 1016 static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse) 1017 { 1018 *inuse = (val & GENMASK(23, 12)) >> 12; 1019 *maxuse = val & GENMASK(11, 0); 1020 } 1021 1022 static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot) 1023 { 1024 struct felix *felix = ocelot_to_felix(ocelot); 1025 struct enetc_mdio_priv *mdio_priv; 1026 struct device *dev = ocelot->dev; 1027 void __iomem *imdio_regs; 1028 struct resource res; 1029 struct enetc_hw *hw; 1030 struct mii_bus *bus; 1031 int port; 1032 int rc; 1033 1034 felix->pcs = devm_kcalloc(dev, felix->info->num_ports, 1035 sizeof(struct phylink_pcs *), 1036 GFP_KERNEL); 1037 if (!felix->pcs) { 1038 dev_err(dev, "failed to allocate array for PCS PHYs\n"); 1039 return -ENOMEM; 1040 } 1041 1042 memcpy(&res, felix->info->imdio_res, sizeof(res)); 1043 res.flags = IORESOURCE_MEM; 1044 res.start += felix->imdio_base; 1045 res.end += felix->imdio_base; 1046 1047 imdio_regs = devm_ioremap_resource(dev, &res); 1048 if (IS_ERR(imdio_regs)) 1049 return PTR_ERR(imdio_regs); 1050 1051 hw = enetc_hw_alloc(dev, imdio_regs); 1052 if (IS_ERR(hw)) { 1053 dev_err(dev, "failed to allocate ENETC HW structure\n"); 1054 return PTR_ERR(hw); 1055 } 1056 1057 bus = mdiobus_alloc_size(sizeof(*mdio_priv)); 1058 if (!bus) 1059 return -ENOMEM; 1060 1061 bus->name = "VSC9959 internal MDIO bus"; 1062 bus->read = enetc_mdio_read; 1063 bus->write = enetc_mdio_write; 1064 bus->parent = dev; 1065 mdio_priv = bus->priv; 1066 mdio_priv->hw = hw; 1067 /* This gets added to imdio_regs, which already maps addresses 1068 * starting with the proper offset. 1069 */ 1070 mdio_priv->mdio_base = 0; 1071 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev)); 1072 1073 /* Needed in order to initialize the bus mutex lock */ 1074 rc = mdiobus_register(bus); 1075 if (rc < 0) { 1076 dev_err(dev, "failed to register MDIO bus\n"); 1077 mdiobus_free(bus); 1078 return rc; 1079 } 1080 1081 felix->imdio = bus; 1082 1083 for (port = 0; port < felix->info->num_ports; port++) { 1084 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1085 struct phylink_pcs *phylink_pcs; 1086 struct mdio_device *mdio_device; 1087 1088 if (dsa_is_unused_port(felix->ds, port)) 1089 continue; 1090 1091 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL) 1092 continue; 1093 1094 mdio_device = mdio_device_create(felix->imdio, port); 1095 if (IS_ERR(mdio_device)) 1096 continue; 1097 1098 phylink_pcs = lynx_pcs_create(mdio_device); 1099 if (!phylink_pcs) { 1100 mdio_device_free(mdio_device); 1101 continue; 1102 } 1103 1104 felix->pcs[port] = phylink_pcs; 1105 1106 dev_info(dev, "Found PCS at internal MDIO address %d\n", port); 1107 } 1108 1109 return 0; 1110 } 1111 1112 static void vsc9959_mdio_bus_free(struct ocelot *ocelot) 1113 { 1114 struct felix *felix = ocelot_to_felix(ocelot); 1115 int port; 1116 1117 for (port = 0; port < ocelot->num_phys_ports; port++) { 1118 struct phylink_pcs *phylink_pcs = felix->pcs[port]; 1119 struct mdio_device *mdio_device; 1120 1121 if (!phylink_pcs) 1122 continue; 1123 1124 mdio_device = lynx_get_mdio_device(phylink_pcs); 1125 mdio_device_free(mdio_device); 1126 lynx_pcs_destroy(phylink_pcs); 1127 } 1128 mdiobus_unregister(felix->imdio); 1129 mdiobus_free(felix->imdio); 1130 } 1131 1132 static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port, 1133 u32 speed) 1134 { 1135 u8 tas_speed; 1136 1137 switch (speed) { 1138 case SPEED_10: 1139 tas_speed = OCELOT_SPEED_10; 1140 break; 1141 case SPEED_100: 1142 tas_speed = OCELOT_SPEED_100; 1143 break; 1144 case SPEED_1000: 1145 tas_speed = OCELOT_SPEED_1000; 1146 break; 1147 case SPEED_2500: 1148 tas_speed = OCELOT_SPEED_2500; 1149 break; 1150 default: 1151 tas_speed = OCELOT_SPEED_1000; 1152 break; 1153 } 1154 1155 ocelot_rmw_rix(ocelot, 1156 QSYS_TAG_CONFIG_LINK_SPEED(tas_speed), 1157 QSYS_TAG_CONFIG_LINK_SPEED_M, 1158 QSYS_TAG_CONFIG, port); 1159 } 1160 1161 static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time, 1162 u64 cycle_time, 1163 struct timespec64 *new_base_ts) 1164 { 1165 struct timespec64 ts; 1166 ktime_t new_base_time; 1167 ktime_t current_time; 1168 1169 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1170 current_time = timespec64_to_ktime(ts); 1171 new_base_time = base_time; 1172 1173 if (base_time < current_time) { 1174 u64 nr_of_cycles = current_time - base_time; 1175 1176 do_div(nr_of_cycles, cycle_time); 1177 new_base_time += cycle_time * (nr_of_cycles + 1); 1178 } 1179 1180 *new_base_ts = ktime_to_timespec64(new_base_time); 1181 } 1182 1183 static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot) 1184 { 1185 return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL); 1186 } 1187 1188 static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix, 1189 struct tc_taprio_sched_entry *entry) 1190 { 1191 ocelot_write(ocelot, 1192 QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) | 1193 QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask), 1194 QSYS_GCL_CFG_REG_1); 1195 ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2); 1196 } 1197 1198 static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port, 1199 struct tc_taprio_qopt_offload *taprio) 1200 { 1201 struct timespec64 base_ts; 1202 int ret, i; 1203 u32 val; 1204 1205 if (!taprio->enable) { 1206 ocelot_rmw_rix(ocelot, 1207 QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF), 1208 QSYS_TAG_CONFIG_ENABLE | 1209 QSYS_TAG_CONFIG_INIT_GATE_STATE_M, 1210 QSYS_TAG_CONFIG, port); 1211 1212 return 0; 1213 } 1214 1215 if (taprio->cycle_time > NSEC_PER_SEC || 1216 taprio->cycle_time_extension >= NSEC_PER_SEC) 1217 return -EINVAL; 1218 1219 if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX) 1220 return -ERANGE; 1221 1222 /* Enable guard band. The switch will schedule frames without taking 1223 * their length into account. Thus we'll always need to enable the 1224 * guard band which reserves the time of a maximum sized frame at the 1225 * end of the time window. 1226 * 1227 * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we 1228 * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n 1229 * operate on the port number. 1230 */ 1231 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) | 1232 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1233 QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M | 1234 QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q, 1235 QSYS_TAS_PARAM_CFG_CTRL); 1236 1237 /* Hardware errata - Admin config could not be overwritten if 1238 * config is pending, need reset the TAS module 1239 */ 1240 val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8); 1241 if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) 1242 return -EBUSY; 1243 1244 ocelot_rmw_rix(ocelot, 1245 QSYS_TAG_CONFIG_ENABLE | 1246 QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) | 1247 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF), 1248 QSYS_TAG_CONFIG_ENABLE | 1249 QSYS_TAG_CONFIG_INIT_GATE_STATE_M | 1250 QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M, 1251 QSYS_TAG_CONFIG, port); 1252 1253 vsc9959_new_base_time(ocelot, taprio->base_time, 1254 taprio->cycle_time, &base_ts); 1255 ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1); 1256 ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2); 1257 val = upper_32_bits(base_ts.tv_sec); 1258 ocelot_write(ocelot, 1259 QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) | 1260 QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries), 1261 QSYS_PARAM_CFG_REG_3); 1262 ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4); 1263 ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5); 1264 1265 for (i = 0; i < taprio->num_entries; i++) 1266 vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]); 1267 1268 ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1269 QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE, 1270 QSYS_TAS_PARAM_CFG_CTRL); 1271 1272 ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val, 1273 !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE), 1274 10, 100000); 1275 1276 return ret; 1277 } 1278 1279 static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port, 1280 struct tc_cbs_qopt_offload *cbs_qopt) 1281 { 1282 struct ocelot *ocelot = ds->priv; 1283 int port_ix = port * 8 + cbs_qopt->queue; 1284 u32 rate, burst; 1285 1286 if (cbs_qopt->queue >= ds->num_tx_queues) 1287 return -EINVAL; 1288 1289 if (!cbs_qopt->enable) { 1290 ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) | 1291 QSYS_CIR_CFG_CIR_BURST(0), 1292 QSYS_CIR_CFG, port_ix); 1293 1294 ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA, 1295 QSYS_SE_CFG, port_ix); 1296 1297 return 0; 1298 } 1299 1300 /* Rate unit is 100 kbps */ 1301 rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100); 1302 /* Avoid using zero rate */ 1303 rate = clamp_t(u32, rate, 1, GENMASK(14, 0)); 1304 /* Burst unit is 4kB */ 1305 burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096); 1306 /* Avoid using zero burst size */ 1307 burst = clamp_t(u32, burst, 1, GENMASK(5, 0)); 1308 ocelot_write_gix(ocelot, 1309 QSYS_CIR_CFG_CIR_RATE(rate) | 1310 QSYS_CIR_CFG_CIR_BURST(burst), 1311 QSYS_CIR_CFG, 1312 port_ix); 1313 1314 ocelot_rmw_gix(ocelot, 1315 QSYS_SE_CFG_SE_FRM_MODE(0) | 1316 QSYS_SE_CFG_SE_AVB_ENA, 1317 QSYS_SE_CFG_SE_AVB_ENA | 1318 QSYS_SE_CFG_SE_FRM_MODE_M, 1319 QSYS_SE_CFG, 1320 port_ix); 1321 1322 return 0; 1323 } 1324 1325 static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port, 1326 enum tc_setup_type type, 1327 void *type_data) 1328 { 1329 struct ocelot *ocelot = ds->priv; 1330 1331 switch (type) { 1332 case TC_SETUP_QDISC_TAPRIO: 1333 return vsc9959_qos_port_tas_set(ocelot, port, type_data); 1334 case TC_SETUP_QDISC_CBS: 1335 return vsc9959_qos_port_cbs_set(ds, port, type_data); 1336 default: 1337 return -EOPNOTSUPP; 1338 } 1339 } 1340 1341 #define VSC9959_PSFP_SFID_MAX 175 1342 #define VSC9959_PSFP_GATE_ID_MAX 183 1343 #define VSC9959_PSFP_POLICER_BASE 63 1344 #define VSC9959_PSFP_POLICER_MAX 383 1345 #define VSC9959_PSFP_GATE_LIST_NUM 4 1346 #define VSC9959_PSFP_GATE_CYCLETIME_MIN 5000 1347 1348 struct felix_stream { 1349 struct list_head list; 1350 unsigned long id; 1351 bool dummy; 1352 int ports; 1353 int port; 1354 u8 dmac[ETH_ALEN]; 1355 u16 vid; 1356 s8 prio; 1357 u8 sfid_valid; 1358 u8 ssid_valid; 1359 u32 sfid; 1360 u32 ssid; 1361 }; 1362 1363 struct felix_stream_filter { 1364 struct list_head list; 1365 refcount_t refcount; 1366 u32 index; 1367 u8 enable; 1368 int portmask; 1369 u8 sg_valid; 1370 u32 sgid; 1371 u8 fm_valid; 1372 u32 fmid; 1373 u8 prio_valid; 1374 u8 prio; 1375 u32 maxsdu; 1376 }; 1377 1378 struct felix_stream_filter_counters { 1379 u32 match; 1380 u32 not_pass_gate; 1381 u32 not_pass_sdu; 1382 u32 red; 1383 }; 1384 1385 struct felix_stream_gate { 1386 u32 index; 1387 u8 enable; 1388 u8 ipv_valid; 1389 u8 init_ipv; 1390 u64 basetime; 1391 u64 cycletime; 1392 u64 cycletime_ext; 1393 u32 num_entries; 1394 struct action_gate_entry entries[]; 1395 }; 1396 1397 struct felix_stream_gate_entry { 1398 struct list_head list; 1399 refcount_t refcount; 1400 u32 index; 1401 }; 1402 1403 static int vsc9959_stream_identify(struct flow_cls_offload *f, 1404 struct felix_stream *stream) 1405 { 1406 struct flow_rule *rule = flow_cls_offload_flow_rule(f); 1407 struct flow_dissector *dissector = rule->match.dissector; 1408 1409 if (dissector->used_keys & 1410 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | 1411 BIT(FLOW_DISSECTOR_KEY_BASIC) | 1412 BIT(FLOW_DISSECTOR_KEY_VLAN) | 1413 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS))) 1414 return -EOPNOTSUPP; 1415 1416 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { 1417 struct flow_match_eth_addrs match; 1418 1419 flow_rule_match_eth_addrs(rule, &match); 1420 ether_addr_copy(stream->dmac, match.key->dst); 1421 if (!is_zero_ether_addr(match.mask->src)) 1422 return -EOPNOTSUPP; 1423 } else { 1424 return -EOPNOTSUPP; 1425 } 1426 1427 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { 1428 struct flow_match_vlan match; 1429 1430 flow_rule_match_vlan(rule, &match); 1431 if (match.mask->vlan_priority) 1432 stream->prio = match.key->vlan_priority; 1433 else 1434 stream->prio = -1; 1435 1436 if (!match.mask->vlan_id) 1437 return -EOPNOTSUPP; 1438 stream->vid = match.key->vlan_id; 1439 } else { 1440 return -EOPNOTSUPP; 1441 } 1442 1443 stream->id = f->cookie; 1444 1445 return 0; 1446 } 1447 1448 static int vsc9959_mact_stream_set(struct ocelot *ocelot, 1449 struct felix_stream *stream, 1450 struct netlink_ext_ack *extack) 1451 { 1452 enum macaccess_entry_type type; 1453 int ret, sfid, ssid; 1454 u32 vid, dst_idx; 1455 u8 mac[ETH_ALEN]; 1456 1457 ether_addr_copy(mac, stream->dmac); 1458 vid = stream->vid; 1459 1460 /* Stream identification desn't support to add a stream with non 1461 * existent MAC (The MAC entry has not been learned in MAC table). 1462 */ 1463 ret = ocelot_mact_lookup(ocelot, &dst_idx, mac, vid, &type); 1464 if (ret) { 1465 if (extack) 1466 NL_SET_ERR_MSG_MOD(extack, "Stream is not learned in MAC table"); 1467 return -EOPNOTSUPP; 1468 } 1469 1470 if ((stream->sfid_valid || stream->ssid_valid) && 1471 type == ENTRYTYPE_NORMAL) 1472 type = ENTRYTYPE_LOCKED; 1473 1474 sfid = stream->sfid_valid ? stream->sfid : -1; 1475 ssid = stream->ssid_valid ? stream->ssid : -1; 1476 1477 ret = ocelot_mact_learn_streamdata(ocelot, dst_idx, mac, vid, type, 1478 sfid, ssid); 1479 1480 return ret; 1481 } 1482 1483 static struct felix_stream * 1484 vsc9959_stream_table_lookup(struct list_head *stream_list, 1485 struct felix_stream *stream) 1486 { 1487 struct felix_stream *tmp; 1488 1489 list_for_each_entry(tmp, stream_list, list) 1490 if (ether_addr_equal(tmp->dmac, stream->dmac) && 1491 tmp->vid == stream->vid) 1492 return tmp; 1493 1494 return NULL; 1495 } 1496 1497 static int vsc9959_stream_table_add(struct ocelot *ocelot, 1498 struct list_head *stream_list, 1499 struct felix_stream *stream, 1500 struct netlink_ext_ack *extack) 1501 { 1502 struct felix_stream *stream_entry; 1503 int ret; 1504 1505 stream_entry = kmemdup(stream, sizeof(*stream_entry), GFP_KERNEL); 1506 if (!stream_entry) 1507 return -ENOMEM; 1508 1509 if (!stream->dummy) { 1510 ret = vsc9959_mact_stream_set(ocelot, stream_entry, extack); 1511 if (ret) { 1512 kfree(stream_entry); 1513 return ret; 1514 } 1515 } 1516 1517 list_add_tail(&stream_entry->list, stream_list); 1518 1519 return 0; 1520 } 1521 1522 static struct felix_stream * 1523 vsc9959_stream_table_get(struct list_head *stream_list, unsigned long id) 1524 { 1525 struct felix_stream *tmp; 1526 1527 list_for_each_entry(tmp, stream_list, list) 1528 if (tmp->id == id) 1529 return tmp; 1530 1531 return NULL; 1532 } 1533 1534 static void vsc9959_stream_table_del(struct ocelot *ocelot, 1535 struct felix_stream *stream) 1536 { 1537 if (!stream->dummy) 1538 vsc9959_mact_stream_set(ocelot, stream, NULL); 1539 1540 list_del(&stream->list); 1541 kfree(stream); 1542 } 1543 1544 static u32 vsc9959_sfi_access_status(struct ocelot *ocelot) 1545 { 1546 return ocelot_read(ocelot, ANA_TABLES_SFIDACCESS); 1547 } 1548 1549 static int vsc9959_psfp_sfi_set(struct ocelot *ocelot, 1550 struct felix_stream_filter *sfi) 1551 { 1552 u32 val; 1553 1554 if (sfi->index > VSC9959_PSFP_SFID_MAX) 1555 return -EINVAL; 1556 1557 if (!sfi->enable) { 1558 ocelot_write(ocelot, ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 1559 ANA_TABLES_SFIDTIDX); 1560 1561 val = ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE); 1562 ocelot_write(ocelot, val, ANA_TABLES_SFIDACCESS); 1563 1564 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1565 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1566 10, 100000); 1567 } 1568 1569 if (sfi->sgid > VSC9959_PSFP_GATE_ID_MAX || 1570 sfi->fmid > VSC9959_PSFP_POLICER_MAX) 1571 return -EINVAL; 1572 1573 ocelot_write(ocelot, 1574 (sfi->sg_valid ? ANA_TABLES_SFIDTIDX_SGID_VALID : 0) | 1575 ANA_TABLES_SFIDTIDX_SGID(sfi->sgid) | 1576 (sfi->fm_valid ? ANA_TABLES_SFIDTIDX_POL_ENA : 0) | 1577 ANA_TABLES_SFIDTIDX_POL_IDX(sfi->fmid) | 1578 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index), 1579 ANA_TABLES_SFIDTIDX); 1580 1581 ocelot_write(ocelot, 1582 (sfi->prio_valid ? ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA : 0) | 1583 ANA_TABLES_SFIDACCESS_IGR_PRIO(sfi->prio) | 1584 ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(sfi->maxsdu) | 1585 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 1586 ANA_TABLES_SFIDACCESS); 1587 1588 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1589 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1590 10, 100000); 1591 } 1592 1593 static int vsc9959_psfp_sfidmask_set(struct ocelot *ocelot, u32 sfid, int ports) 1594 { 1595 u32 val; 1596 1597 ocelot_rmw(ocelot, 1598 ANA_TABLES_SFIDTIDX_SFID_INDEX(sfid), 1599 ANA_TABLES_SFIDTIDX_SFID_INDEX_M, 1600 ANA_TABLES_SFIDTIDX); 1601 1602 ocelot_write(ocelot, 1603 ANA_TABLES_SFID_MASK_IGR_PORT_MASK(ports) | 1604 ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA, 1605 ANA_TABLES_SFID_MASK); 1606 1607 ocelot_rmw(ocelot, 1608 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE), 1609 ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M, 1610 ANA_TABLES_SFIDACCESS); 1611 1612 return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val, 1613 (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)), 1614 10, 100000); 1615 } 1616 1617 static int vsc9959_psfp_sfi_list_add(struct ocelot *ocelot, 1618 struct felix_stream_filter *sfi, 1619 struct list_head *pos) 1620 { 1621 struct felix_stream_filter *sfi_entry; 1622 int ret; 1623 1624 sfi_entry = kmemdup(sfi, sizeof(*sfi_entry), GFP_KERNEL); 1625 if (!sfi_entry) 1626 return -ENOMEM; 1627 1628 refcount_set(&sfi_entry->refcount, 1); 1629 1630 ret = vsc9959_psfp_sfi_set(ocelot, sfi_entry); 1631 if (ret) { 1632 kfree(sfi_entry); 1633 return ret; 1634 } 1635 1636 vsc9959_psfp_sfidmask_set(ocelot, sfi->index, sfi->portmask); 1637 1638 list_add(&sfi_entry->list, pos); 1639 1640 return 0; 1641 } 1642 1643 static int vsc9959_psfp_sfi_table_add(struct ocelot *ocelot, 1644 struct felix_stream_filter *sfi) 1645 { 1646 struct list_head *pos, *q, *last; 1647 struct felix_stream_filter *tmp; 1648 struct ocelot_psfp_list *psfp; 1649 u32 insert = 0; 1650 1651 psfp = &ocelot->psfp; 1652 last = &psfp->sfi_list; 1653 1654 list_for_each_safe(pos, q, &psfp->sfi_list) { 1655 tmp = list_entry(pos, struct felix_stream_filter, list); 1656 if (sfi->sg_valid == tmp->sg_valid && 1657 sfi->fm_valid == tmp->fm_valid && 1658 sfi->portmask == tmp->portmask && 1659 tmp->sgid == sfi->sgid && 1660 tmp->fmid == sfi->fmid) { 1661 sfi->index = tmp->index; 1662 refcount_inc(&tmp->refcount); 1663 return 0; 1664 } 1665 /* Make sure that the index is increasing in order. */ 1666 if (tmp->index == insert) { 1667 last = pos; 1668 insert++; 1669 } 1670 } 1671 sfi->index = insert; 1672 1673 return vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 1674 } 1675 1676 static int vsc9959_psfp_sfi_table_add2(struct ocelot *ocelot, 1677 struct felix_stream_filter *sfi, 1678 struct felix_stream_filter *sfi2) 1679 { 1680 struct felix_stream_filter *tmp; 1681 struct list_head *pos, *q, *last; 1682 struct ocelot_psfp_list *psfp; 1683 u32 insert = 0; 1684 int ret; 1685 1686 psfp = &ocelot->psfp; 1687 last = &psfp->sfi_list; 1688 1689 list_for_each_safe(pos, q, &psfp->sfi_list) { 1690 tmp = list_entry(pos, struct felix_stream_filter, list); 1691 /* Make sure that the index is increasing in order. */ 1692 if (tmp->index >= insert + 2) 1693 break; 1694 1695 insert = tmp->index + 1; 1696 last = pos; 1697 } 1698 sfi->index = insert; 1699 1700 ret = vsc9959_psfp_sfi_list_add(ocelot, sfi, last); 1701 if (ret) 1702 return ret; 1703 1704 sfi2->index = insert + 1; 1705 1706 return vsc9959_psfp_sfi_list_add(ocelot, sfi2, last->next); 1707 } 1708 1709 static struct felix_stream_filter * 1710 vsc9959_psfp_sfi_table_get(struct list_head *sfi_list, u32 index) 1711 { 1712 struct felix_stream_filter *tmp; 1713 1714 list_for_each_entry(tmp, sfi_list, list) 1715 if (tmp->index == index) 1716 return tmp; 1717 1718 return NULL; 1719 } 1720 1721 static void vsc9959_psfp_sfi_table_del(struct ocelot *ocelot, u32 index) 1722 { 1723 struct felix_stream_filter *tmp, *n; 1724 struct ocelot_psfp_list *psfp; 1725 u8 z; 1726 1727 psfp = &ocelot->psfp; 1728 1729 list_for_each_entry_safe(tmp, n, &psfp->sfi_list, list) 1730 if (tmp->index == index) { 1731 z = refcount_dec_and_test(&tmp->refcount); 1732 if (z) { 1733 tmp->enable = 0; 1734 vsc9959_psfp_sfi_set(ocelot, tmp); 1735 list_del(&tmp->list); 1736 kfree(tmp); 1737 } 1738 break; 1739 } 1740 } 1741 1742 static void vsc9959_psfp_parse_gate(const struct flow_action_entry *entry, 1743 struct felix_stream_gate *sgi) 1744 { 1745 sgi->index = entry->hw_index; 1746 sgi->ipv_valid = (entry->gate.prio < 0) ? 0 : 1; 1747 sgi->init_ipv = (sgi->ipv_valid) ? entry->gate.prio : 0; 1748 sgi->basetime = entry->gate.basetime; 1749 sgi->cycletime = entry->gate.cycletime; 1750 sgi->num_entries = entry->gate.num_entries; 1751 sgi->enable = 1; 1752 1753 memcpy(sgi->entries, entry->gate.entries, 1754 entry->gate.num_entries * sizeof(struct action_gate_entry)); 1755 } 1756 1757 static u32 vsc9959_sgi_cfg_status(struct ocelot *ocelot) 1758 { 1759 return ocelot_read(ocelot, ANA_SG_ACCESS_CTRL); 1760 } 1761 1762 static int vsc9959_psfp_sgi_set(struct ocelot *ocelot, 1763 struct felix_stream_gate *sgi) 1764 { 1765 struct action_gate_entry *e; 1766 struct timespec64 base_ts; 1767 u32 interval_sum = 0; 1768 u32 val; 1769 int i; 1770 1771 if (sgi->index > VSC9959_PSFP_GATE_ID_MAX) 1772 return -EINVAL; 1773 1774 ocelot_write(ocelot, ANA_SG_ACCESS_CTRL_SGID(sgi->index), 1775 ANA_SG_ACCESS_CTRL); 1776 1777 if (!sgi->enable) { 1778 ocelot_rmw(ocelot, ANA_SG_CONFIG_REG_3_INIT_GATE_STATE, 1779 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 1780 ANA_SG_CONFIG_REG_3_GATE_ENABLE, 1781 ANA_SG_CONFIG_REG_3); 1782 1783 return 0; 1784 } 1785 1786 if (sgi->cycletime < VSC9959_PSFP_GATE_CYCLETIME_MIN || 1787 sgi->cycletime > NSEC_PER_SEC) 1788 return -EINVAL; 1789 1790 if (sgi->num_entries > VSC9959_PSFP_GATE_LIST_NUM) 1791 return -EINVAL; 1792 1793 vsc9959_new_base_time(ocelot, sgi->basetime, sgi->cycletime, &base_ts); 1794 ocelot_write(ocelot, base_ts.tv_nsec, ANA_SG_CONFIG_REG_1); 1795 val = lower_32_bits(base_ts.tv_sec); 1796 ocelot_write(ocelot, val, ANA_SG_CONFIG_REG_2); 1797 1798 val = upper_32_bits(base_ts.tv_sec); 1799 ocelot_write(ocelot, 1800 (sgi->ipv_valid ? ANA_SG_CONFIG_REG_3_IPV_VALID : 0) | 1801 ANA_SG_CONFIG_REG_3_INIT_IPV(sgi->init_ipv) | 1802 ANA_SG_CONFIG_REG_3_GATE_ENABLE | 1803 ANA_SG_CONFIG_REG_3_LIST_LENGTH(sgi->num_entries) | 1804 ANA_SG_CONFIG_REG_3_INIT_GATE_STATE | 1805 ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(val), 1806 ANA_SG_CONFIG_REG_3); 1807 1808 ocelot_write(ocelot, sgi->cycletime, ANA_SG_CONFIG_REG_4); 1809 1810 e = sgi->entries; 1811 for (i = 0; i < sgi->num_entries; i++) { 1812 u32 ips = (e[i].ipv < 0) ? 0 : (e[i].ipv + 8); 1813 1814 ocelot_write_rix(ocelot, ANA_SG_GCL_GS_CONFIG_IPS(ips) | 1815 (e[i].gate_state ? 1816 ANA_SG_GCL_GS_CONFIG_GATE_STATE : 0), 1817 ANA_SG_GCL_GS_CONFIG, i); 1818 1819 interval_sum += e[i].interval; 1820 ocelot_write_rix(ocelot, interval_sum, ANA_SG_GCL_TI_CONFIG, i); 1821 } 1822 1823 ocelot_rmw(ocelot, ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 1824 ANA_SG_ACCESS_CTRL_CONFIG_CHANGE, 1825 ANA_SG_ACCESS_CTRL); 1826 1827 return readx_poll_timeout(vsc9959_sgi_cfg_status, ocelot, val, 1828 (!(ANA_SG_ACCESS_CTRL_CONFIG_CHANGE & val)), 1829 10, 100000); 1830 } 1831 1832 static int vsc9959_psfp_sgi_table_add(struct ocelot *ocelot, 1833 struct felix_stream_gate *sgi) 1834 { 1835 struct felix_stream_gate_entry *tmp; 1836 struct ocelot_psfp_list *psfp; 1837 int ret; 1838 1839 psfp = &ocelot->psfp; 1840 1841 list_for_each_entry(tmp, &psfp->sgi_list, list) 1842 if (tmp->index == sgi->index) { 1843 refcount_inc(&tmp->refcount); 1844 return 0; 1845 } 1846 1847 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL); 1848 if (!tmp) 1849 return -ENOMEM; 1850 1851 ret = vsc9959_psfp_sgi_set(ocelot, sgi); 1852 if (ret) { 1853 kfree(tmp); 1854 return ret; 1855 } 1856 1857 tmp->index = sgi->index; 1858 refcount_set(&tmp->refcount, 1); 1859 list_add_tail(&tmp->list, &psfp->sgi_list); 1860 1861 return 0; 1862 } 1863 1864 static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot, 1865 u32 index) 1866 { 1867 struct felix_stream_gate_entry *tmp, *n; 1868 struct felix_stream_gate sgi = {0}; 1869 struct ocelot_psfp_list *psfp; 1870 u8 z; 1871 1872 psfp = &ocelot->psfp; 1873 1874 list_for_each_entry_safe(tmp, n, &psfp->sgi_list, list) 1875 if (tmp->index == index) { 1876 z = refcount_dec_and_test(&tmp->refcount); 1877 if (z) { 1878 sgi.index = index; 1879 sgi.enable = 0; 1880 vsc9959_psfp_sgi_set(ocelot, &sgi); 1881 list_del(&tmp->list); 1882 kfree(tmp); 1883 } 1884 break; 1885 } 1886 } 1887 1888 static void vsc9959_psfp_counters_get(struct ocelot *ocelot, u32 index, 1889 struct felix_stream_filter_counters *counters) 1890 { 1891 ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(index), 1892 SYS_STAT_CFG_STAT_VIEW_M, 1893 SYS_STAT_CFG); 1894 1895 counters->match = ocelot_read_gix(ocelot, SYS_CNT, 0x200); 1896 counters->not_pass_gate = ocelot_read_gix(ocelot, SYS_CNT, 0x201); 1897 counters->not_pass_sdu = ocelot_read_gix(ocelot, SYS_CNT, 0x202); 1898 counters->red = ocelot_read_gix(ocelot, SYS_CNT, 0x203); 1899 1900 /* Clear the PSFP counter. */ 1901 ocelot_write(ocelot, 1902 SYS_STAT_CFG_STAT_VIEW(index) | 1903 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10), 1904 SYS_STAT_CFG); 1905 } 1906 1907 static int vsc9959_psfp_filter_add(struct ocelot *ocelot, int port, 1908 struct flow_cls_offload *f) 1909 { 1910 struct netlink_ext_ack *extack = f->common.extack; 1911 struct felix_stream_filter old_sfi, *sfi_entry; 1912 struct felix_stream_filter sfi = {0}; 1913 const struct flow_action_entry *a; 1914 struct felix_stream *stream_entry; 1915 struct felix_stream stream = {0}; 1916 struct felix_stream_gate *sgi; 1917 struct ocelot_psfp_list *psfp; 1918 struct ocelot_policer pol; 1919 int ret, i, size; 1920 u64 rate, burst; 1921 u32 index; 1922 1923 psfp = &ocelot->psfp; 1924 1925 ret = vsc9959_stream_identify(f, &stream); 1926 if (ret) { 1927 NL_SET_ERR_MSG_MOD(extack, "Only can match on VID, PCP, and dest MAC"); 1928 return ret; 1929 } 1930 1931 flow_action_for_each(i, a, &f->rule->action) { 1932 switch (a->id) { 1933 case FLOW_ACTION_GATE: 1934 size = struct_size(sgi, entries, a->gate.num_entries); 1935 sgi = kzalloc(size, GFP_KERNEL); 1936 vsc9959_psfp_parse_gate(a, sgi); 1937 ret = vsc9959_psfp_sgi_table_add(ocelot, sgi); 1938 if (ret) { 1939 kfree(sgi); 1940 goto err; 1941 } 1942 sfi.sg_valid = 1; 1943 sfi.sgid = sgi->index; 1944 kfree(sgi); 1945 break; 1946 case FLOW_ACTION_POLICE: 1947 index = a->hw_index + VSC9959_PSFP_POLICER_BASE; 1948 if (index > VSC9959_PSFP_POLICER_MAX) { 1949 ret = -EINVAL; 1950 goto err; 1951 } 1952 1953 rate = a->police.rate_bytes_ps; 1954 burst = rate * PSCHED_NS2TICKS(a->police.burst); 1955 pol = (struct ocelot_policer) { 1956 .burst = div_u64(burst, PSCHED_TICKS_PER_SEC), 1957 .rate = div_u64(rate, 1000) * 8, 1958 }; 1959 ret = ocelot_vcap_policer_add(ocelot, index, &pol); 1960 if (ret) 1961 goto err; 1962 1963 sfi.fm_valid = 1; 1964 sfi.fmid = index; 1965 sfi.maxsdu = a->police.mtu; 1966 break; 1967 default: 1968 return -EOPNOTSUPP; 1969 } 1970 } 1971 1972 stream.ports = BIT(port); 1973 stream.port = port; 1974 1975 sfi.portmask = stream.ports; 1976 sfi.prio_valid = (stream.prio < 0 ? 0 : 1); 1977 sfi.prio = (sfi.prio_valid ? stream.prio : 0); 1978 sfi.enable = 1; 1979 1980 /* Check if stream is set. */ 1981 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &stream); 1982 if (stream_entry) { 1983 if (stream_entry->ports & BIT(port)) { 1984 NL_SET_ERR_MSG_MOD(extack, 1985 "The stream is added on this port"); 1986 ret = -EEXIST; 1987 goto err; 1988 } 1989 1990 if (stream_entry->ports != BIT(stream_entry->port)) { 1991 NL_SET_ERR_MSG_MOD(extack, 1992 "The stream is added on two ports"); 1993 ret = -EEXIST; 1994 goto err; 1995 } 1996 1997 stream_entry->ports |= BIT(port); 1998 stream.ports = stream_entry->ports; 1999 2000 sfi_entry = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, 2001 stream_entry->sfid); 2002 memcpy(&old_sfi, sfi_entry, sizeof(old_sfi)); 2003 2004 vsc9959_psfp_sfi_table_del(ocelot, stream_entry->sfid); 2005 2006 old_sfi.portmask = stream_entry->ports; 2007 sfi.portmask = stream.ports; 2008 2009 if (stream_entry->port > port) { 2010 ret = vsc9959_psfp_sfi_table_add2(ocelot, &sfi, 2011 &old_sfi); 2012 stream_entry->dummy = true; 2013 } else { 2014 ret = vsc9959_psfp_sfi_table_add2(ocelot, &old_sfi, 2015 &sfi); 2016 stream.dummy = true; 2017 } 2018 if (ret) 2019 goto err; 2020 2021 stream_entry->sfid = old_sfi.index; 2022 } else { 2023 ret = vsc9959_psfp_sfi_table_add(ocelot, &sfi); 2024 if (ret) 2025 goto err; 2026 } 2027 2028 stream.sfid = sfi.index; 2029 stream.sfid_valid = 1; 2030 ret = vsc9959_stream_table_add(ocelot, &psfp->stream_list, 2031 &stream, extack); 2032 if (ret) { 2033 vsc9959_psfp_sfi_table_del(ocelot, stream.sfid); 2034 goto err; 2035 } 2036 2037 return 0; 2038 2039 err: 2040 if (sfi.sg_valid) 2041 vsc9959_psfp_sgi_table_del(ocelot, sfi.sgid); 2042 2043 if (sfi.fm_valid) 2044 ocelot_vcap_policer_del(ocelot, sfi.fmid); 2045 2046 return ret; 2047 } 2048 2049 static int vsc9959_psfp_filter_del(struct ocelot *ocelot, 2050 struct flow_cls_offload *f) 2051 { 2052 struct felix_stream *stream, tmp, *stream_entry; 2053 static struct felix_stream_filter *sfi; 2054 struct ocelot_psfp_list *psfp; 2055 2056 psfp = &ocelot->psfp; 2057 2058 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 2059 if (!stream) 2060 return -ENOMEM; 2061 2062 sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid); 2063 if (!sfi) 2064 return -ENOMEM; 2065 2066 if (sfi->sg_valid) 2067 vsc9959_psfp_sgi_table_del(ocelot, sfi->sgid); 2068 2069 if (sfi->fm_valid) 2070 ocelot_vcap_policer_del(ocelot, sfi->fmid); 2071 2072 vsc9959_psfp_sfi_table_del(ocelot, stream->sfid); 2073 2074 memcpy(&tmp, stream, sizeof(tmp)); 2075 2076 stream->sfid_valid = 0; 2077 vsc9959_stream_table_del(ocelot, stream); 2078 2079 stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &tmp); 2080 if (stream_entry) { 2081 stream_entry->ports = BIT(stream_entry->port); 2082 if (stream_entry->dummy) { 2083 stream_entry->dummy = false; 2084 vsc9959_mact_stream_set(ocelot, stream_entry, NULL); 2085 } 2086 vsc9959_psfp_sfidmask_set(ocelot, stream_entry->sfid, 2087 stream_entry->ports); 2088 } 2089 2090 return 0; 2091 } 2092 2093 static int vsc9959_psfp_stats_get(struct ocelot *ocelot, 2094 struct flow_cls_offload *f, 2095 struct flow_stats *stats) 2096 { 2097 struct felix_stream_filter_counters counters; 2098 struct ocelot_psfp_list *psfp; 2099 struct felix_stream *stream; 2100 2101 psfp = &ocelot->psfp; 2102 stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie); 2103 if (!stream) 2104 return -ENOMEM; 2105 2106 vsc9959_psfp_counters_get(ocelot, stream->sfid, &counters); 2107 2108 stats->pkts = counters.match; 2109 stats->drops = counters.not_pass_gate + counters.not_pass_sdu + 2110 counters.red; 2111 2112 return 0; 2113 } 2114 2115 static void vsc9959_psfp_init(struct ocelot *ocelot) 2116 { 2117 struct ocelot_psfp_list *psfp = &ocelot->psfp; 2118 2119 INIT_LIST_HEAD(&psfp->stream_list); 2120 INIT_LIST_HEAD(&psfp->sfi_list); 2121 INIT_LIST_HEAD(&psfp->sgi_list); 2122 } 2123 2124 /* When using cut-through forwarding and the egress port runs at a higher data 2125 * rate than the ingress port, the packet currently under transmission would 2126 * suffer an underrun since it would be transmitted faster than it is received. 2127 * The Felix switch implementation of cut-through forwarding does not check in 2128 * hardware whether this condition is satisfied or not, so we must restrict the 2129 * list of ports that have cut-through forwarding enabled on egress to only be 2130 * the ports operating at the lowest link speed within their respective 2131 * forwarding domain. 2132 */ 2133 static void vsc9959_cut_through_fwd(struct ocelot *ocelot) 2134 { 2135 struct felix *felix = ocelot_to_felix(ocelot); 2136 struct dsa_switch *ds = felix->ds; 2137 int port, other_port; 2138 2139 lockdep_assert_held(&ocelot->fwd_domain_lock); 2140 2141 for (port = 0; port < ocelot->num_phys_ports; port++) { 2142 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2143 int min_speed = ocelot_port->speed; 2144 unsigned long mask = 0; 2145 u32 tmp, val = 0; 2146 2147 /* Disable cut-through on ports that are down */ 2148 if (ocelot_port->speed <= 0) 2149 goto set; 2150 2151 if (dsa_is_cpu_port(ds, port)) { 2152 /* Ocelot switches forward from the NPI port towards 2153 * any port, regardless of it being in the NPI port's 2154 * forwarding domain or not. 2155 */ 2156 mask = dsa_user_ports(ds); 2157 } else { 2158 mask = ocelot_get_bridge_fwd_mask(ocelot, port); 2159 mask &= ~BIT(port); 2160 if (ocelot->npi >= 0) 2161 mask |= BIT(ocelot->npi); 2162 else 2163 mask |= ocelot_get_dsa_8021q_cpu_mask(ocelot); 2164 } 2165 2166 /* Calculate the minimum link speed, among the ports that are 2167 * up, of this source port's forwarding domain. 2168 */ 2169 for_each_set_bit(other_port, &mask, ocelot->num_phys_ports) { 2170 struct ocelot_port *other_ocelot_port; 2171 2172 other_ocelot_port = ocelot->ports[other_port]; 2173 if (other_ocelot_port->speed <= 0) 2174 continue; 2175 2176 if (min_speed > other_ocelot_port->speed) 2177 min_speed = other_ocelot_port->speed; 2178 } 2179 2180 /* Enable cut-through forwarding for all traffic classes. */ 2181 if (ocelot_port->speed == min_speed) 2182 val = GENMASK(7, 0); 2183 2184 set: 2185 tmp = ocelot_read_rix(ocelot, ANA_CUT_THRU_CFG, port); 2186 if (tmp == val) 2187 continue; 2188 2189 dev_dbg(ocelot->dev, 2190 "port %d fwd mask 0x%lx speed %d min_speed %d, %s cut-through forwarding\n", 2191 port, mask, ocelot_port->speed, min_speed, 2192 val ? "enabling" : "disabling"); 2193 2194 ocelot_write_rix(ocelot, val, ANA_CUT_THRU_CFG, port); 2195 } 2196 } 2197 2198 static const struct ocelot_ops vsc9959_ops = { 2199 .reset = vsc9959_reset, 2200 .wm_enc = vsc9959_wm_enc, 2201 .wm_dec = vsc9959_wm_dec, 2202 .wm_stat = vsc9959_wm_stat, 2203 .port_to_netdev = felix_port_to_netdev, 2204 .netdev_to_port = felix_netdev_to_port, 2205 .psfp_init = vsc9959_psfp_init, 2206 .psfp_filter_add = vsc9959_psfp_filter_add, 2207 .psfp_filter_del = vsc9959_psfp_filter_del, 2208 .psfp_stats_get = vsc9959_psfp_stats_get, 2209 .cut_through_fwd = vsc9959_cut_through_fwd, 2210 }; 2211 2212 static const struct felix_info felix_info_vsc9959 = { 2213 .target_io_res = vsc9959_target_io_res, 2214 .port_io_res = vsc9959_port_io_res, 2215 .imdio_res = &vsc9959_imdio_res, 2216 .regfields = vsc9959_regfields, 2217 .map = vsc9959_regmap, 2218 .ops = &vsc9959_ops, 2219 .stats_layout = vsc9959_stats_layout, 2220 .num_stats = ARRAY_SIZE(vsc9959_stats_layout), 2221 .vcap = vsc9959_vcap_props, 2222 .vcap_pol_base = VSC9959_VCAP_POLICER_BASE, 2223 .vcap_pol_max = VSC9959_VCAP_POLICER_MAX, 2224 .vcap_pol_base2 = 0, 2225 .vcap_pol_max2 = 0, 2226 .num_mact_rows = 2048, 2227 .num_ports = 6, 2228 .num_tx_queues = OCELOT_NUM_TC, 2229 .quirk_no_xtr_irq = true, 2230 .ptp_caps = &vsc9959_ptp_caps, 2231 .mdio_bus_alloc = vsc9959_mdio_bus_alloc, 2232 .mdio_bus_free = vsc9959_mdio_bus_free, 2233 .phylink_validate = vsc9959_phylink_validate, 2234 .prevalidate_phy_mode = vsc9959_prevalidate_phy_mode, 2235 .port_setup_tc = vsc9959_port_setup_tc, 2236 .port_sched_speed_set = vsc9959_sched_speed_set, 2237 .init_regmap = ocelot_regmap_init, 2238 }; 2239 2240 static irqreturn_t felix_irq_handler(int irq, void *data) 2241 { 2242 struct ocelot *ocelot = (struct ocelot *)data; 2243 2244 /* The INTB interrupt is used for both PTP TX timestamp interrupt 2245 * and preemption status change interrupt on each port. 2246 * 2247 * - Get txtstamp if have 2248 * - TODO: handle preemption. Without handling it, driver may get 2249 * interrupt storm. 2250 */ 2251 2252 ocelot_get_txtstamp(ocelot); 2253 2254 return IRQ_HANDLED; 2255 } 2256 2257 static int felix_pci_probe(struct pci_dev *pdev, 2258 const struct pci_device_id *id) 2259 { 2260 struct dsa_switch *ds; 2261 struct ocelot *ocelot; 2262 struct felix *felix; 2263 int err; 2264 2265 if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) { 2266 dev_info(&pdev->dev, "device is disabled, skipping\n"); 2267 return -ENODEV; 2268 } 2269 2270 err = pci_enable_device(pdev); 2271 if (err) { 2272 dev_err(&pdev->dev, "device enable failed\n"); 2273 goto err_pci_enable; 2274 } 2275 2276 felix = kzalloc(sizeof(struct felix), GFP_KERNEL); 2277 if (!felix) { 2278 err = -ENOMEM; 2279 dev_err(&pdev->dev, "Failed to allocate driver memory\n"); 2280 goto err_alloc_felix; 2281 } 2282 2283 pci_set_drvdata(pdev, felix); 2284 ocelot = &felix->ocelot; 2285 ocelot->dev = &pdev->dev; 2286 ocelot->num_flooding_pgids = OCELOT_NUM_TC; 2287 felix->info = &felix_info_vsc9959; 2288 felix->switch_base = pci_resource_start(pdev, VSC9959_SWITCH_PCI_BAR); 2289 felix->imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR); 2290 2291 pci_set_master(pdev); 2292 2293 err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL, 2294 &felix_irq_handler, IRQF_ONESHOT, 2295 "felix-intb", ocelot); 2296 if (err) { 2297 dev_err(&pdev->dev, "Failed to request irq\n"); 2298 goto err_alloc_irq; 2299 } 2300 2301 ocelot->ptp = 1; 2302 2303 ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL); 2304 if (!ds) { 2305 err = -ENOMEM; 2306 dev_err(&pdev->dev, "Failed to allocate DSA switch\n"); 2307 goto err_alloc_ds; 2308 } 2309 2310 ds->dev = &pdev->dev; 2311 ds->num_ports = felix->info->num_ports; 2312 ds->num_tx_queues = felix->info->num_tx_queues; 2313 ds->ops = &felix_switch_ops; 2314 ds->priv = ocelot; 2315 felix->ds = ds; 2316 felix->tag_proto = DSA_TAG_PROTO_OCELOT; 2317 2318 err = dsa_register_switch(ds); 2319 if (err) { 2320 dev_err(&pdev->dev, "Failed to register DSA switch: %d\n", err); 2321 goto err_register_ds; 2322 } 2323 2324 return 0; 2325 2326 err_register_ds: 2327 kfree(ds); 2328 err_alloc_ds: 2329 err_alloc_irq: 2330 kfree(felix); 2331 err_alloc_felix: 2332 pci_disable_device(pdev); 2333 err_pci_enable: 2334 return err; 2335 } 2336 2337 static void felix_pci_remove(struct pci_dev *pdev) 2338 { 2339 struct felix *felix = pci_get_drvdata(pdev); 2340 2341 if (!felix) 2342 return; 2343 2344 dsa_unregister_switch(felix->ds); 2345 2346 kfree(felix->ds); 2347 kfree(felix); 2348 2349 pci_disable_device(pdev); 2350 2351 pci_set_drvdata(pdev, NULL); 2352 } 2353 2354 static void felix_pci_shutdown(struct pci_dev *pdev) 2355 { 2356 struct felix *felix = pci_get_drvdata(pdev); 2357 2358 if (!felix) 2359 return; 2360 2361 dsa_switch_shutdown(felix->ds); 2362 2363 pci_set_drvdata(pdev, NULL); 2364 } 2365 2366 static struct pci_device_id felix_ids[] = { 2367 { 2368 /* NXP LS1028A */ 2369 PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0), 2370 }, 2371 { 0, } 2372 }; 2373 MODULE_DEVICE_TABLE(pci, felix_ids); 2374 2375 static struct pci_driver felix_vsc9959_pci_driver = { 2376 .name = "mscc_felix", 2377 .id_table = felix_ids, 2378 .probe = felix_pci_probe, 2379 .remove = felix_pci_remove, 2380 .shutdown = felix_pci_shutdown, 2381 }; 2382 module_pci_driver(felix_vsc9959_pci_driver); 2383 2384 MODULE_DESCRIPTION("Felix Switch driver"); 2385 MODULE_LICENSE("GPL v2"); 2386