xref: /linux/drivers/net/dsa/ocelot/felix_vsc9959.c (revision 00389c58ffe993782a8ba4bb5a34a102b1f6fe24) 
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright 2017 Microsemi Corporation
3  * Copyright 2018-2019 NXP
4  */
5 #include <linux/fsl/enetc_mdio.h>
6 #include <soc/mscc/ocelot_qsys.h>
7 #include <soc/mscc/ocelot_vcap.h>
8 #include <soc/mscc/ocelot_ana.h>
9 #include <soc/mscc/ocelot_ptp.h>
10 #include <soc/mscc/ocelot_sys.h>
11 #include <net/tc_act/tc_gate.h>
12 #include <soc/mscc/ocelot.h>
13 #include <linux/dsa/ocelot.h>
14 #include <linux/pcs-lynx.h>
15 #include <net/pkt_sched.h>
16 #include <linux/iopoll.h>
17 #include <linux/mdio.h>
18 #include <linux/pci.h>
19 #include "felix.h"
20 
21 #define VSC9959_NUM_PORTS		6
22 
23 #define VSC9959_TAS_GCL_ENTRY_MAX	63
24 #define VSC9959_VCAP_POLICER_BASE	63
25 #define VSC9959_VCAP_POLICER_MAX	383
26 #define VSC9959_SWITCH_PCI_BAR		4
27 #define VSC9959_IMDIO_PCI_BAR		0
28 
29 #define VSC9959_PORT_MODE_SERDES	(OCELOT_PORT_MODE_SGMII | \
30 					 OCELOT_PORT_MODE_QSGMII | \
31 					 OCELOT_PORT_MODE_2500BASEX | \
32 					 OCELOT_PORT_MODE_USXGMII)
33 
34 static const u32 vsc9959_port_modes[VSC9959_NUM_PORTS] = {
35 	VSC9959_PORT_MODE_SERDES,
36 	VSC9959_PORT_MODE_SERDES,
37 	VSC9959_PORT_MODE_SERDES,
38 	VSC9959_PORT_MODE_SERDES,
39 	OCELOT_PORT_MODE_INTERNAL,
40 };
41 
42 static const u32 vsc9959_ana_regmap[] = {
43 	REG(ANA_ADVLEARN,			0x0089a0),
44 	REG(ANA_VLANMASK,			0x0089a4),
45 	REG_RESERVED(ANA_PORT_B_DOMAIN),
46 	REG(ANA_ANAGEFIL,			0x0089ac),
47 	REG(ANA_ANEVENTS,			0x0089b0),
48 	REG(ANA_STORMLIMIT_BURST,		0x0089b4),
49 	REG(ANA_STORMLIMIT_CFG,			0x0089b8),
50 	REG(ANA_ISOLATED_PORTS,			0x0089c8),
51 	REG(ANA_COMMUNITY_PORTS,		0x0089cc),
52 	REG(ANA_AUTOAGE,			0x0089d0),
53 	REG(ANA_MACTOPTIONS,			0x0089d4),
54 	REG(ANA_LEARNDISC,			0x0089d8),
55 	REG(ANA_AGENCTRL,			0x0089dc),
56 	REG(ANA_MIRRORPORTS,			0x0089e0),
57 	REG(ANA_EMIRRORPORTS,			0x0089e4),
58 	REG(ANA_FLOODING,			0x0089e8),
59 	REG(ANA_FLOODING_IPMC,			0x008a08),
60 	REG(ANA_SFLOW_CFG,			0x008a0c),
61 	REG(ANA_PORT_MODE,			0x008a28),
62 	REG(ANA_CUT_THRU_CFG,			0x008a48),
63 	REG(ANA_PGID_PGID,			0x008400),
64 	REG(ANA_TABLES_ANMOVED,			0x007f1c),
65 	REG(ANA_TABLES_MACHDATA,		0x007f20),
66 	REG(ANA_TABLES_MACLDATA,		0x007f24),
67 	REG(ANA_TABLES_STREAMDATA,		0x007f28),
68 	REG(ANA_TABLES_MACACCESS,		0x007f2c),
69 	REG(ANA_TABLES_MACTINDX,		0x007f30),
70 	REG(ANA_TABLES_VLANACCESS,		0x007f34),
71 	REG(ANA_TABLES_VLANTIDX,		0x007f38),
72 	REG(ANA_TABLES_ISDXACCESS,		0x007f3c),
73 	REG(ANA_TABLES_ISDXTIDX,		0x007f40),
74 	REG(ANA_TABLES_ENTRYLIM,		0x007f00),
75 	REG(ANA_TABLES_PTP_ID_HIGH,		0x007f44),
76 	REG(ANA_TABLES_PTP_ID_LOW,		0x007f48),
77 	REG(ANA_TABLES_STREAMACCESS,		0x007f4c),
78 	REG(ANA_TABLES_STREAMTIDX,		0x007f50),
79 	REG(ANA_TABLES_SEQ_HISTORY,		0x007f54),
80 	REG(ANA_TABLES_SEQ_MASK,		0x007f58),
81 	REG(ANA_TABLES_SFID_MASK,		0x007f5c),
82 	REG(ANA_TABLES_SFIDACCESS,		0x007f60),
83 	REG(ANA_TABLES_SFIDTIDX,		0x007f64),
84 	REG(ANA_MSTI_STATE,			0x008600),
85 	REG(ANA_OAM_UPM_LM_CNT,			0x008000),
86 	REG(ANA_SG_ACCESS_CTRL,			0x008a64),
87 	REG(ANA_SG_CONFIG_REG_1,		0x007fb0),
88 	REG(ANA_SG_CONFIG_REG_2,		0x007fb4),
89 	REG(ANA_SG_CONFIG_REG_3,		0x007fb8),
90 	REG(ANA_SG_CONFIG_REG_4,		0x007fbc),
91 	REG(ANA_SG_CONFIG_REG_5,		0x007fc0),
92 	REG(ANA_SG_GCL_GS_CONFIG,		0x007f80),
93 	REG(ANA_SG_GCL_TI_CONFIG,		0x007f90),
94 	REG(ANA_SG_STATUS_REG_1,		0x008980),
95 	REG(ANA_SG_STATUS_REG_2,		0x008984),
96 	REG(ANA_SG_STATUS_REG_3,		0x008988),
97 	REG(ANA_PORT_VLAN_CFG,			0x007800),
98 	REG(ANA_PORT_DROP_CFG,			0x007804),
99 	REG(ANA_PORT_QOS_CFG,			0x007808),
100 	REG(ANA_PORT_VCAP_CFG,			0x00780c),
101 	REG(ANA_PORT_VCAP_S1_KEY_CFG,		0x007810),
102 	REG(ANA_PORT_VCAP_S2_CFG,		0x00781c),
103 	REG(ANA_PORT_PCP_DEI_MAP,		0x007820),
104 	REG(ANA_PORT_CPU_FWD_CFG,		0x007860),
105 	REG(ANA_PORT_CPU_FWD_BPDU_CFG,		0x007864),
106 	REG(ANA_PORT_CPU_FWD_GARP_CFG,		0x007868),
107 	REG(ANA_PORT_CPU_FWD_CCM_CFG,		0x00786c),
108 	REG(ANA_PORT_PORT_CFG,			0x007870),
109 	REG(ANA_PORT_POL_CFG,			0x007874),
110 	REG(ANA_PORT_PTP_CFG,			0x007878),
111 	REG(ANA_PORT_PTP_DLY1_CFG,		0x00787c),
112 	REG(ANA_PORT_PTP_DLY2_CFG,		0x007880),
113 	REG(ANA_PORT_SFID_CFG,			0x007884),
114 	REG(ANA_PFC_PFC_CFG,			0x008800),
115 	REG_RESERVED(ANA_PFC_PFC_TIMER),
116 	REG_RESERVED(ANA_IPT_OAM_MEP_CFG),
117 	REG_RESERVED(ANA_IPT_IPT),
118 	REG_RESERVED(ANA_PPT_PPT),
119 	REG_RESERVED(ANA_FID_MAP_FID_MAP),
120 	REG(ANA_AGGR_CFG,			0x008a68),
121 	REG(ANA_CPUQ_CFG,			0x008a6c),
122 	REG_RESERVED(ANA_CPUQ_CFG2),
123 	REG(ANA_CPUQ_8021_CFG,			0x008a74),
124 	REG(ANA_DSCP_CFG,			0x008ab4),
125 	REG(ANA_DSCP_REWR_CFG,			0x008bb4),
126 	REG(ANA_VCAP_RNG_TYPE_CFG,		0x008bf4),
127 	REG(ANA_VCAP_RNG_VAL_CFG,		0x008c14),
128 	REG_RESERVED(ANA_VRAP_CFG),
129 	REG_RESERVED(ANA_VRAP_HDR_DATA),
130 	REG_RESERVED(ANA_VRAP_HDR_MASK),
131 	REG(ANA_DISCARD_CFG,			0x008c40),
132 	REG(ANA_FID_CFG,			0x008c44),
133 	REG(ANA_POL_PIR_CFG,			0x004000),
134 	REG(ANA_POL_CIR_CFG,			0x004004),
135 	REG(ANA_POL_MODE_CFG,			0x004008),
136 	REG(ANA_POL_PIR_STATE,			0x00400c),
137 	REG(ANA_POL_CIR_STATE,			0x004010),
138 	REG_RESERVED(ANA_POL_STATE),
139 	REG(ANA_POL_FLOWC,			0x008c48),
140 	REG(ANA_POL_HYST,			0x008cb4),
141 	REG_RESERVED(ANA_POL_MISC_CFG),
142 };
143 
144 static const u32 vsc9959_qs_regmap[] = {
145 	REG(QS_XTR_GRP_CFG,			0x000000),
146 	REG(QS_XTR_RD,				0x000008),
147 	REG(QS_XTR_FRM_PRUNING,			0x000010),
148 	REG(QS_XTR_FLUSH,			0x000018),
149 	REG(QS_XTR_DATA_PRESENT,		0x00001c),
150 	REG(QS_XTR_CFG,				0x000020),
151 	REG(QS_INJ_GRP_CFG,			0x000024),
152 	REG(QS_INJ_WR,				0x00002c),
153 	REG(QS_INJ_CTRL,			0x000034),
154 	REG(QS_INJ_STATUS,			0x00003c),
155 	REG(QS_INJ_ERR,				0x000040),
156 	REG_RESERVED(QS_INH_DBG),
157 };
158 
159 static const u32 vsc9959_vcap_regmap[] = {
160 	/* VCAP_CORE_CFG */
161 	REG(VCAP_CORE_UPDATE_CTRL,		0x000000),
162 	REG(VCAP_CORE_MV_CFG,			0x000004),
163 	/* VCAP_CORE_CACHE */
164 	REG(VCAP_CACHE_ENTRY_DAT,		0x000008),
165 	REG(VCAP_CACHE_MASK_DAT,		0x000108),
166 	REG(VCAP_CACHE_ACTION_DAT,		0x000208),
167 	REG(VCAP_CACHE_CNT_DAT,			0x000308),
168 	REG(VCAP_CACHE_TG_DAT,			0x000388),
169 	/* VCAP_CONST */
170 	REG(VCAP_CONST_VCAP_VER,		0x000398),
171 	REG(VCAP_CONST_ENTRY_WIDTH,		0x00039c),
172 	REG(VCAP_CONST_ENTRY_CNT,		0x0003a0),
173 	REG(VCAP_CONST_ENTRY_SWCNT,		0x0003a4),
174 	REG(VCAP_CONST_ENTRY_TG_WIDTH,		0x0003a8),
175 	REG(VCAP_CONST_ACTION_DEF_CNT,		0x0003ac),
176 	REG(VCAP_CONST_ACTION_WIDTH,		0x0003b0),
177 	REG(VCAP_CONST_CNT_WIDTH,		0x0003b4),
178 	REG(VCAP_CONST_CORE_CNT,		0x0003b8),
179 	REG(VCAP_CONST_IF_CNT,			0x0003bc),
180 };
181 
182 static const u32 vsc9959_qsys_regmap[] = {
183 	REG(QSYS_PORT_MODE,			0x00f460),
184 	REG(QSYS_SWITCH_PORT_MODE,		0x00f480),
185 	REG(QSYS_STAT_CNT_CFG,			0x00f49c),
186 	REG(QSYS_EEE_CFG,			0x00f4a0),
187 	REG(QSYS_EEE_THRES,			0x00f4b8),
188 	REG(QSYS_IGR_NO_SHARING,		0x00f4bc),
189 	REG(QSYS_EGR_NO_SHARING,		0x00f4c0),
190 	REG(QSYS_SW_STATUS,			0x00f4c4),
191 	REG(QSYS_EXT_CPU_CFG,			0x00f4e0),
192 	REG_RESERVED(QSYS_PAD_CFG),
193 	REG(QSYS_CPU_GROUP_MAP,			0x00f4e8),
194 	REG_RESERVED(QSYS_QMAP),
195 	REG_RESERVED(QSYS_ISDX_SGRP),
196 	REG_RESERVED(QSYS_TIMED_FRAME_ENTRY),
197 	REG(QSYS_TFRM_MISC,			0x00f50c),
198 	REG(QSYS_TFRM_PORT_DLY,			0x00f510),
199 	REG(QSYS_TFRM_TIMER_CFG_1,		0x00f514),
200 	REG(QSYS_TFRM_TIMER_CFG_2,		0x00f518),
201 	REG(QSYS_TFRM_TIMER_CFG_3,		0x00f51c),
202 	REG(QSYS_TFRM_TIMER_CFG_4,		0x00f520),
203 	REG(QSYS_TFRM_TIMER_CFG_5,		0x00f524),
204 	REG(QSYS_TFRM_TIMER_CFG_6,		0x00f528),
205 	REG(QSYS_TFRM_TIMER_CFG_7,		0x00f52c),
206 	REG(QSYS_TFRM_TIMER_CFG_8,		0x00f530),
207 	REG(QSYS_RED_PROFILE,			0x00f534),
208 	REG(QSYS_RES_QOS_MODE,			0x00f574),
209 	REG(QSYS_RES_CFG,			0x00c000),
210 	REG(QSYS_RES_STAT,			0x00c004),
211 	REG(QSYS_EGR_DROP_MODE,			0x00f578),
212 	REG(QSYS_EQ_CTRL,			0x00f57c),
213 	REG_RESERVED(QSYS_EVENTS_CORE),
214 	REG(QSYS_QMAXSDU_CFG_0,			0x00f584),
215 	REG(QSYS_QMAXSDU_CFG_1,			0x00f5a0),
216 	REG(QSYS_QMAXSDU_CFG_2,			0x00f5bc),
217 	REG(QSYS_QMAXSDU_CFG_3,			0x00f5d8),
218 	REG(QSYS_QMAXSDU_CFG_4,			0x00f5f4),
219 	REG(QSYS_QMAXSDU_CFG_5,			0x00f610),
220 	REG(QSYS_QMAXSDU_CFG_6,			0x00f62c),
221 	REG(QSYS_QMAXSDU_CFG_7,			0x00f648),
222 	REG(QSYS_PREEMPTION_CFG,		0x00f664),
223 	REG(QSYS_CIR_CFG,			0x000000),
224 	REG(QSYS_EIR_CFG,			0x000004),
225 	REG(QSYS_SE_CFG,			0x000008),
226 	REG(QSYS_SE_DWRR_CFG,			0x00000c),
227 	REG_RESERVED(QSYS_SE_CONNECT),
228 	REG(QSYS_SE_DLB_SENSE,			0x000040),
229 	REG(QSYS_CIR_STATE,			0x000044),
230 	REG(QSYS_EIR_STATE,			0x000048),
231 	REG_RESERVED(QSYS_SE_STATE),
232 	REG(QSYS_HSCH_MISC_CFG,			0x00f67c),
233 	REG(QSYS_TAG_CONFIG,			0x00f680),
234 	REG(QSYS_TAS_PARAM_CFG_CTRL,		0x00f698),
235 	REG(QSYS_PORT_MAX_SDU,			0x00f69c),
236 	REG(QSYS_PARAM_CFG_REG_1,		0x00f440),
237 	REG(QSYS_PARAM_CFG_REG_2,		0x00f444),
238 	REG(QSYS_PARAM_CFG_REG_3,		0x00f448),
239 	REG(QSYS_PARAM_CFG_REG_4,		0x00f44c),
240 	REG(QSYS_PARAM_CFG_REG_5,		0x00f450),
241 	REG(QSYS_GCL_CFG_REG_1,			0x00f454),
242 	REG(QSYS_GCL_CFG_REG_2,			0x00f458),
243 	REG(QSYS_PARAM_STATUS_REG_1,		0x00f400),
244 	REG(QSYS_PARAM_STATUS_REG_2,		0x00f404),
245 	REG(QSYS_PARAM_STATUS_REG_3,		0x00f408),
246 	REG(QSYS_PARAM_STATUS_REG_4,		0x00f40c),
247 	REG(QSYS_PARAM_STATUS_REG_5,		0x00f410),
248 	REG(QSYS_PARAM_STATUS_REG_6,		0x00f414),
249 	REG(QSYS_PARAM_STATUS_REG_7,		0x00f418),
250 	REG(QSYS_PARAM_STATUS_REG_8,		0x00f41c),
251 	REG(QSYS_PARAM_STATUS_REG_9,		0x00f420),
252 	REG(QSYS_GCL_STATUS_REG_1,		0x00f424),
253 	REG(QSYS_GCL_STATUS_REG_2,		0x00f428),
254 };
255 
256 static const u32 vsc9959_rew_regmap[] = {
257 	REG(REW_PORT_VLAN_CFG,			0x000000),
258 	REG(REW_TAG_CFG,			0x000004),
259 	REG(REW_PORT_CFG,			0x000008),
260 	REG(REW_DSCP_CFG,			0x00000c),
261 	REG(REW_PCP_DEI_QOS_MAP_CFG,		0x000010),
262 	REG(REW_PTP_CFG,			0x000050),
263 	REG(REW_PTP_DLY1_CFG,			0x000054),
264 	REG(REW_RED_TAG_CFG,			0x000058),
265 	REG(REW_DSCP_REMAP_DP1_CFG,		0x000410),
266 	REG(REW_DSCP_REMAP_CFG,			0x000510),
267 	REG_RESERVED(REW_STAT_CFG),
268 	REG_RESERVED(REW_REW_STICKY),
269 	REG_RESERVED(REW_PPT),
270 };
271 
272 static const u32 vsc9959_sys_regmap[] = {
273 	REG(SYS_COUNT_RX_OCTETS,		0x000000),
274 	REG(SYS_COUNT_RX_MULTICAST,		0x000008),
275 	REG(SYS_COUNT_RX_SHORTS,		0x000010),
276 	REG(SYS_COUNT_RX_FRAGMENTS,		0x000014),
277 	REG(SYS_COUNT_RX_JABBERS,		0x000018),
278 	REG(SYS_COUNT_RX_64,			0x000024),
279 	REG(SYS_COUNT_RX_65_127,		0x000028),
280 	REG(SYS_COUNT_RX_128_255,		0x00002c),
281 	REG(SYS_COUNT_RX_256_1023,		0x000030),
282 	REG(SYS_COUNT_RX_1024_1526,		0x000034),
283 	REG(SYS_COUNT_RX_1527_MAX,		0x000038),
284 	REG(SYS_COUNT_RX_LONGS,			0x000044),
285 	REG(SYS_COUNT_TX_OCTETS,		0x000200),
286 	REG(SYS_COUNT_TX_COLLISION,		0x000210),
287 	REG(SYS_COUNT_TX_DROPS,			0x000214),
288 	REG(SYS_COUNT_TX_64,			0x00021c),
289 	REG(SYS_COUNT_TX_65_127,		0x000220),
290 	REG(SYS_COUNT_TX_128_511,		0x000224),
291 	REG(SYS_COUNT_TX_512_1023,		0x000228),
292 	REG(SYS_COUNT_TX_1024_1526,		0x00022c),
293 	REG(SYS_COUNT_TX_1527_MAX,		0x000230),
294 	REG(SYS_COUNT_TX_AGING,			0x000278),
295 	REG(SYS_RESET_CFG,			0x000e00),
296 	REG(SYS_SR_ETYPE_CFG,			0x000e04),
297 	REG(SYS_VLAN_ETYPE_CFG,			0x000e08),
298 	REG(SYS_PORT_MODE,			0x000e0c),
299 	REG(SYS_FRONT_PORT_MODE,		0x000e2c),
300 	REG(SYS_FRM_AGING,			0x000e44),
301 	REG(SYS_STAT_CFG,			0x000e48),
302 	REG(SYS_SW_STATUS,			0x000e4c),
303 	REG_RESERVED(SYS_MISC_CFG),
304 	REG(SYS_REW_MAC_HIGH_CFG,		0x000e6c),
305 	REG(SYS_REW_MAC_LOW_CFG,		0x000e84),
306 	REG(SYS_TIMESTAMP_OFFSET,		0x000e9c),
307 	REG(SYS_PAUSE_CFG,			0x000ea0),
308 	REG(SYS_PAUSE_TOT_CFG,			0x000ebc),
309 	REG(SYS_ATOP,				0x000ec0),
310 	REG(SYS_ATOP_TOT_CFG,			0x000edc),
311 	REG(SYS_MAC_FC_CFG,			0x000ee0),
312 	REG(SYS_MMGT,				0x000ef8),
313 	REG_RESERVED(SYS_MMGT_FAST),
314 	REG_RESERVED(SYS_EVENTS_DIF),
315 	REG_RESERVED(SYS_EVENTS_CORE),
316 	REG(SYS_CNT,				0x000000),
317 	REG(SYS_PTP_STATUS,			0x000f14),
318 	REG(SYS_PTP_TXSTAMP,			0x000f18),
319 	REG(SYS_PTP_NXT,			0x000f1c),
320 	REG(SYS_PTP_CFG,			0x000f20),
321 	REG(SYS_RAM_INIT,			0x000f24),
322 	REG_RESERVED(SYS_CM_ADDR),
323 	REG_RESERVED(SYS_CM_DATA_WR),
324 	REG_RESERVED(SYS_CM_DATA_RD),
325 	REG_RESERVED(SYS_CM_OP),
326 	REG_RESERVED(SYS_CM_DATA),
327 };
328 
329 static const u32 vsc9959_ptp_regmap[] = {
330 	REG(PTP_PIN_CFG,			0x000000),
331 	REG(PTP_PIN_TOD_SEC_MSB,		0x000004),
332 	REG(PTP_PIN_TOD_SEC_LSB,		0x000008),
333 	REG(PTP_PIN_TOD_NSEC,			0x00000c),
334 	REG(PTP_PIN_WF_HIGH_PERIOD,		0x000014),
335 	REG(PTP_PIN_WF_LOW_PERIOD,		0x000018),
336 	REG(PTP_CFG_MISC,			0x0000a0),
337 	REG(PTP_CLK_CFG_ADJ_CFG,		0x0000a4),
338 	REG(PTP_CLK_CFG_ADJ_FREQ,		0x0000a8),
339 };
340 
341 static const u32 vsc9959_gcb_regmap[] = {
342 	REG(GCB_SOFT_RST,			0x000004),
343 };
344 
345 static const u32 vsc9959_dev_gmii_regmap[] = {
346 	REG(DEV_CLOCK_CFG,			0x0),
347 	REG(DEV_PORT_MISC,			0x4),
348 	REG(DEV_EVENTS,				0x8),
349 	REG(DEV_EEE_CFG,			0xc),
350 	REG(DEV_RX_PATH_DELAY,			0x10),
351 	REG(DEV_TX_PATH_DELAY,			0x14),
352 	REG(DEV_PTP_PREDICT_CFG,		0x18),
353 	REG(DEV_MAC_ENA_CFG,			0x1c),
354 	REG(DEV_MAC_MODE_CFG,			0x20),
355 	REG(DEV_MAC_MAXLEN_CFG,			0x24),
356 	REG(DEV_MAC_TAGS_CFG,			0x28),
357 	REG(DEV_MAC_ADV_CHK_CFG,		0x2c),
358 	REG(DEV_MAC_IFG_CFG,			0x30),
359 	REG(DEV_MAC_HDX_CFG,			0x34),
360 	REG(DEV_MAC_DBG_CFG,			0x38),
361 	REG(DEV_MAC_FC_MAC_LOW_CFG,		0x3c),
362 	REG(DEV_MAC_FC_MAC_HIGH_CFG,		0x40),
363 	REG(DEV_MAC_STICKY,			0x44),
364 	REG_RESERVED(PCS1G_CFG),
365 	REG_RESERVED(PCS1G_MODE_CFG),
366 	REG_RESERVED(PCS1G_SD_CFG),
367 	REG_RESERVED(PCS1G_ANEG_CFG),
368 	REG_RESERVED(PCS1G_ANEG_NP_CFG),
369 	REG_RESERVED(PCS1G_LB_CFG),
370 	REG_RESERVED(PCS1G_DBG_CFG),
371 	REG_RESERVED(PCS1G_CDET_CFG),
372 	REG_RESERVED(PCS1G_ANEG_STATUS),
373 	REG_RESERVED(PCS1G_ANEG_NP_STATUS),
374 	REG_RESERVED(PCS1G_LINK_STATUS),
375 	REG_RESERVED(PCS1G_LINK_DOWN_CNT),
376 	REG_RESERVED(PCS1G_STICKY),
377 	REG_RESERVED(PCS1G_DEBUG_STATUS),
378 	REG_RESERVED(PCS1G_LPI_CFG),
379 	REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT),
380 	REG_RESERVED(PCS1G_LPI_STATUS),
381 	REG_RESERVED(PCS1G_TSTPAT_MODE_CFG),
382 	REG_RESERVED(PCS1G_TSTPAT_STATUS),
383 	REG_RESERVED(DEV_PCS_FX100_CFG),
384 	REG_RESERVED(DEV_PCS_FX100_STATUS),
385 };
386 
387 static const u32 *vsc9959_regmap[TARGET_MAX] = {
388 	[ANA]	= vsc9959_ana_regmap,
389 	[QS]	= vsc9959_qs_regmap,
390 	[QSYS]	= vsc9959_qsys_regmap,
391 	[REW]	= vsc9959_rew_regmap,
392 	[SYS]	= vsc9959_sys_regmap,
393 	[S0]	= vsc9959_vcap_regmap,
394 	[S1]	= vsc9959_vcap_regmap,
395 	[S2]	= vsc9959_vcap_regmap,
396 	[PTP]	= vsc9959_ptp_regmap,
397 	[GCB]	= vsc9959_gcb_regmap,
398 	[DEV_GMII] = vsc9959_dev_gmii_regmap,
399 };
400 
401 /* Addresses are relative to the PCI device's base address */
402 static const struct resource vsc9959_target_io_res[TARGET_MAX] = {
403 	[ANA] = {
404 		.start	= 0x0280000,
405 		.end	= 0x028ffff,
406 		.name	= "ana",
407 	},
408 	[QS] = {
409 		.start	= 0x0080000,
410 		.end	= 0x00800ff,
411 		.name	= "qs",
412 	},
413 	[QSYS] = {
414 		.start	= 0x0200000,
415 		.end	= 0x021ffff,
416 		.name	= "qsys",
417 	},
418 	[REW] = {
419 		.start	= 0x0030000,
420 		.end	= 0x003ffff,
421 		.name	= "rew",
422 	},
423 	[SYS] = {
424 		.start	= 0x0010000,
425 		.end	= 0x001ffff,
426 		.name	= "sys",
427 	},
428 	[S0] = {
429 		.start	= 0x0040000,
430 		.end	= 0x00403ff,
431 		.name	= "s0",
432 	},
433 	[S1] = {
434 		.start	= 0x0050000,
435 		.end	= 0x00503ff,
436 		.name	= "s1",
437 	},
438 	[S2] = {
439 		.start	= 0x0060000,
440 		.end	= 0x00603ff,
441 		.name	= "s2",
442 	},
443 	[PTP] = {
444 		.start	= 0x0090000,
445 		.end	= 0x00900cb,
446 		.name	= "ptp",
447 	},
448 	[GCB] = {
449 		.start	= 0x0070000,
450 		.end	= 0x00701ff,
451 		.name	= "devcpu_gcb",
452 	},
453 };
454 
455 static const struct resource vsc9959_port_io_res[] = {
456 	{
457 		.start	= 0x0100000,
458 		.end	= 0x010ffff,
459 		.name	= "port0",
460 	},
461 	{
462 		.start	= 0x0110000,
463 		.end	= 0x011ffff,
464 		.name	= "port1",
465 	},
466 	{
467 		.start	= 0x0120000,
468 		.end	= 0x012ffff,
469 		.name	= "port2",
470 	},
471 	{
472 		.start	= 0x0130000,
473 		.end	= 0x013ffff,
474 		.name	= "port3",
475 	},
476 	{
477 		.start	= 0x0140000,
478 		.end	= 0x014ffff,
479 		.name	= "port4",
480 	},
481 	{
482 		.start	= 0x0150000,
483 		.end	= 0x015ffff,
484 		.name	= "port5",
485 	},
486 };
487 
488 /* Port MAC 0 Internal MDIO bus through which the SerDes acting as an
489  * SGMII/QSGMII MAC PCS can be found.
490  */
491 static const struct resource vsc9959_imdio_res = {
492 	.start		= 0x8030,
493 	.end		= 0x8040,
494 	.name		= "imdio",
495 };
496 
497 static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = {
498 	[ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6),
499 	[ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5),
500 	[ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30),
501 	[ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 26, 26),
502 	[ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 24, 24),
503 	[ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 23, 23),
504 	[ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 22, 22),
505 	[ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 21, 21),
506 	[ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 20, 20),
507 	[ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 19, 19),
508 	[ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
509 	[ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 17, 17),
510 	[ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 15, 15),
511 	[ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 14, 14),
512 	[ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 13, 13),
513 	[ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 12, 12),
514 	[ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
515 	[ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
516 	[ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 9, 9),
517 	[ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 8, 8),
518 	[ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 7, 7),
519 	[ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
520 	[ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
521 	[ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 4, 4),
522 	[ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 3, 3),
523 	[ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 2, 2),
524 	[ANA_ANEVENTS_SEQ_GEN_ERR_0] = REG_FIELD(ANA_ANEVENTS, 1, 1),
525 	[ANA_ANEVENTS_SEQ_GEN_ERR_1] = REG_FIELD(ANA_ANEVENTS, 0, 0),
526 	[ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16),
527 	[ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12),
528 	[ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10),
529 	[SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0),
530 	[GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0),
531 	/* Replicated per number of ports (7), register size 4 per port */
532 	[QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4),
533 	[QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4),
534 	[QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4),
535 	[QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4),
536 	[QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4),
537 	[QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4),
538 	[SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4),
539 	[SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4),
540 	[SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4),
541 	[SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4),
542 	[SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 10, 18, 7, 4),
543 	[SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 9, 7, 4),
544 	[SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 7, 4),
545 };
546 
547 static const struct ocelot_stat_layout vsc9959_stats_layout[] = {
548 	{ .offset = 0x00,	.name = "rx_octets", },
549 	{ .offset = 0x01,	.name = "rx_unicast", },
550 	{ .offset = 0x02,	.name = "rx_multicast", },
551 	{ .offset = 0x03,	.name = "rx_broadcast", },
552 	{ .offset = 0x04,	.name = "rx_shorts", },
553 	{ .offset = 0x05,	.name = "rx_fragments", },
554 	{ .offset = 0x06,	.name = "rx_jabbers", },
555 	{ .offset = 0x07,	.name = "rx_crc_align_errs", },
556 	{ .offset = 0x08,	.name = "rx_sym_errs", },
557 	{ .offset = 0x09,	.name = "rx_frames_below_65_octets", },
558 	{ .offset = 0x0A,	.name = "rx_frames_65_to_127_octets", },
559 	{ .offset = 0x0B,	.name = "rx_frames_128_to_255_octets", },
560 	{ .offset = 0x0C,	.name = "rx_frames_256_to_511_octets", },
561 	{ .offset = 0x0D,	.name = "rx_frames_512_to_1023_octets", },
562 	{ .offset = 0x0E,	.name = "rx_frames_1024_to_1526_octets", },
563 	{ .offset = 0x0F,	.name = "rx_frames_over_1526_octets", },
564 	{ .offset = 0x10,	.name = "rx_pause", },
565 	{ .offset = 0x11,	.name = "rx_control", },
566 	{ .offset = 0x12,	.name = "rx_longs", },
567 	{ .offset = 0x13,	.name = "rx_classified_drops", },
568 	{ .offset = 0x14,	.name = "rx_red_prio_0", },
569 	{ .offset = 0x15,	.name = "rx_red_prio_1", },
570 	{ .offset = 0x16,	.name = "rx_red_prio_2", },
571 	{ .offset = 0x17,	.name = "rx_red_prio_3", },
572 	{ .offset = 0x18,	.name = "rx_red_prio_4", },
573 	{ .offset = 0x19,	.name = "rx_red_prio_5", },
574 	{ .offset = 0x1A,	.name = "rx_red_prio_6", },
575 	{ .offset = 0x1B,	.name = "rx_red_prio_7", },
576 	{ .offset = 0x1C,	.name = "rx_yellow_prio_0", },
577 	{ .offset = 0x1D,	.name = "rx_yellow_prio_1", },
578 	{ .offset = 0x1E,	.name = "rx_yellow_prio_2", },
579 	{ .offset = 0x1F,	.name = "rx_yellow_prio_3", },
580 	{ .offset = 0x20,	.name = "rx_yellow_prio_4", },
581 	{ .offset = 0x21,	.name = "rx_yellow_prio_5", },
582 	{ .offset = 0x22,	.name = "rx_yellow_prio_6", },
583 	{ .offset = 0x23,	.name = "rx_yellow_prio_7", },
584 	{ .offset = 0x24,	.name = "rx_green_prio_0", },
585 	{ .offset = 0x25,	.name = "rx_green_prio_1", },
586 	{ .offset = 0x26,	.name = "rx_green_prio_2", },
587 	{ .offset = 0x27,	.name = "rx_green_prio_3", },
588 	{ .offset = 0x28,	.name = "rx_green_prio_4", },
589 	{ .offset = 0x29,	.name = "rx_green_prio_5", },
590 	{ .offset = 0x2A,	.name = "rx_green_prio_6", },
591 	{ .offset = 0x2B,	.name = "rx_green_prio_7", },
592 	{ .offset = 0x80,	.name = "tx_octets", },
593 	{ .offset = 0x81,	.name = "tx_unicast", },
594 	{ .offset = 0x82,	.name = "tx_multicast", },
595 	{ .offset = 0x83,	.name = "tx_broadcast", },
596 	{ .offset = 0x84,	.name = "tx_collision", },
597 	{ .offset = 0x85,	.name = "tx_drops", },
598 	{ .offset = 0x86,	.name = "tx_pause", },
599 	{ .offset = 0x87,	.name = "tx_frames_below_65_octets", },
600 	{ .offset = 0x88,	.name = "tx_frames_65_to_127_octets", },
601 	{ .offset = 0x89,	.name = "tx_frames_128_255_octets", },
602 	{ .offset = 0x8B,	.name = "tx_frames_256_511_octets", },
603 	{ .offset = 0x8C,	.name = "tx_frames_1024_1526_octets", },
604 	{ .offset = 0x8D,	.name = "tx_frames_over_1526_octets", },
605 	{ .offset = 0x8E,	.name = "tx_yellow_prio_0", },
606 	{ .offset = 0x8F,	.name = "tx_yellow_prio_1", },
607 	{ .offset = 0x90,	.name = "tx_yellow_prio_2", },
608 	{ .offset = 0x91,	.name = "tx_yellow_prio_3", },
609 	{ .offset = 0x92,	.name = "tx_yellow_prio_4", },
610 	{ .offset = 0x93,	.name = "tx_yellow_prio_5", },
611 	{ .offset = 0x94,	.name = "tx_yellow_prio_6", },
612 	{ .offset = 0x95,	.name = "tx_yellow_prio_7", },
613 	{ .offset = 0x96,	.name = "tx_green_prio_0", },
614 	{ .offset = 0x97,	.name = "tx_green_prio_1", },
615 	{ .offset = 0x98,	.name = "tx_green_prio_2", },
616 	{ .offset = 0x99,	.name = "tx_green_prio_3", },
617 	{ .offset = 0x9A,	.name = "tx_green_prio_4", },
618 	{ .offset = 0x9B,	.name = "tx_green_prio_5", },
619 	{ .offset = 0x9C,	.name = "tx_green_prio_6", },
620 	{ .offset = 0x9D,	.name = "tx_green_prio_7", },
621 	{ .offset = 0x9E,	.name = "tx_aged", },
622 	{ .offset = 0x100,	.name = "drop_local", },
623 	{ .offset = 0x101,	.name = "drop_tail", },
624 	{ .offset = 0x102,	.name = "drop_yellow_prio_0", },
625 	{ .offset = 0x103,	.name = "drop_yellow_prio_1", },
626 	{ .offset = 0x104,	.name = "drop_yellow_prio_2", },
627 	{ .offset = 0x105,	.name = "drop_yellow_prio_3", },
628 	{ .offset = 0x106,	.name = "drop_yellow_prio_4", },
629 	{ .offset = 0x107,	.name = "drop_yellow_prio_5", },
630 	{ .offset = 0x108,	.name = "drop_yellow_prio_6", },
631 	{ .offset = 0x109,	.name = "drop_yellow_prio_7", },
632 	{ .offset = 0x10A,	.name = "drop_green_prio_0", },
633 	{ .offset = 0x10B,	.name = "drop_green_prio_1", },
634 	{ .offset = 0x10C,	.name = "drop_green_prio_2", },
635 	{ .offset = 0x10D,	.name = "drop_green_prio_3", },
636 	{ .offset = 0x10E,	.name = "drop_green_prio_4", },
637 	{ .offset = 0x10F,	.name = "drop_green_prio_5", },
638 	{ .offset = 0x110,	.name = "drop_green_prio_6", },
639 	{ .offset = 0x111,	.name = "drop_green_prio_7", },
640 };
641 
642 static const struct vcap_field vsc9959_vcap_es0_keys[] = {
643 	[VCAP_ES0_EGR_PORT]			= {  0,  3},
644 	[VCAP_ES0_IGR_PORT]			= {  3,  3},
645 	[VCAP_ES0_RSV]				= {  6,  2},
646 	[VCAP_ES0_L2_MC]			= {  8,  1},
647 	[VCAP_ES0_L2_BC]			= {  9,  1},
648 	[VCAP_ES0_VID]				= { 10, 12},
649 	[VCAP_ES0_DP]				= { 22,  1},
650 	[VCAP_ES0_PCP]				= { 23,  3},
651 };
652 
653 static const struct vcap_field vsc9959_vcap_es0_actions[] = {
654 	[VCAP_ES0_ACT_PUSH_OUTER_TAG]		= {  0,  2},
655 	[VCAP_ES0_ACT_PUSH_INNER_TAG]		= {  2,  1},
656 	[VCAP_ES0_ACT_TAG_A_TPID_SEL]		= {  3,  2},
657 	[VCAP_ES0_ACT_TAG_A_VID_SEL]		= {  5,  1},
658 	[VCAP_ES0_ACT_TAG_A_PCP_SEL]		= {  6,  2},
659 	[VCAP_ES0_ACT_TAG_A_DEI_SEL]		= {  8,  2},
660 	[VCAP_ES0_ACT_TAG_B_TPID_SEL]		= { 10,  2},
661 	[VCAP_ES0_ACT_TAG_B_VID_SEL]		= { 12,  1},
662 	[VCAP_ES0_ACT_TAG_B_PCP_SEL]		= { 13,  2},
663 	[VCAP_ES0_ACT_TAG_B_DEI_SEL]		= { 15,  2},
664 	[VCAP_ES0_ACT_VID_A_VAL]		= { 17, 12},
665 	[VCAP_ES0_ACT_PCP_A_VAL]		= { 29,  3},
666 	[VCAP_ES0_ACT_DEI_A_VAL]		= { 32,  1},
667 	[VCAP_ES0_ACT_VID_B_VAL]		= { 33, 12},
668 	[VCAP_ES0_ACT_PCP_B_VAL]		= { 45,  3},
669 	[VCAP_ES0_ACT_DEI_B_VAL]		= { 48,  1},
670 	[VCAP_ES0_ACT_RSV]			= { 49, 23},
671 	[VCAP_ES0_ACT_HIT_STICKY]		= { 72,  1},
672 };
673 
674 static const struct vcap_field vsc9959_vcap_is1_keys[] = {
675 	[VCAP_IS1_HK_TYPE]			= {  0,   1},
676 	[VCAP_IS1_HK_LOOKUP]			= {  1,   2},
677 	[VCAP_IS1_HK_IGR_PORT_MASK]		= {  3,   7},
678 	[VCAP_IS1_HK_RSV]			= { 10,   9},
679 	[VCAP_IS1_HK_OAM_Y1731]			= { 19,   1},
680 	[VCAP_IS1_HK_L2_MC]			= { 20,   1},
681 	[VCAP_IS1_HK_L2_BC]			= { 21,   1},
682 	[VCAP_IS1_HK_IP_MC]			= { 22,   1},
683 	[VCAP_IS1_HK_VLAN_TAGGED]		= { 23,   1},
684 	[VCAP_IS1_HK_VLAN_DBL_TAGGED]		= { 24,   1},
685 	[VCAP_IS1_HK_TPID]			= { 25,   1},
686 	[VCAP_IS1_HK_VID]			= { 26,  12},
687 	[VCAP_IS1_HK_DEI]			= { 38,   1},
688 	[VCAP_IS1_HK_PCP]			= { 39,   3},
689 	/* Specific Fields for IS1 Half Key S1_NORMAL */
690 	[VCAP_IS1_HK_L2_SMAC]			= { 42,  48},
691 	[VCAP_IS1_HK_ETYPE_LEN]			= { 90,   1},
692 	[VCAP_IS1_HK_ETYPE]			= { 91,  16},
693 	[VCAP_IS1_HK_IP_SNAP]			= {107,   1},
694 	[VCAP_IS1_HK_IP4]			= {108,   1},
695 	/* Layer-3 Information */
696 	[VCAP_IS1_HK_L3_FRAGMENT]		= {109,   1},
697 	[VCAP_IS1_HK_L3_FRAG_OFS_GT0]		= {110,   1},
698 	[VCAP_IS1_HK_L3_OPTIONS]		= {111,   1},
699 	[VCAP_IS1_HK_L3_DSCP]			= {112,   6},
700 	[VCAP_IS1_HK_L3_IP4_SIP]		= {118,  32},
701 	/* Layer-4 Information */
702 	[VCAP_IS1_HK_TCP_UDP]			= {150,   1},
703 	[VCAP_IS1_HK_TCP]			= {151,   1},
704 	[VCAP_IS1_HK_L4_SPORT]			= {152,  16},
705 	[VCAP_IS1_HK_L4_RNG]			= {168,   8},
706 	/* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */
707 	[VCAP_IS1_HK_IP4_INNER_TPID]            = { 42,   1},
708 	[VCAP_IS1_HK_IP4_INNER_VID]		= { 43,  12},
709 	[VCAP_IS1_HK_IP4_INNER_DEI]		= { 55,   1},
710 	[VCAP_IS1_HK_IP4_INNER_PCP]		= { 56,   3},
711 	[VCAP_IS1_HK_IP4_IP4]			= { 59,   1},
712 	[VCAP_IS1_HK_IP4_L3_FRAGMENT]		= { 60,   1},
713 	[VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0]	= { 61,   1},
714 	[VCAP_IS1_HK_IP4_L3_OPTIONS]		= { 62,   1},
715 	[VCAP_IS1_HK_IP4_L3_DSCP]		= { 63,   6},
716 	[VCAP_IS1_HK_IP4_L3_IP4_DIP]		= { 69,  32},
717 	[VCAP_IS1_HK_IP4_L3_IP4_SIP]		= {101,  32},
718 	[VCAP_IS1_HK_IP4_L3_PROTO]		= {133,   8},
719 	[VCAP_IS1_HK_IP4_TCP_UDP]		= {141,   1},
720 	[VCAP_IS1_HK_IP4_TCP]			= {142,   1},
721 	[VCAP_IS1_HK_IP4_L4_RNG]		= {143,   8},
722 	[VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE]	= {151,  32},
723 };
724 
725 static const struct vcap_field vsc9959_vcap_is1_actions[] = {
726 	[VCAP_IS1_ACT_DSCP_ENA]			= {  0,  1},
727 	[VCAP_IS1_ACT_DSCP_VAL]			= {  1,  6},
728 	[VCAP_IS1_ACT_QOS_ENA]			= {  7,  1},
729 	[VCAP_IS1_ACT_QOS_VAL]			= {  8,  3},
730 	[VCAP_IS1_ACT_DP_ENA]			= { 11,  1},
731 	[VCAP_IS1_ACT_DP_VAL]			= { 12,  1},
732 	[VCAP_IS1_ACT_PAG_OVERRIDE_MASK]	= { 13,  8},
733 	[VCAP_IS1_ACT_PAG_VAL]			= { 21,  8},
734 	[VCAP_IS1_ACT_RSV]			= { 29,  9},
735 	/* The fields below are incorrectly shifted by 2 in the manual */
736 	[VCAP_IS1_ACT_VID_REPLACE_ENA]		= { 38,  1},
737 	[VCAP_IS1_ACT_VID_ADD_VAL]		= { 39, 12},
738 	[VCAP_IS1_ACT_FID_SEL]			= { 51,  2},
739 	[VCAP_IS1_ACT_FID_VAL]			= { 53, 13},
740 	[VCAP_IS1_ACT_PCP_DEI_ENA]		= { 66,  1},
741 	[VCAP_IS1_ACT_PCP_VAL]			= { 67,  3},
742 	[VCAP_IS1_ACT_DEI_VAL]			= { 70,  1},
743 	[VCAP_IS1_ACT_VLAN_POP_CNT_ENA]		= { 71,  1},
744 	[VCAP_IS1_ACT_VLAN_POP_CNT]		= { 72,  2},
745 	[VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA]	= { 74,  4},
746 	[VCAP_IS1_ACT_HIT_STICKY]		= { 78,  1},
747 };
748 
749 static struct vcap_field vsc9959_vcap_is2_keys[] = {
750 	/* Common: 41 bits */
751 	[VCAP_IS2_TYPE]				= {  0,   4},
752 	[VCAP_IS2_HK_FIRST]			= {  4,   1},
753 	[VCAP_IS2_HK_PAG]			= {  5,   8},
754 	[VCAP_IS2_HK_IGR_PORT_MASK]		= { 13,   7},
755 	[VCAP_IS2_HK_RSV2]			= { 20,   1},
756 	[VCAP_IS2_HK_HOST_MATCH]		= { 21,   1},
757 	[VCAP_IS2_HK_L2_MC]			= { 22,   1},
758 	[VCAP_IS2_HK_L2_BC]			= { 23,   1},
759 	[VCAP_IS2_HK_VLAN_TAGGED]		= { 24,   1},
760 	[VCAP_IS2_HK_VID]			= { 25,  12},
761 	[VCAP_IS2_HK_DEI]			= { 37,   1},
762 	[VCAP_IS2_HK_PCP]			= { 38,   3},
763 	/* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
764 	[VCAP_IS2_HK_L2_DMAC]			= { 41,  48},
765 	[VCAP_IS2_HK_L2_SMAC]			= { 89,  48},
766 	/* MAC_ETYPE (TYPE=000) */
767 	[VCAP_IS2_HK_MAC_ETYPE_ETYPE]		= {137,  16},
768 	[VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0]	= {153,  16},
769 	[VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1]	= {169,   8},
770 	[VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2]	= {177,   3},
771 	/* MAC_LLC (TYPE=001) */
772 	[VCAP_IS2_HK_MAC_LLC_L2_LLC]		= {137,  40},
773 	/* MAC_SNAP (TYPE=010) */
774 	[VCAP_IS2_HK_MAC_SNAP_L2_SNAP]		= {137,  40},
775 	/* MAC_ARP (TYPE=011) */
776 	[VCAP_IS2_HK_MAC_ARP_SMAC]		= { 41,  48},
777 	[VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK]	= { 89,   1},
778 	[VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK]	= { 90,   1},
779 	[VCAP_IS2_HK_MAC_ARP_LEN_OK]		= { 91,   1},
780 	[VCAP_IS2_HK_MAC_ARP_TARGET_MATCH]	= { 92,   1},
781 	[VCAP_IS2_HK_MAC_ARP_SENDER_MATCH]	= { 93,   1},
782 	[VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN]	= { 94,   1},
783 	[VCAP_IS2_HK_MAC_ARP_OPCODE]		= { 95,   2},
784 	[VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP]	= { 97,  32},
785 	[VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP]	= {129,  32},
786 	[VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP]	= {161,   1},
787 	/* IP4_TCP_UDP / IP4_OTHER common */
788 	[VCAP_IS2_HK_IP4]			= { 41,   1},
789 	[VCAP_IS2_HK_L3_FRAGMENT]		= { 42,   1},
790 	[VCAP_IS2_HK_L3_FRAG_OFS_GT0]		= { 43,   1},
791 	[VCAP_IS2_HK_L3_OPTIONS]		= { 44,   1},
792 	[VCAP_IS2_HK_IP4_L3_TTL_GT0]		= { 45,   1},
793 	[VCAP_IS2_HK_L3_TOS]			= { 46,   8},
794 	[VCAP_IS2_HK_L3_IP4_DIP]		= { 54,  32},
795 	[VCAP_IS2_HK_L3_IP4_SIP]		= { 86,  32},
796 	[VCAP_IS2_HK_DIP_EQ_SIP]		= {118,   1},
797 	/* IP4_TCP_UDP (TYPE=100) */
798 	[VCAP_IS2_HK_TCP]			= {119,   1},
799 	[VCAP_IS2_HK_L4_DPORT]			= {120,  16},
800 	[VCAP_IS2_HK_L4_SPORT]			= {136,  16},
801 	[VCAP_IS2_HK_L4_RNG]			= {152,   8},
802 	[VCAP_IS2_HK_L4_SPORT_EQ_DPORT]		= {160,   1},
803 	[VCAP_IS2_HK_L4_SEQUENCE_EQ0]		= {161,   1},
804 	[VCAP_IS2_HK_L4_FIN]			= {162,   1},
805 	[VCAP_IS2_HK_L4_SYN]			= {163,   1},
806 	[VCAP_IS2_HK_L4_RST]			= {164,   1},
807 	[VCAP_IS2_HK_L4_PSH]			= {165,   1},
808 	[VCAP_IS2_HK_L4_ACK]			= {166,   1},
809 	[VCAP_IS2_HK_L4_URG]			= {167,   1},
810 	[VCAP_IS2_HK_L4_1588_DOM]		= {168,   8},
811 	[VCAP_IS2_HK_L4_1588_VER]		= {176,   4},
812 	/* IP4_OTHER (TYPE=101) */
813 	[VCAP_IS2_HK_IP4_L3_PROTO]		= {119,   8},
814 	[VCAP_IS2_HK_L3_PAYLOAD]		= {127,  56},
815 	/* IP6_STD (TYPE=110) */
816 	[VCAP_IS2_HK_IP6_L3_TTL_GT0]		= { 41,   1},
817 	[VCAP_IS2_HK_L3_IP6_SIP]		= { 42, 128},
818 	[VCAP_IS2_HK_IP6_L3_PROTO]		= {170,   8},
819 	/* OAM (TYPE=111) */
820 	[VCAP_IS2_HK_OAM_MEL_FLAGS]		= {137,   7},
821 	[VCAP_IS2_HK_OAM_VER]			= {144,   5},
822 	[VCAP_IS2_HK_OAM_OPCODE]		= {149,   8},
823 	[VCAP_IS2_HK_OAM_FLAGS]			= {157,   8},
824 	[VCAP_IS2_HK_OAM_MEPID]			= {165,  16},
825 	[VCAP_IS2_HK_OAM_CCM_CNTS_EQ0]		= {181,   1},
826 	[VCAP_IS2_HK_OAM_IS_Y1731]		= {182,   1},
827 };
828 
829 static struct vcap_field vsc9959_vcap_is2_actions[] = {
830 	[VCAP_IS2_ACT_HIT_ME_ONCE]		= {  0,  1},
831 	[VCAP_IS2_ACT_CPU_COPY_ENA]		= {  1,  1},
832 	[VCAP_IS2_ACT_CPU_QU_NUM]		= {  2,  3},
833 	[VCAP_IS2_ACT_MASK_MODE]		= {  5,  2},
834 	[VCAP_IS2_ACT_MIRROR_ENA]		= {  7,  1},
835 	[VCAP_IS2_ACT_LRN_DIS]			= {  8,  1},
836 	[VCAP_IS2_ACT_POLICE_ENA]		= {  9,  1},
837 	[VCAP_IS2_ACT_POLICE_IDX]		= { 10,  9},
838 	[VCAP_IS2_ACT_POLICE_VCAP_ONLY]		= { 19,  1},
839 	[VCAP_IS2_ACT_PORT_MASK]		= { 20,  6},
840 	[VCAP_IS2_ACT_REW_OP]			= { 26,  9},
841 	[VCAP_IS2_ACT_SMAC_REPLACE_ENA]		= { 35,  1},
842 	[VCAP_IS2_ACT_RSV]			= { 36,  2},
843 	[VCAP_IS2_ACT_ACL_ID]			= { 38,  6},
844 	[VCAP_IS2_ACT_HIT_CNT]			= { 44, 32},
845 };
846 
847 static struct vcap_props vsc9959_vcap_props[] = {
848 	[VCAP_ES0] = {
849 		.action_type_width = 0,
850 		.action_table = {
851 			[ES0_ACTION_TYPE_NORMAL] = {
852 				.width = 72, /* HIT_STICKY not included */
853 				.count = 1,
854 			},
855 		},
856 		.target = S0,
857 		.keys = vsc9959_vcap_es0_keys,
858 		.actions = vsc9959_vcap_es0_actions,
859 	},
860 	[VCAP_IS1] = {
861 		.action_type_width = 0,
862 		.action_table = {
863 			[IS1_ACTION_TYPE_NORMAL] = {
864 				.width = 78, /* HIT_STICKY not included */
865 				.count = 4,
866 			},
867 		},
868 		.target = S1,
869 		.keys = vsc9959_vcap_is1_keys,
870 		.actions = vsc9959_vcap_is1_actions,
871 	},
872 	[VCAP_IS2] = {
873 		.action_type_width = 1,
874 		.action_table = {
875 			[IS2_ACTION_TYPE_NORMAL] = {
876 				.width = 44,
877 				.count = 2
878 			},
879 			[IS2_ACTION_TYPE_SMAC_SIP] = {
880 				.width = 6,
881 				.count = 4
882 			},
883 		},
884 		.target = S2,
885 		.keys = vsc9959_vcap_is2_keys,
886 		.actions = vsc9959_vcap_is2_actions,
887 	},
888 };
889 
890 static const struct ptp_clock_info vsc9959_ptp_caps = {
891 	.owner		= THIS_MODULE,
892 	.name		= "felix ptp",
893 	.max_adj	= 0x7fffffff,
894 	.n_alarm	= 0,
895 	.n_ext_ts	= 0,
896 	.n_per_out	= OCELOT_PTP_PINS_NUM,
897 	.n_pins		= OCELOT_PTP_PINS_NUM,
898 	.pps		= 0,
899 	.gettime64	= ocelot_ptp_gettime64,
900 	.settime64	= ocelot_ptp_settime64,
901 	.adjtime	= ocelot_ptp_adjtime,
902 	.adjfine	= ocelot_ptp_adjfine,
903 	.verify		= ocelot_ptp_verify,
904 	.enable		= ocelot_ptp_enable,
905 };
906 
907 #define VSC9959_INIT_TIMEOUT			50000
908 #define VSC9959_GCB_RST_SLEEP			100
909 #define VSC9959_SYS_RAMINIT_SLEEP		80
910 
911 static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot)
912 {
913 	int val;
914 
915 	ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val);
916 
917 	return val;
918 }
919 
920 static int vsc9959_sys_ram_init_status(struct ocelot *ocelot)
921 {
922 	return ocelot_read(ocelot, SYS_RAM_INIT);
923 }
924 
925 /* CORE_ENA is in SYS:SYSTEM:RESET_CFG
926  * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT
927  */
928 static int vsc9959_reset(struct ocelot *ocelot)
929 {
930 	int val, err;
931 
932 	/* soft-reset the switch core */
933 	ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1);
934 
935 	err = readx_poll_timeout(vsc9959_gcb_soft_rst_status, ocelot, val, !val,
936 				 VSC9959_GCB_RST_SLEEP, VSC9959_INIT_TIMEOUT);
937 	if (err) {
938 		dev_err(ocelot->dev, "timeout: switch core reset\n");
939 		return err;
940 	}
941 
942 	/* initialize switch mem ~40us */
943 	ocelot_write(ocelot, SYS_RAM_INIT_RAM_INIT, SYS_RAM_INIT);
944 	err = readx_poll_timeout(vsc9959_sys_ram_init_status, ocelot, val, !val,
945 				 VSC9959_SYS_RAMINIT_SLEEP,
946 				 VSC9959_INIT_TIMEOUT);
947 	if (err) {
948 		dev_err(ocelot->dev, "timeout: switch sram init\n");
949 		return err;
950 	}
951 
952 	/* enable switch core */
953 	ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1);
954 
955 	return 0;
956 }
957 
958 static void vsc9959_phylink_validate(struct ocelot *ocelot, int port,
959 				     unsigned long *supported,
960 				     struct phylink_link_state *state)
961 {
962 	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
963 
964 	phylink_set_port_modes(mask);
965 	phylink_set(mask, Autoneg);
966 	phylink_set(mask, Pause);
967 	phylink_set(mask, Asym_Pause);
968 	phylink_set(mask, 10baseT_Half);
969 	phylink_set(mask, 10baseT_Full);
970 	phylink_set(mask, 100baseT_Half);
971 	phylink_set(mask, 100baseT_Full);
972 	phylink_set(mask, 1000baseT_Half);
973 	phylink_set(mask, 1000baseT_Full);
974 
975 	if (state->interface == PHY_INTERFACE_MODE_INTERNAL ||
976 	    state->interface == PHY_INTERFACE_MODE_2500BASEX ||
977 	    state->interface == PHY_INTERFACE_MODE_USXGMII) {
978 		phylink_set(mask, 2500baseT_Full);
979 		phylink_set(mask, 2500baseX_Full);
980 	}
981 
982 	linkmode_and(supported, supported, mask);
983 	linkmode_and(state->advertising, state->advertising, mask);
984 }
985 
986 /* Watermark encode
987  * Bit 8:   Unit; 0:1, 1:16
988  * Bit 7-0: Value to be multiplied with unit
989  */
990 static u16 vsc9959_wm_enc(u16 value)
991 {
992 	WARN_ON(value >= 16 * BIT(8));
993 
994 	if (value >= BIT(8))
995 		return BIT(8) | (value / 16);
996 
997 	return value;
998 }
999 
1000 static u16 vsc9959_wm_dec(u16 wm)
1001 {
1002 	WARN_ON(wm & ~GENMASK(8, 0));
1003 
1004 	if (wm & BIT(8))
1005 		return (wm & GENMASK(7, 0)) * 16;
1006 
1007 	return wm;
1008 }
1009 
1010 static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse)
1011 {
1012 	*inuse = (val & GENMASK(23, 12)) >> 12;
1013 	*maxuse = val & GENMASK(11, 0);
1014 }
1015 
1016 static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot)
1017 {
1018 	struct felix *felix = ocelot_to_felix(ocelot);
1019 	struct enetc_mdio_priv *mdio_priv;
1020 	struct device *dev = ocelot->dev;
1021 	void __iomem *imdio_regs;
1022 	struct resource res;
1023 	struct enetc_hw *hw;
1024 	struct mii_bus *bus;
1025 	int port;
1026 	int rc;
1027 
1028 	felix->pcs = devm_kcalloc(dev, felix->info->num_ports,
1029 				  sizeof(struct phylink_pcs *),
1030 				  GFP_KERNEL);
1031 	if (!felix->pcs) {
1032 		dev_err(dev, "failed to allocate array for PCS PHYs\n");
1033 		return -ENOMEM;
1034 	}
1035 
1036 	memcpy(&res, felix->info->imdio_res, sizeof(res));
1037 	res.flags = IORESOURCE_MEM;
1038 	res.start += felix->imdio_base;
1039 	res.end += felix->imdio_base;
1040 
1041 	imdio_regs = devm_ioremap_resource(dev, &res);
1042 	if (IS_ERR(imdio_regs))
1043 		return PTR_ERR(imdio_regs);
1044 
1045 	hw = enetc_hw_alloc(dev, imdio_regs);
1046 	if (IS_ERR(hw)) {
1047 		dev_err(dev, "failed to allocate ENETC HW structure\n");
1048 		return PTR_ERR(hw);
1049 	}
1050 
1051 	bus = mdiobus_alloc_size(sizeof(*mdio_priv));
1052 	if (!bus)
1053 		return -ENOMEM;
1054 
1055 	bus->name = "VSC9959 internal MDIO bus";
1056 	bus->read = enetc_mdio_read;
1057 	bus->write = enetc_mdio_write;
1058 	bus->parent = dev;
1059 	mdio_priv = bus->priv;
1060 	mdio_priv->hw = hw;
1061 	/* This gets added to imdio_regs, which already maps addresses
1062 	 * starting with the proper offset.
1063 	 */
1064 	mdio_priv->mdio_base = 0;
1065 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
1066 
1067 	/* Needed in order to initialize the bus mutex lock */
1068 	rc = mdiobus_register(bus);
1069 	if (rc < 0) {
1070 		dev_err(dev, "failed to register MDIO bus\n");
1071 		mdiobus_free(bus);
1072 		return rc;
1073 	}
1074 
1075 	felix->imdio = bus;
1076 
1077 	for (port = 0; port < felix->info->num_ports; port++) {
1078 		struct ocelot_port *ocelot_port = ocelot->ports[port];
1079 		struct phylink_pcs *phylink_pcs;
1080 		struct mdio_device *mdio_device;
1081 
1082 		if (dsa_is_unused_port(felix->ds, port))
1083 			continue;
1084 
1085 		if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL)
1086 			continue;
1087 
1088 		mdio_device = mdio_device_create(felix->imdio, port);
1089 		if (IS_ERR(mdio_device))
1090 			continue;
1091 
1092 		phylink_pcs = lynx_pcs_create(mdio_device);
1093 		if (!phylink_pcs) {
1094 			mdio_device_free(mdio_device);
1095 			continue;
1096 		}
1097 
1098 		felix->pcs[port] = phylink_pcs;
1099 
1100 		dev_info(dev, "Found PCS at internal MDIO address %d\n", port);
1101 	}
1102 
1103 	return 0;
1104 }
1105 
1106 static void vsc9959_mdio_bus_free(struct ocelot *ocelot)
1107 {
1108 	struct felix *felix = ocelot_to_felix(ocelot);
1109 	int port;
1110 
1111 	for (port = 0; port < ocelot->num_phys_ports; port++) {
1112 		struct phylink_pcs *phylink_pcs = felix->pcs[port];
1113 		struct mdio_device *mdio_device;
1114 
1115 		if (!phylink_pcs)
1116 			continue;
1117 
1118 		mdio_device = lynx_get_mdio_device(phylink_pcs);
1119 		mdio_device_free(mdio_device);
1120 		lynx_pcs_destroy(phylink_pcs);
1121 	}
1122 	mdiobus_unregister(felix->imdio);
1123 	mdiobus_free(felix->imdio);
1124 }
1125 
1126 static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port,
1127 				    u32 speed)
1128 {
1129 	u8 tas_speed;
1130 
1131 	switch (speed) {
1132 	case SPEED_10:
1133 		tas_speed = OCELOT_SPEED_10;
1134 		break;
1135 	case SPEED_100:
1136 		tas_speed = OCELOT_SPEED_100;
1137 		break;
1138 	case SPEED_1000:
1139 		tas_speed = OCELOT_SPEED_1000;
1140 		break;
1141 	case SPEED_2500:
1142 		tas_speed = OCELOT_SPEED_2500;
1143 		break;
1144 	default:
1145 		tas_speed = OCELOT_SPEED_1000;
1146 		break;
1147 	}
1148 
1149 	ocelot_rmw_rix(ocelot,
1150 		       QSYS_TAG_CONFIG_LINK_SPEED(tas_speed),
1151 		       QSYS_TAG_CONFIG_LINK_SPEED_M,
1152 		       QSYS_TAG_CONFIG, port);
1153 }
1154 
1155 static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time,
1156 				  u64 cycle_time,
1157 				  struct timespec64 *new_base_ts)
1158 {
1159 	struct timespec64 ts;
1160 	ktime_t new_base_time;
1161 	ktime_t current_time;
1162 
1163 	ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
1164 	current_time = timespec64_to_ktime(ts);
1165 	new_base_time = base_time;
1166 
1167 	if (base_time < current_time) {
1168 		u64 nr_of_cycles = current_time - base_time;
1169 
1170 		do_div(nr_of_cycles, cycle_time);
1171 		new_base_time += cycle_time * (nr_of_cycles + 1);
1172 	}
1173 
1174 	*new_base_ts = ktime_to_timespec64(new_base_time);
1175 }
1176 
1177 static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot)
1178 {
1179 	return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL);
1180 }
1181 
1182 static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix,
1183 				struct tc_taprio_sched_entry *entry)
1184 {
1185 	ocelot_write(ocelot,
1186 		     QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(gcl_ix) |
1187 		     QSYS_GCL_CFG_REG_1_GATE_STATE(entry->gate_mask),
1188 		     QSYS_GCL_CFG_REG_1);
1189 	ocelot_write(ocelot, entry->interval, QSYS_GCL_CFG_REG_2);
1190 }
1191 
1192 static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port,
1193 				    struct tc_taprio_qopt_offload *taprio)
1194 {
1195 	struct timespec64 base_ts;
1196 	int ret, i;
1197 	u32 val;
1198 
1199 	if (!taprio->enable) {
1200 		ocelot_rmw_rix(ocelot,
1201 			       QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF),
1202 			       QSYS_TAG_CONFIG_ENABLE |
1203 			       QSYS_TAG_CONFIG_INIT_GATE_STATE_M,
1204 			       QSYS_TAG_CONFIG, port);
1205 
1206 		return 0;
1207 	}
1208 
1209 	if (taprio->cycle_time > NSEC_PER_SEC ||
1210 	    taprio->cycle_time_extension >= NSEC_PER_SEC)
1211 		return -EINVAL;
1212 
1213 	if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX)
1214 		return -ERANGE;
1215 
1216 	/* Enable guard band. The switch will schedule frames without taking
1217 	 * their length into account. Thus we'll always need to enable the
1218 	 * guard band which reserves the time of a maximum sized frame at the
1219 	 * end of the time window.
1220 	 *
1221 	 * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we
1222 	 * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n
1223 	 * operate on the port number.
1224 	 */
1225 	ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(port) |
1226 		   QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1227 		   QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M |
1228 		   QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q,
1229 		   QSYS_TAS_PARAM_CFG_CTRL);
1230 
1231 	/* Hardware errata -  Admin config could not be overwritten if
1232 	 * config is pending, need reset the TAS module
1233 	 */
1234 	val = ocelot_read(ocelot, QSYS_PARAM_STATUS_REG_8);
1235 	if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING)
1236 		return  -EBUSY;
1237 
1238 	ocelot_rmw_rix(ocelot,
1239 		       QSYS_TAG_CONFIG_ENABLE |
1240 		       QSYS_TAG_CONFIG_INIT_GATE_STATE(0xFF) |
1241 		       QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(0xFF),
1242 		       QSYS_TAG_CONFIG_ENABLE |
1243 		       QSYS_TAG_CONFIG_INIT_GATE_STATE_M |
1244 		       QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M,
1245 		       QSYS_TAG_CONFIG, port);
1246 
1247 	vsc9959_new_base_time(ocelot, taprio->base_time,
1248 			      taprio->cycle_time, &base_ts);
1249 	ocelot_write(ocelot, base_ts.tv_nsec, QSYS_PARAM_CFG_REG_1);
1250 	ocelot_write(ocelot, lower_32_bits(base_ts.tv_sec), QSYS_PARAM_CFG_REG_2);
1251 	val = upper_32_bits(base_ts.tv_sec);
1252 	ocelot_write(ocelot,
1253 		     QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(val) |
1254 		     QSYS_PARAM_CFG_REG_3_LIST_LENGTH(taprio->num_entries),
1255 		     QSYS_PARAM_CFG_REG_3);
1256 	ocelot_write(ocelot, taprio->cycle_time, QSYS_PARAM_CFG_REG_4);
1257 	ocelot_write(ocelot, taprio->cycle_time_extension, QSYS_PARAM_CFG_REG_5);
1258 
1259 	for (i = 0; i < taprio->num_entries; i++)
1260 		vsc9959_tas_gcl_set(ocelot, i, &taprio->entries[i]);
1261 
1262 	ocelot_rmw(ocelot, QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1263 		   QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE,
1264 		   QSYS_TAS_PARAM_CFG_CTRL);
1265 
1266 	ret = readx_poll_timeout(vsc9959_tas_read_cfg_status, ocelot, val,
1267 				 !(val & QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE),
1268 				 10, 100000);
1269 
1270 	return ret;
1271 }
1272 
1273 static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port,
1274 				    struct tc_cbs_qopt_offload *cbs_qopt)
1275 {
1276 	struct ocelot *ocelot = ds->priv;
1277 	int port_ix = port * 8 + cbs_qopt->queue;
1278 	u32 rate, burst;
1279 
1280 	if (cbs_qopt->queue >= ds->num_tx_queues)
1281 		return -EINVAL;
1282 
1283 	if (!cbs_qopt->enable) {
1284 		ocelot_write_gix(ocelot, QSYS_CIR_CFG_CIR_RATE(0) |
1285 				 QSYS_CIR_CFG_CIR_BURST(0),
1286 				 QSYS_CIR_CFG, port_ix);
1287 
1288 		ocelot_rmw_gix(ocelot, 0, QSYS_SE_CFG_SE_AVB_ENA,
1289 			       QSYS_SE_CFG, port_ix);
1290 
1291 		return 0;
1292 	}
1293 
1294 	/* Rate unit is 100 kbps */
1295 	rate = DIV_ROUND_UP(cbs_qopt->idleslope, 100);
1296 	/* Avoid using zero rate */
1297 	rate = clamp_t(u32, rate, 1, GENMASK(14, 0));
1298 	/* Burst unit is 4kB */
1299 	burst = DIV_ROUND_UP(cbs_qopt->hicredit, 4096);
1300 	/* Avoid using zero burst size */
1301 	burst = clamp_t(u32, burst, 1, GENMASK(5, 0));
1302 	ocelot_write_gix(ocelot,
1303 			 QSYS_CIR_CFG_CIR_RATE(rate) |
1304 			 QSYS_CIR_CFG_CIR_BURST(burst),
1305 			 QSYS_CIR_CFG,
1306 			 port_ix);
1307 
1308 	ocelot_rmw_gix(ocelot,
1309 		       QSYS_SE_CFG_SE_FRM_MODE(0) |
1310 		       QSYS_SE_CFG_SE_AVB_ENA,
1311 		       QSYS_SE_CFG_SE_AVB_ENA |
1312 		       QSYS_SE_CFG_SE_FRM_MODE_M,
1313 		       QSYS_SE_CFG,
1314 		       port_ix);
1315 
1316 	return 0;
1317 }
1318 
1319 static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port,
1320 				 enum tc_setup_type type,
1321 				 void *type_data)
1322 {
1323 	struct ocelot *ocelot = ds->priv;
1324 
1325 	switch (type) {
1326 	case TC_SETUP_QDISC_TAPRIO:
1327 		return vsc9959_qos_port_tas_set(ocelot, port, type_data);
1328 	case TC_SETUP_QDISC_CBS:
1329 		return vsc9959_qos_port_cbs_set(ds, port, type_data);
1330 	default:
1331 		return -EOPNOTSUPP;
1332 	}
1333 }
1334 
1335 #define VSC9959_PSFP_SFID_MAX			175
1336 #define VSC9959_PSFP_GATE_ID_MAX		183
1337 #define VSC9959_PSFP_POLICER_BASE		63
1338 #define VSC9959_PSFP_POLICER_MAX		383
1339 #define VSC9959_PSFP_GATE_LIST_NUM		4
1340 #define VSC9959_PSFP_GATE_CYCLETIME_MIN		5000
1341 
1342 struct felix_stream {
1343 	struct list_head list;
1344 	unsigned long id;
1345 	bool dummy;
1346 	int ports;
1347 	int port;
1348 	u8 dmac[ETH_ALEN];
1349 	u16 vid;
1350 	s8 prio;
1351 	u8 sfid_valid;
1352 	u8 ssid_valid;
1353 	u32 sfid;
1354 	u32 ssid;
1355 };
1356 
1357 struct felix_stream_filter {
1358 	struct list_head list;
1359 	refcount_t refcount;
1360 	u32 index;
1361 	u8 enable;
1362 	int portmask;
1363 	u8 sg_valid;
1364 	u32 sgid;
1365 	u8 fm_valid;
1366 	u32 fmid;
1367 	u8 prio_valid;
1368 	u8 prio;
1369 	u32 maxsdu;
1370 };
1371 
1372 struct felix_stream_filter_counters {
1373 	u32 match;
1374 	u32 not_pass_gate;
1375 	u32 not_pass_sdu;
1376 	u32 red;
1377 };
1378 
1379 struct felix_stream_gate {
1380 	u32 index;
1381 	u8 enable;
1382 	u8 ipv_valid;
1383 	u8 init_ipv;
1384 	u64 basetime;
1385 	u64 cycletime;
1386 	u64 cycletime_ext;
1387 	u32 num_entries;
1388 	struct action_gate_entry entries[];
1389 };
1390 
1391 struct felix_stream_gate_entry {
1392 	struct list_head list;
1393 	refcount_t refcount;
1394 	u32 index;
1395 };
1396 
1397 static int vsc9959_stream_identify(struct flow_cls_offload *f,
1398 				   struct felix_stream *stream)
1399 {
1400 	struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1401 	struct flow_dissector *dissector = rule->match.dissector;
1402 
1403 	if (dissector->used_keys &
1404 	    ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1405 	      BIT(FLOW_DISSECTOR_KEY_BASIC) |
1406 	      BIT(FLOW_DISSECTOR_KEY_VLAN) |
1407 	      BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS)))
1408 		return -EOPNOTSUPP;
1409 
1410 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1411 		struct flow_match_eth_addrs match;
1412 
1413 		flow_rule_match_eth_addrs(rule, &match);
1414 		ether_addr_copy(stream->dmac, match.key->dst);
1415 		if (!is_zero_ether_addr(match.mask->src))
1416 			return -EOPNOTSUPP;
1417 	} else {
1418 		return -EOPNOTSUPP;
1419 	}
1420 
1421 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
1422 		struct flow_match_vlan match;
1423 
1424 		flow_rule_match_vlan(rule, &match);
1425 		if (match.mask->vlan_priority)
1426 			stream->prio = match.key->vlan_priority;
1427 		else
1428 			stream->prio = -1;
1429 
1430 		if (!match.mask->vlan_id)
1431 			return -EOPNOTSUPP;
1432 		stream->vid = match.key->vlan_id;
1433 	} else {
1434 		return -EOPNOTSUPP;
1435 	}
1436 
1437 	stream->id = f->cookie;
1438 
1439 	return 0;
1440 }
1441 
1442 static int vsc9959_mact_stream_set(struct ocelot *ocelot,
1443 				   struct felix_stream *stream,
1444 				   struct netlink_ext_ack *extack)
1445 {
1446 	enum macaccess_entry_type type;
1447 	int ret, sfid, ssid;
1448 	u32 vid, dst_idx;
1449 	u8 mac[ETH_ALEN];
1450 
1451 	ether_addr_copy(mac, stream->dmac);
1452 	vid = stream->vid;
1453 
1454 	/* Stream identification desn't support to add a stream with non
1455 	 * existent MAC (The MAC entry has not been learned in MAC table).
1456 	 */
1457 	ret = ocelot_mact_lookup(ocelot, &dst_idx, mac, vid, &type);
1458 	if (ret) {
1459 		if (extack)
1460 			NL_SET_ERR_MSG_MOD(extack, "Stream is not learned in MAC table");
1461 		return -EOPNOTSUPP;
1462 	}
1463 
1464 	if ((stream->sfid_valid || stream->ssid_valid) &&
1465 	    type == ENTRYTYPE_NORMAL)
1466 		type = ENTRYTYPE_LOCKED;
1467 
1468 	sfid = stream->sfid_valid ? stream->sfid : -1;
1469 	ssid = stream->ssid_valid ? stream->ssid : -1;
1470 
1471 	ret = ocelot_mact_learn_streamdata(ocelot, dst_idx, mac, vid, type,
1472 					   sfid, ssid);
1473 
1474 	return ret;
1475 }
1476 
1477 static struct felix_stream *
1478 vsc9959_stream_table_lookup(struct list_head *stream_list,
1479 			    struct felix_stream *stream)
1480 {
1481 	struct felix_stream *tmp;
1482 
1483 	list_for_each_entry(tmp, stream_list, list)
1484 		if (ether_addr_equal(tmp->dmac, stream->dmac) &&
1485 		    tmp->vid == stream->vid)
1486 			return tmp;
1487 
1488 	return NULL;
1489 }
1490 
1491 static int vsc9959_stream_table_add(struct ocelot *ocelot,
1492 				    struct list_head *stream_list,
1493 				    struct felix_stream *stream,
1494 				    struct netlink_ext_ack *extack)
1495 {
1496 	struct felix_stream *stream_entry;
1497 	int ret;
1498 
1499 	stream_entry = kmemdup(stream, sizeof(*stream_entry), GFP_KERNEL);
1500 	if (!stream_entry)
1501 		return -ENOMEM;
1502 
1503 	if (!stream->dummy) {
1504 		ret = vsc9959_mact_stream_set(ocelot, stream_entry, extack);
1505 		if (ret) {
1506 			kfree(stream_entry);
1507 			return ret;
1508 		}
1509 	}
1510 
1511 	list_add_tail(&stream_entry->list, stream_list);
1512 
1513 	return 0;
1514 }
1515 
1516 static struct felix_stream *
1517 vsc9959_stream_table_get(struct list_head *stream_list, unsigned long id)
1518 {
1519 	struct felix_stream *tmp;
1520 
1521 	list_for_each_entry(tmp, stream_list, list)
1522 		if (tmp->id == id)
1523 			return tmp;
1524 
1525 	return NULL;
1526 }
1527 
1528 static void vsc9959_stream_table_del(struct ocelot *ocelot,
1529 				     struct felix_stream *stream)
1530 {
1531 	if (!stream->dummy)
1532 		vsc9959_mact_stream_set(ocelot, stream, NULL);
1533 
1534 	list_del(&stream->list);
1535 	kfree(stream);
1536 }
1537 
1538 static u32 vsc9959_sfi_access_status(struct ocelot *ocelot)
1539 {
1540 	return ocelot_read(ocelot, ANA_TABLES_SFIDACCESS);
1541 }
1542 
1543 static int vsc9959_psfp_sfi_set(struct ocelot *ocelot,
1544 				struct felix_stream_filter *sfi)
1545 {
1546 	u32 val;
1547 
1548 	if (sfi->index > VSC9959_PSFP_SFID_MAX)
1549 		return -EINVAL;
1550 
1551 	if (!sfi->enable) {
1552 		ocelot_write(ocelot, ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index),
1553 			     ANA_TABLES_SFIDTIDX);
1554 
1555 		val = ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE);
1556 		ocelot_write(ocelot, val, ANA_TABLES_SFIDACCESS);
1557 
1558 		return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,
1559 					  (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)),
1560 					  10, 100000);
1561 	}
1562 
1563 	if (sfi->sgid > VSC9959_PSFP_GATE_ID_MAX ||
1564 	    sfi->fmid > VSC9959_PSFP_POLICER_MAX)
1565 		return -EINVAL;
1566 
1567 	ocelot_write(ocelot,
1568 		     (sfi->sg_valid ? ANA_TABLES_SFIDTIDX_SGID_VALID : 0) |
1569 		     ANA_TABLES_SFIDTIDX_SGID(sfi->sgid) |
1570 		     (sfi->fm_valid ? ANA_TABLES_SFIDTIDX_POL_ENA : 0) |
1571 		     ANA_TABLES_SFIDTIDX_POL_IDX(sfi->fmid) |
1572 		     ANA_TABLES_SFIDTIDX_SFID_INDEX(sfi->index),
1573 		     ANA_TABLES_SFIDTIDX);
1574 
1575 	ocelot_write(ocelot,
1576 		     (sfi->prio_valid ? ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA : 0) |
1577 		     ANA_TABLES_SFIDACCESS_IGR_PRIO(sfi->prio) |
1578 		     ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(sfi->maxsdu) |
1579 		     ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE),
1580 		     ANA_TABLES_SFIDACCESS);
1581 
1582 	return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,
1583 				  (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)),
1584 				  10, 100000);
1585 }
1586 
1587 static int vsc9959_psfp_sfidmask_set(struct ocelot *ocelot, u32 sfid, int ports)
1588 {
1589 	u32 val;
1590 
1591 	ocelot_rmw(ocelot,
1592 		   ANA_TABLES_SFIDTIDX_SFID_INDEX(sfid),
1593 		   ANA_TABLES_SFIDTIDX_SFID_INDEX_M,
1594 		   ANA_TABLES_SFIDTIDX);
1595 
1596 	ocelot_write(ocelot,
1597 		     ANA_TABLES_SFID_MASK_IGR_PORT_MASK(ports) |
1598 		     ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA,
1599 		     ANA_TABLES_SFID_MASK);
1600 
1601 	ocelot_rmw(ocelot,
1602 		   ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(SFIDACCESS_CMD_WRITE),
1603 		   ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M,
1604 		   ANA_TABLES_SFIDACCESS);
1605 
1606 	return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,
1607 				  (!ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(val)),
1608 				  10, 100000);
1609 }
1610 
1611 static int vsc9959_psfp_sfi_list_add(struct ocelot *ocelot,
1612 				     struct felix_stream_filter *sfi,
1613 				     struct list_head *pos)
1614 {
1615 	struct felix_stream_filter *sfi_entry;
1616 	int ret;
1617 
1618 	sfi_entry = kmemdup(sfi, sizeof(*sfi_entry), GFP_KERNEL);
1619 	if (!sfi_entry)
1620 		return -ENOMEM;
1621 
1622 	refcount_set(&sfi_entry->refcount, 1);
1623 
1624 	ret = vsc9959_psfp_sfi_set(ocelot, sfi_entry);
1625 	if (ret) {
1626 		kfree(sfi_entry);
1627 		return ret;
1628 	}
1629 
1630 	vsc9959_psfp_sfidmask_set(ocelot, sfi->index, sfi->portmask);
1631 
1632 	list_add(&sfi_entry->list, pos);
1633 
1634 	return 0;
1635 }
1636 
1637 static int vsc9959_psfp_sfi_table_add(struct ocelot *ocelot,
1638 				      struct felix_stream_filter *sfi)
1639 {
1640 	struct list_head *pos, *q, *last;
1641 	struct felix_stream_filter *tmp;
1642 	struct ocelot_psfp_list *psfp;
1643 	u32 insert = 0;
1644 
1645 	psfp = &ocelot->psfp;
1646 	last = &psfp->sfi_list;
1647 
1648 	list_for_each_safe(pos, q, &psfp->sfi_list) {
1649 		tmp = list_entry(pos, struct felix_stream_filter, list);
1650 		if (sfi->sg_valid == tmp->sg_valid &&
1651 		    sfi->fm_valid == tmp->fm_valid &&
1652 		    sfi->portmask == tmp->portmask &&
1653 		    tmp->sgid == sfi->sgid &&
1654 		    tmp->fmid == sfi->fmid) {
1655 			sfi->index = tmp->index;
1656 			refcount_inc(&tmp->refcount);
1657 			return 0;
1658 		}
1659 		/* Make sure that the index is increasing in order. */
1660 		if (tmp->index == insert) {
1661 			last = pos;
1662 			insert++;
1663 		}
1664 	}
1665 	sfi->index = insert;
1666 
1667 	return vsc9959_psfp_sfi_list_add(ocelot, sfi, last);
1668 }
1669 
1670 static int vsc9959_psfp_sfi_table_add2(struct ocelot *ocelot,
1671 				       struct felix_stream_filter *sfi,
1672 				       struct felix_stream_filter *sfi2)
1673 {
1674 	struct felix_stream_filter *tmp;
1675 	struct list_head *pos, *q, *last;
1676 	struct ocelot_psfp_list *psfp;
1677 	u32 insert = 0;
1678 	int ret;
1679 
1680 	psfp = &ocelot->psfp;
1681 	last = &psfp->sfi_list;
1682 
1683 	list_for_each_safe(pos, q, &psfp->sfi_list) {
1684 		tmp = list_entry(pos, struct felix_stream_filter, list);
1685 		/* Make sure that the index is increasing in order. */
1686 		if (tmp->index >= insert + 2)
1687 			break;
1688 
1689 		insert = tmp->index + 1;
1690 		last = pos;
1691 	}
1692 	sfi->index = insert;
1693 
1694 	ret = vsc9959_psfp_sfi_list_add(ocelot, sfi, last);
1695 	if (ret)
1696 		return ret;
1697 
1698 	sfi2->index = insert + 1;
1699 
1700 	return vsc9959_psfp_sfi_list_add(ocelot, sfi2, last->next);
1701 }
1702 
1703 static struct felix_stream_filter *
1704 vsc9959_psfp_sfi_table_get(struct list_head *sfi_list, u32 index)
1705 {
1706 	struct felix_stream_filter *tmp;
1707 
1708 	list_for_each_entry(tmp, sfi_list, list)
1709 		if (tmp->index == index)
1710 			return tmp;
1711 
1712 	return NULL;
1713 }
1714 
1715 static void vsc9959_psfp_sfi_table_del(struct ocelot *ocelot, u32 index)
1716 {
1717 	struct felix_stream_filter *tmp, *n;
1718 	struct ocelot_psfp_list *psfp;
1719 	u8 z;
1720 
1721 	psfp = &ocelot->psfp;
1722 
1723 	list_for_each_entry_safe(tmp, n, &psfp->sfi_list, list)
1724 		if (tmp->index == index) {
1725 			z = refcount_dec_and_test(&tmp->refcount);
1726 			if (z) {
1727 				tmp->enable = 0;
1728 				vsc9959_psfp_sfi_set(ocelot, tmp);
1729 				list_del(&tmp->list);
1730 				kfree(tmp);
1731 			}
1732 			break;
1733 		}
1734 }
1735 
1736 static void vsc9959_psfp_parse_gate(const struct flow_action_entry *entry,
1737 				    struct felix_stream_gate *sgi)
1738 {
1739 	sgi->index = entry->hw_index;
1740 	sgi->ipv_valid = (entry->gate.prio < 0) ? 0 : 1;
1741 	sgi->init_ipv = (sgi->ipv_valid) ? entry->gate.prio : 0;
1742 	sgi->basetime = entry->gate.basetime;
1743 	sgi->cycletime = entry->gate.cycletime;
1744 	sgi->num_entries = entry->gate.num_entries;
1745 	sgi->enable = 1;
1746 
1747 	memcpy(sgi->entries, entry->gate.entries,
1748 	       entry->gate.num_entries * sizeof(struct action_gate_entry));
1749 }
1750 
1751 static u32 vsc9959_sgi_cfg_status(struct ocelot *ocelot)
1752 {
1753 	return ocelot_read(ocelot, ANA_SG_ACCESS_CTRL);
1754 }
1755 
1756 static int vsc9959_psfp_sgi_set(struct ocelot *ocelot,
1757 				struct felix_stream_gate *sgi)
1758 {
1759 	struct action_gate_entry *e;
1760 	struct timespec64 base_ts;
1761 	u32 interval_sum = 0;
1762 	u32 val;
1763 	int i;
1764 
1765 	if (sgi->index > VSC9959_PSFP_GATE_ID_MAX)
1766 		return -EINVAL;
1767 
1768 	ocelot_write(ocelot, ANA_SG_ACCESS_CTRL_SGID(sgi->index),
1769 		     ANA_SG_ACCESS_CTRL);
1770 
1771 	if (!sgi->enable) {
1772 		ocelot_rmw(ocelot, ANA_SG_CONFIG_REG_3_INIT_GATE_STATE,
1773 			   ANA_SG_CONFIG_REG_3_INIT_GATE_STATE |
1774 			   ANA_SG_CONFIG_REG_3_GATE_ENABLE,
1775 			   ANA_SG_CONFIG_REG_3);
1776 
1777 		return 0;
1778 	}
1779 
1780 	if (sgi->cycletime < VSC9959_PSFP_GATE_CYCLETIME_MIN ||
1781 	    sgi->cycletime > NSEC_PER_SEC)
1782 		return -EINVAL;
1783 
1784 	if (sgi->num_entries > VSC9959_PSFP_GATE_LIST_NUM)
1785 		return -EINVAL;
1786 
1787 	vsc9959_new_base_time(ocelot, sgi->basetime, sgi->cycletime, &base_ts);
1788 	ocelot_write(ocelot, base_ts.tv_nsec, ANA_SG_CONFIG_REG_1);
1789 	val = lower_32_bits(base_ts.tv_sec);
1790 	ocelot_write(ocelot, val, ANA_SG_CONFIG_REG_2);
1791 
1792 	val = upper_32_bits(base_ts.tv_sec);
1793 	ocelot_write(ocelot,
1794 		     (sgi->ipv_valid ? ANA_SG_CONFIG_REG_3_IPV_VALID : 0) |
1795 		     ANA_SG_CONFIG_REG_3_INIT_IPV(sgi->init_ipv) |
1796 		     ANA_SG_CONFIG_REG_3_GATE_ENABLE |
1797 		     ANA_SG_CONFIG_REG_3_LIST_LENGTH(sgi->num_entries) |
1798 		     ANA_SG_CONFIG_REG_3_INIT_GATE_STATE |
1799 		     ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(val),
1800 		     ANA_SG_CONFIG_REG_3);
1801 
1802 	ocelot_write(ocelot, sgi->cycletime, ANA_SG_CONFIG_REG_4);
1803 
1804 	e = sgi->entries;
1805 	for (i = 0; i < sgi->num_entries; i++) {
1806 		u32 ips = (e[i].ipv < 0) ? 0 : (e[i].ipv + 8);
1807 
1808 		ocelot_write_rix(ocelot, ANA_SG_GCL_GS_CONFIG_IPS(ips) |
1809 				 (e[i].gate_state ?
1810 				  ANA_SG_GCL_GS_CONFIG_GATE_STATE : 0),
1811 				 ANA_SG_GCL_GS_CONFIG, i);
1812 
1813 		interval_sum += e[i].interval;
1814 		ocelot_write_rix(ocelot, interval_sum, ANA_SG_GCL_TI_CONFIG, i);
1815 	}
1816 
1817 	ocelot_rmw(ocelot, ANA_SG_ACCESS_CTRL_CONFIG_CHANGE,
1818 		   ANA_SG_ACCESS_CTRL_CONFIG_CHANGE,
1819 		   ANA_SG_ACCESS_CTRL);
1820 
1821 	return readx_poll_timeout(vsc9959_sgi_cfg_status, ocelot, val,
1822 				  (!(ANA_SG_ACCESS_CTRL_CONFIG_CHANGE & val)),
1823 				  10, 100000);
1824 }
1825 
1826 static int vsc9959_psfp_sgi_table_add(struct ocelot *ocelot,
1827 				      struct felix_stream_gate *sgi)
1828 {
1829 	struct felix_stream_gate_entry *tmp;
1830 	struct ocelot_psfp_list *psfp;
1831 	int ret;
1832 
1833 	psfp = &ocelot->psfp;
1834 
1835 	list_for_each_entry(tmp, &psfp->sgi_list, list)
1836 		if (tmp->index == sgi->index) {
1837 			refcount_inc(&tmp->refcount);
1838 			return 0;
1839 		}
1840 
1841 	tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
1842 	if (!tmp)
1843 		return -ENOMEM;
1844 
1845 	ret = vsc9959_psfp_sgi_set(ocelot, sgi);
1846 	if (ret) {
1847 		kfree(tmp);
1848 		return ret;
1849 	}
1850 
1851 	tmp->index = sgi->index;
1852 	refcount_set(&tmp->refcount, 1);
1853 	list_add_tail(&tmp->list, &psfp->sgi_list);
1854 
1855 	return 0;
1856 }
1857 
1858 static void vsc9959_psfp_sgi_table_del(struct ocelot *ocelot,
1859 				       u32 index)
1860 {
1861 	struct felix_stream_gate_entry *tmp, *n;
1862 	struct felix_stream_gate sgi = {0};
1863 	struct ocelot_psfp_list *psfp;
1864 	u8 z;
1865 
1866 	psfp = &ocelot->psfp;
1867 
1868 	list_for_each_entry_safe(tmp, n, &psfp->sgi_list, list)
1869 		if (tmp->index == index) {
1870 			z = refcount_dec_and_test(&tmp->refcount);
1871 			if (z) {
1872 				sgi.index = index;
1873 				sgi.enable = 0;
1874 				vsc9959_psfp_sgi_set(ocelot, &sgi);
1875 				list_del(&tmp->list);
1876 				kfree(tmp);
1877 			}
1878 			break;
1879 		}
1880 }
1881 
1882 static void vsc9959_psfp_counters_get(struct ocelot *ocelot, u32 index,
1883 				      struct felix_stream_filter_counters *counters)
1884 {
1885 	ocelot_rmw(ocelot, SYS_STAT_CFG_STAT_VIEW(index),
1886 		   SYS_STAT_CFG_STAT_VIEW_M,
1887 		   SYS_STAT_CFG);
1888 
1889 	counters->match = ocelot_read_gix(ocelot, SYS_CNT, 0x200);
1890 	counters->not_pass_gate = ocelot_read_gix(ocelot, SYS_CNT, 0x201);
1891 	counters->not_pass_sdu = ocelot_read_gix(ocelot, SYS_CNT, 0x202);
1892 	counters->red = ocelot_read_gix(ocelot, SYS_CNT, 0x203);
1893 
1894 	/* Clear the PSFP counter. */
1895 	ocelot_write(ocelot,
1896 		     SYS_STAT_CFG_STAT_VIEW(index) |
1897 		     SYS_STAT_CFG_STAT_CLEAR_SHOT(0x10),
1898 		     SYS_STAT_CFG);
1899 }
1900 
1901 static int vsc9959_psfp_filter_add(struct ocelot *ocelot, int port,
1902 				   struct flow_cls_offload *f)
1903 {
1904 	struct netlink_ext_ack *extack = f->common.extack;
1905 	struct felix_stream_filter old_sfi, *sfi_entry;
1906 	struct felix_stream_filter sfi = {0};
1907 	const struct flow_action_entry *a;
1908 	struct felix_stream *stream_entry;
1909 	struct felix_stream stream = {0};
1910 	struct felix_stream_gate *sgi;
1911 	struct ocelot_psfp_list *psfp;
1912 	struct ocelot_policer pol;
1913 	int ret, i, size;
1914 	u64 rate, burst;
1915 	u32 index;
1916 
1917 	psfp = &ocelot->psfp;
1918 
1919 	ret = vsc9959_stream_identify(f, &stream);
1920 	if (ret) {
1921 		NL_SET_ERR_MSG_MOD(extack, "Only can match on VID, PCP, and dest MAC");
1922 		return ret;
1923 	}
1924 
1925 	flow_action_for_each(i, a, &f->rule->action) {
1926 		switch (a->id) {
1927 		case FLOW_ACTION_GATE:
1928 			size = struct_size(sgi, entries, a->gate.num_entries);
1929 			sgi = kzalloc(size, GFP_KERNEL);
1930 			vsc9959_psfp_parse_gate(a, sgi);
1931 			ret = vsc9959_psfp_sgi_table_add(ocelot, sgi);
1932 			if (ret) {
1933 				kfree(sgi);
1934 				goto err;
1935 			}
1936 			sfi.sg_valid = 1;
1937 			sfi.sgid = sgi->index;
1938 			kfree(sgi);
1939 			break;
1940 		case FLOW_ACTION_POLICE:
1941 			index = a->hw_index + VSC9959_PSFP_POLICER_BASE;
1942 			if (index > VSC9959_PSFP_POLICER_MAX) {
1943 				ret = -EINVAL;
1944 				goto err;
1945 			}
1946 
1947 			rate = a->police.rate_bytes_ps;
1948 			burst = rate * PSCHED_NS2TICKS(a->police.burst);
1949 			pol = (struct ocelot_policer) {
1950 				.burst = div_u64(burst, PSCHED_TICKS_PER_SEC),
1951 				.rate = div_u64(rate, 1000) * 8,
1952 			};
1953 			ret = ocelot_vcap_policer_add(ocelot, index, &pol);
1954 			if (ret)
1955 				goto err;
1956 
1957 			sfi.fm_valid = 1;
1958 			sfi.fmid = index;
1959 			sfi.maxsdu = a->police.mtu;
1960 			break;
1961 		default:
1962 			return -EOPNOTSUPP;
1963 		}
1964 	}
1965 
1966 	stream.ports = BIT(port);
1967 	stream.port = port;
1968 
1969 	sfi.portmask = stream.ports;
1970 	sfi.prio_valid = (stream.prio < 0 ? 0 : 1);
1971 	sfi.prio = (sfi.prio_valid ? stream.prio : 0);
1972 	sfi.enable = 1;
1973 
1974 	/* Check if stream is set. */
1975 	stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &stream);
1976 	if (stream_entry) {
1977 		if (stream_entry->ports & BIT(port)) {
1978 			NL_SET_ERR_MSG_MOD(extack,
1979 					   "The stream is added on this port");
1980 			ret = -EEXIST;
1981 			goto err;
1982 		}
1983 
1984 		if (stream_entry->ports != BIT(stream_entry->port)) {
1985 			NL_SET_ERR_MSG_MOD(extack,
1986 					   "The stream is added on two ports");
1987 			ret = -EEXIST;
1988 			goto err;
1989 		}
1990 
1991 		stream_entry->ports |= BIT(port);
1992 		stream.ports = stream_entry->ports;
1993 
1994 		sfi_entry = vsc9959_psfp_sfi_table_get(&psfp->sfi_list,
1995 						       stream_entry->sfid);
1996 		memcpy(&old_sfi, sfi_entry, sizeof(old_sfi));
1997 
1998 		vsc9959_psfp_sfi_table_del(ocelot, stream_entry->sfid);
1999 
2000 		old_sfi.portmask = stream_entry->ports;
2001 		sfi.portmask = stream.ports;
2002 
2003 		if (stream_entry->port > port) {
2004 			ret = vsc9959_psfp_sfi_table_add2(ocelot, &sfi,
2005 							  &old_sfi);
2006 			stream_entry->dummy = true;
2007 		} else {
2008 			ret = vsc9959_psfp_sfi_table_add2(ocelot, &old_sfi,
2009 							  &sfi);
2010 			stream.dummy = true;
2011 		}
2012 		if (ret)
2013 			goto err;
2014 
2015 		stream_entry->sfid = old_sfi.index;
2016 	} else {
2017 		ret = vsc9959_psfp_sfi_table_add(ocelot, &sfi);
2018 		if (ret)
2019 			goto err;
2020 	}
2021 
2022 	stream.sfid = sfi.index;
2023 	stream.sfid_valid = 1;
2024 	ret = vsc9959_stream_table_add(ocelot, &psfp->stream_list,
2025 				       &stream, extack);
2026 	if (ret) {
2027 		vsc9959_psfp_sfi_table_del(ocelot, stream.sfid);
2028 		goto err;
2029 	}
2030 
2031 	return 0;
2032 
2033 err:
2034 	if (sfi.sg_valid)
2035 		vsc9959_psfp_sgi_table_del(ocelot, sfi.sgid);
2036 
2037 	if (sfi.fm_valid)
2038 		ocelot_vcap_policer_del(ocelot, sfi.fmid);
2039 
2040 	return ret;
2041 }
2042 
2043 static int vsc9959_psfp_filter_del(struct ocelot *ocelot,
2044 				   struct flow_cls_offload *f)
2045 {
2046 	struct felix_stream *stream, tmp, *stream_entry;
2047 	static struct felix_stream_filter *sfi;
2048 	struct ocelot_psfp_list *psfp;
2049 
2050 	psfp = &ocelot->psfp;
2051 
2052 	stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie);
2053 	if (!stream)
2054 		return -ENOMEM;
2055 
2056 	sfi = vsc9959_psfp_sfi_table_get(&psfp->sfi_list, stream->sfid);
2057 	if (!sfi)
2058 		return -ENOMEM;
2059 
2060 	if (sfi->sg_valid)
2061 		vsc9959_psfp_sgi_table_del(ocelot, sfi->sgid);
2062 
2063 	if (sfi->fm_valid)
2064 		ocelot_vcap_policer_del(ocelot, sfi->fmid);
2065 
2066 	vsc9959_psfp_sfi_table_del(ocelot, stream->sfid);
2067 
2068 	memcpy(&tmp, stream, sizeof(tmp));
2069 
2070 	stream->sfid_valid = 0;
2071 	vsc9959_stream_table_del(ocelot, stream);
2072 
2073 	stream_entry = vsc9959_stream_table_lookup(&psfp->stream_list, &tmp);
2074 	if (stream_entry) {
2075 		stream_entry->ports = BIT(stream_entry->port);
2076 		if (stream_entry->dummy) {
2077 			stream_entry->dummy = false;
2078 			vsc9959_mact_stream_set(ocelot, stream_entry, NULL);
2079 		}
2080 		vsc9959_psfp_sfidmask_set(ocelot, stream_entry->sfid,
2081 					  stream_entry->ports);
2082 	}
2083 
2084 	return 0;
2085 }
2086 
2087 static int vsc9959_psfp_stats_get(struct ocelot *ocelot,
2088 				  struct flow_cls_offload *f,
2089 				  struct flow_stats *stats)
2090 {
2091 	struct felix_stream_filter_counters counters;
2092 	struct ocelot_psfp_list *psfp;
2093 	struct felix_stream *stream;
2094 
2095 	psfp = &ocelot->psfp;
2096 	stream = vsc9959_stream_table_get(&psfp->stream_list, f->cookie);
2097 	if (!stream)
2098 		return -ENOMEM;
2099 
2100 	vsc9959_psfp_counters_get(ocelot, stream->sfid, &counters);
2101 
2102 	stats->pkts = counters.match;
2103 	stats->drops = counters.not_pass_gate + counters.not_pass_sdu +
2104 		       counters.red;
2105 
2106 	return 0;
2107 }
2108 
2109 static void vsc9959_psfp_init(struct ocelot *ocelot)
2110 {
2111 	struct ocelot_psfp_list *psfp = &ocelot->psfp;
2112 
2113 	INIT_LIST_HEAD(&psfp->stream_list);
2114 	INIT_LIST_HEAD(&psfp->sfi_list);
2115 	INIT_LIST_HEAD(&psfp->sgi_list);
2116 }
2117 
2118 /* When using cut-through forwarding and the egress port runs at a higher data
2119  * rate than the ingress port, the packet currently under transmission would
2120  * suffer an underrun since it would be transmitted faster than it is received.
2121  * The Felix switch implementation of cut-through forwarding does not check in
2122  * hardware whether this condition is satisfied or not, so we must restrict the
2123  * list of ports that have cut-through forwarding enabled on egress to only be
2124  * the ports operating at the lowest link speed within their respective
2125  * forwarding domain.
2126  */
2127 static void vsc9959_cut_through_fwd(struct ocelot *ocelot)
2128 {
2129 	struct felix *felix = ocelot_to_felix(ocelot);
2130 	struct dsa_switch *ds = felix->ds;
2131 	int port, other_port;
2132 
2133 	lockdep_assert_held(&ocelot->fwd_domain_lock);
2134 
2135 	for (port = 0; port < ocelot->num_phys_ports; port++) {
2136 		struct ocelot_port *ocelot_port = ocelot->ports[port];
2137 		int min_speed = ocelot_port->speed;
2138 		unsigned long mask = 0;
2139 		u32 tmp, val = 0;
2140 
2141 		/* Disable cut-through on ports that are down */
2142 		if (ocelot_port->speed <= 0)
2143 			goto set;
2144 
2145 		if (dsa_is_cpu_port(ds, port)) {
2146 			/* Ocelot switches forward from the NPI port towards
2147 			 * any port, regardless of it being in the NPI port's
2148 			 * forwarding domain or not.
2149 			 */
2150 			mask = dsa_user_ports(ds);
2151 		} else {
2152 			mask = ocelot_get_bridge_fwd_mask(ocelot, port);
2153 			mask &= ~BIT(port);
2154 			if (ocelot->npi >= 0)
2155 				mask |= BIT(ocelot->npi);
2156 			else
2157 				mask |= ocelot_get_dsa_8021q_cpu_mask(ocelot);
2158 		}
2159 
2160 		/* Calculate the minimum link speed, among the ports that are
2161 		 * up, of this source port's forwarding domain.
2162 		 */
2163 		for_each_set_bit(other_port, &mask, ocelot->num_phys_ports) {
2164 			struct ocelot_port *other_ocelot_port;
2165 
2166 			other_ocelot_port = ocelot->ports[other_port];
2167 			if (other_ocelot_port->speed <= 0)
2168 				continue;
2169 
2170 			if (min_speed > other_ocelot_port->speed)
2171 				min_speed = other_ocelot_port->speed;
2172 		}
2173 
2174 		/* Enable cut-through forwarding for all traffic classes. */
2175 		if (ocelot_port->speed == min_speed)
2176 			val = GENMASK(7, 0);
2177 
2178 set:
2179 		tmp = ocelot_read_rix(ocelot, ANA_CUT_THRU_CFG, port);
2180 		if (tmp == val)
2181 			continue;
2182 
2183 		dev_dbg(ocelot->dev,
2184 			"port %d fwd mask 0x%lx speed %d min_speed %d, %s cut-through forwarding\n",
2185 			port, mask, ocelot_port->speed, min_speed,
2186 			val ? "enabling" : "disabling");
2187 
2188 		ocelot_write_rix(ocelot, val, ANA_CUT_THRU_CFG, port);
2189 	}
2190 }
2191 
2192 static const struct ocelot_ops vsc9959_ops = {
2193 	.reset			= vsc9959_reset,
2194 	.wm_enc			= vsc9959_wm_enc,
2195 	.wm_dec			= vsc9959_wm_dec,
2196 	.wm_stat		= vsc9959_wm_stat,
2197 	.port_to_netdev		= felix_port_to_netdev,
2198 	.netdev_to_port		= felix_netdev_to_port,
2199 	.psfp_init		= vsc9959_psfp_init,
2200 	.psfp_filter_add	= vsc9959_psfp_filter_add,
2201 	.psfp_filter_del	= vsc9959_psfp_filter_del,
2202 	.psfp_stats_get		= vsc9959_psfp_stats_get,
2203 	.cut_through_fwd	= vsc9959_cut_through_fwd,
2204 };
2205 
2206 static const struct felix_info felix_info_vsc9959 = {
2207 	.target_io_res		= vsc9959_target_io_res,
2208 	.port_io_res		= vsc9959_port_io_res,
2209 	.imdio_res		= &vsc9959_imdio_res,
2210 	.regfields		= vsc9959_regfields,
2211 	.map			= vsc9959_regmap,
2212 	.ops			= &vsc9959_ops,
2213 	.stats_layout		= vsc9959_stats_layout,
2214 	.num_stats		= ARRAY_SIZE(vsc9959_stats_layout),
2215 	.vcap			= vsc9959_vcap_props,
2216 	.vcap_pol_base		= VSC9959_VCAP_POLICER_BASE,
2217 	.vcap_pol_max		= VSC9959_VCAP_POLICER_MAX,
2218 	.vcap_pol_base2		= 0,
2219 	.vcap_pol_max2		= 0,
2220 	.num_mact_rows		= 2048,
2221 	.num_ports		= VSC9959_NUM_PORTS,
2222 	.num_tx_queues		= OCELOT_NUM_TC,
2223 	.quirk_no_xtr_irq	= true,
2224 	.ptp_caps		= &vsc9959_ptp_caps,
2225 	.mdio_bus_alloc		= vsc9959_mdio_bus_alloc,
2226 	.mdio_bus_free		= vsc9959_mdio_bus_free,
2227 	.phylink_validate	= vsc9959_phylink_validate,
2228 	.port_modes		= vsc9959_port_modes,
2229 	.port_setup_tc		= vsc9959_port_setup_tc,
2230 	.port_sched_speed_set	= vsc9959_sched_speed_set,
2231 	.init_regmap		= ocelot_regmap_init,
2232 };
2233 
2234 static irqreturn_t felix_irq_handler(int irq, void *data)
2235 {
2236 	struct ocelot *ocelot = (struct ocelot *)data;
2237 
2238 	/* The INTB interrupt is used for both PTP TX timestamp interrupt
2239 	 * and preemption status change interrupt on each port.
2240 	 *
2241 	 * - Get txtstamp if have
2242 	 * - TODO: handle preemption. Without handling it, driver may get
2243 	 *   interrupt storm.
2244 	 */
2245 
2246 	ocelot_get_txtstamp(ocelot);
2247 
2248 	return IRQ_HANDLED;
2249 }
2250 
2251 static int felix_pci_probe(struct pci_dev *pdev,
2252 			   const struct pci_device_id *id)
2253 {
2254 	struct dsa_switch *ds;
2255 	struct ocelot *ocelot;
2256 	struct felix *felix;
2257 	int err;
2258 
2259 	if (pdev->dev.of_node && !of_device_is_available(pdev->dev.of_node)) {
2260 		dev_info(&pdev->dev, "device is disabled, skipping\n");
2261 		return -ENODEV;
2262 	}
2263 
2264 	err = pci_enable_device(pdev);
2265 	if (err) {
2266 		dev_err(&pdev->dev, "device enable failed\n");
2267 		goto err_pci_enable;
2268 	}
2269 
2270 	felix = kzalloc(sizeof(struct felix), GFP_KERNEL);
2271 	if (!felix) {
2272 		err = -ENOMEM;
2273 		dev_err(&pdev->dev, "Failed to allocate driver memory\n");
2274 		goto err_alloc_felix;
2275 	}
2276 
2277 	pci_set_drvdata(pdev, felix);
2278 	ocelot = &felix->ocelot;
2279 	ocelot->dev = &pdev->dev;
2280 	ocelot->num_flooding_pgids = OCELOT_NUM_TC;
2281 	felix->info = &felix_info_vsc9959;
2282 	felix->switch_base = pci_resource_start(pdev, VSC9959_SWITCH_PCI_BAR);
2283 	felix->imdio_base = pci_resource_start(pdev, VSC9959_IMDIO_PCI_BAR);
2284 
2285 	pci_set_master(pdev);
2286 
2287 	err = devm_request_threaded_irq(&pdev->dev, pdev->irq, NULL,
2288 					&felix_irq_handler, IRQF_ONESHOT,
2289 					"felix-intb", ocelot);
2290 	if (err) {
2291 		dev_err(&pdev->dev, "Failed to request irq\n");
2292 		goto err_alloc_irq;
2293 	}
2294 
2295 	ocelot->ptp = 1;
2296 
2297 	ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL);
2298 	if (!ds) {
2299 		err = -ENOMEM;
2300 		dev_err(&pdev->dev, "Failed to allocate DSA switch\n");
2301 		goto err_alloc_ds;
2302 	}
2303 
2304 	ds->dev = &pdev->dev;
2305 	ds->num_ports = felix->info->num_ports;
2306 	ds->num_tx_queues = felix->info->num_tx_queues;
2307 	ds->ops = &felix_switch_ops;
2308 	ds->priv = ocelot;
2309 	felix->ds = ds;
2310 	felix->tag_proto = DSA_TAG_PROTO_OCELOT;
2311 
2312 	err = dsa_register_switch(ds);
2313 	if (err) {
2314 		dev_err(&pdev->dev, "Failed to register DSA switch: %d\n", err);
2315 		goto err_register_ds;
2316 	}
2317 
2318 	return 0;
2319 
2320 err_register_ds:
2321 	kfree(ds);
2322 err_alloc_ds:
2323 err_alloc_irq:
2324 	kfree(felix);
2325 err_alloc_felix:
2326 	pci_disable_device(pdev);
2327 err_pci_enable:
2328 	return err;
2329 }
2330 
2331 static void felix_pci_remove(struct pci_dev *pdev)
2332 {
2333 	struct felix *felix = pci_get_drvdata(pdev);
2334 
2335 	if (!felix)
2336 		return;
2337 
2338 	dsa_unregister_switch(felix->ds);
2339 
2340 	kfree(felix->ds);
2341 	kfree(felix);
2342 
2343 	pci_disable_device(pdev);
2344 
2345 	pci_set_drvdata(pdev, NULL);
2346 }
2347 
2348 static void felix_pci_shutdown(struct pci_dev *pdev)
2349 {
2350 	struct felix *felix = pci_get_drvdata(pdev);
2351 
2352 	if (!felix)
2353 		return;
2354 
2355 	dsa_switch_shutdown(felix->ds);
2356 
2357 	pci_set_drvdata(pdev, NULL);
2358 }
2359 
2360 static struct pci_device_id felix_ids[] = {
2361 	{
2362 		/* NXP LS1028A */
2363 		PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0xEEF0),
2364 	},
2365 	{ 0, }
2366 };
2367 MODULE_DEVICE_TABLE(pci, felix_ids);
2368 
2369 static struct pci_driver felix_vsc9959_pci_driver = {
2370 	.name		= "mscc_felix",
2371 	.id_table	= felix_ids,
2372 	.probe		= felix_pci_probe,
2373 	.remove		= felix_pci_remove,
2374 	.shutdown	= felix_pci_shutdown,
2375 };
2376 module_pci_driver(felix_vsc9959_pci_driver);
2377 
2378 MODULE_DESCRIPTION("Felix Switch driver");
2379 MODULE_LICENSE("GPL v2");
2380