1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright 2019-2021 NXP 3 * 4 * This is an umbrella module for all network switches that are 5 * register-compatible with Ocelot and that perform I/O to their host CPU 6 * through an NPI (Node Processor Interface) Ethernet port. 7 */ 8 #include <uapi/linux/if_bridge.h> 9 #include <soc/mscc/ocelot_vcap.h> 10 #include <soc/mscc/ocelot_qsys.h> 11 #include <soc/mscc/ocelot_sys.h> 12 #include <soc/mscc/ocelot_dev.h> 13 #include <soc/mscc/ocelot_ana.h> 14 #include <soc/mscc/ocelot_ptp.h> 15 #include <soc/mscc/ocelot.h> 16 #include <linux/dsa/8021q.h> 17 #include <linux/dsa/ocelot.h> 18 #include <linux/platform_device.h> 19 #include <linux/ptp_classify.h> 20 #include <linux/module.h> 21 #include <linux/of_net.h> 22 #include <linux/pci.h> 23 #include <linux/of.h> 24 #include <net/pkt_sched.h> 25 #include <net/dsa.h> 26 #include "felix.h" 27 28 /* Translate the DSA database API into the ocelot switch library API, 29 * which uses VID 0 for all ports that aren't part of a bridge, 30 * and expects the bridge_dev to be NULL in that case. 31 */ 32 static struct net_device *felix_classify_db(struct dsa_db db) 33 { 34 switch (db.type) { 35 case DSA_DB_PORT: 36 case DSA_DB_LAG: 37 return NULL; 38 case DSA_DB_BRIDGE: 39 return db.bridge.dev; 40 default: 41 return ERR_PTR(-EOPNOTSUPP); 42 } 43 } 44 45 /* We are called before felix_npi_port_init(), so ocelot->npi is -1. */ 46 static int felix_migrate_fdbs_to_npi_port(struct dsa_switch *ds, int port, 47 const unsigned char *addr, u16 vid, 48 struct dsa_db db) 49 { 50 struct net_device *bridge_dev = felix_classify_db(db); 51 struct ocelot *ocelot = ds->priv; 52 int cpu = ocelot->num_phys_ports; 53 int err; 54 55 err = ocelot_fdb_del(ocelot, port, addr, vid, bridge_dev); 56 if (err) 57 return err; 58 59 return ocelot_fdb_add(ocelot, cpu, addr, vid, bridge_dev); 60 } 61 62 static int felix_migrate_mdbs_to_npi_port(struct dsa_switch *ds, int port, 63 const unsigned char *addr, u16 vid, 64 struct dsa_db db) 65 { 66 struct net_device *bridge_dev = felix_classify_db(db); 67 struct switchdev_obj_port_mdb mdb; 68 struct ocelot *ocelot = ds->priv; 69 int cpu = ocelot->num_phys_ports; 70 int err; 71 72 memset(&mdb, 0, sizeof(mdb)); 73 ether_addr_copy(mdb.addr, addr); 74 mdb.vid = vid; 75 76 err = ocelot_port_mdb_del(ocelot, port, &mdb, bridge_dev); 77 if (err) 78 return err; 79 80 return ocelot_port_mdb_add(ocelot, cpu, &mdb, bridge_dev); 81 } 82 83 static void felix_migrate_pgid_bit(struct dsa_switch *ds, int from, int to, 84 int pgid) 85 { 86 struct ocelot *ocelot = ds->priv; 87 bool on; 88 u32 val; 89 90 val = ocelot_read_rix(ocelot, ANA_PGID_PGID, pgid); 91 on = !!(val & BIT(from)); 92 val &= ~BIT(from); 93 if (on) 94 val |= BIT(to); 95 else 96 val &= ~BIT(to); 97 98 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, pgid); 99 } 100 101 static void felix_migrate_flood_to_npi_port(struct dsa_switch *ds, int port) 102 { 103 struct ocelot *ocelot = ds->priv; 104 105 felix_migrate_pgid_bit(ds, port, ocelot->num_phys_ports, PGID_UC); 106 felix_migrate_pgid_bit(ds, port, ocelot->num_phys_ports, PGID_MC); 107 felix_migrate_pgid_bit(ds, port, ocelot->num_phys_ports, PGID_BC); 108 } 109 110 static void 111 felix_migrate_flood_to_tag_8021q_port(struct dsa_switch *ds, int port) 112 { 113 struct ocelot *ocelot = ds->priv; 114 115 felix_migrate_pgid_bit(ds, ocelot->num_phys_ports, port, PGID_UC); 116 felix_migrate_pgid_bit(ds, ocelot->num_phys_ports, port, PGID_MC); 117 felix_migrate_pgid_bit(ds, ocelot->num_phys_ports, port, PGID_BC); 118 } 119 120 /* ocelot->npi was already set to -1 by felix_npi_port_deinit, so 121 * ocelot_fdb_add() will not redirect FDB entries towards the 122 * CPU port module here, which is what we want. 123 */ 124 static int 125 felix_migrate_fdbs_to_tag_8021q_port(struct dsa_switch *ds, int port, 126 const unsigned char *addr, u16 vid, 127 struct dsa_db db) 128 { 129 struct net_device *bridge_dev = felix_classify_db(db); 130 struct ocelot *ocelot = ds->priv; 131 int cpu = ocelot->num_phys_ports; 132 int err; 133 134 err = ocelot_fdb_del(ocelot, cpu, addr, vid, bridge_dev); 135 if (err) 136 return err; 137 138 return ocelot_fdb_add(ocelot, port, addr, vid, bridge_dev); 139 } 140 141 static int 142 felix_migrate_mdbs_to_tag_8021q_port(struct dsa_switch *ds, int port, 143 const unsigned char *addr, u16 vid, 144 struct dsa_db db) 145 { 146 struct net_device *bridge_dev = felix_classify_db(db); 147 struct switchdev_obj_port_mdb mdb; 148 struct ocelot *ocelot = ds->priv; 149 int cpu = ocelot->num_phys_ports; 150 int err; 151 152 memset(&mdb, 0, sizeof(mdb)); 153 ether_addr_copy(mdb.addr, addr); 154 mdb.vid = vid; 155 156 err = ocelot_port_mdb_del(ocelot, cpu, &mdb, bridge_dev); 157 if (err) 158 return err; 159 160 return ocelot_port_mdb_add(ocelot, port, &mdb, bridge_dev); 161 } 162 163 /* Set up VCAP ES0 rules for pushing a tag_8021q VLAN towards the CPU such that 164 * the tagger can perform RX source port identification. 165 */ 166 static int felix_tag_8021q_vlan_add_rx(struct felix *felix, int port, u16 vid) 167 { 168 struct ocelot_vcap_filter *outer_tagging_rule; 169 struct ocelot *ocelot = &felix->ocelot; 170 struct dsa_switch *ds = felix->ds; 171 int key_length, upstream, err; 172 173 key_length = ocelot->vcap[VCAP_ES0].keys[VCAP_ES0_IGR_PORT].length; 174 upstream = dsa_upstream_port(ds, port); 175 176 outer_tagging_rule = kzalloc(sizeof(struct ocelot_vcap_filter), 177 GFP_KERNEL); 178 if (!outer_tagging_rule) 179 return -ENOMEM; 180 181 outer_tagging_rule->key_type = OCELOT_VCAP_KEY_ANY; 182 outer_tagging_rule->prio = 1; 183 outer_tagging_rule->id.cookie = OCELOT_VCAP_ES0_TAG_8021Q_RXVLAN(ocelot, port); 184 outer_tagging_rule->id.tc_offload = false; 185 outer_tagging_rule->block_id = VCAP_ES0; 186 outer_tagging_rule->type = OCELOT_VCAP_FILTER_OFFLOAD; 187 outer_tagging_rule->lookup = 0; 188 outer_tagging_rule->ingress_port.value = port; 189 outer_tagging_rule->ingress_port.mask = GENMASK(key_length - 1, 0); 190 outer_tagging_rule->egress_port.value = upstream; 191 outer_tagging_rule->egress_port.mask = GENMASK(key_length - 1, 0); 192 outer_tagging_rule->action.push_outer_tag = OCELOT_ES0_TAG; 193 outer_tagging_rule->action.tag_a_tpid_sel = OCELOT_TAG_TPID_SEL_8021AD; 194 outer_tagging_rule->action.tag_a_vid_sel = 1; 195 outer_tagging_rule->action.vid_a_val = vid; 196 197 err = ocelot_vcap_filter_add(ocelot, outer_tagging_rule, NULL); 198 if (err) 199 kfree(outer_tagging_rule); 200 201 return err; 202 } 203 204 static int felix_tag_8021q_vlan_del_rx(struct felix *felix, int port, u16 vid) 205 { 206 struct ocelot_vcap_filter *outer_tagging_rule; 207 struct ocelot_vcap_block *block_vcap_es0; 208 struct ocelot *ocelot = &felix->ocelot; 209 210 block_vcap_es0 = &ocelot->block[VCAP_ES0]; 211 212 outer_tagging_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_es0, 213 port, false); 214 if (!outer_tagging_rule) 215 return -ENOENT; 216 217 return ocelot_vcap_filter_del(ocelot, outer_tagging_rule); 218 } 219 220 /* Set up VCAP IS1 rules for stripping the tag_8021q VLAN on TX and VCAP IS2 221 * rules for steering those tagged packets towards the correct destination port 222 */ 223 static int felix_tag_8021q_vlan_add_tx(struct felix *felix, int port, u16 vid) 224 { 225 struct ocelot_vcap_filter *untagging_rule, *redirect_rule; 226 struct ocelot *ocelot = &felix->ocelot; 227 struct dsa_switch *ds = felix->ds; 228 int upstream, err; 229 230 untagging_rule = kzalloc(sizeof(struct ocelot_vcap_filter), GFP_KERNEL); 231 if (!untagging_rule) 232 return -ENOMEM; 233 234 redirect_rule = kzalloc(sizeof(struct ocelot_vcap_filter), GFP_KERNEL); 235 if (!redirect_rule) { 236 kfree(untagging_rule); 237 return -ENOMEM; 238 } 239 240 upstream = dsa_upstream_port(ds, port); 241 242 untagging_rule->key_type = OCELOT_VCAP_KEY_ANY; 243 untagging_rule->ingress_port_mask = BIT(upstream); 244 untagging_rule->vlan.vid.value = vid; 245 untagging_rule->vlan.vid.mask = VLAN_VID_MASK; 246 untagging_rule->prio = 1; 247 untagging_rule->id.cookie = OCELOT_VCAP_IS1_TAG_8021Q_TXVLAN(ocelot, port); 248 untagging_rule->id.tc_offload = false; 249 untagging_rule->block_id = VCAP_IS1; 250 untagging_rule->type = OCELOT_VCAP_FILTER_OFFLOAD; 251 untagging_rule->lookup = 0; 252 untagging_rule->action.vlan_pop_cnt_ena = true; 253 untagging_rule->action.vlan_pop_cnt = 1; 254 untagging_rule->action.pag_override_mask = 0xff; 255 untagging_rule->action.pag_val = port; 256 257 err = ocelot_vcap_filter_add(ocelot, untagging_rule, NULL); 258 if (err) { 259 kfree(untagging_rule); 260 kfree(redirect_rule); 261 return err; 262 } 263 264 redirect_rule->key_type = OCELOT_VCAP_KEY_ANY; 265 redirect_rule->ingress_port_mask = BIT(upstream); 266 redirect_rule->pag = port; 267 redirect_rule->prio = 1; 268 redirect_rule->id.cookie = OCELOT_VCAP_IS2_TAG_8021Q_TXVLAN(ocelot, port); 269 redirect_rule->id.tc_offload = false; 270 redirect_rule->block_id = VCAP_IS2; 271 redirect_rule->type = OCELOT_VCAP_FILTER_OFFLOAD; 272 redirect_rule->lookup = 0; 273 redirect_rule->action.mask_mode = OCELOT_MASK_MODE_REDIRECT; 274 redirect_rule->action.port_mask = BIT(port); 275 276 err = ocelot_vcap_filter_add(ocelot, redirect_rule, NULL); 277 if (err) { 278 ocelot_vcap_filter_del(ocelot, untagging_rule); 279 kfree(redirect_rule); 280 return err; 281 } 282 283 return 0; 284 } 285 286 static int felix_tag_8021q_vlan_del_tx(struct felix *felix, int port, u16 vid) 287 { 288 struct ocelot_vcap_filter *untagging_rule, *redirect_rule; 289 struct ocelot_vcap_block *block_vcap_is1; 290 struct ocelot_vcap_block *block_vcap_is2; 291 struct ocelot *ocelot = &felix->ocelot; 292 int err; 293 294 block_vcap_is1 = &ocelot->block[VCAP_IS1]; 295 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 296 297 untagging_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is1, 298 port, false); 299 if (!untagging_rule) 300 return -ENOENT; 301 302 err = ocelot_vcap_filter_del(ocelot, untagging_rule); 303 if (err) 304 return err; 305 306 redirect_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, 307 port, false); 308 if (!redirect_rule) 309 return -ENOENT; 310 311 return ocelot_vcap_filter_del(ocelot, redirect_rule); 312 } 313 314 static int felix_tag_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid, 315 u16 flags) 316 { 317 struct ocelot *ocelot = ds->priv; 318 int err; 319 320 /* tag_8021q.c assumes we are implementing this via port VLAN 321 * membership, which we aren't. So we don't need to add any VCAP filter 322 * for the CPU port. 323 */ 324 if (!dsa_is_user_port(ds, port)) 325 return 0; 326 327 err = felix_tag_8021q_vlan_add_rx(ocelot_to_felix(ocelot), port, vid); 328 if (err) 329 return err; 330 331 err = felix_tag_8021q_vlan_add_tx(ocelot_to_felix(ocelot), port, vid); 332 if (err) { 333 felix_tag_8021q_vlan_del_rx(ocelot_to_felix(ocelot), port, vid); 334 return err; 335 } 336 337 return 0; 338 } 339 340 static int felix_tag_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid) 341 { 342 struct ocelot *ocelot = ds->priv; 343 int err; 344 345 if (!dsa_is_user_port(ds, port)) 346 return 0; 347 348 err = felix_tag_8021q_vlan_del_rx(ocelot_to_felix(ocelot), port, vid); 349 if (err) 350 return err; 351 352 err = felix_tag_8021q_vlan_del_tx(ocelot_to_felix(ocelot), port, vid); 353 if (err) { 354 felix_tag_8021q_vlan_add_rx(ocelot_to_felix(ocelot), port, vid); 355 return err; 356 } 357 358 return 0; 359 } 360 361 /* Alternatively to using the NPI functionality, that same hardware MAC 362 * connected internally to the enetc or fman DSA master can be configured to 363 * use the software-defined tag_8021q frame format. As far as the hardware is 364 * concerned, it thinks it is a "dumb switch" - the queues of the CPU port 365 * module are now disconnected from it, but can still be accessed through 366 * register-based MMIO. 367 */ 368 static void felix_8021q_cpu_port_init(struct ocelot *ocelot, int port) 369 { 370 mutex_lock(&ocelot->fwd_domain_lock); 371 372 ocelot_port_set_dsa_8021q_cpu(ocelot, port); 373 374 /* Overwrite PGID_CPU with the non-tagging port */ 375 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, PGID_CPU); 376 377 ocelot_apply_bridge_fwd_mask(ocelot, true); 378 379 mutex_unlock(&ocelot->fwd_domain_lock); 380 } 381 382 static void felix_8021q_cpu_port_deinit(struct ocelot *ocelot, int port) 383 { 384 mutex_lock(&ocelot->fwd_domain_lock); 385 386 ocelot_port_unset_dsa_8021q_cpu(ocelot, port); 387 388 /* Restore PGID_CPU */ 389 ocelot_write_rix(ocelot, BIT(ocelot->num_phys_ports), ANA_PGID_PGID, 390 PGID_CPU); 391 392 ocelot_apply_bridge_fwd_mask(ocelot, true); 393 394 mutex_unlock(&ocelot->fwd_domain_lock); 395 } 396 397 /* On switches with no extraction IRQ wired, trapped packets need to be 398 * replicated over Ethernet as well, otherwise we'd get no notification of 399 * their arrival when using the ocelot-8021q tagging protocol. 400 */ 401 static int felix_update_trapping_destinations(struct dsa_switch *ds, 402 bool using_tag_8021q) 403 { 404 struct ocelot *ocelot = ds->priv; 405 struct felix *felix = ocelot_to_felix(ocelot); 406 struct ocelot_vcap_filter *trap; 407 enum ocelot_mask_mode mask_mode; 408 unsigned long port_mask; 409 struct dsa_port *dp; 410 bool cpu_copy_ena; 411 int cpu = -1, err; 412 413 if (!felix->info->quirk_no_xtr_irq) 414 return 0; 415 416 /* Figure out the current CPU port */ 417 dsa_switch_for_each_cpu_port(dp, ds) { 418 cpu = dp->index; 419 break; 420 } 421 422 /* We are sure that "cpu" was found, otherwise 423 * dsa_tree_setup_default_cpu() would have failed earlier. 424 */ 425 426 /* Make sure all traps are set up for that destination */ 427 list_for_each_entry(trap, &ocelot->traps, trap_list) { 428 /* Figure out the current trapping destination */ 429 if (using_tag_8021q) { 430 /* Redirect to the tag_8021q CPU port. If timestamps 431 * are necessary, also copy trapped packets to the CPU 432 * port module. 433 */ 434 mask_mode = OCELOT_MASK_MODE_REDIRECT; 435 port_mask = BIT(cpu); 436 cpu_copy_ena = !!trap->take_ts; 437 } else { 438 /* Trap packets only to the CPU port module, which is 439 * redirected to the NPI port (the DSA CPU port) 440 */ 441 mask_mode = OCELOT_MASK_MODE_PERMIT_DENY; 442 port_mask = 0; 443 cpu_copy_ena = true; 444 } 445 446 if (trap->action.mask_mode == mask_mode && 447 trap->action.port_mask == port_mask && 448 trap->action.cpu_copy_ena == cpu_copy_ena) 449 continue; 450 451 trap->action.mask_mode = mask_mode; 452 trap->action.port_mask = port_mask; 453 trap->action.cpu_copy_ena = cpu_copy_ena; 454 455 err = ocelot_vcap_filter_replace(ocelot, trap); 456 if (err) 457 return err; 458 } 459 460 return 0; 461 } 462 463 static int felix_setup_tag_8021q(struct dsa_switch *ds, int cpu, bool change) 464 { 465 struct ocelot *ocelot = ds->priv; 466 struct dsa_port *dp; 467 int err; 468 469 felix_8021q_cpu_port_init(ocelot, cpu); 470 471 dsa_switch_for_each_available_port(dp, ds) { 472 /* This overwrites ocelot_init(): 473 * Do not forward BPDU frames to the CPU port module, 474 * for 2 reasons: 475 * - When these packets are injected from the tag_8021q 476 * CPU port, we want them to go out, not loop back 477 * into the system. 478 * - STP traffic ingressing on a user port should go to 479 * the tag_8021q CPU port, not to the hardware CPU 480 * port module. 481 */ 482 ocelot_write_gix(ocelot, 483 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0), 484 ANA_PORT_CPU_FWD_BPDU_CFG, dp->index); 485 } 486 487 err = dsa_tag_8021q_register(ds, htons(ETH_P_8021AD)); 488 if (err) 489 return err; 490 491 if (change) { 492 err = dsa_port_walk_fdbs(ds, cpu, 493 felix_migrate_fdbs_to_tag_8021q_port); 494 if (err) 495 goto out_tag_8021q_unregister; 496 497 err = dsa_port_walk_mdbs(ds, cpu, 498 felix_migrate_mdbs_to_tag_8021q_port); 499 if (err) 500 goto out_migrate_fdbs; 501 502 felix_migrate_flood_to_tag_8021q_port(ds, cpu); 503 } 504 505 err = felix_update_trapping_destinations(ds, true); 506 if (err) 507 goto out_migrate_flood; 508 509 /* The ownership of the CPU port module's queues might have just been 510 * transferred to the tag_8021q tagger from the NPI-based tagger. 511 * So there might still be all sorts of crap in the queues. On the 512 * other hand, the MMIO-based matching of PTP frames is very brittle, 513 * so we need to be careful that there are no extra frames to be 514 * dequeued over MMIO, since we would never know to discard them. 515 */ 516 ocelot_drain_cpu_queue(ocelot, 0); 517 518 return 0; 519 520 out_migrate_flood: 521 if (change) 522 felix_migrate_flood_to_npi_port(ds, cpu); 523 if (change) 524 dsa_port_walk_mdbs(ds, cpu, felix_migrate_mdbs_to_npi_port); 525 out_migrate_fdbs: 526 if (change) 527 dsa_port_walk_fdbs(ds, cpu, felix_migrate_fdbs_to_npi_port); 528 out_tag_8021q_unregister: 529 dsa_tag_8021q_unregister(ds); 530 return err; 531 } 532 533 static void felix_teardown_tag_8021q(struct dsa_switch *ds, int cpu) 534 { 535 struct ocelot *ocelot = ds->priv; 536 struct dsa_port *dp; 537 int err; 538 539 err = felix_update_trapping_destinations(ds, false); 540 if (err) 541 dev_err(ds->dev, "felix_teardown_mmio_filtering returned %d", 542 err); 543 544 dsa_tag_8021q_unregister(ds); 545 546 dsa_switch_for_each_available_port(dp, ds) { 547 /* Restore the logic from ocelot_init: 548 * do not forward BPDU frames to the front ports. 549 */ 550 ocelot_write_gix(ocelot, 551 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 552 ANA_PORT_CPU_FWD_BPDU_CFG, 553 dp->index); 554 } 555 556 felix_8021q_cpu_port_deinit(ocelot, cpu); 557 } 558 559 /* The CPU port module is connected to the Node Processor Interface (NPI). This 560 * is the mode through which frames can be injected from and extracted to an 561 * external CPU, over Ethernet. In NXP SoCs, the "external CPU" is the ARM CPU 562 * running Linux, and this forms a DSA setup together with the enetc or fman 563 * DSA master. 564 */ 565 static void felix_npi_port_init(struct ocelot *ocelot, int port) 566 { 567 ocelot->npi = port; 568 569 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M | 570 QSYS_EXT_CPU_CFG_EXT_CPU_PORT(port), 571 QSYS_EXT_CPU_CFG); 572 573 /* NPI port Injection/Extraction configuration */ 574 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_XTR_HDR, 575 ocelot->npi_xtr_prefix); 576 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_INJ_HDR, 577 ocelot->npi_inj_prefix); 578 579 /* Disable transmission of pause frames */ 580 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 581 } 582 583 static void felix_npi_port_deinit(struct ocelot *ocelot, int port) 584 { 585 /* Restore hardware defaults */ 586 int unused_port = ocelot->num_phys_ports + 2; 587 588 ocelot->npi = -1; 589 590 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPU_PORT(unused_port), 591 QSYS_EXT_CPU_CFG); 592 593 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_XTR_HDR, 594 OCELOT_TAG_PREFIX_DISABLED); 595 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_INJ_HDR, 596 OCELOT_TAG_PREFIX_DISABLED); 597 598 /* Enable transmission of pause frames */ 599 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 600 } 601 602 static int felix_setup_tag_npi(struct dsa_switch *ds, int cpu, bool change) 603 { 604 struct ocelot *ocelot = ds->priv; 605 int err; 606 607 if (change) { 608 err = dsa_port_walk_fdbs(ds, cpu, 609 felix_migrate_fdbs_to_npi_port); 610 if (err) 611 return err; 612 613 err = dsa_port_walk_mdbs(ds, cpu, 614 felix_migrate_mdbs_to_npi_port); 615 if (err) 616 goto out_migrate_fdbs; 617 618 felix_migrate_flood_to_npi_port(ds, cpu); 619 } 620 621 felix_npi_port_init(ocelot, cpu); 622 623 return 0; 624 625 out_migrate_fdbs: 626 if (change) 627 dsa_port_walk_fdbs(ds, cpu, 628 felix_migrate_fdbs_to_tag_8021q_port); 629 630 return err; 631 } 632 633 static void felix_teardown_tag_npi(struct dsa_switch *ds, int cpu) 634 { 635 struct ocelot *ocelot = ds->priv; 636 637 felix_npi_port_deinit(ocelot, cpu); 638 } 639 640 static int felix_set_tag_protocol(struct dsa_switch *ds, int cpu, 641 enum dsa_tag_protocol proto, bool change) 642 { 643 int err; 644 645 switch (proto) { 646 case DSA_TAG_PROTO_SEVILLE: 647 case DSA_TAG_PROTO_OCELOT: 648 err = felix_setup_tag_npi(ds, cpu, change); 649 break; 650 case DSA_TAG_PROTO_OCELOT_8021Q: 651 err = felix_setup_tag_8021q(ds, cpu, change); 652 break; 653 default: 654 err = -EPROTONOSUPPORT; 655 } 656 657 return err; 658 } 659 660 static void felix_del_tag_protocol(struct dsa_switch *ds, int cpu, 661 enum dsa_tag_protocol proto) 662 { 663 switch (proto) { 664 case DSA_TAG_PROTO_SEVILLE: 665 case DSA_TAG_PROTO_OCELOT: 666 felix_teardown_tag_npi(ds, cpu); 667 break; 668 case DSA_TAG_PROTO_OCELOT_8021Q: 669 felix_teardown_tag_8021q(ds, cpu); 670 break; 671 default: 672 break; 673 } 674 } 675 676 /* This always leaves the switch in a consistent state, because although the 677 * tag_8021q setup can fail, the NPI setup can't. So either the change is made, 678 * or the restoration is guaranteed to work. 679 */ 680 static int felix_change_tag_protocol(struct dsa_switch *ds, int cpu, 681 enum dsa_tag_protocol proto) 682 { 683 struct ocelot *ocelot = ds->priv; 684 struct felix *felix = ocelot_to_felix(ocelot); 685 enum dsa_tag_protocol old_proto = felix->tag_proto; 686 int err; 687 688 if (proto != DSA_TAG_PROTO_SEVILLE && 689 proto != DSA_TAG_PROTO_OCELOT && 690 proto != DSA_TAG_PROTO_OCELOT_8021Q) 691 return -EPROTONOSUPPORT; 692 693 felix_del_tag_protocol(ds, cpu, old_proto); 694 695 err = felix_set_tag_protocol(ds, cpu, proto, true); 696 if (err) { 697 felix_set_tag_protocol(ds, cpu, old_proto, true); 698 return err; 699 } 700 701 felix->tag_proto = proto; 702 703 return 0; 704 } 705 706 static enum dsa_tag_protocol felix_get_tag_protocol(struct dsa_switch *ds, 707 int port, 708 enum dsa_tag_protocol mp) 709 { 710 struct ocelot *ocelot = ds->priv; 711 struct felix *felix = ocelot_to_felix(ocelot); 712 713 return felix->tag_proto; 714 } 715 716 static int felix_set_ageing_time(struct dsa_switch *ds, 717 unsigned int ageing_time) 718 { 719 struct ocelot *ocelot = ds->priv; 720 721 ocelot_set_ageing_time(ocelot, ageing_time); 722 723 return 0; 724 } 725 726 static void felix_port_fast_age(struct dsa_switch *ds, int port) 727 { 728 struct ocelot *ocelot = ds->priv; 729 int err; 730 731 err = ocelot_mact_flush(ocelot, port); 732 if (err) 733 dev_err(ds->dev, "Flushing MAC table on port %d returned %pe\n", 734 port, ERR_PTR(err)); 735 } 736 737 static int felix_fdb_dump(struct dsa_switch *ds, int port, 738 dsa_fdb_dump_cb_t *cb, void *data) 739 { 740 struct ocelot *ocelot = ds->priv; 741 742 return ocelot_fdb_dump(ocelot, port, cb, data); 743 } 744 745 static int felix_fdb_add(struct dsa_switch *ds, int port, 746 const unsigned char *addr, u16 vid, 747 struct dsa_db db) 748 { 749 struct net_device *bridge_dev = felix_classify_db(db); 750 struct ocelot *ocelot = ds->priv; 751 752 if (IS_ERR(bridge_dev)) 753 return PTR_ERR(bridge_dev); 754 755 return ocelot_fdb_add(ocelot, port, addr, vid, bridge_dev); 756 } 757 758 static int felix_fdb_del(struct dsa_switch *ds, int port, 759 const unsigned char *addr, u16 vid, 760 struct dsa_db db) 761 { 762 struct net_device *bridge_dev = felix_classify_db(db); 763 struct ocelot *ocelot = ds->priv; 764 765 if (IS_ERR(bridge_dev)) 766 return PTR_ERR(bridge_dev); 767 768 return ocelot_fdb_del(ocelot, port, addr, vid, bridge_dev); 769 } 770 771 static int felix_lag_fdb_add(struct dsa_switch *ds, struct dsa_lag lag, 772 const unsigned char *addr, u16 vid, 773 struct dsa_db db) 774 { 775 struct net_device *bridge_dev = felix_classify_db(db); 776 struct ocelot *ocelot = ds->priv; 777 778 if (IS_ERR(bridge_dev)) 779 return PTR_ERR(bridge_dev); 780 781 return ocelot_lag_fdb_add(ocelot, lag.dev, addr, vid, bridge_dev); 782 } 783 784 static int felix_lag_fdb_del(struct dsa_switch *ds, struct dsa_lag lag, 785 const unsigned char *addr, u16 vid, 786 struct dsa_db db) 787 { 788 struct net_device *bridge_dev = felix_classify_db(db); 789 struct ocelot *ocelot = ds->priv; 790 791 if (IS_ERR(bridge_dev)) 792 return PTR_ERR(bridge_dev); 793 794 return ocelot_lag_fdb_del(ocelot, lag.dev, addr, vid, bridge_dev); 795 } 796 797 static int felix_mdb_add(struct dsa_switch *ds, int port, 798 const struct switchdev_obj_port_mdb *mdb, 799 struct dsa_db db) 800 { 801 struct net_device *bridge_dev = felix_classify_db(db); 802 struct ocelot *ocelot = ds->priv; 803 804 if (IS_ERR(bridge_dev)) 805 return PTR_ERR(bridge_dev); 806 807 return ocelot_port_mdb_add(ocelot, port, mdb, bridge_dev); 808 } 809 810 static int felix_mdb_del(struct dsa_switch *ds, int port, 811 const struct switchdev_obj_port_mdb *mdb, 812 struct dsa_db db) 813 { 814 struct net_device *bridge_dev = felix_classify_db(db); 815 struct ocelot *ocelot = ds->priv; 816 817 if (IS_ERR(bridge_dev)) 818 return PTR_ERR(bridge_dev); 819 820 return ocelot_port_mdb_del(ocelot, port, mdb, bridge_dev); 821 } 822 823 static void felix_bridge_stp_state_set(struct dsa_switch *ds, int port, 824 u8 state) 825 { 826 struct ocelot *ocelot = ds->priv; 827 828 return ocelot_bridge_stp_state_set(ocelot, port, state); 829 } 830 831 static int felix_pre_bridge_flags(struct dsa_switch *ds, int port, 832 struct switchdev_brport_flags val, 833 struct netlink_ext_ack *extack) 834 { 835 struct ocelot *ocelot = ds->priv; 836 837 return ocelot_port_pre_bridge_flags(ocelot, port, val); 838 } 839 840 static int felix_bridge_flags(struct dsa_switch *ds, int port, 841 struct switchdev_brport_flags val, 842 struct netlink_ext_ack *extack) 843 { 844 struct ocelot *ocelot = ds->priv; 845 846 ocelot_port_bridge_flags(ocelot, port, val); 847 848 return 0; 849 } 850 851 static int felix_bridge_join(struct dsa_switch *ds, int port, 852 struct dsa_bridge bridge, bool *tx_fwd_offload, 853 struct netlink_ext_ack *extack) 854 { 855 struct ocelot *ocelot = ds->priv; 856 857 return ocelot_port_bridge_join(ocelot, port, bridge.dev, bridge.num, 858 extack); 859 } 860 861 static void felix_bridge_leave(struct dsa_switch *ds, int port, 862 struct dsa_bridge bridge) 863 { 864 struct ocelot *ocelot = ds->priv; 865 866 ocelot_port_bridge_leave(ocelot, port, bridge.dev); 867 } 868 869 static int felix_lag_join(struct dsa_switch *ds, int port, 870 struct dsa_lag lag, 871 struct netdev_lag_upper_info *info) 872 { 873 struct ocelot *ocelot = ds->priv; 874 875 return ocelot_port_lag_join(ocelot, port, lag.dev, info); 876 } 877 878 static int felix_lag_leave(struct dsa_switch *ds, int port, 879 struct dsa_lag lag) 880 { 881 struct ocelot *ocelot = ds->priv; 882 883 ocelot_port_lag_leave(ocelot, port, lag.dev); 884 885 return 0; 886 } 887 888 static int felix_lag_change(struct dsa_switch *ds, int port) 889 { 890 struct dsa_port *dp = dsa_to_port(ds, port); 891 struct ocelot *ocelot = ds->priv; 892 893 ocelot_port_lag_change(ocelot, port, dp->lag_tx_enabled); 894 895 return 0; 896 } 897 898 static int felix_vlan_prepare(struct dsa_switch *ds, int port, 899 const struct switchdev_obj_port_vlan *vlan, 900 struct netlink_ext_ack *extack) 901 { 902 struct ocelot *ocelot = ds->priv; 903 u16 flags = vlan->flags; 904 905 /* Ocelot switches copy frames as-is to the CPU, so the flags: 906 * egress-untagged or not, pvid or not, make no difference. This 907 * behavior is already better than what DSA just tries to approximate 908 * when it installs the VLAN with the same flags on the CPU port. 909 * Just accept any configuration, and don't let ocelot deny installing 910 * multiple native VLANs on the NPI port, because the switch doesn't 911 * look at the port tag settings towards the NPI interface anyway. 912 */ 913 if (port == ocelot->npi) 914 return 0; 915 916 return ocelot_vlan_prepare(ocelot, port, vlan->vid, 917 flags & BRIDGE_VLAN_INFO_PVID, 918 flags & BRIDGE_VLAN_INFO_UNTAGGED, 919 extack); 920 } 921 922 static int felix_vlan_filtering(struct dsa_switch *ds, int port, bool enabled, 923 struct netlink_ext_ack *extack) 924 { 925 struct ocelot *ocelot = ds->priv; 926 927 return ocelot_port_vlan_filtering(ocelot, port, enabled, extack); 928 } 929 930 static int felix_vlan_add(struct dsa_switch *ds, int port, 931 const struct switchdev_obj_port_vlan *vlan, 932 struct netlink_ext_ack *extack) 933 { 934 struct ocelot *ocelot = ds->priv; 935 u16 flags = vlan->flags; 936 int err; 937 938 err = felix_vlan_prepare(ds, port, vlan, extack); 939 if (err) 940 return err; 941 942 return ocelot_vlan_add(ocelot, port, vlan->vid, 943 flags & BRIDGE_VLAN_INFO_PVID, 944 flags & BRIDGE_VLAN_INFO_UNTAGGED); 945 } 946 947 static int felix_vlan_del(struct dsa_switch *ds, int port, 948 const struct switchdev_obj_port_vlan *vlan) 949 { 950 struct ocelot *ocelot = ds->priv; 951 952 return ocelot_vlan_del(ocelot, port, vlan->vid); 953 } 954 955 static void felix_phylink_get_caps(struct dsa_switch *ds, int port, 956 struct phylink_config *config) 957 { 958 struct ocelot *ocelot = ds->priv; 959 960 /* This driver does not make use of the speed, duplex, pause or the 961 * advertisement in its mac_config, so it is safe to mark this driver 962 * as non-legacy. 963 */ 964 config->legacy_pre_march2020 = false; 965 966 __set_bit(ocelot->ports[port]->phy_mode, 967 config->supported_interfaces); 968 } 969 970 static void felix_phylink_validate(struct dsa_switch *ds, int port, 971 unsigned long *supported, 972 struct phylink_link_state *state) 973 { 974 struct ocelot *ocelot = ds->priv; 975 struct felix *felix = ocelot_to_felix(ocelot); 976 977 if (felix->info->phylink_validate) 978 felix->info->phylink_validate(ocelot, port, supported, state); 979 } 980 981 static struct phylink_pcs *felix_phylink_mac_select_pcs(struct dsa_switch *ds, 982 int port, 983 phy_interface_t iface) 984 { 985 struct ocelot *ocelot = ds->priv; 986 struct felix *felix = ocelot_to_felix(ocelot); 987 struct phylink_pcs *pcs = NULL; 988 989 if (felix->pcs && felix->pcs[port]) 990 pcs = felix->pcs[port]; 991 992 return pcs; 993 } 994 995 static void felix_phylink_mac_link_down(struct dsa_switch *ds, int port, 996 unsigned int link_an_mode, 997 phy_interface_t interface) 998 { 999 struct ocelot *ocelot = ds->priv; 1000 1001 ocelot_phylink_mac_link_down(ocelot, port, link_an_mode, interface, 1002 FELIX_MAC_QUIRKS); 1003 } 1004 1005 static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port, 1006 unsigned int link_an_mode, 1007 phy_interface_t interface, 1008 struct phy_device *phydev, 1009 int speed, int duplex, 1010 bool tx_pause, bool rx_pause) 1011 { 1012 struct ocelot *ocelot = ds->priv; 1013 struct felix *felix = ocelot_to_felix(ocelot); 1014 1015 ocelot_phylink_mac_link_up(ocelot, port, phydev, link_an_mode, 1016 interface, speed, duplex, tx_pause, rx_pause, 1017 FELIX_MAC_QUIRKS); 1018 1019 if (felix->info->port_sched_speed_set) 1020 felix->info->port_sched_speed_set(ocelot, port, speed); 1021 } 1022 1023 static void felix_port_qos_map_init(struct ocelot *ocelot, int port) 1024 { 1025 int i; 1026 1027 ocelot_rmw_gix(ocelot, 1028 ANA_PORT_QOS_CFG_QOS_PCP_ENA, 1029 ANA_PORT_QOS_CFG_QOS_PCP_ENA, 1030 ANA_PORT_QOS_CFG, 1031 port); 1032 1033 for (i = 0; i < OCELOT_NUM_TC * 2; i++) { 1034 ocelot_rmw_ix(ocelot, 1035 (ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL & i) | 1036 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(i), 1037 ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL | 1038 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M, 1039 ANA_PORT_PCP_DEI_MAP, 1040 port, i); 1041 } 1042 } 1043 1044 static void felix_get_strings(struct dsa_switch *ds, int port, 1045 u32 stringset, u8 *data) 1046 { 1047 struct ocelot *ocelot = ds->priv; 1048 1049 return ocelot_get_strings(ocelot, port, stringset, data); 1050 } 1051 1052 static void felix_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data) 1053 { 1054 struct ocelot *ocelot = ds->priv; 1055 1056 ocelot_get_ethtool_stats(ocelot, port, data); 1057 } 1058 1059 static int felix_get_sset_count(struct dsa_switch *ds, int port, int sset) 1060 { 1061 struct ocelot *ocelot = ds->priv; 1062 1063 return ocelot_get_sset_count(ocelot, port, sset); 1064 } 1065 1066 static int felix_get_ts_info(struct dsa_switch *ds, int port, 1067 struct ethtool_ts_info *info) 1068 { 1069 struct ocelot *ocelot = ds->priv; 1070 1071 return ocelot_get_ts_info(ocelot, port, info); 1072 } 1073 1074 static const u32 felix_phy_match_table[PHY_INTERFACE_MODE_MAX] = { 1075 [PHY_INTERFACE_MODE_INTERNAL] = OCELOT_PORT_MODE_INTERNAL, 1076 [PHY_INTERFACE_MODE_SGMII] = OCELOT_PORT_MODE_SGMII, 1077 [PHY_INTERFACE_MODE_QSGMII] = OCELOT_PORT_MODE_QSGMII, 1078 [PHY_INTERFACE_MODE_USXGMII] = OCELOT_PORT_MODE_USXGMII, 1079 [PHY_INTERFACE_MODE_2500BASEX] = OCELOT_PORT_MODE_2500BASEX, 1080 }; 1081 1082 static int felix_validate_phy_mode(struct felix *felix, int port, 1083 phy_interface_t phy_mode) 1084 { 1085 u32 modes = felix->info->port_modes[port]; 1086 1087 if (felix_phy_match_table[phy_mode] & modes) 1088 return 0; 1089 return -EOPNOTSUPP; 1090 } 1091 1092 static int felix_parse_ports_node(struct felix *felix, 1093 struct device_node *ports_node, 1094 phy_interface_t *port_phy_modes) 1095 { 1096 struct device *dev = felix->ocelot.dev; 1097 struct device_node *child; 1098 1099 for_each_available_child_of_node(ports_node, child) { 1100 phy_interface_t phy_mode; 1101 u32 port; 1102 int err; 1103 1104 /* Get switch port number from DT */ 1105 if (of_property_read_u32(child, "reg", &port) < 0) { 1106 dev_err(dev, "Port number not defined in device tree " 1107 "(property \"reg\")\n"); 1108 of_node_put(child); 1109 return -ENODEV; 1110 } 1111 1112 /* Get PHY mode from DT */ 1113 err = of_get_phy_mode(child, &phy_mode); 1114 if (err) { 1115 dev_err(dev, "Failed to read phy-mode or " 1116 "phy-interface-type property for port %d\n", 1117 port); 1118 of_node_put(child); 1119 return -ENODEV; 1120 } 1121 1122 err = felix_validate_phy_mode(felix, port, phy_mode); 1123 if (err < 0) { 1124 dev_err(dev, "Unsupported PHY mode %s on port %d\n", 1125 phy_modes(phy_mode), port); 1126 of_node_put(child); 1127 return err; 1128 } 1129 1130 port_phy_modes[port] = phy_mode; 1131 } 1132 1133 return 0; 1134 } 1135 1136 static int felix_parse_dt(struct felix *felix, phy_interface_t *port_phy_modes) 1137 { 1138 struct device *dev = felix->ocelot.dev; 1139 struct device_node *switch_node; 1140 struct device_node *ports_node; 1141 int err; 1142 1143 switch_node = dev->of_node; 1144 1145 ports_node = of_get_child_by_name(switch_node, "ports"); 1146 if (!ports_node) 1147 ports_node = of_get_child_by_name(switch_node, "ethernet-ports"); 1148 if (!ports_node) { 1149 dev_err(dev, "Incorrect bindings: absent \"ports\" or \"ethernet-ports\" node\n"); 1150 return -ENODEV; 1151 } 1152 1153 err = felix_parse_ports_node(felix, ports_node, port_phy_modes); 1154 of_node_put(ports_node); 1155 1156 return err; 1157 } 1158 1159 static int felix_init_structs(struct felix *felix, int num_phys_ports) 1160 { 1161 struct ocelot *ocelot = &felix->ocelot; 1162 phy_interface_t *port_phy_modes; 1163 struct resource res; 1164 int port, i, err; 1165 1166 ocelot->num_phys_ports = num_phys_ports; 1167 ocelot->ports = devm_kcalloc(ocelot->dev, num_phys_ports, 1168 sizeof(struct ocelot_port *), GFP_KERNEL); 1169 if (!ocelot->ports) 1170 return -ENOMEM; 1171 1172 ocelot->map = felix->info->map; 1173 ocelot->stats_layout = felix->info->stats_layout; 1174 ocelot->num_stats = felix->info->num_stats; 1175 ocelot->num_mact_rows = felix->info->num_mact_rows; 1176 ocelot->vcap = felix->info->vcap; 1177 ocelot->vcap_pol.base = felix->info->vcap_pol_base; 1178 ocelot->vcap_pol.max = felix->info->vcap_pol_max; 1179 ocelot->vcap_pol.base2 = felix->info->vcap_pol_base2; 1180 ocelot->vcap_pol.max2 = felix->info->vcap_pol_max2; 1181 ocelot->ops = felix->info->ops; 1182 ocelot->npi_inj_prefix = OCELOT_TAG_PREFIX_SHORT; 1183 ocelot->npi_xtr_prefix = OCELOT_TAG_PREFIX_SHORT; 1184 ocelot->devlink = felix->ds->devlink; 1185 1186 port_phy_modes = kcalloc(num_phys_ports, sizeof(phy_interface_t), 1187 GFP_KERNEL); 1188 if (!port_phy_modes) 1189 return -ENOMEM; 1190 1191 err = felix_parse_dt(felix, port_phy_modes); 1192 if (err) { 1193 kfree(port_phy_modes); 1194 return err; 1195 } 1196 1197 for (i = 0; i < TARGET_MAX; i++) { 1198 struct regmap *target; 1199 1200 if (!felix->info->target_io_res[i].name) 1201 continue; 1202 1203 memcpy(&res, &felix->info->target_io_res[i], sizeof(res)); 1204 res.flags = IORESOURCE_MEM; 1205 res.start += felix->switch_base; 1206 res.end += felix->switch_base; 1207 1208 target = felix->info->init_regmap(ocelot, &res); 1209 if (IS_ERR(target)) { 1210 dev_err(ocelot->dev, 1211 "Failed to map device memory space\n"); 1212 kfree(port_phy_modes); 1213 return PTR_ERR(target); 1214 } 1215 1216 ocelot->targets[i] = target; 1217 } 1218 1219 err = ocelot_regfields_init(ocelot, felix->info->regfields); 1220 if (err) { 1221 dev_err(ocelot->dev, "failed to init reg fields map\n"); 1222 kfree(port_phy_modes); 1223 return err; 1224 } 1225 1226 for (port = 0; port < num_phys_ports; port++) { 1227 struct ocelot_port *ocelot_port; 1228 struct regmap *target; 1229 1230 ocelot_port = devm_kzalloc(ocelot->dev, 1231 sizeof(struct ocelot_port), 1232 GFP_KERNEL); 1233 if (!ocelot_port) { 1234 dev_err(ocelot->dev, 1235 "failed to allocate port memory\n"); 1236 kfree(port_phy_modes); 1237 return -ENOMEM; 1238 } 1239 1240 memcpy(&res, &felix->info->port_io_res[port], sizeof(res)); 1241 res.flags = IORESOURCE_MEM; 1242 res.start += felix->switch_base; 1243 res.end += felix->switch_base; 1244 1245 target = felix->info->init_regmap(ocelot, &res); 1246 if (IS_ERR(target)) { 1247 dev_err(ocelot->dev, 1248 "Failed to map memory space for port %d\n", 1249 port); 1250 kfree(port_phy_modes); 1251 return PTR_ERR(target); 1252 } 1253 1254 ocelot_port->phy_mode = port_phy_modes[port]; 1255 ocelot_port->ocelot = ocelot; 1256 ocelot_port->target = target; 1257 ocelot->ports[port] = ocelot_port; 1258 } 1259 1260 kfree(port_phy_modes); 1261 1262 if (felix->info->mdio_bus_alloc) { 1263 err = felix->info->mdio_bus_alloc(ocelot); 1264 if (err < 0) 1265 return err; 1266 } 1267 1268 return 0; 1269 } 1270 1271 static void ocelot_port_purge_txtstamp_skb(struct ocelot *ocelot, int port, 1272 struct sk_buff *skb) 1273 { 1274 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1275 struct sk_buff *clone = OCELOT_SKB_CB(skb)->clone; 1276 struct sk_buff *skb_match = NULL, *skb_tmp; 1277 unsigned long flags; 1278 1279 if (!clone) 1280 return; 1281 1282 spin_lock_irqsave(&ocelot_port->tx_skbs.lock, flags); 1283 1284 skb_queue_walk_safe(&ocelot_port->tx_skbs, skb, skb_tmp) { 1285 if (skb != clone) 1286 continue; 1287 __skb_unlink(skb, &ocelot_port->tx_skbs); 1288 skb_match = skb; 1289 break; 1290 } 1291 1292 spin_unlock_irqrestore(&ocelot_port->tx_skbs.lock, flags); 1293 1294 WARN_ONCE(!skb_match, 1295 "Could not find skb clone in TX timestamping list\n"); 1296 } 1297 1298 #define work_to_xmit_work(w) \ 1299 container_of((w), struct felix_deferred_xmit_work, work) 1300 1301 static void felix_port_deferred_xmit(struct kthread_work *work) 1302 { 1303 struct felix_deferred_xmit_work *xmit_work = work_to_xmit_work(work); 1304 struct dsa_switch *ds = xmit_work->dp->ds; 1305 struct sk_buff *skb = xmit_work->skb; 1306 u32 rew_op = ocelot_ptp_rew_op(skb); 1307 struct ocelot *ocelot = ds->priv; 1308 int port = xmit_work->dp->index; 1309 int retries = 10; 1310 1311 do { 1312 if (ocelot_can_inject(ocelot, 0)) 1313 break; 1314 1315 cpu_relax(); 1316 } while (--retries); 1317 1318 if (!retries) { 1319 dev_err(ocelot->dev, "port %d failed to inject skb\n", 1320 port); 1321 ocelot_port_purge_txtstamp_skb(ocelot, port, skb); 1322 kfree_skb(skb); 1323 return; 1324 } 1325 1326 ocelot_port_inject_frame(ocelot, port, 0, rew_op, skb); 1327 1328 consume_skb(skb); 1329 kfree(xmit_work); 1330 } 1331 1332 static int felix_connect_tag_protocol(struct dsa_switch *ds, 1333 enum dsa_tag_protocol proto) 1334 { 1335 struct ocelot_8021q_tagger_data *tagger_data; 1336 1337 switch (proto) { 1338 case DSA_TAG_PROTO_OCELOT_8021Q: 1339 tagger_data = ocelot_8021q_tagger_data(ds); 1340 tagger_data->xmit_work_fn = felix_port_deferred_xmit; 1341 return 0; 1342 case DSA_TAG_PROTO_OCELOT: 1343 case DSA_TAG_PROTO_SEVILLE: 1344 return 0; 1345 default: 1346 return -EPROTONOSUPPORT; 1347 } 1348 } 1349 1350 /* Hardware initialization done here so that we can allocate structures with 1351 * devm without fear of dsa_register_switch returning -EPROBE_DEFER and causing 1352 * us to allocate structures twice (leak memory) and map PCI memory twice 1353 * (which will not work). 1354 */ 1355 static int felix_setup(struct dsa_switch *ds) 1356 { 1357 struct ocelot *ocelot = ds->priv; 1358 struct felix *felix = ocelot_to_felix(ocelot); 1359 struct dsa_port *dp; 1360 int err; 1361 1362 err = felix_init_structs(felix, ds->num_ports); 1363 if (err) 1364 return err; 1365 1366 err = ocelot_init(ocelot); 1367 if (err) 1368 goto out_mdiobus_free; 1369 1370 if (ocelot->ptp) { 1371 err = ocelot_init_timestamp(ocelot, felix->info->ptp_caps); 1372 if (err) { 1373 dev_err(ocelot->dev, 1374 "Timestamp initialization failed\n"); 1375 ocelot->ptp = 0; 1376 } 1377 } 1378 1379 dsa_switch_for_each_available_port(dp, ds) { 1380 ocelot_init_port(ocelot, dp->index); 1381 1382 /* Set the default QoS Classification based on PCP and DEI 1383 * bits of vlan tag. 1384 */ 1385 felix_port_qos_map_init(ocelot, dp->index); 1386 } 1387 1388 err = ocelot_devlink_sb_register(ocelot); 1389 if (err) 1390 goto out_deinit_ports; 1391 1392 dsa_switch_for_each_cpu_port(dp, ds) { 1393 /* The initial tag protocol is NPI which always returns 0, so 1394 * there's no real point in checking for errors. 1395 */ 1396 felix_set_tag_protocol(ds, dp->index, felix->tag_proto, false); 1397 break; 1398 } 1399 1400 ds->mtu_enforcement_ingress = true; 1401 ds->assisted_learning_on_cpu_port = true; 1402 ds->fdb_isolation = true; 1403 ds->max_num_bridges = ds->num_ports; 1404 1405 return 0; 1406 1407 out_deinit_ports: 1408 dsa_switch_for_each_available_port(dp, ds) 1409 ocelot_deinit_port(ocelot, dp->index); 1410 1411 ocelot_deinit_timestamp(ocelot); 1412 ocelot_deinit(ocelot); 1413 1414 out_mdiobus_free: 1415 if (felix->info->mdio_bus_free) 1416 felix->info->mdio_bus_free(ocelot); 1417 1418 return err; 1419 } 1420 1421 static void felix_teardown(struct dsa_switch *ds) 1422 { 1423 struct ocelot *ocelot = ds->priv; 1424 struct felix *felix = ocelot_to_felix(ocelot); 1425 struct dsa_port *dp; 1426 1427 dsa_switch_for_each_cpu_port(dp, ds) { 1428 felix_del_tag_protocol(ds, dp->index, felix->tag_proto); 1429 break; 1430 } 1431 1432 dsa_switch_for_each_available_port(dp, ds) 1433 ocelot_deinit_port(ocelot, dp->index); 1434 1435 ocelot_devlink_sb_unregister(ocelot); 1436 ocelot_deinit_timestamp(ocelot); 1437 ocelot_deinit(ocelot); 1438 1439 if (felix->info->mdio_bus_free) 1440 felix->info->mdio_bus_free(ocelot); 1441 } 1442 1443 static int felix_hwtstamp_get(struct dsa_switch *ds, int port, 1444 struct ifreq *ifr) 1445 { 1446 struct ocelot *ocelot = ds->priv; 1447 1448 return ocelot_hwstamp_get(ocelot, port, ifr); 1449 } 1450 1451 static int felix_hwtstamp_set(struct dsa_switch *ds, int port, 1452 struct ifreq *ifr) 1453 { 1454 struct ocelot *ocelot = ds->priv; 1455 struct felix *felix = ocelot_to_felix(ocelot); 1456 bool using_tag_8021q; 1457 int err; 1458 1459 err = ocelot_hwstamp_set(ocelot, port, ifr); 1460 if (err) 1461 return err; 1462 1463 using_tag_8021q = felix->tag_proto == DSA_TAG_PROTO_OCELOT_8021Q; 1464 1465 return felix_update_trapping_destinations(ds, using_tag_8021q); 1466 } 1467 1468 static bool felix_check_xtr_pkt(struct ocelot *ocelot) 1469 { 1470 struct felix *felix = ocelot_to_felix(ocelot); 1471 int err = 0, grp = 0; 1472 1473 if (felix->tag_proto != DSA_TAG_PROTO_OCELOT_8021Q) 1474 return false; 1475 1476 if (!felix->info->quirk_no_xtr_irq) 1477 return false; 1478 1479 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) { 1480 struct sk_buff *skb; 1481 unsigned int type; 1482 1483 err = ocelot_xtr_poll_frame(ocelot, grp, &skb); 1484 if (err) 1485 goto out; 1486 1487 /* We trap to the CPU port module all PTP frames, but 1488 * felix_rxtstamp() only gets called for event frames. 1489 * So we need to avoid sending duplicate general 1490 * message frames by running a second BPF classifier 1491 * here and dropping those. 1492 */ 1493 __skb_push(skb, ETH_HLEN); 1494 1495 type = ptp_classify_raw(skb); 1496 1497 __skb_pull(skb, ETH_HLEN); 1498 1499 if (type == PTP_CLASS_NONE) { 1500 kfree_skb(skb); 1501 continue; 1502 } 1503 1504 netif_rx(skb); 1505 } 1506 1507 out: 1508 if (err < 0) { 1509 dev_err_ratelimited(ocelot->dev, 1510 "Error during packet extraction: %pe\n", 1511 ERR_PTR(err)); 1512 ocelot_drain_cpu_queue(ocelot, 0); 1513 } 1514 1515 return true; 1516 } 1517 1518 static bool felix_rxtstamp(struct dsa_switch *ds, int port, 1519 struct sk_buff *skb, unsigned int type) 1520 { 1521 u32 tstamp_lo = OCELOT_SKB_CB(skb)->tstamp_lo; 1522 struct skb_shared_hwtstamps *shhwtstamps; 1523 struct ocelot *ocelot = ds->priv; 1524 struct timespec64 ts; 1525 u32 tstamp_hi; 1526 u64 tstamp; 1527 1528 /* If the "no XTR IRQ" workaround is in use, tell DSA to defer this skb 1529 * for RX timestamping. Then free it, and poll for its copy through 1530 * MMIO in the CPU port module, and inject that into the stack from 1531 * ocelot_xtr_poll(). 1532 */ 1533 if (felix_check_xtr_pkt(ocelot)) { 1534 kfree_skb(skb); 1535 return true; 1536 } 1537 1538 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1539 tstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 1540 1541 tstamp_hi = tstamp >> 32; 1542 if ((tstamp & 0xffffffff) < tstamp_lo) 1543 tstamp_hi--; 1544 1545 tstamp = ((u64)tstamp_hi << 32) | tstamp_lo; 1546 1547 shhwtstamps = skb_hwtstamps(skb); 1548 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 1549 shhwtstamps->hwtstamp = tstamp; 1550 return false; 1551 } 1552 1553 static void felix_txtstamp(struct dsa_switch *ds, int port, 1554 struct sk_buff *skb) 1555 { 1556 struct ocelot *ocelot = ds->priv; 1557 struct sk_buff *clone = NULL; 1558 1559 if (!ocelot->ptp) 1560 return; 1561 1562 if (ocelot_port_txtstamp_request(ocelot, port, skb, &clone)) { 1563 dev_err_ratelimited(ds->dev, 1564 "port %d delivering skb without TX timestamp\n", 1565 port); 1566 return; 1567 } 1568 1569 if (clone) 1570 OCELOT_SKB_CB(skb)->clone = clone; 1571 } 1572 1573 static int felix_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1574 { 1575 struct ocelot *ocelot = ds->priv; 1576 1577 ocelot_port_set_maxlen(ocelot, port, new_mtu); 1578 1579 return 0; 1580 } 1581 1582 static int felix_get_max_mtu(struct dsa_switch *ds, int port) 1583 { 1584 struct ocelot *ocelot = ds->priv; 1585 1586 return ocelot_get_max_mtu(ocelot, port); 1587 } 1588 1589 static int felix_cls_flower_add(struct dsa_switch *ds, int port, 1590 struct flow_cls_offload *cls, bool ingress) 1591 { 1592 struct ocelot *ocelot = ds->priv; 1593 struct felix *felix = ocelot_to_felix(ocelot); 1594 bool using_tag_8021q; 1595 int err; 1596 1597 err = ocelot_cls_flower_replace(ocelot, port, cls, ingress); 1598 if (err) 1599 return err; 1600 1601 using_tag_8021q = felix->tag_proto == DSA_TAG_PROTO_OCELOT_8021Q; 1602 1603 return felix_update_trapping_destinations(ds, using_tag_8021q); 1604 } 1605 1606 static int felix_cls_flower_del(struct dsa_switch *ds, int port, 1607 struct flow_cls_offload *cls, bool ingress) 1608 { 1609 struct ocelot *ocelot = ds->priv; 1610 1611 return ocelot_cls_flower_destroy(ocelot, port, cls, ingress); 1612 } 1613 1614 static int felix_cls_flower_stats(struct dsa_switch *ds, int port, 1615 struct flow_cls_offload *cls, bool ingress) 1616 { 1617 struct ocelot *ocelot = ds->priv; 1618 1619 return ocelot_cls_flower_stats(ocelot, port, cls, ingress); 1620 } 1621 1622 static int felix_port_policer_add(struct dsa_switch *ds, int port, 1623 struct dsa_mall_policer_tc_entry *policer) 1624 { 1625 struct ocelot *ocelot = ds->priv; 1626 struct ocelot_policer pol = { 1627 .rate = div_u64(policer->rate_bytes_per_sec, 1000) * 8, 1628 .burst = policer->burst, 1629 }; 1630 1631 return ocelot_port_policer_add(ocelot, port, &pol); 1632 } 1633 1634 static void felix_port_policer_del(struct dsa_switch *ds, int port) 1635 { 1636 struct ocelot *ocelot = ds->priv; 1637 1638 ocelot_port_policer_del(ocelot, port); 1639 } 1640 1641 static int felix_port_setup_tc(struct dsa_switch *ds, int port, 1642 enum tc_setup_type type, 1643 void *type_data) 1644 { 1645 struct ocelot *ocelot = ds->priv; 1646 struct felix *felix = ocelot_to_felix(ocelot); 1647 1648 if (felix->info->port_setup_tc) 1649 return felix->info->port_setup_tc(ds, port, type, type_data); 1650 else 1651 return -EOPNOTSUPP; 1652 } 1653 1654 static int felix_sb_pool_get(struct dsa_switch *ds, unsigned int sb_index, 1655 u16 pool_index, 1656 struct devlink_sb_pool_info *pool_info) 1657 { 1658 struct ocelot *ocelot = ds->priv; 1659 1660 return ocelot_sb_pool_get(ocelot, sb_index, pool_index, pool_info); 1661 } 1662 1663 static int felix_sb_pool_set(struct dsa_switch *ds, unsigned int sb_index, 1664 u16 pool_index, u32 size, 1665 enum devlink_sb_threshold_type threshold_type, 1666 struct netlink_ext_ack *extack) 1667 { 1668 struct ocelot *ocelot = ds->priv; 1669 1670 return ocelot_sb_pool_set(ocelot, sb_index, pool_index, size, 1671 threshold_type, extack); 1672 } 1673 1674 static int felix_sb_port_pool_get(struct dsa_switch *ds, int port, 1675 unsigned int sb_index, u16 pool_index, 1676 u32 *p_threshold) 1677 { 1678 struct ocelot *ocelot = ds->priv; 1679 1680 return ocelot_sb_port_pool_get(ocelot, port, sb_index, pool_index, 1681 p_threshold); 1682 } 1683 1684 static int felix_sb_port_pool_set(struct dsa_switch *ds, int port, 1685 unsigned int sb_index, u16 pool_index, 1686 u32 threshold, struct netlink_ext_ack *extack) 1687 { 1688 struct ocelot *ocelot = ds->priv; 1689 1690 return ocelot_sb_port_pool_set(ocelot, port, sb_index, pool_index, 1691 threshold, extack); 1692 } 1693 1694 static int felix_sb_tc_pool_bind_get(struct dsa_switch *ds, int port, 1695 unsigned int sb_index, u16 tc_index, 1696 enum devlink_sb_pool_type pool_type, 1697 u16 *p_pool_index, u32 *p_threshold) 1698 { 1699 struct ocelot *ocelot = ds->priv; 1700 1701 return ocelot_sb_tc_pool_bind_get(ocelot, port, sb_index, tc_index, 1702 pool_type, p_pool_index, 1703 p_threshold); 1704 } 1705 1706 static int felix_sb_tc_pool_bind_set(struct dsa_switch *ds, int port, 1707 unsigned int sb_index, u16 tc_index, 1708 enum devlink_sb_pool_type pool_type, 1709 u16 pool_index, u32 threshold, 1710 struct netlink_ext_ack *extack) 1711 { 1712 struct ocelot *ocelot = ds->priv; 1713 1714 return ocelot_sb_tc_pool_bind_set(ocelot, port, sb_index, tc_index, 1715 pool_type, pool_index, threshold, 1716 extack); 1717 } 1718 1719 static int felix_sb_occ_snapshot(struct dsa_switch *ds, 1720 unsigned int sb_index) 1721 { 1722 struct ocelot *ocelot = ds->priv; 1723 1724 return ocelot_sb_occ_snapshot(ocelot, sb_index); 1725 } 1726 1727 static int felix_sb_occ_max_clear(struct dsa_switch *ds, 1728 unsigned int sb_index) 1729 { 1730 struct ocelot *ocelot = ds->priv; 1731 1732 return ocelot_sb_occ_max_clear(ocelot, sb_index); 1733 } 1734 1735 static int felix_sb_occ_port_pool_get(struct dsa_switch *ds, int port, 1736 unsigned int sb_index, u16 pool_index, 1737 u32 *p_cur, u32 *p_max) 1738 { 1739 struct ocelot *ocelot = ds->priv; 1740 1741 return ocelot_sb_occ_port_pool_get(ocelot, port, sb_index, pool_index, 1742 p_cur, p_max); 1743 } 1744 1745 static int felix_sb_occ_tc_port_bind_get(struct dsa_switch *ds, int port, 1746 unsigned int sb_index, u16 tc_index, 1747 enum devlink_sb_pool_type pool_type, 1748 u32 *p_cur, u32 *p_max) 1749 { 1750 struct ocelot *ocelot = ds->priv; 1751 1752 return ocelot_sb_occ_tc_port_bind_get(ocelot, port, sb_index, tc_index, 1753 pool_type, p_cur, p_max); 1754 } 1755 1756 static int felix_mrp_add(struct dsa_switch *ds, int port, 1757 const struct switchdev_obj_mrp *mrp) 1758 { 1759 struct ocelot *ocelot = ds->priv; 1760 1761 return ocelot_mrp_add(ocelot, port, mrp); 1762 } 1763 1764 static int felix_mrp_del(struct dsa_switch *ds, int port, 1765 const struct switchdev_obj_mrp *mrp) 1766 { 1767 struct ocelot *ocelot = ds->priv; 1768 1769 return ocelot_mrp_add(ocelot, port, mrp); 1770 } 1771 1772 static int 1773 felix_mrp_add_ring_role(struct dsa_switch *ds, int port, 1774 const struct switchdev_obj_ring_role_mrp *mrp) 1775 { 1776 struct ocelot *ocelot = ds->priv; 1777 1778 return ocelot_mrp_add_ring_role(ocelot, port, mrp); 1779 } 1780 1781 static int 1782 felix_mrp_del_ring_role(struct dsa_switch *ds, int port, 1783 const struct switchdev_obj_ring_role_mrp *mrp) 1784 { 1785 struct ocelot *ocelot = ds->priv; 1786 1787 return ocelot_mrp_del_ring_role(ocelot, port, mrp); 1788 } 1789 1790 const struct dsa_switch_ops felix_switch_ops = { 1791 .get_tag_protocol = felix_get_tag_protocol, 1792 .change_tag_protocol = felix_change_tag_protocol, 1793 .connect_tag_protocol = felix_connect_tag_protocol, 1794 .setup = felix_setup, 1795 .teardown = felix_teardown, 1796 .set_ageing_time = felix_set_ageing_time, 1797 .get_strings = felix_get_strings, 1798 .get_ethtool_stats = felix_get_ethtool_stats, 1799 .get_sset_count = felix_get_sset_count, 1800 .get_ts_info = felix_get_ts_info, 1801 .phylink_get_caps = felix_phylink_get_caps, 1802 .phylink_validate = felix_phylink_validate, 1803 .phylink_mac_select_pcs = felix_phylink_mac_select_pcs, 1804 .phylink_mac_link_down = felix_phylink_mac_link_down, 1805 .phylink_mac_link_up = felix_phylink_mac_link_up, 1806 .port_fast_age = felix_port_fast_age, 1807 .port_fdb_dump = felix_fdb_dump, 1808 .port_fdb_add = felix_fdb_add, 1809 .port_fdb_del = felix_fdb_del, 1810 .lag_fdb_add = felix_lag_fdb_add, 1811 .lag_fdb_del = felix_lag_fdb_del, 1812 .port_mdb_add = felix_mdb_add, 1813 .port_mdb_del = felix_mdb_del, 1814 .port_pre_bridge_flags = felix_pre_bridge_flags, 1815 .port_bridge_flags = felix_bridge_flags, 1816 .port_bridge_join = felix_bridge_join, 1817 .port_bridge_leave = felix_bridge_leave, 1818 .port_lag_join = felix_lag_join, 1819 .port_lag_leave = felix_lag_leave, 1820 .port_lag_change = felix_lag_change, 1821 .port_stp_state_set = felix_bridge_stp_state_set, 1822 .port_vlan_filtering = felix_vlan_filtering, 1823 .port_vlan_add = felix_vlan_add, 1824 .port_vlan_del = felix_vlan_del, 1825 .port_hwtstamp_get = felix_hwtstamp_get, 1826 .port_hwtstamp_set = felix_hwtstamp_set, 1827 .port_rxtstamp = felix_rxtstamp, 1828 .port_txtstamp = felix_txtstamp, 1829 .port_change_mtu = felix_change_mtu, 1830 .port_max_mtu = felix_get_max_mtu, 1831 .port_policer_add = felix_port_policer_add, 1832 .port_policer_del = felix_port_policer_del, 1833 .cls_flower_add = felix_cls_flower_add, 1834 .cls_flower_del = felix_cls_flower_del, 1835 .cls_flower_stats = felix_cls_flower_stats, 1836 .port_setup_tc = felix_port_setup_tc, 1837 .devlink_sb_pool_get = felix_sb_pool_get, 1838 .devlink_sb_pool_set = felix_sb_pool_set, 1839 .devlink_sb_port_pool_get = felix_sb_port_pool_get, 1840 .devlink_sb_port_pool_set = felix_sb_port_pool_set, 1841 .devlink_sb_tc_pool_bind_get = felix_sb_tc_pool_bind_get, 1842 .devlink_sb_tc_pool_bind_set = felix_sb_tc_pool_bind_set, 1843 .devlink_sb_occ_snapshot = felix_sb_occ_snapshot, 1844 .devlink_sb_occ_max_clear = felix_sb_occ_max_clear, 1845 .devlink_sb_occ_port_pool_get = felix_sb_occ_port_pool_get, 1846 .devlink_sb_occ_tc_port_bind_get= felix_sb_occ_tc_port_bind_get, 1847 .port_mrp_add = felix_mrp_add, 1848 .port_mrp_del = felix_mrp_del, 1849 .port_mrp_add_ring_role = felix_mrp_add_ring_role, 1850 .port_mrp_del_ring_role = felix_mrp_del_ring_role, 1851 .tag_8021q_vlan_add = felix_tag_8021q_vlan_add, 1852 .tag_8021q_vlan_del = felix_tag_8021q_vlan_del, 1853 }; 1854 1855 struct net_device *felix_port_to_netdev(struct ocelot *ocelot, int port) 1856 { 1857 struct felix *felix = ocelot_to_felix(ocelot); 1858 struct dsa_switch *ds = felix->ds; 1859 1860 if (!dsa_is_user_port(ds, port)) 1861 return NULL; 1862 1863 return dsa_to_port(ds, port)->slave; 1864 } 1865 1866 int felix_netdev_to_port(struct net_device *dev) 1867 { 1868 struct dsa_port *dp; 1869 1870 dp = dsa_port_from_netdev(dev); 1871 if (IS_ERR(dp)) 1872 return -EINVAL; 1873 1874 return dp->index; 1875 } 1876