1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright 2019 NXP Semiconductors 3 * 4 * This is an umbrella module for all network switches that are 5 * register-compatible with Ocelot and that perform I/O to their host CPU 6 * through an NPI (Node Processor Interface) Ethernet port. 7 */ 8 #include <uapi/linux/if_bridge.h> 9 #include <soc/mscc/ocelot_vcap.h> 10 #include <soc/mscc/ocelot_qsys.h> 11 #include <soc/mscc/ocelot_sys.h> 12 #include <soc/mscc/ocelot_dev.h> 13 #include <soc/mscc/ocelot_ana.h> 14 #include <soc/mscc/ocelot_ptp.h> 15 #include <soc/mscc/ocelot.h> 16 #include <linux/platform_device.h> 17 #include <linux/packing.h> 18 #include <linux/module.h> 19 #include <linux/of_net.h> 20 #include <linux/pci.h> 21 #include <linux/of.h> 22 #include <net/pkt_sched.h> 23 #include <net/dsa.h> 24 #include "felix.h" 25 26 static enum dsa_tag_protocol felix_get_tag_protocol(struct dsa_switch *ds, 27 int port, 28 enum dsa_tag_protocol mp) 29 { 30 return DSA_TAG_PROTO_OCELOT; 31 } 32 33 static int felix_set_ageing_time(struct dsa_switch *ds, 34 unsigned int ageing_time) 35 { 36 struct ocelot *ocelot = ds->priv; 37 38 ocelot_set_ageing_time(ocelot, ageing_time); 39 40 return 0; 41 } 42 43 static int felix_fdb_dump(struct dsa_switch *ds, int port, 44 dsa_fdb_dump_cb_t *cb, void *data) 45 { 46 struct ocelot *ocelot = ds->priv; 47 48 return ocelot_fdb_dump(ocelot, port, cb, data); 49 } 50 51 static int felix_fdb_add(struct dsa_switch *ds, int port, 52 const unsigned char *addr, u16 vid) 53 { 54 struct ocelot *ocelot = ds->priv; 55 56 return ocelot_fdb_add(ocelot, port, addr, vid); 57 } 58 59 static int felix_fdb_del(struct dsa_switch *ds, int port, 60 const unsigned char *addr, u16 vid) 61 { 62 struct ocelot *ocelot = ds->priv; 63 64 return ocelot_fdb_del(ocelot, port, addr, vid); 65 } 66 67 /* This callback needs to be present */ 68 static int felix_mdb_prepare(struct dsa_switch *ds, int port, 69 const struct switchdev_obj_port_mdb *mdb) 70 { 71 return 0; 72 } 73 74 static void felix_mdb_add(struct dsa_switch *ds, int port, 75 const struct switchdev_obj_port_mdb *mdb) 76 { 77 struct ocelot *ocelot = ds->priv; 78 79 ocelot_port_mdb_add(ocelot, port, mdb); 80 } 81 82 static int felix_mdb_del(struct dsa_switch *ds, int port, 83 const struct switchdev_obj_port_mdb *mdb) 84 { 85 struct ocelot *ocelot = ds->priv; 86 87 return ocelot_port_mdb_del(ocelot, port, mdb); 88 } 89 90 static void felix_bridge_stp_state_set(struct dsa_switch *ds, int port, 91 u8 state) 92 { 93 struct ocelot *ocelot = ds->priv; 94 95 return ocelot_bridge_stp_state_set(ocelot, port, state); 96 } 97 98 static int felix_bridge_join(struct dsa_switch *ds, int port, 99 struct net_device *br) 100 { 101 struct ocelot *ocelot = ds->priv; 102 103 return ocelot_port_bridge_join(ocelot, port, br); 104 } 105 106 static void felix_bridge_leave(struct dsa_switch *ds, int port, 107 struct net_device *br) 108 { 109 struct ocelot *ocelot = ds->priv; 110 111 ocelot_port_bridge_leave(ocelot, port, br); 112 } 113 114 /* This callback needs to be present */ 115 static int felix_vlan_prepare(struct dsa_switch *ds, int port, 116 const struct switchdev_obj_port_vlan *vlan) 117 { 118 return 0; 119 } 120 121 static int felix_vlan_filtering(struct dsa_switch *ds, int port, bool enabled) 122 { 123 struct ocelot *ocelot = ds->priv; 124 125 ocelot_port_vlan_filtering(ocelot, port, enabled); 126 127 return 0; 128 } 129 130 static void felix_vlan_add(struct dsa_switch *ds, int port, 131 const struct switchdev_obj_port_vlan *vlan) 132 { 133 struct ocelot *ocelot = ds->priv; 134 u16 flags = vlan->flags; 135 u16 vid; 136 int err; 137 138 if (dsa_is_cpu_port(ds, port)) 139 flags &= ~BRIDGE_VLAN_INFO_UNTAGGED; 140 141 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 142 err = ocelot_vlan_add(ocelot, port, vid, 143 flags & BRIDGE_VLAN_INFO_PVID, 144 flags & BRIDGE_VLAN_INFO_UNTAGGED); 145 if (err) { 146 dev_err(ds->dev, "Failed to add VLAN %d to port %d: %d\n", 147 vid, port, err); 148 return; 149 } 150 } 151 } 152 153 static int felix_vlan_del(struct dsa_switch *ds, int port, 154 const struct switchdev_obj_port_vlan *vlan) 155 { 156 struct ocelot *ocelot = ds->priv; 157 u16 vid; 158 int err; 159 160 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 161 err = ocelot_vlan_del(ocelot, port, vid); 162 if (err) { 163 dev_err(ds->dev, "Failed to remove VLAN %d from port %d: %d\n", 164 vid, port, err); 165 return err; 166 } 167 } 168 return 0; 169 } 170 171 static int felix_port_enable(struct dsa_switch *ds, int port, 172 struct phy_device *phy) 173 { 174 struct ocelot *ocelot = ds->priv; 175 176 ocelot_port_enable(ocelot, port, phy); 177 178 return 0; 179 } 180 181 static void felix_port_disable(struct dsa_switch *ds, int port) 182 { 183 struct ocelot *ocelot = ds->priv; 184 185 return ocelot_port_disable(ocelot, port); 186 } 187 188 static void felix_phylink_validate(struct dsa_switch *ds, int port, 189 unsigned long *supported, 190 struct phylink_link_state *state) 191 { 192 struct ocelot *ocelot = ds->priv; 193 struct felix *felix = ocelot_to_felix(ocelot); 194 195 if (felix->info->phylink_validate) 196 felix->info->phylink_validate(ocelot, port, supported, state); 197 } 198 199 static int felix_phylink_mac_pcs_get_state(struct dsa_switch *ds, int port, 200 struct phylink_link_state *state) 201 { 202 struct ocelot *ocelot = ds->priv; 203 struct felix *felix = ocelot_to_felix(ocelot); 204 205 if (felix->info->pcs_link_state) 206 felix->info->pcs_link_state(ocelot, port, state); 207 208 return 0; 209 } 210 211 static void felix_phylink_mac_config(struct dsa_switch *ds, int port, 212 unsigned int link_an_mode, 213 const struct phylink_link_state *state) 214 { 215 struct ocelot *ocelot = ds->priv; 216 struct felix *felix = ocelot_to_felix(ocelot); 217 218 if (felix->info->pcs_config) 219 felix->info->pcs_config(ocelot, port, link_an_mode, state); 220 } 221 222 static void felix_phylink_mac_link_down(struct dsa_switch *ds, int port, 223 unsigned int link_an_mode, 224 phy_interface_t interface) 225 { 226 struct ocelot *ocelot = ds->priv; 227 struct ocelot_port *ocelot_port = ocelot->ports[port]; 228 229 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG); 230 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0); 231 } 232 233 static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port, 234 unsigned int link_an_mode, 235 phy_interface_t interface, 236 struct phy_device *phydev, 237 int speed, int duplex, 238 bool tx_pause, bool rx_pause) 239 { 240 struct ocelot *ocelot = ds->priv; 241 struct ocelot_port *ocelot_port = ocelot->ports[port]; 242 struct felix *felix = ocelot_to_felix(ocelot); 243 u32 mac_fc_cfg; 244 245 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and 246 * PORT_RST bits in DEV_CLOCK_CFG. Note that the way this system is 247 * integrated is that the MAC speed is fixed and it's the PCS who is 248 * performing the rate adaptation, so we have to write "1000Mbps" into 249 * the LINK_SPEED field of DEV_CLOCK_CFG (which is also its default 250 * value). 251 */ 252 ocelot_port_writel(ocelot_port, 253 DEV_CLOCK_CFG_LINK_SPEED(OCELOT_SPEED_1000), 254 DEV_CLOCK_CFG); 255 256 switch (speed) { 257 case SPEED_10: 258 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(3); 259 break; 260 case SPEED_100: 261 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(2); 262 break; 263 case SPEED_1000: 264 case SPEED_2500: 265 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(1); 266 break; 267 default: 268 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n", 269 port, speed); 270 return; 271 } 272 273 /* handle Rx pause in all cases, with 2500base-X this is used for rate 274 * adaptation. 275 */ 276 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA; 277 278 if (tx_pause) 279 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA | 280 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 281 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 282 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA; 283 284 /* Flow control. Link speed is only used here to evaluate the time 285 * specification in incoming pause frames. 286 */ 287 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port); 288 289 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 290 291 /* Undo the effects of felix_phylink_mac_link_down: 292 * enable MAC module 293 */ 294 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 295 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 296 297 /* Enable receiving frames on the port, and activate auto-learning of 298 * MAC addresses. 299 */ 300 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 301 ANA_PORT_PORT_CFG_RECV_ENA | 302 ANA_PORT_PORT_CFG_PORTID_VAL(port), 303 ANA_PORT_PORT_CFG, port); 304 305 /* Core: Enable port for frame transfer */ 306 ocelot_fields_write(ocelot, port, 307 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1); 308 309 if (felix->info->pcs_link_up) 310 felix->info->pcs_link_up(ocelot, port, link_an_mode, interface, 311 speed, duplex); 312 313 if (felix->info->port_sched_speed_set) 314 felix->info->port_sched_speed_set(ocelot, port, speed); 315 } 316 317 static void felix_port_qos_map_init(struct ocelot *ocelot, int port) 318 { 319 int i; 320 321 ocelot_rmw_gix(ocelot, 322 ANA_PORT_QOS_CFG_QOS_PCP_ENA, 323 ANA_PORT_QOS_CFG_QOS_PCP_ENA, 324 ANA_PORT_QOS_CFG, 325 port); 326 327 for (i = 0; i < FELIX_NUM_TC * 2; i++) { 328 ocelot_rmw_ix(ocelot, 329 (ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL & i) | 330 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(i), 331 ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL | 332 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M, 333 ANA_PORT_PCP_DEI_MAP, 334 port, i); 335 } 336 } 337 338 static void felix_get_strings(struct dsa_switch *ds, int port, 339 u32 stringset, u8 *data) 340 { 341 struct ocelot *ocelot = ds->priv; 342 343 return ocelot_get_strings(ocelot, port, stringset, data); 344 } 345 346 static void felix_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data) 347 { 348 struct ocelot *ocelot = ds->priv; 349 350 ocelot_get_ethtool_stats(ocelot, port, data); 351 } 352 353 static int felix_get_sset_count(struct dsa_switch *ds, int port, int sset) 354 { 355 struct ocelot *ocelot = ds->priv; 356 357 return ocelot_get_sset_count(ocelot, port, sset); 358 } 359 360 static int felix_get_ts_info(struct dsa_switch *ds, int port, 361 struct ethtool_ts_info *info) 362 { 363 struct ocelot *ocelot = ds->priv; 364 365 return ocelot_get_ts_info(ocelot, port, info); 366 } 367 368 static int felix_parse_ports_node(struct felix *felix, 369 struct device_node *ports_node, 370 phy_interface_t *port_phy_modes) 371 { 372 struct ocelot *ocelot = &felix->ocelot; 373 struct device *dev = felix->ocelot.dev; 374 struct device_node *child; 375 376 for_each_available_child_of_node(ports_node, child) { 377 phy_interface_t phy_mode; 378 u32 port; 379 int err; 380 381 /* Get switch port number from DT */ 382 if (of_property_read_u32(child, "reg", &port) < 0) { 383 dev_err(dev, "Port number not defined in device tree " 384 "(property \"reg\")\n"); 385 of_node_put(child); 386 return -ENODEV; 387 } 388 389 /* Get PHY mode from DT */ 390 err = of_get_phy_mode(child, &phy_mode); 391 if (err) { 392 dev_err(dev, "Failed to read phy-mode or " 393 "phy-interface-type property for port %d\n", 394 port); 395 of_node_put(child); 396 return -ENODEV; 397 } 398 399 err = felix->info->prevalidate_phy_mode(ocelot, port, phy_mode); 400 if (err < 0) { 401 dev_err(dev, "Unsupported PHY mode %s on port %d\n", 402 phy_modes(phy_mode), port); 403 return err; 404 } 405 406 port_phy_modes[port] = phy_mode; 407 } 408 409 return 0; 410 } 411 412 static int felix_parse_dt(struct felix *felix, phy_interface_t *port_phy_modes) 413 { 414 struct device *dev = felix->ocelot.dev; 415 struct device_node *switch_node; 416 struct device_node *ports_node; 417 int err; 418 419 switch_node = dev->of_node; 420 421 ports_node = of_get_child_by_name(switch_node, "ports"); 422 if (!ports_node) { 423 dev_err(dev, "Incorrect bindings: absent \"ports\" node\n"); 424 return -ENODEV; 425 } 426 427 err = felix_parse_ports_node(felix, ports_node, port_phy_modes); 428 of_node_put(ports_node); 429 430 return err; 431 } 432 433 static int felix_init_structs(struct felix *felix, int num_phys_ports) 434 { 435 struct ocelot *ocelot = &felix->ocelot; 436 phy_interface_t *port_phy_modes; 437 struct resource res; 438 int port, i, err; 439 440 ocelot->num_phys_ports = num_phys_ports; 441 ocelot->ports = devm_kcalloc(ocelot->dev, num_phys_ports, 442 sizeof(struct ocelot_port *), GFP_KERNEL); 443 if (!ocelot->ports) 444 return -ENOMEM; 445 446 ocelot->map = felix->info->map; 447 ocelot->stats_layout = felix->info->stats_layout; 448 ocelot->num_stats = felix->info->num_stats; 449 ocelot->shared_queue_sz = felix->info->shared_queue_sz; 450 ocelot->num_mact_rows = felix->info->num_mact_rows; 451 ocelot->vcap_is2_keys = felix->info->vcap_is2_keys; 452 ocelot->vcap_is2_actions= felix->info->vcap_is2_actions; 453 ocelot->vcap = felix->info->vcap; 454 ocelot->ops = felix->info->ops; 455 456 port_phy_modes = kcalloc(num_phys_ports, sizeof(phy_interface_t), 457 GFP_KERNEL); 458 if (!port_phy_modes) 459 return -ENOMEM; 460 461 err = felix_parse_dt(felix, port_phy_modes); 462 if (err) { 463 kfree(port_phy_modes); 464 return err; 465 } 466 467 for (i = 0; i < TARGET_MAX; i++) { 468 struct regmap *target; 469 470 if (!felix->info->target_io_res[i].name) 471 continue; 472 473 memcpy(&res, &felix->info->target_io_res[i], sizeof(res)); 474 res.flags = IORESOURCE_MEM; 475 res.start += felix->switch_base; 476 res.end += felix->switch_base; 477 478 target = ocelot_regmap_init(ocelot, &res); 479 if (IS_ERR(target)) { 480 dev_err(ocelot->dev, 481 "Failed to map device memory space\n"); 482 kfree(port_phy_modes); 483 return PTR_ERR(target); 484 } 485 486 ocelot->targets[i] = target; 487 } 488 489 err = ocelot_regfields_init(ocelot, felix->info->regfields); 490 if (err) { 491 dev_err(ocelot->dev, "failed to init reg fields map\n"); 492 kfree(port_phy_modes); 493 return err; 494 } 495 496 for (port = 0; port < num_phys_ports; port++) { 497 struct ocelot_port *ocelot_port; 498 struct regmap *target; 499 u8 *template; 500 501 ocelot_port = devm_kzalloc(ocelot->dev, 502 sizeof(struct ocelot_port), 503 GFP_KERNEL); 504 if (!ocelot_port) { 505 dev_err(ocelot->dev, 506 "failed to allocate port memory\n"); 507 kfree(port_phy_modes); 508 return -ENOMEM; 509 } 510 511 memcpy(&res, &felix->info->port_io_res[port], sizeof(res)); 512 res.flags = IORESOURCE_MEM; 513 res.start += felix->switch_base; 514 res.end += felix->switch_base; 515 516 target = ocelot_regmap_init(ocelot, &res); 517 if (IS_ERR(target)) { 518 dev_err(ocelot->dev, 519 "Failed to map memory space for port %d\n", 520 port); 521 kfree(port_phy_modes); 522 return PTR_ERR(target); 523 } 524 525 template = devm_kzalloc(ocelot->dev, OCELOT_TAG_LEN, 526 GFP_KERNEL); 527 if (!template) { 528 dev_err(ocelot->dev, 529 "Failed to allocate memory for DSA tag\n"); 530 kfree(port_phy_modes); 531 return -ENOMEM; 532 } 533 534 ocelot_port->phy_mode = port_phy_modes[port]; 535 ocelot_port->ocelot = ocelot; 536 ocelot_port->target = target; 537 ocelot_port->xmit_template = template; 538 ocelot->ports[port] = ocelot_port; 539 540 felix->info->xmit_template_populate(ocelot, port); 541 } 542 543 kfree(port_phy_modes); 544 545 if (felix->info->mdio_bus_alloc) { 546 err = felix->info->mdio_bus_alloc(ocelot); 547 if (err < 0) 548 return err; 549 } 550 551 return 0; 552 } 553 554 static struct ptp_clock_info ocelot_ptp_clock_info = { 555 .owner = THIS_MODULE, 556 .name = "felix ptp", 557 .max_adj = 0x7fffffff, 558 .n_alarm = 0, 559 .n_ext_ts = 0, 560 .n_per_out = OCELOT_PTP_PINS_NUM, 561 .n_pins = OCELOT_PTP_PINS_NUM, 562 .pps = 0, 563 .gettime64 = ocelot_ptp_gettime64, 564 .settime64 = ocelot_ptp_settime64, 565 .adjtime = ocelot_ptp_adjtime, 566 .adjfine = ocelot_ptp_adjfine, 567 .verify = ocelot_ptp_verify, 568 .enable = ocelot_ptp_enable, 569 }; 570 571 /* Hardware initialization done here so that we can allocate structures with 572 * devm without fear of dsa_register_switch returning -EPROBE_DEFER and causing 573 * us to allocate structures twice (leak memory) and map PCI memory twice 574 * (which will not work). 575 */ 576 static int felix_setup(struct dsa_switch *ds) 577 { 578 struct ocelot *ocelot = ds->priv; 579 struct felix *felix = ocelot_to_felix(ocelot); 580 int port, err; 581 int tc; 582 583 err = felix_init_structs(felix, ds->num_ports); 584 if (err) 585 return err; 586 587 ocelot_init(ocelot); 588 if (ocelot->ptp) { 589 err = ocelot_init_timestamp(ocelot, &ocelot_ptp_clock_info); 590 if (err) { 591 dev_err(ocelot->dev, 592 "Timestamp initialization failed\n"); 593 ocelot->ptp = 0; 594 } 595 } 596 597 for (port = 0; port < ds->num_ports; port++) { 598 ocelot_init_port(ocelot, port); 599 600 /* Bring up the CPU port module and configure the NPI port */ 601 if (dsa_is_cpu_port(ds, port)) 602 ocelot_configure_cpu(ocelot, port, 603 OCELOT_TAG_PREFIX_NONE, 604 OCELOT_TAG_PREFIX_LONG); 605 606 /* Set the default QoS Classification based on PCP and DEI 607 * bits of vlan tag. 608 */ 609 felix_port_qos_map_init(ocelot, port); 610 } 611 612 /* Include the CPU port module in the forwarding mask for unknown 613 * unicast - the hardware default value for ANA_FLOODING_FLD_UNICAST 614 * excludes BIT(ocelot->num_phys_ports), and so does ocelot_init, since 615 * Ocelot relies on whitelisting MAC addresses towards PGID_CPU. 616 */ 617 ocelot_write_rix(ocelot, 618 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 619 ANA_PGID_PGID, PGID_UC); 620 /* Setup the per-traffic class flooding PGIDs */ 621 for (tc = 0; tc < FELIX_NUM_TC; tc++) 622 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 623 ANA_FLOODING_FLD_BROADCAST(PGID_MC) | 624 ANA_FLOODING_FLD_UNICAST(PGID_UC), 625 ANA_FLOODING, tc); 626 627 ds->mtu_enforcement_ingress = true; 628 ds->configure_vlan_while_not_filtering = true; 629 /* It looks like the MAC/PCS interrupt register - PM0_IEVENT (0x8040) 630 * isn't instantiated for the Felix PF. 631 * In-band AN may take a few ms to complete, so we need to poll. 632 */ 633 ds->pcs_poll = true; 634 635 return 0; 636 } 637 638 static void felix_teardown(struct dsa_switch *ds) 639 { 640 struct ocelot *ocelot = ds->priv; 641 struct felix *felix = ocelot_to_felix(ocelot); 642 643 if (felix->info->mdio_bus_free) 644 felix->info->mdio_bus_free(ocelot); 645 646 ocelot_deinit_timestamp(ocelot); 647 /* stop workqueue thread */ 648 ocelot_deinit(ocelot); 649 } 650 651 static int felix_hwtstamp_get(struct dsa_switch *ds, int port, 652 struct ifreq *ifr) 653 { 654 struct ocelot *ocelot = ds->priv; 655 656 return ocelot_hwstamp_get(ocelot, port, ifr); 657 } 658 659 static int felix_hwtstamp_set(struct dsa_switch *ds, int port, 660 struct ifreq *ifr) 661 { 662 struct ocelot *ocelot = ds->priv; 663 664 return ocelot_hwstamp_set(ocelot, port, ifr); 665 } 666 667 static bool felix_rxtstamp(struct dsa_switch *ds, int port, 668 struct sk_buff *skb, unsigned int type) 669 { 670 struct skb_shared_hwtstamps *shhwtstamps; 671 struct ocelot *ocelot = ds->priv; 672 u8 *extraction = skb->data - ETH_HLEN - OCELOT_TAG_LEN; 673 u32 tstamp_lo, tstamp_hi; 674 struct timespec64 ts; 675 u64 tstamp, val; 676 677 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 678 tstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 679 680 packing(extraction, &val, 116, 85, OCELOT_TAG_LEN, UNPACK, 0); 681 tstamp_lo = (u32)val; 682 683 tstamp_hi = tstamp >> 32; 684 if ((tstamp & 0xffffffff) < tstamp_lo) 685 tstamp_hi--; 686 687 tstamp = ((u64)tstamp_hi << 32) | tstamp_lo; 688 689 shhwtstamps = skb_hwtstamps(skb); 690 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 691 shhwtstamps->hwtstamp = tstamp; 692 return false; 693 } 694 695 static bool felix_txtstamp(struct dsa_switch *ds, int port, 696 struct sk_buff *clone, unsigned int type) 697 { 698 struct ocelot *ocelot = ds->priv; 699 struct ocelot_port *ocelot_port = ocelot->ports[port]; 700 701 if (!ocelot_port_add_txtstamp_skb(ocelot_port, clone)) 702 return true; 703 704 return false; 705 } 706 707 static int felix_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 708 { 709 struct ocelot *ocelot = ds->priv; 710 711 ocelot_port_set_maxlen(ocelot, port, new_mtu); 712 713 return 0; 714 } 715 716 static int felix_get_max_mtu(struct dsa_switch *ds, int port) 717 { 718 struct ocelot *ocelot = ds->priv; 719 720 return ocelot_get_max_mtu(ocelot, port); 721 } 722 723 static int felix_cls_flower_add(struct dsa_switch *ds, int port, 724 struct flow_cls_offload *cls, bool ingress) 725 { 726 struct ocelot *ocelot = ds->priv; 727 728 return ocelot_cls_flower_replace(ocelot, port, cls, ingress); 729 } 730 731 static int felix_cls_flower_del(struct dsa_switch *ds, int port, 732 struct flow_cls_offload *cls, bool ingress) 733 { 734 struct ocelot *ocelot = ds->priv; 735 736 return ocelot_cls_flower_destroy(ocelot, port, cls, ingress); 737 } 738 739 static int felix_cls_flower_stats(struct dsa_switch *ds, int port, 740 struct flow_cls_offload *cls, bool ingress) 741 { 742 struct ocelot *ocelot = ds->priv; 743 744 return ocelot_cls_flower_stats(ocelot, port, cls, ingress); 745 } 746 747 static int felix_port_policer_add(struct dsa_switch *ds, int port, 748 struct dsa_mall_policer_tc_entry *policer) 749 { 750 struct ocelot *ocelot = ds->priv; 751 struct ocelot_policer pol = { 752 .rate = div_u64(policer->rate_bytes_per_sec, 1000) * 8, 753 .burst = policer->burst, 754 }; 755 756 return ocelot_port_policer_add(ocelot, port, &pol); 757 } 758 759 static void felix_port_policer_del(struct dsa_switch *ds, int port) 760 { 761 struct ocelot *ocelot = ds->priv; 762 763 ocelot_port_policer_del(ocelot, port); 764 } 765 766 static int felix_port_setup_tc(struct dsa_switch *ds, int port, 767 enum tc_setup_type type, 768 void *type_data) 769 { 770 struct ocelot *ocelot = ds->priv; 771 struct felix *felix = ocelot_to_felix(ocelot); 772 773 if (felix->info->port_setup_tc) 774 return felix->info->port_setup_tc(ds, port, type, type_data); 775 else 776 return -EOPNOTSUPP; 777 } 778 779 const struct dsa_switch_ops felix_switch_ops = { 780 .get_tag_protocol = felix_get_tag_protocol, 781 .setup = felix_setup, 782 .teardown = felix_teardown, 783 .set_ageing_time = felix_set_ageing_time, 784 .get_strings = felix_get_strings, 785 .get_ethtool_stats = felix_get_ethtool_stats, 786 .get_sset_count = felix_get_sset_count, 787 .get_ts_info = felix_get_ts_info, 788 .phylink_validate = felix_phylink_validate, 789 .phylink_mac_link_state = felix_phylink_mac_pcs_get_state, 790 .phylink_mac_config = felix_phylink_mac_config, 791 .phylink_mac_link_down = felix_phylink_mac_link_down, 792 .phylink_mac_link_up = felix_phylink_mac_link_up, 793 .port_enable = felix_port_enable, 794 .port_disable = felix_port_disable, 795 .port_fdb_dump = felix_fdb_dump, 796 .port_fdb_add = felix_fdb_add, 797 .port_fdb_del = felix_fdb_del, 798 .port_mdb_prepare = felix_mdb_prepare, 799 .port_mdb_add = felix_mdb_add, 800 .port_mdb_del = felix_mdb_del, 801 .port_bridge_join = felix_bridge_join, 802 .port_bridge_leave = felix_bridge_leave, 803 .port_stp_state_set = felix_bridge_stp_state_set, 804 .port_vlan_prepare = felix_vlan_prepare, 805 .port_vlan_filtering = felix_vlan_filtering, 806 .port_vlan_add = felix_vlan_add, 807 .port_vlan_del = felix_vlan_del, 808 .port_hwtstamp_get = felix_hwtstamp_get, 809 .port_hwtstamp_set = felix_hwtstamp_set, 810 .port_rxtstamp = felix_rxtstamp, 811 .port_txtstamp = felix_txtstamp, 812 .port_change_mtu = felix_change_mtu, 813 .port_max_mtu = felix_get_max_mtu, 814 .port_policer_add = felix_port_policer_add, 815 .port_policer_del = felix_port_policer_del, 816 .cls_flower_add = felix_cls_flower_add, 817 .cls_flower_del = felix_cls_flower_del, 818 .cls_flower_stats = felix_cls_flower_stats, 819 .port_setup_tc = felix_port_setup_tc, 820 }; 821 822 static int __init felix_init(void) 823 { 824 int err; 825 826 err = pci_register_driver(&felix_vsc9959_pci_driver); 827 if (err) 828 return err; 829 830 err = platform_driver_register(&seville_vsc9953_driver); 831 if (err) 832 return err; 833 834 return 0; 835 } 836 module_init(felix_init); 837 838 static void __exit felix_exit(void) 839 { 840 pci_unregister_driver(&felix_vsc9959_pci_driver); 841 platform_driver_unregister(&seville_vsc9953_driver); 842 } 843 module_exit(felix_exit); 844 845 MODULE_DESCRIPTION("Felix Switch driver"); 846 MODULE_LICENSE("GPL v2"); 847