1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright 2019-2021 NXP 3 * 4 * This is an umbrella module for all network switches that are 5 * register-compatible with Ocelot and that perform I/O to their host CPU 6 * through an NPI (Node Processor Interface) Ethernet port. 7 */ 8 #include <uapi/linux/if_bridge.h> 9 #include <soc/mscc/ocelot_vcap.h> 10 #include <soc/mscc/ocelot_qsys.h> 11 #include <soc/mscc/ocelot_sys.h> 12 #include <soc/mscc/ocelot_dev.h> 13 #include <soc/mscc/ocelot_ana.h> 14 #include <soc/mscc/ocelot_ptp.h> 15 #include <soc/mscc/ocelot.h> 16 #include <linux/dsa/8021q.h> 17 #include <linux/dsa/ocelot.h> 18 #include <linux/platform_device.h> 19 #include <linux/ptp_classify.h> 20 #include <linux/module.h> 21 #include <linux/of_net.h> 22 #include <linux/pci.h> 23 #include <linux/of.h> 24 #include <net/pkt_sched.h> 25 #include <net/dsa.h> 26 #include "felix.h" 27 28 /* Translate the DSA database API into the ocelot switch library API, 29 * which uses VID 0 for all ports that aren't part of a bridge, 30 * and expects the bridge_dev to be NULL in that case. 31 */ 32 static struct net_device *felix_classify_db(struct dsa_db db) 33 { 34 switch (db.type) { 35 case DSA_DB_PORT: 36 case DSA_DB_LAG: 37 return NULL; 38 case DSA_DB_BRIDGE: 39 return db.bridge.dev; 40 default: 41 return ERR_PTR(-EOPNOTSUPP); 42 } 43 } 44 45 static int felix_cpu_port_for_conduit(struct dsa_switch *ds, 46 struct net_device *conduit) 47 { 48 struct ocelot *ocelot = ds->priv; 49 struct dsa_port *cpu_dp; 50 int lag; 51 52 if (netif_is_lag_master(conduit)) { 53 mutex_lock(&ocelot->fwd_domain_lock); 54 lag = ocelot_bond_get_id(ocelot, conduit); 55 mutex_unlock(&ocelot->fwd_domain_lock); 56 57 return lag; 58 } 59 60 cpu_dp = conduit->dsa_ptr; 61 return cpu_dp->index; 62 } 63 64 /** 65 * felix_update_tag_8021q_rx_rule - Update VCAP ES0 tag_8021q rule after 66 * vlan_filtering change 67 * @outer_tagging_rule: Pointer to VCAP filter on which the update is performed 68 * @vlan_filtering: Current bridge VLAN filtering setting 69 * 70 * Source port identification for tag_8021q is done using VCAP ES0 rules on the 71 * CPU port(s). The ES0 tag B (inner tag from the packet) can be configured as 72 * either: 73 * - push_inner_tag=0: the inner tag is never pushed into the frame 74 * (and we lose info about the classified VLAN). This is 75 * good when the classified VLAN is a discardable quantity 76 * for the software RX path: it is either set to 77 * OCELOT_STANDALONE_PVID, or to 78 * ocelot_vlan_unaware_pvid(bridge). 79 * - push_inner_tag=1: the inner tag is always pushed. This is good when the 80 * classified VLAN is not a discardable quantity (the port 81 * is under a VLAN-aware bridge, and software needs to 82 * continue processing the packet in the same VLAN as the 83 * hardware). 84 * The point is that what is good for a VLAN-unaware port is not good for a 85 * VLAN-aware port, and vice versa. Thus, the RX tagging rules must be kept in 86 * sync with the VLAN filtering state of the port. 87 */ 88 static void 89 felix_update_tag_8021q_rx_rule(struct ocelot_vcap_filter *outer_tagging_rule, 90 bool vlan_filtering) 91 { 92 if (vlan_filtering) 93 outer_tagging_rule->action.push_inner_tag = OCELOT_ES0_TAG; 94 else 95 outer_tagging_rule->action.push_inner_tag = OCELOT_NO_ES0_TAG; 96 } 97 98 /* Set up VCAP ES0 rules for pushing a tag_8021q VLAN towards the CPU such that 99 * the tagger can perform RX source port identification. 100 */ 101 static int felix_tag_8021q_vlan_add_rx(struct dsa_switch *ds, int port, 102 int upstream, u16 vid, 103 bool vlan_filtering) 104 { 105 struct ocelot_vcap_filter *outer_tagging_rule; 106 struct ocelot *ocelot = ds->priv; 107 unsigned long cookie; 108 int key_length, err; 109 110 key_length = ocelot->vcap[VCAP_ES0].keys[VCAP_ES0_IGR_PORT].length; 111 112 outer_tagging_rule = kzalloc_obj(struct ocelot_vcap_filter); 113 if (!outer_tagging_rule) 114 return -ENOMEM; 115 116 cookie = OCELOT_VCAP_ES0_TAG_8021Q_RXVLAN(ocelot, port, upstream); 117 118 outer_tagging_rule->key_type = OCELOT_VCAP_KEY_ANY; 119 outer_tagging_rule->prio = 1; 120 outer_tagging_rule->id.cookie = cookie; 121 outer_tagging_rule->id.tc_offload = false; 122 outer_tagging_rule->block_id = VCAP_ES0; 123 outer_tagging_rule->type = OCELOT_VCAP_FILTER_OFFLOAD; 124 outer_tagging_rule->lookup = 0; 125 outer_tagging_rule->ingress_port.value = port; 126 outer_tagging_rule->ingress_port.mask = GENMASK(key_length - 1, 0); 127 outer_tagging_rule->egress_port.value = upstream; 128 outer_tagging_rule->egress_port.mask = GENMASK(key_length - 1, 0); 129 outer_tagging_rule->action.push_outer_tag = OCELOT_ES0_TAG; 130 outer_tagging_rule->action.tag_a_tpid_sel = OCELOT_TAG_TPID_SEL_8021AD; 131 outer_tagging_rule->action.tag_a_vid_sel = 1; 132 outer_tagging_rule->action.vid_a_val = vid; 133 felix_update_tag_8021q_rx_rule(outer_tagging_rule, vlan_filtering); 134 outer_tagging_rule->action.tag_b_tpid_sel = OCELOT_TAG_TPID_SEL_8021Q; 135 /* Leave TAG_B_VID_SEL at 0 (Classified VID + VID_B_VAL). Since we also 136 * leave VID_B_VAL at 0, this makes ES0 tag B (the inner tag) equal to 137 * the classified VID, which we need to see in the DSA tagger's receive 138 * path. Note: the inner tag is only visible in the packet when pushed 139 * (push_inner_tag == OCELOT_ES0_TAG). 140 */ 141 142 err = ocelot_vcap_filter_add(ocelot, outer_tagging_rule, NULL); 143 if (err) 144 kfree(outer_tagging_rule); 145 146 return err; 147 } 148 149 static int felix_tag_8021q_vlan_del_rx(struct dsa_switch *ds, int port, 150 int upstream, u16 vid) 151 { 152 struct ocelot_vcap_filter *outer_tagging_rule; 153 struct ocelot_vcap_block *block_vcap_es0; 154 struct ocelot *ocelot = ds->priv; 155 unsigned long cookie; 156 157 block_vcap_es0 = &ocelot->block[VCAP_ES0]; 158 cookie = OCELOT_VCAP_ES0_TAG_8021Q_RXVLAN(ocelot, port, upstream); 159 160 outer_tagging_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_es0, 161 cookie, false); 162 if (!outer_tagging_rule) 163 return -ENOENT; 164 165 return ocelot_vcap_filter_del(ocelot, outer_tagging_rule); 166 } 167 168 /* Set up VCAP IS1 rules for stripping the tag_8021q VLAN on TX and VCAP IS2 169 * rules for steering those tagged packets towards the correct destination port 170 */ 171 static int felix_tag_8021q_vlan_add_tx(struct dsa_switch *ds, int port, 172 u16 vid) 173 { 174 struct ocelot_vcap_filter *untagging_rule, *redirect_rule; 175 unsigned long cpu_ports = dsa_cpu_ports(ds); 176 struct ocelot *ocelot = ds->priv; 177 unsigned long cookie; 178 int err; 179 180 untagging_rule = kzalloc_obj(struct ocelot_vcap_filter); 181 if (!untagging_rule) 182 return -ENOMEM; 183 184 redirect_rule = kzalloc_obj(struct ocelot_vcap_filter); 185 if (!redirect_rule) { 186 kfree(untagging_rule); 187 return -ENOMEM; 188 } 189 190 cookie = OCELOT_VCAP_IS1_TAG_8021Q_TXVLAN(ocelot, port); 191 192 untagging_rule->key_type = OCELOT_VCAP_KEY_ANY; 193 untagging_rule->ingress_port_mask = cpu_ports; 194 untagging_rule->vlan.vid.value = vid; 195 untagging_rule->vlan.vid.mask = VLAN_VID_MASK; 196 untagging_rule->prio = 1; 197 untagging_rule->id.cookie = cookie; 198 untagging_rule->id.tc_offload = false; 199 untagging_rule->block_id = VCAP_IS1; 200 untagging_rule->type = OCELOT_VCAP_FILTER_OFFLOAD; 201 untagging_rule->lookup = 0; 202 untagging_rule->action.vlan_pop_cnt_ena = true; 203 untagging_rule->action.vlan_pop_cnt = 1; 204 untagging_rule->action.pag_override_mask = 0xff; 205 untagging_rule->action.pag_val = port; 206 207 err = ocelot_vcap_filter_add(ocelot, untagging_rule, NULL); 208 if (err) { 209 kfree(untagging_rule); 210 kfree(redirect_rule); 211 return err; 212 } 213 214 cookie = OCELOT_VCAP_IS2_TAG_8021Q_TXVLAN(ocelot, port); 215 216 redirect_rule->key_type = OCELOT_VCAP_KEY_ANY; 217 redirect_rule->ingress_port_mask = cpu_ports; 218 redirect_rule->pag = port; 219 redirect_rule->prio = 1; 220 redirect_rule->id.cookie = cookie; 221 redirect_rule->id.tc_offload = false; 222 redirect_rule->block_id = VCAP_IS2; 223 redirect_rule->type = OCELOT_VCAP_FILTER_OFFLOAD; 224 redirect_rule->lookup = 0; 225 redirect_rule->action.mask_mode = OCELOT_MASK_MODE_REDIRECT; 226 redirect_rule->action.port_mask = BIT(port); 227 228 err = ocelot_vcap_filter_add(ocelot, redirect_rule, NULL); 229 if (err) { 230 ocelot_vcap_filter_del(ocelot, untagging_rule); 231 kfree(redirect_rule); 232 return err; 233 } 234 235 return 0; 236 } 237 238 static int felix_tag_8021q_vlan_del_tx(struct dsa_switch *ds, int port, u16 vid) 239 { 240 struct ocelot_vcap_filter *untagging_rule, *redirect_rule; 241 struct ocelot_vcap_block *block_vcap_is1; 242 struct ocelot_vcap_block *block_vcap_is2; 243 struct ocelot *ocelot = ds->priv; 244 unsigned long cookie; 245 int err; 246 247 block_vcap_is1 = &ocelot->block[VCAP_IS1]; 248 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 249 250 cookie = OCELOT_VCAP_IS1_TAG_8021Q_TXVLAN(ocelot, port); 251 untagging_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is1, 252 cookie, false); 253 if (!untagging_rule) 254 return -ENOENT; 255 256 err = ocelot_vcap_filter_del(ocelot, untagging_rule); 257 if (err) 258 return err; 259 260 cookie = OCELOT_VCAP_IS2_TAG_8021Q_TXVLAN(ocelot, port); 261 redirect_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, 262 cookie, false); 263 if (!redirect_rule) 264 return -ENOENT; 265 266 return ocelot_vcap_filter_del(ocelot, redirect_rule); 267 } 268 269 static int felix_tag_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid, 270 u16 flags) 271 { 272 struct dsa_port *dp = dsa_to_port(ds, port); 273 struct dsa_port *cpu_dp; 274 int err; 275 276 /* tag_8021q.c assumes we are implementing this via port VLAN 277 * membership, which we aren't. So we don't need to add any VCAP filter 278 * for the CPU port. 279 */ 280 if (!dsa_port_is_user(dp)) 281 return 0; 282 283 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 284 err = felix_tag_8021q_vlan_add_rx(ds, port, cpu_dp->index, vid, 285 dsa_port_is_vlan_filtering(dp)); 286 if (err) 287 return err; 288 } 289 290 err = felix_tag_8021q_vlan_add_tx(ds, port, vid); 291 if (err) 292 goto add_tx_failed; 293 294 return 0; 295 296 add_tx_failed: 297 dsa_switch_for_each_cpu_port(cpu_dp, ds) 298 felix_tag_8021q_vlan_del_rx(ds, port, cpu_dp->index, vid); 299 300 return err; 301 } 302 303 static int felix_tag_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid) 304 { 305 struct dsa_port *dp = dsa_to_port(ds, port); 306 struct dsa_port *cpu_dp; 307 int err; 308 309 if (!dsa_port_is_user(dp)) 310 return 0; 311 312 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 313 err = felix_tag_8021q_vlan_del_rx(ds, port, cpu_dp->index, vid); 314 if (err) 315 return err; 316 } 317 318 err = felix_tag_8021q_vlan_del_tx(ds, port, vid); 319 if (err) 320 goto del_tx_failed; 321 322 return 0; 323 324 del_tx_failed: 325 dsa_switch_for_each_cpu_port(cpu_dp, ds) 326 felix_tag_8021q_vlan_add_rx(ds, port, cpu_dp->index, vid, 327 dsa_port_is_vlan_filtering(dp)); 328 329 return err; 330 } 331 332 static int felix_update_tag_8021q_rx_rules(struct dsa_switch *ds, int port, 333 bool vlan_filtering) 334 { 335 struct ocelot_vcap_filter *outer_tagging_rule; 336 struct ocelot_vcap_block *block_vcap_es0; 337 struct ocelot *ocelot = ds->priv; 338 struct dsa_port *cpu_dp; 339 unsigned long cookie; 340 int err; 341 342 block_vcap_es0 = &ocelot->block[VCAP_ES0]; 343 344 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 345 cookie = OCELOT_VCAP_ES0_TAG_8021Q_RXVLAN(ocelot, port, 346 cpu_dp->index); 347 348 outer_tagging_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_es0, 349 cookie, false); 350 351 felix_update_tag_8021q_rx_rule(outer_tagging_rule, vlan_filtering); 352 353 err = ocelot_vcap_filter_replace(ocelot, outer_tagging_rule); 354 if (err) 355 return err; 356 } 357 358 return 0; 359 } 360 361 static int felix_trap_get_cpu_port(struct dsa_switch *ds, 362 const struct ocelot_vcap_filter *trap) 363 { 364 struct dsa_port *dp; 365 int first_port; 366 367 if (WARN_ON(!trap->ingress_port_mask)) 368 return -1; 369 370 first_port = __ffs(trap->ingress_port_mask); 371 dp = dsa_to_port(ds, first_port); 372 373 return dp->cpu_dp->index; 374 } 375 376 /* On switches with no extraction IRQ wired, trapped packets need to be 377 * replicated over Ethernet as well, otherwise we'd get no notification of 378 * their arrival when using the ocelot-8021q tagging protocol. 379 */ 380 static int felix_update_trapping_destinations(struct dsa_switch *ds, 381 bool using_tag_8021q) 382 { 383 struct ocelot *ocelot = ds->priv; 384 struct felix *felix = ocelot_to_felix(ocelot); 385 struct ocelot_vcap_block *block_vcap_is2; 386 struct ocelot_vcap_filter *trap; 387 enum ocelot_mask_mode mask_mode; 388 unsigned long port_mask; 389 bool cpu_copy_ena; 390 int err; 391 392 if (!felix->info->quirk_no_xtr_irq) 393 return 0; 394 395 /* We are sure that "cpu" was found, otherwise 396 * dsa_tree_setup_default_cpu() would have failed earlier. 397 */ 398 block_vcap_is2 = &ocelot->block[VCAP_IS2]; 399 400 /* Make sure all traps are set up for that destination */ 401 list_for_each_entry(trap, &block_vcap_is2->rules, list) { 402 if (!trap->is_trap) 403 continue; 404 405 /* Figure out the current trapping destination */ 406 if (using_tag_8021q) { 407 /* Redirect to the tag_8021q CPU port. If timestamps 408 * are necessary, also copy trapped packets to the CPU 409 * port module. 410 */ 411 mask_mode = OCELOT_MASK_MODE_REDIRECT; 412 port_mask = BIT(felix_trap_get_cpu_port(ds, trap)); 413 cpu_copy_ena = !!trap->take_ts; 414 } else { 415 /* Trap packets only to the CPU port module, which is 416 * redirected to the NPI port (the DSA CPU port) 417 */ 418 mask_mode = OCELOT_MASK_MODE_PERMIT_DENY; 419 port_mask = 0; 420 cpu_copy_ena = true; 421 } 422 423 if (trap->action.mask_mode == mask_mode && 424 trap->action.port_mask == port_mask && 425 trap->action.cpu_copy_ena == cpu_copy_ena) 426 continue; 427 428 trap->action.mask_mode = mask_mode; 429 trap->action.port_mask = port_mask; 430 trap->action.cpu_copy_ena = cpu_copy_ena; 431 432 err = ocelot_vcap_filter_replace(ocelot, trap); 433 if (err) 434 return err; 435 } 436 437 return 0; 438 } 439 440 /* The CPU port module is connected to the Node Processor Interface (NPI). This 441 * is the mode through which frames can be injected from and extracted to an 442 * external CPU, over Ethernet. In NXP SoCs, the "external CPU" is the ARM CPU 443 * running Linux, and this forms a DSA setup together with the enetc or fman 444 * DSA conduit. 445 */ 446 static void felix_npi_port_init(struct ocelot *ocelot, int port) 447 { 448 ocelot->npi = port; 449 450 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M | 451 QSYS_EXT_CPU_CFG_EXT_CPU_PORT(port), 452 QSYS_EXT_CPU_CFG); 453 454 /* NPI port Injection/Extraction configuration */ 455 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_XTR_HDR, 456 ocelot->npi_xtr_prefix); 457 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_INJ_HDR, 458 ocelot->npi_inj_prefix); 459 460 /* Disable transmission of pause frames */ 461 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0); 462 } 463 464 static void felix_npi_port_deinit(struct ocelot *ocelot, int port) 465 { 466 /* Restore hardware defaults */ 467 int unused_port = ocelot->num_phys_ports + 2; 468 469 ocelot->npi = -1; 470 471 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPU_PORT(unused_port), 472 QSYS_EXT_CPU_CFG); 473 474 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_XTR_HDR, 475 OCELOT_TAG_PREFIX_DISABLED); 476 ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_INJ_HDR, 477 OCELOT_TAG_PREFIX_DISABLED); 478 479 /* Enable transmission of pause frames */ 480 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1); 481 } 482 483 static int felix_tag_npi_setup(struct dsa_switch *ds) 484 { 485 struct dsa_port *dp, *first_cpu_dp = NULL; 486 struct ocelot *ocelot = ds->priv; 487 488 dsa_switch_for_each_user_port(dp, ds) { 489 if (first_cpu_dp && dp->cpu_dp != first_cpu_dp) { 490 dev_err(ds->dev, "Multiple NPI ports not supported\n"); 491 return -EINVAL; 492 } 493 494 first_cpu_dp = dp->cpu_dp; 495 } 496 497 if (!first_cpu_dp) 498 return -EINVAL; 499 500 felix_npi_port_init(ocelot, first_cpu_dp->index); 501 502 return 0; 503 } 504 505 static void felix_tag_npi_teardown(struct dsa_switch *ds) 506 { 507 struct ocelot *ocelot = ds->priv; 508 509 felix_npi_port_deinit(ocelot, ocelot->npi); 510 } 511 512 static unsigned long felix_tag_npi_get_host_fwd_mask(struct dsa_switch *ds) 513 { 514 struct ocelot *ocelot = ds->priv; 515 516 return BIT(ocelot->num_phys_ports); 517 } 518 519 static int felix_tag_npi_change_conduit(struct dsa_switch *ds, int port, 520 struct net_device *conduit, 521 struct netlink_ext_ack *extack) 522 { 523 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 524 struct ocelot *ocelot = ds->priv; 525 526 if (netif_is_lag_master(conduit)) { 527 NL_SET_ERR_MSG_MOD(extack, 528 "LAG DSA conduit only supported using ocelot-8021q"); 529 return -EOPNOTSUPP; 530 } 531 532 /* Changing the NPI port breaks user ports still assigned to the old 533 * one, so only allow it while they're down, and don't allow them to 534 * come back up until they're all changed to the new one. 535 */ 536 dsa_switch_for_each_user_port(other_dp, ds) { 537 struct net_device *user = other_dp->user; 538 539 if (other_dp != dp && (user->flags & IFF_UP) && 540 dsa_port_to_conduit(other_dp) != conduit) { 541 NL_SET_ERR_MSG_MOD(extack, 542 "Cannot change while old conduit still has users"); 543 return -EOPNOTSUPP; 544 } 545 } 546 547 felix_npi_port_deinit(ocelot, ocelot->npi); 548 felix_npi_port_init(ocelot, felix_cpu_port_for_conduit(ds, conduit)); 549 550 return 0; 551 } 552 553 /* Alternatively to using the NPI functionality, that same hardware MAC 554 * connected internally to the enetc or fman DSA conduit can be configured to 555 * use the software-defined tag_8021q frame format. As far as the hardware is 556 * concerned, it thinks it is a "dumb switch" - the queues of the CPU port 557 * module are now disconnected from it, but can still be accessed through 558 * register-based MMIO. 559 */ 560 static const struct felix_tag_proto_ops felix_tag_npi_proto_ops = { 561 .setup = felix_tag_npi_setup, 562 .teardown = felix_tag_npi_teardown, 563 .get_host_fwd_mask = felix_tag_npi_get_host_fwd_mask, 564 .change_conduit = felix_tag_npi_change_conduit, 565 }; 566 567 static int felix_tag_8021q_setup(struct dsa_switch *ds) 568 { 569 struct ocelot *ocelot = ds->priv; 570 struct dsa_port *dp; 571 int err; 572 573 err = dsa_tag_8021q_register(ds, htons(ETH_P_8021AD)); 574 if (err) 575 return err; 576 577 dsa_switch_for_each_cpu_port(dp, ds) 578 ocelot_port_setup_dsa_8021q_cpu(ocelot, dp->index); 579 580 dsa_switch_for_each_user_port(dp, ds) 581 ocelot_port_assign_dsa_8021q_cpu(ocelot, dp->index, 582 dp->cpu_dp->index); 583 584 dsa_switch_for_each_available_port(dp, ds) 585 /* This overwrites ocelot_init(): 586 * Do not forward BPDU frames to the CPU port module, 587 * for 2 reasons: 588 * - When these packets are injected from the tag_8021q 589 * CPU port, we want them to go out, not loop back 590 * into the system. 591 * - STP traffic ingressing on a user port should go to 592 * the tag_8021q CPU port, not to the hardware CPU 593 * port module. 594 */ 595 ocelot_write_gix(ocelot, 596 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0), 597 ANA_PORT_CPU_FWD_BPDU_CFG, dp->index); 598 599 /* The ownership of the CPU port module's queues might have just been 600 * transferred to the tag_8021q tagger from the NPI-based tagger. 601 * So there might still be all sorts of crap in the queues. On the 602 * other hand, the MMIO-based matching of PTP frames is very brittle, 603 * so we need to be careful that there are no extra frames to be 604 * dequeued over MMIO, since we would never know to discard them. 605 */ 606 ocelot_lock_xtr_grp_bh(ocelot, 0); 607 ocelot_drain_cpu_queue(ocelot, 0); 608 ocelot_unlock_xtr_grp_bh(ocelot, 0); 609 610 /* Problem: when using push_inner_tag=1 for ES0 tag B, we lose info 611 * about whether the received packets were VLAN-tagged on the wire, 612 * since they are always tagged on egress towards the CPU port. 613 * 614 * Since using push_inner_tag=1 is unavoidable for VLAN-aware bridges, 615 * we must work around the fallout by untagging in software to make 616 * untagged reception work more or less as expected. 617 */ 618 ds->untag_vlan_aware_bridge_pvid = true; 619 620 return 0; 621 } 622 623 static void felix_tag_8021q_teardown(struct dsa_switch *ds) 624 { 625 struct ocelot *ocelot = ds->priv; 626 struct dsa_port *dp; 627 628 dsa_switch_for_each_available_port(dp, ds) 629 /* Restore the logic from ocelot_init: 630 * do not forward BPDU frames to the front ports. 631 */ 632 ocelot_write_gix(ocelot, 633 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 634 ANA_PORT_CPU_FWD_BPDU_CFG, 635 dp->index); 636 637 dsa_switch_for_each_user_port(dp, ds) 638 ocelot_port_unassign_dsa_8021q_cpu(ocelot, dp->index); 639 640 dsa_switch_for_each_cpu_port(dp, ds) 641 ocelot_port_teardown_dsa_8021q_cpu(ocelot, dp->index); 642 643 dsa_tag_8021q_unregister(ds); 644 645 ds->untag_vlan_aware_bridge_pvid = false; 646 } 647 648 static unsigned long felix_tag_8021q_get_host_fwd_mask(struct dsa_switch *ds) 649 { 650 return dsa_cpu_ports(ds); 651 } 652 653 static int felix_tag_8021q_change_conduit(struct dsa_switch *ds, int port, 654 struct net_device *conduit, 655 struct netlink_ext_ack *extack) 656 { 657 int cpu = felix_cpu_port_for_conduit(ds, conduit); 658 struct ocelot *ocelot = ds->priv; 659 660 ocelot_port_unassign_dsa_8021q_cpu(ocelot, port); 661 ocelot_port_assign_dsa_8021q_cpu(ocelot, port, cpu); 662 663 return felix_update_trapping_destinations(ds, true); 664 } 665 666 static const struct felix_tag_proto_ops felix_tag_8021q_proto_ops = { 667 .setup = felix_tag_8021q_setup, 668 .teardown = felix_tag_8021q_teardown, 669 .get_host_fwd_mask = felix_tag_8021q_get_host_fwd_mask, 670 .change_conduit = felix_tag_8021q_change_conduit, 671 }; 672 673 static void felix_set_host_flood(struct dsa_switch *ds, unsigned long mask, 674 bool uc, bool mc, bool bc) 675 { 676 struct ocelot *ocelot = ds->priv; 677 unsigned long val; 678 679 val = uc ? mask : 0; 680 ocelot_rmw_rix(ocelot, val, mask, ANA_PGID_PGID, PGID_UC); 681 682 val = mc ? mask : 0; 683 ocelot_rmw_rix(ocelot, val, mask, ANA_PGID_PGID, PGID_MC); 684 ocelot_rmw_rix(ocelot, val, mask, ANA_PGID_PGID, PGID_MCIPV4); 685 ocelot_rmw_rix(ocelot, val, mask, ANA_PGID_PGID, PGID_MCIPV6); 686 687 val = bc ? mask : 0; 688 ocelot_rmw_rix(ocelot, val, mask, ANA_PGID_PGID, PGID_BC); 689 } 690 691 static void 692 felix_migrate_host_flood(struct dsa_switch *ds, 693 const struct felix_tag_proto_ops *proto_ops, 694 const struct felix_tag_proto_ops *old_proto_ops) 695 { 696 struct ocelot *ocelot = ds->priv; 697 struct felix *felix = ocelot_to_felix(ocelot); 698 unsigned long mask; 699 700 if (old_proto_ops) { 701 mask = old_proto_ops->get_host_fwd_mask(ds); 702 felix_set_host_flood(ds, mask, false, false, false); 703 } 704 705 mask = proto_ops->get_host_fwd_mask(ds); 706 felix_set_host_flood(ds, mask, !!felix->host_flood_uc_mask, 707 !!felix->host_flood_mc_mask, true); 708 } 709 710 static int felix_migrate_mdbs(struct dsa_switch *ds, 711 const struct felix_tag_proto_ops *proto_ops, 712 const struct felix_tag_proto_ops *old_proto_ops) 713 { 714 struct ocelot *ocelot = ds->priv; 715 unsigned long from, to; 716 717 if (!old_proto_ops) 718 return 0; 719 720 from = old_proto_ops->get_host_fwd_mask(ds); 721 to = proto_ops->get_host_fwd_mask(ds); 722 723 return ocelot_migrate_mdbs(ocelot, from, to); 724 } 725 726 /* Configure the shared hardware resources for a transition between 727 * @old_proto_ops and @proto_ops. 728 * Manual migration is needed because as far as DSA is concerned, no change of 729 * the CPU port is taking place here, just of the tagging protocol. 730 */ 731 static int 732 felix_tag_proto_setup_shared(struct dsa_switch *ds, 733 const struct felix_tag_proto_ops *proto_ops, 734 const struct felix_tag_proto_ops *old_proto_ops) 735 { 736 bool using_tag_8021q = (proto_ops == &felix_tag_8021q_proto_ops); 737 int err; 738 739 err = felix_migrate_mdbs(ds, proto_ops, old_proto_ops); 740 if (err) 741 return err; 742 743 felix_update_trapping_destinations(ds, using_tag_8021q); 744 745 felix_migrate_host_flood(ds, proto_ops, old_proto_ops); 746 747 return 0; 748 } 749 750 /* This always leaves the switch in a consistent state, because although the 751 * tag_8021q setup can fail, the NPI setup can't. So either the change is made, 752 * or the restoration is guaranteed to work. 753 */ 754 static int felix_change_tag_protocol(struct dsa_switch *ds, 755 enum dsa_tag_protocol proto) 756 { 757 const struct felix_tag_proto_ops *old_proto_ops, *proto_ops; 758 struct ocelot *ocelot = ds->priv; 759 struct felix *felix = ocelot_to_felix(ocelot); 760 int err; 761 762 switch (proto) { 763 case DSA_TAG_PROTO_SEVILLE: 764 case DSA_TAG_PROTO_OCELOT: 765 proto_ops = &felix_tag_npi_proto_ops; 766 break; 767 case DSA_TAG_PROTO_OCELOT_8021Q: 768 proto_ops = &felix_tag_8021q_proto_ops; 769 break; 770 default: 771 return -EPROTONOSUPPORT; 772 } 773 774 old_proto_ops = felix->tag_proto_ops; 775 776 if (proto_ops == old_proto_ops) 777 return 0; 778 779 err = proto_ops->setup(ds); 780 if (err) 781 goto setup_failed; 782 783 err = felix_tag_proto_setup_shared(ds, proto_ops, old_proto_ops); 784 if (err) 785 goto setup_shared_failed; 786 787 if (old_proto_ops) 788 old_proto_ops->teardown(ds); 789 790 felix->tag_proto_ops = proto_ops; 791 felix->tag_proto = proto; 792 793 return 0; 794 795 setup_shared_failed: 796 proto_ops->teardown(ds); 797 setup_failed: 798 return err; 799 } 800 801 static enum dsa_tag_protocol felix_get_tag_protocol(struct dsa_switch *ds, 802 int port, 803 enum dsa_tag_protocol mp) 804 { 805 struct ocelot *ocelot = ds->priv; 806 struct felix *felix = ocelot_to_felix(ocelot); 807 808 return felix->tag_proto; 809 } 810 811 static void felix_port_set_host_flood(struct dsa_switch *ds, int port, 812 bool uc, bool mc) 813 { 814 struct ocelot *ocelot = ds->priv; 815 struct felix *felix = ocelot_to_felix(ocelot); 816 unsigned long mask; 817 818 if (uc) 819 felix->host_flood_uc_mask |= BIT(port); 820 else 821 felix->host_flood_uc_mask &= ~BIT(port); 822 823 if (mc) 824 felix->host_flood_mc_mask |= BIT(port); 825 else 826 felix->host_flood_mc_mask &= ~BIT(port); 827 828 mask = felix->tag_proto_ops->get_host_fwd_mask(ds); 829 felix_set_host_flood(ds, mask, !!felix->host_flood_uc_mask, 830 !!felix->host_flood_mc_mask, true); 831 } 832 833 static int felix_port_change_conduit(struct dsa_switch *ds, int port, 834 struct net_device *conduit, 835 struct netlink_ext_ack *extack) 836 { 837 struct ocelot *ocelot = ds->priv; 838 struct felix *felix = ocelot_to_felix(ocelot); 839 840 return felix->tag_proto_ops->change_conduit(ds, port, conduit, extack); 841 } 842 843 static int felix_set_ageing_time(struct dsa_switch *ds, 844 unsigned int ageing_time) 845 { 846 struct ocelot *ocelot = ds->priv; 847 848 ocelot_set_ageing_time(ocelot, ageing_time); 849 850 return 0; 851 } 852 853 static void felix_port_fast_age(struct dsa_switch *ds, int port) 854 { 855 struct ocelot *ocelot = ds->priv; 856 int err; 857 858 err = ocelot_mact_flush(ocelot, port); 859 if (err) 860 dev_err(ds->dev, "Flushing MAC table on port %d returned %pe\n", 861 port, ERR_PTR(err)); 862 } 863 864 static int felix_fdb_dump(struct dsa_switch *ds, int port, 865 dsa_fdb_dump_cb_t *cb, void *data) 866 { 867 struct ocelot *ocelot = ds->priv; 868 869 return ocelot_fdb_dump(ocelot, port, cb, data); 870 } 871 872 static int felix_fdb_add(struct dsa_switch *ds, int port, 873 const unsigned char *addr, u16 vid, 874 struct dsa_db db) 875 { 876 struct net_device *bridge_dev = felix_classify_db(db); 877 struct dsa_port *dp = dsa_to_port(ds, port); 878 struct ocelot *ocelot = ds->priv; 879 880 if (IS_ERR(bridge_dev)) 881 return PTR_ERR(bridge_dev); 882 883 if (dsa_port_is_cpu(dp) && !bridge_dev && 884 dsa_fdb_present_in_other_db(ds, port, addr, vid, db)) 885 return 0; 886 887 if (dsa_port_is_cpu(dp)) 888 port = PGID_CPU; 889 890 return ocelot_fdb_add(ocelot, port, addr, vid, bridge_dev); 891 } 892 893 static int felix_fdb_del(struct dsa_switch *ds, int port, 894 const unsigned char *addr, u16 vid, 895 struct dsa_db db) 896 { 897 struct net_device *bridge_dev = felix_classify_db(db); 898 struct dsa_port *dp = dsa_to_port(ds, port); 899 struct ocelot *ocelot = ds->priv; 900 901 if (IS_ERR(bridge_dev)) 902 return PTR_ERR(bridge_dev); 903 904 if (dsa_port_is_cpu(dp) && !bridge_dev && 905 dsa_fdb_present_in_other_db(ds, port, addr, vid, db)) 906 return 0; 907 908 if (dsa_port_is_cpu(dp)) 909 port = PGID_CPU; 910 911 return ocelot_fdb_del(ocelot, port, addr, vid, bridge_dev); 912 } 913 914 static int felix_lag_fdb_add(struct dsa_switch *ds, struct dsa_lag lag, 915 const unsigned char *addr, u16 vid, 916 struct dsa_db db) 917 { 918 struct net_device *bridge_dev = felix_classify_db(db); 919 struct ocelot *ocelot = ds->priv; 920 921 if (IS_ERR(bridge_dev)) 922 return PTR_ERR(bridge_dev); 923 924 return ocelot_lag_fdb_add(ocelot, lag.dev, addr, vid, bridge_dev); 925 } 926 927 static int felix_lag_fdb_del(struct dsa_switch *ds, struct dsa_lag lag, 928 const unsigned char *addr, u16 vid, 929 struct dsa_db db) 930 { 931 struct net_device *bridge_dev = felix_classify_db(db); 932 struct ocelot *ocelot = ds->priv; 933 934 if (IS_ERR(bridge_dev)) 935 return PTR_ERR(bridge_dev); 936 937 return ocelot_lag_fdb_del(ocelot, lag.dev, addr, vid, bridge_dev); 938 } 939 940 static int felix_mdb_add(struct dsa_switch *ds, int port, 941 const struct switchdev_obj_port_mdb *mdb, 942 struct dsa_db db) 943 { 944 struct net_device *bridge_dev = felix_classify_db(db); 945 struct ocelot *ocelot = ds->priv; 946 947 if (IS_ERR(bridge_dev)) 948 return PTR_ERR(bridge_dev); 949 950 if (dsa_is_cpu_port(ds, port) && !bridge_dev && 951 dsa_mdb_present_in_other_db(ds, port, mdb, db)) 952 return 0; 953 954 if (port == ocelot->npi) 955 port = ocelot->num_phys_ports; 956 957 return ocelot_port_mdb_add(ocelot, port, mdb, bridge_dev); 958 } 959 960 static int felix_mdb_del(struct dsa_switch *ds, int port, 961 const struct switchdev_obj_port_mdb *mdb, 962 struct dsa_db db) 963 { 964 struct net_device *bridge_dev = felix_classify_db(db); 965 struct ocelot *ocelot = ds->priv; 966 967 if (IS_ERR(bridge_dev)) 968 return PTR_ERR(bridge_dev); 969 970 if (dsa_is_cpu_port(ds, port) && !bridge_dev && 971 dsa_mdb_present_in_other_db(ds, port, mdb, db)) 972 return 0; 973 974 if (port == ocelot->npi) 975 port = ocelot->num_phys_ports; 976 977 return ocelot_port_mdb_del(ocelot, port, mdb, bridge_dev); 978 } 979 980 static void felix_bridge_stp_state_set(struct dsa_switch *ds, int port, 981 u8 state) 982 { 983 struct ocelot *ocelot = ds->priv; 984 985 return ocelot_bridge_stp_state_set(ocelot, port, state); 986 } 987 988 static int felix_pre_bridge_flags(struct dsa_switch *ds, int port, 989 struct switchdev_brport_flags val, 990 struct netlink_ext_ack *extack) 991 { 992 struct ocelot *ocelot = ds->priv; 993 994 return ocelot_port_pre_bridge_flags(ocelot, port, val); 995 } 996 997 static int felix_bridge_flags(struct dsa_switch *ds, int port, 998 struct switchdev_brport_flags val, 999 struct netlink_ext_ack *extack) 1000 { 1001 struct ocelot *ocelot = ds->priv; 1002 1003 if (port == ocelot->npi) 1004 port = ocelot->num_phys_ports; 1005 1006 ocelot_port_bridge_flags(ocelot, port, val); 1007 1008 return 0; 1009 } 1010 1011 static int felix_bridge_join(struct dsa_switch *ds, int port, 1012 struct dsa_bridge bridge, bool *tx_fwd_offload, 1013 struct netlink_ext_ack *extack) 1014 { 1015 struct ocelot *ocelot = ds->priv; 1016 1017 return ocelot_port_bridge_join(ocelot, port, bridge.dev, bridge.num, 1018 extack); 1019 } 1020 1021 static void felix_bridge_leave(struct dsa_switch *ds, int port, 1022 struct dsa_bridge bridge) 1023 { 1024 struct ocelot *ocelot = ds->priv; 1025 1026 ocelot_port_bridge_leave(ocelot, port, bridge.dev); 1027 } 1028 1029 static int felix_lag_join(struct dsa_switch *ds, int port, 1030 struct dsa_lag lag, 1031 struct netdev_lag_upper_info *info, 1032 struct netlink_ext_ack *extack) 1033 { 1034 struct ocelot *ocelot = ds->priv; 1035 int err; 1036 1037 err = ocelot_port_lag_join(ocelot, port, lag.dev, info, extack); 1038 if (err) 1039 return err; 1040 1041 /* Update the logical LAG port that serves as tag_8021q CPU port */ 1042 if (!dsa_is_cpu_port(ds, port)) 1043 return 0; 1044 1045 return felix_port_change_conduit(ds, port, lag.dev, extack); 1046 } 1047 1048 static int felix_lag_leave(struct dsa_switch *ds, int port, 1049 struct dsa_lag lag) 1050 { 1051 struct ocelot *ocelot = ds->priv; 1052 1053 ocelot_port_lag_leave(ocelot, port, lag.dev); 1054 1055 /* Update the logical LAG port that serves as tag_8021q CPU port */ 1056 if (!dsa_is_cpu_port(ds, port)) 1057 return 0; 1058 1059 return felix_port_change_conduit(ds, port, lag.dev, NULL); 1060 } 1061 1062 static int felix_lag_change(struct dsa_switch *ds, int port) 1063 { 1064 struct dsa_port *dp = dsa_to_port(ds, port); 1065 struct ocelot *ocelot = ds->priv; 1066 1067 ocelot_port_lag_change(ocelot, port, dp->lag_tx_enabled); 1068 1069 return 0; 1070 } 1071 1072 static int felix_vlan_prepare(struct dsa_switch *ds, int port, 1073 const struct switchdev_obj_port_vlan *vlan, 1074 struct netlink_ext_ack *extack) 1075 { 1076 struct ocelot *ocelot = ds->priv; 1077 u16 flags = vlan->flags; 1078 1079 /* Ocelot switches copy frames as-is to the CPU, so the flags: 1080 * egress-untagged or not, pvid or not, make no difference. This 1081 * behavior is already better than what DSA just tries to approximate 1082 * when it installs the VLAN with the same flags on the CPU port. 1083 * Just accept any configuration, and don't let ocelot deny installing 1084 * multiple native VLANs on the NPI port, because the switch doesn't 1085 * look at the port tag settings towards the NPI interface anyway. 1086 */ 1087 if (port == ocelot->npi) 1088 return 0; 1089 1090 return ocelot_vlan_prepare(ocelot, port, vlan->vid, 1091 flags & BRIDGE_VLAN_INFO_PVID, 1092 flags & BRIDGE_VLAN_INFO_UNTAGGED, 1093 extack); 1094 } 1095 1096 static int felix_vlan_filtering(struct dsa_switch *ds, int port, bool enabled, 1097 struct netlink_ext_ack *extack) 1098 { 1099 struct ocelot *ocelot = ds->priv; 1100 bool using_tag_8021q; 1101 struct felix *felix; 1102 int err; 1103 1104 err = ocelot_port_vlan_filtering(ocelot, port, enabled, extack); 1105 if (err) 1106 return err; 1107 1108 felix = ocelot_to_felix(ocelot); 1109 using_tag_8021q = felix->tag_proto == DSA_TAG_PROTO_OCELOT_8021Q; 1110 if (using_tag_8021q) { 1111 err = felix_update_tag_8021q_rx_rules(ds, port, enabled); 1112 if (err) 1113 return err; 1114 } 1115 1116 return 0; 1117 } 1118 1119 static int felix_vlan_add(struct dsa_switch *ds, int port, 1120 const struct switchdev_obj_port_vlan *vlan, 1121 struct netlink_ext_ack *extack) 1122 { 1123 struct ocelot *ocelot = ds->priv; 1124 u16 flags = vlan->flags; 1125 int err; 1126 1127 err = felix_vlan_prepare(ds, port, vlan, extack); 1128 if (err) 1129 return err; 1130 1131 return ocelot_vlan_add(ocelot, port, vlan->vid, 1132 flags & BRIDGE_VLAN_INFO_PVID, 1133 flags & BRIDGE_VLAN_INFO_UNTAGGED); 1134 } 1135 1136 static int felix_vlan_del(struct dsa_switch *ds, int port, 1137 const struct switchdev_obj_port_vlan *vlan) 1138 { 1139 struct ocelot *ocelot = ds->priv; 1140 1141 return ocelot_vlan_del(ocelot, port, vlan->vid); 1142 } 1143 1144 static void felix_phylink_get_caps(struct dsa_switch *ds, int port, 1145 struct phylink_config *config) 1146 { 1147 struct ocelot *ocelot = ds->priv; 1148 1149 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1150 MAC_10 | MAC_100 | MAC_1000FD | 1151 MAC_2500FD; 1152 1153 __set_bit(ocelot->ports[port]->phy_mode, 1154 config->supported_interfaces); 1155 if (ocelot->ports[port]->phy_mode == PHY_INTERFACE_MODE_USXGMII) 1156 __set_bit(PHY_INTERFACE_MODE_10G_QXGMII, 1157 config->supported_interfaces); 1158 } 1159 1160 static void felix_phylink_mac_config(struct phylink_config *config, 1161 unsigned int mode, 1162 const struct phylink_link_state *state) 1163 { 1164 struct dsa_port *dp = dsa_phylink_to_port(config); 1165 struct ocelot *ocelot = dp->ds->priv; 1166 int port = dp->index; 1167 struct felix *felix; 1168 1169 felix = ocelot_to_felix(ocelot); 1170 1171 if (felix->info->phylink_mac_config) 1172 felix->info->phylink_mac_config(ocelot, port, mode, state); 1173 } 1174 1175 static struct phylink_pcs * 1176 felix_phylink_mac_select_pcs(struct phylink_config *config, 1177 phy_interface_t iface) 1178 { 1179 struct dsa_port *dp = dsa_phylink_to_port(config); 1180 struct ocelot *ocelot = dp->ds->priv; 1181 struct phylink_pcs *pcs = NULL; 1182 int port = dp->index; 1183 struct felix *felix; 1184 1185 felix = ocelot_to_felix(ocelot); 1186 1187 if (felix->pcs && felix->pcs[port]) 1188 pcs = felix->pcs[port]; 1189 1190 return pcs; 1191 } 1192 1193 static void felix_phylink_mac_link_down(struct phylink_config *config, 1194 unsigned int link_an_mode, 1195 phy_interface_t interface) 1196 { 1197 struct dsa_port *dp = dsa_phylink_to_port(config); 1198 struct ocelot *ocelot = dp->ds->priv; 1199 int port = dp->index; 1200 struct felix *felix; 1201 1202 felix = ocelot_to_felix(ocelot); 1203 1204 ocelot_phylink_mac_link_down(ocelot, port, link_an_mode, interface, 1205 felix->info->quirks); 1206 } 1207 1208 static void felix_phylink_mac_link_up(struct phylink_config *config, 1209 struct phy_device *phydev, 1210 unsigned int link_an_mode, 1211 phy_interface_t interface, 1212 int speed, int duplex, 1213 bool tx_pause, bool rx_pause) 1214 { 1215 struct dsa_port *dp = dsa_phylink_to_port(config); 1216 struct ocelot *ocelot = dp->ds->priv; 1217 int port = dp->index; 1218 struct felix *felix; 1219 1220 felix = ocelot_to_felix(ocelot); 1221 1222 ocelot_phylink_mac_link_up(ocelot, port, phydev, link_an_mode, 1223 interface, speed, duplex, tx_pause, rx_pause, 1224 felix->info->quirks); 1225 1226 if (felix->info->port_sched_speed_set) 1227 felix->info->port_sched_speed_set(ocelot, port, speed); 1228 } 1229 1230 static int felix_port_enable(struct dsa_switch *ds, int port, 1231 struct phy_device *phydev) 1232 { 1233 struct dsa_port *dp = dsa_to_port(ds, port); 1234 struct ocelot *ocelot = ds->priv; 1235 struct felix *felix = ocelot_to_felix(ocelot); 1236 1237 if (!dsa_port_is_user(dp)) 1238 return 0; 1239 1240 if (ocelot->npi >= 0) { 1241 struct net_device *conduit = dsa_port_to_conduit(dp); 1242 1243 if (felix_cpu_port_for_conduit(ds, conduit) != ocelot->npi) { 1244 dev_err(ds->dev, "Multiple conduits are not allowed\n"); 1245 return -EINVAL; 1246 } 1247 } 1248 1249 if (!dp->hsr_dev || felix->tag_proto == DSA_TAG_PROTO_OCELOT_8021Q) 1250 return 0; 1251 1252 return dsa_port_simple_hsr_join(ds, port, dp->hsr_dev, NULL); 1253 } 1254 1255 static void felix_port_disable(struct dsa_switch *ds, int port) 1256 { 1257 struct dsa_port *dp = dsa_to_port(ds, port); 1258 struct ocelot *ocelot = ds->priv; 1259 struct felix *felix = ocelot_to_felix(ocelot); 1260 1261 if (!dsa_port_is_user(dp)) 1262 return; 1263 1264 if (!dp->hsr_dev || felix->tag_proto == DSA_TAG_PROTO_OCELOT_8021Q) 1265 return; 1266 1267 dsa_port_simple_hsr_leave(ds, port, dp->hsr_dev); 1268 } 1269 1270 static void felix_port_qos_map_init(struct ocelot *ocelot, int port) 1271 { 1272 int i; 1273 1274 ocelot_rmw_gix(ocelot, 1275 ANA_PORT_QOS_CFG_QOS_PCP_ENA, 1276 ANA_PORT_QOS_CFG_QOS_PCP_ENA, 1277 ANA_PORT_QOS_CFG, 1278 port); 1279 1280 for (i = 0; i < OCELOT_NUM_TC * 2; i++) { 1281 ocelot_rmw_ix(ocelot, 1282 (ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL & i) | 1283 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(i), 1284 ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL | 1285 ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M, 1286 ANA_PORT_PCP_DEI_MAP, 1287 port, i); 1288 } 1289 } 1290 1291 static void felix_get_stats64(struct dsa_switch *ds, int port, 1292 struct rtnl_link_stats64 *stats) 1293 { 1294 struct ocelot *ocelot = ds->priv; 1295 1296 ocelot_port_get_stats64(ocelot, port, stats); 1297 } 1298 1299 static void felix_get_pause_stats(struct dsa_switch *ds, int port, 1300 struct ethtool_pause_stats *pause_stats) 1301 { 1302 struct ocelot *ocelot = ds->priv; 1303 1304 ocelot_port_get_pause_stats(ocelot, port, pause_stats); 1305 } 1306 1307 static void felix_get_rmon_stats(struct dsa_switch *ds, int port, 1308 struct ethtool_rmon_stats *rmon_stats, 1309 const struct ethtool_rmon_hist_range **ranges) 1310 { 1311 struct ocelot *ocelot = ds->priv; 1312 1313 ocelot_port_get_rmon_stats(ocelot, port, rmon_stats, ranges); 1314 } 1315 1316 static void felix_get_eth_ctrl_stats(struct dsa_switch *ds, int port, 1317 struct ethtool_eth_ctrl_stats *ctrl_stats) 1318 { 1319 struct ocelot *ocelot = ds->priv; 1320 1321 ocelot_port_get_eth_ctrl_stats(ocelot, port, ctrl_stats); 1322 } 1323 1324 static void felix_get_eth_mac_stats(struct dsa_switch *ds, int port, 1325 struct ethtool_eth_mac_stats *mac_stats) 1326 { 1327 struct ocelot *ocelot = ds->priv; 1328 1329 ocelot_port_get_eth_mac_stats(ocelot, port, mac_stats); 1330 } 1331 1332 static void felix_get_eth_phy_stats(struct dsa_switch *ds, int port, 1333 struct ethtool_eth_phy_stats *phy_stats) 1334 { 1335 struct ocelot *ocelot = ds->priv; 1336 1337 ocelot_port_get_eth_phy_stats(ocelot, port, phy_stats); 1338 } 1339 1340 static void felix_get_ts_stats(struct dsa_switch *ds, int port, 1341 struct ethtool_ts_stats *ts_stats) 1342 { 1343 struct ocelot *ocelot = ds->priv; 1344 1345 ocelot_port_get_ts_stats(ocelot, port, ts_stats); 1346 } 1347 1348 static void felix_get_strings(struct dsa_switch *ds, int port, 1349 u32 stringset, u8 *data) 1350 { 1351 struct ocelot *ocelot = ds->priv; 1352 1353 return ocelot_get_strings(ocelot, port, stringset, data); 1354 } 1355 1356 static void felix_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data) 1357 { 1358 struct ocelot *ocelot = ds->priv; 1359 1360 ocelot_get_ethtool_stats(ocelot, port, data); 1361 } 1362 1363 static int felix_get_sset_count(struct dsa_switch *ds, int port, int sset) 1364 { 1365 struct ocelot *ocelot = ds->priv; 1366 1367 return ocelot_get_sset_count(ocelot, port, sset); 1368 } 1369 1370 static int felix_get_ts_info(struct dsa_switch *ds, int port, 1371 struct kernel_ethtool_ts_info *info) 1372 { 1373 struct ocelot *ocelot = ds->priv; 1374 1375 return ocelot_get_ts_info(ocelot, port, info); 1376 } 1377 1378 static const u32 felix_phy_match_table[PHY_INTERFACE_MODE_MAX] = { 1379 [PHY_INTERFACE_MODE_INTERNAL] = OCELOT_PORT_MODE_INTERNAL, 1380 [PHY_INTERFACE_MODE_SGMII] = OCELOT_PORT_MODE_SGMII, 1381 [PHY_INTERFACE_MODE_QSGMII] = OCELOT_PORT_MODE_QSGMII, 1382 [PHY_INTERFACE_MODE_USXGMII] = OCELOT_PORT_MODE_USXGMII, 1383 [PHY_INTERFACE_MODE_10G_QXGMII] = OCELOT_PORT_MODE_10G_QXGMII, 1384 [PHY_INTERFACE_MODE_1000BASEX] = OCELOT_PORT_MODE_1000BASEX, 1385 [PHY_INTERFACE_MODE_2500BASEX] = OCELOT_PORT_MODE_2500BASEX, 1386 }; 1387 1388 static int felix_validate_phy_mode(struct felix *felix, int port, 1389 phy_interface_t phy_mode) 1390 { 1391 u32 modes = felix->info->port_modes[port]; 1392 1393 if (felix_phy_match_table[phy_mode] & modes) 1394 return 0; 1395 return -EOPNOTSUPP; 1396 } 1397 1398 static int felix_parse_ports_node(struct felix *felix, 1399 struct device_node *ports_node, 1400 phy_interface_t *port_phy_modes) 1401 { 1402 struct device *dev = felix->ocelot.dev; 1403 1404 for_each_available_child_of_node_scoped(ports_node, child) { 1405 phy_interface_t phy_mode; 1406 u32 port; 1407 int err; 1408 1409 /* Get switch port number from DT */ 1410 if (of_property_read_u32(child, "reg", &port) < 0) { 1411 dev_err(dev, "Port number not defined in device tree " 1412 "(property \"reg\")\n"); 1413 return -ENODEV; 1414 } 1415 1416 /* Get PHY mode from DT */ 1417 err = of_get_phy_mode(child, &phy_mode); 1418 if (err) { 1419 dev_err(dev, "Failed to read phy-mode or " 1420 "phy-interface-type property for port %d\n", 1421 port); 1422 return -ENODEV; 1423 } 1424 1425 err = felix_validate_phy_mode(felix, port, phy_mode); 1426 if (err < 0) { 1427 dev_info(dev, "Unsupported PHY mode %s on port %d\n", 1428 phy_modes(phy_mode), port); 1429 1430 /* Leave port_phy_modes[port] = 0, which is also 1431 * PHY_INTERFACE_MODE_NA. This will perform a 1432 * best-effort to bring up as many ports as possible. 1433 */ 1434 continue; 1435 } 1436 1437 port_phy_modes[port] = phy_mode; 1438 } 1439 1440 return 0; 1441 } 1442 1443 static int felix_parse_dt(struct felix *felix, phy_interface_t *port_phy_modes) 1444 { 1445 struct device *dev = felix->ocelot.dev; 1446 struct device_node *switch_node; 1447 struct device_node *ports_node; 1448 int err; 1449 1450 switch_node = dev->of_node; 1451 1452 ports_node = of_get_child_by_name(switch_node, "ports"); 1453 if (!ports_node) 1454 ports_node = of_get_child_by_name(switch_node, "ethernet-ports"); 1455 if (!ports_node) { 1456 dev_err(dev, "Incorrect bindings: absent \"ports\" or \"ethernet-ports\" node\n"); 1457 return -ENODEV; 1458 } 1459 1460 err = felix_parse_ports_node(felix, ports_node, port_phy_modes); 1461 of_node_put(ports_node); 1462 1463 return err; 1464 } 1465 1466 static struct regmap *felix_request_regmap_by_name(struct felix *felix, 1467 const char *resource_name) 1468 { 1469 struct ocelot *ocelot = &felix->ocelot; 1470 struct resource res; 1471 int i; 1472 1473 /* In an MFD configuration, regmaps are registered directly to the 1474 * parent device before the child devices are probed, so there is no 1475 * need to initialize a new one. 1476 */ 1477 if (!felix->info->resources) 1478 return dev_get_regmap(ocelot->dev->parent, resource_name); 1479 1480 for (i = 0; i < felix->info->num_resources; i++) { 1481 if (strcmp(resource_name, felix->info->resources[i].name)) 1482 continue; 1483 1484 memcpy(&res, &felix->info->resources[i], sizeof(res)); 1485 res.start += felix->switch_base; 1486 res.end += felix->switch_base; 1487 1488 return ocelot_regmap_init(ocelot, &res); 1489 } 1490 1491 return ERR_PTR(-ENOENT); 1492 } 1493 1494 static struct regmap *felix_request_regmap(struct felix *felix, 1495 enum ocelot_target target) 1496 { 1497 const char *resource_name = felix->info->resource_names[target]; 1498 1499 /* If the driver didn't provide a resource name for the target, 1500 * the resource is optional. 1501 */ 1502 if (!resource_name) 1503 return NULL; 1504 1505 return felix_request_regmap_by_name(felix, resource_name); 1506 } 1507 1508 static struct regmap *felix_request_port_regmap(struct felix *felix, int port) 1509 { 1510 char resource_name[32]; 1511 1512 sprintf(resource_name, "port%d", port); 1513 1514 return felix_request_regmap_by_name(felix, resource_name); 1515 } 1516 1517 static int felix_init_structs(struct felix *felix, int num_phys_ports) 1518 { 1519 struct ocelot *ocelot = &felix->ocelot; 1520 phy_interface_t *port_phy_modes; 1521 struct regmap *target; 1522 int port, i, err; 1523 1524 ocelot->num_phys_ports = num_phys_ports; 1525 ocelot->ports = devm_kcalloc(ocelot->dev, num_phys_ports, 1526 sizeof(struct ocelot_port *), GFP_KERNEL); 1527 if (!ocelot->ports) 1528 return -ENOMEM; 1529 1530 ocelot->map = felix->info->map; 1531 ocelot->num_mact_rows = felix->info->num_mact_rows; 1532 ocelot->vcap = felix->info->vcap; 1533 ocelot->vcap_pol.base = felix->info->vcap_pol_base; 1534 ocelot->vcap_pol.max = felix->info->vcap_pol_max; 1535 ocelot->vcap_pol.base2 = felix->info->vcap_pol_base2; 1536 ocelot->vcap_pol.max2 = felix->info->vcap_pol_max2; 1537 ocelot->ops = felix->info->ops; 1538 ocelot->npi_inj_prefix = OCELOT_TAG_PREFIX_SHORT; 1539 ocelot->npi_xtr_prefix = OCELOT_TAG_PREFIX_SHORT; 1540 ocelot->devlink = felix->ds->devlink; 1541 1542 port_phy_modes = kzalloc_objs(phy_interface_t, num_phys_ports); 1543 if (!port_phy_modes) 1544 return -ENOMEM; 1545 1546 err = felix_parse_dt(felix, port_phy_modes); 1547 if (err) { 1548 kfree(port_phy_modes); 1549 return err; 1550 } 1551 1552 for (i = 0; i < TARGET_MAX; i++) { 1553 target = felix_request_regmap(felix, i); 1554 if (IS_ERR(target)) { 1555 dev_err(ocelot->dev, 1556 "Failed to map device memory space: %pe\n", 1557 target); 1558 kfree(port_phy_modes); 1559 return PTR_ERR(target); 1560 } 1561 1562 ocelot->targets[i] = target; 1563 } 1564 1565 err = ocelot_regfields_init(ocelot, felix->info->regfields); 1566 if (err) { 1567 dev_err(ocelot->dev, "failed to init reg fields map\n"); 1568 kfree(port_phy_modes); 1569 return err; 1570 } 1571 1572 for (port = 0; port < num_phys_ports; port++) { 1573 struct ocelot_port *ocelot_port; 1574 1575 ocelot_port = devm_kzalloc(ocelot->dev, 1576 sizeof(struct ocelot_port), 1577 GFP_KERNEL); 1578 if (!ocelot_port) { 1579 dev_err(ocelot->dev, 1580 "failed to allocate port memory\n"); 1581 kfree(port_phy_modes); 1582 return -ENOMEM; 1583 } 1584 1585 target = felix_request_port_regmap(felix, port); 1586 if (IS_ERR(target)) { 1587 dev_err(ocelot->dev, 1588 "Failed to map memory space for port %d: %pe\n", 1589 port, target); 1590 kfree(port_phy_modes); 1591 return PTR_ERR(target); 1592 } 1593 1594 ocelot_port->phy_mode = port_phy_modes[port]; 1595 ocelot_port->ocelot = ocelot; 1596 ocelot_port->target = target; 1597 ocelot_port->index = port; 1598 ocelot->ports[port] = ocelot_port; 1599 } 1600 1601 kfree(port_phy_modes); 1602 1603 if (felix->info->mdio_bus_alloc) { 1604 err = felix->info->mdio_bus_alloc(ocelot); 1605 if (err < 0) 1606 return err; 1607 } 1608 1609 return 0; 1610 } 1611 1612 static void ocelot_port_purge_txtstamp_skb(struct ocelot *ocelot, int port, 1613 struct sk_buff *skb) 1614 { 1615 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1616 struct sk_buff *clone = OCELOT_SKB_CB(skb)->clone; 1617 struct sk_buff *skb_match = NULL, *skb_tmp; 1618 unsigned long flags; 1619 1620 if (!clone) 1621 return; 1622 1623 spin_lock_irqsave(&ocelot_port->tx_skbs.lock, flags); 1624 1625 skb_queue_walk_safe(&ocelot_port->tx_skbs, skb, skb_tmp) { 1626 if (skb != clone) 1627 continue; 1628 __skb_unlink(skb, &ocelot_port->tx_skbs); 1629 skb_match = skb; 1630 break; 1631 } 1632 1633 spin_unlock_irqrestore(&ocelot_port->tx_skbs.lock, flags); 1634 1635 WARN_ONCE(!skb_match, 1636 "Could not find skb clone in TX timestamping list\n"); 1637 } 1638 1639 #define work_to_xmit_work(w) \ 1640 container_of((w), struct felix_deferred_xmit_work, work) 1641 1642 static void felix_port_deferred_xmit(struct kthread_work *work) 1643 { 1644 struct felix_deferred_xmit_work *xmit_work = work_to_xmit_work(work); 1645 struct dsa_switch *ds = xmit_work->dp->ds; 1646 struct sk_buff *skb = xmit_work->skb; 1647 u32 rew_op = ocelot_ptp_rew_op(skb); 1648 struct ocelot *ocelot = ds->priv; 1649 int port = xmit_work->dp->index; 1650 int retries = 10; 1651 1652 ocelot_lock_inj_grp(ocelot, 0); 1653 1654 do { 1655 if (ocelot_can_inject(ocelot, 0)) 1656 break; 1657 1658 cpu_relax(); 1659 } while (--retries); 1660 1661 if (!retries) { 1662 ocelot_unlock_inj_grp(ocelot, 0); 1663 dev_err(ocelot->dev, "port %d failed to inject skb\n", 1664 port); 1665 ocelot_port_purge_txtstamp_skb(ocelot, port, skb); 1666 kfree_skb(skb); 1667 return; 1668 } 1669 1670 ocelot_port_inject_frame(ocelot, port, 0, rew_op, skb); 1671 1672 ocelot_unlock_inj_grp(ocelot, 0); 1673 1674 consume_skb(skb); 1675 kfree(xmit_work); 1676 } 1677 1678 static int felix_connect_tag_protocol(struct dsa_switch *ds, 1679 enum dsa_tag_protocol proto) 1680 { 1681 struct ocelot_8021q_tagger_data *tagger_data; 1682 1683 switch (proto) { 1684 case DSA_TAG_PROTO_OCELOT_8021Q: 1685 tagger_data = ocelot_8021q_tagger_data(ds); 1686 tagger_data->xmit_work_fn = felix_port_deferred_xmit; 1687 return 0; 1688 case DSA_TAG_PROTO_OCELOT: 1689 case DSA_TAG_PROTO_SEVILLE: 1690 return 0; 1691 default: 1692 return -EPROTONOSUPPORT; 1693 } 1694 } 1695 1696 static int felix_setup(struct dsa_switch *ds) 1697 { 1698 struct ocelot *ocelot = ds->priv; 1699 struct felix *felix = ocelot_to_felix(ocelot); 1700 struct dsa_port *dp; 1701 int err; 1702 1703 err = felix_init_structs(felix, ds->num_ports); 1704 if (err) 1705 return err; 1706 1707 if (ocelot->targets[HSIO]) 1708 ocelot_pll5_init(ocelot); 1709 1710 err = ocelot_init(ocelot); 1711 if (err) 1712 goto out_mdiobus_free; 1713 1714 if (ocelot->ptp) { 1715 err = ocelot_init_timestamp(ocelot, felix->info->ptp_caps); 1716 if (err) { 1717 dev_err(ocelot->dev, 1718 "Timestamp initialization failed\n"); 1719 ocelot->ptp = 0; 1720 } 1721 } 1722 1723 dsa_switch_for_each_available_port(dp, ds) { 1724 ocelot_init_port(ocelot, dp->index); 1725 1726 if (felix->info->configure_serdes) 1727 felix->info->configure_serdes(ocelot, dp->index, 1728 dp->dn); 1729 1730 /* Set the default QoS Classification based on PCP and DEI 1731 * bits of vlan tag. 1732 */ 1733 felix_port_qos_map_init(ocelot, dp->index); 1734 } 1735 1736 if (felix->info->request_irq) { 1737 err = felix->info->request_irq(ocelot); 1738 if (err) { 1739 dev_err(ocelot->dev, "Failed to request IRQ: %pe\n", 1740 ERR_PTR(err)); 1741 goto out_deinit_ports; 1742 } 1743 } 1744 1745 err = ocelot_devlink_sb_register(ocelot); 1746 if (err) 1747 goto out_deinit_ports; 1748 1749 /* The initial tag protocol is NPI which won't fail during initial 1750 * setup, there's no real point in checking for errors. 1751 */ 1752 felix_change_tag_protocol(ds, felix->tag_proto); 1753 1754 ds->mtu_enforcement_ingress = true; 1755 ds->assisted_learning_on_cpu_port = true; 1756 ds->fdb_isolation = true; 1757 ds->max_num_bridges = ds->num_ports; 1758 1759 return 0; 1760 1761 out_deinit_ports: 1762 dsa_switch_for_each_available_port(dp, ds) 1763 ocelot_deinit_port(ocelot, dp->index); 1764 1765 ocelot_deinit_timestamp(ocelot); 1766 ocelot_deinit(ocelot); 1767 1768 out_mdiobus_free: 1769 if (felix->info->mdio_bus_free) 1770 felix->info->mdio_bus_free(ocelot); 1771 1772 return err; 1773 } 1774 1775 static void felix_teardown(struct dsa_switch *ds) 1776 { 1777 struct ocelot *ocelot = ds->priv; 1778 struct felix *felix = ocelot_to_felix(ocelot); 1779 struct dsa_port *dp; 1780 1781 rtnl_lock(); 1782 if (felix->tag_proto_ops) 1783 felix->tag_proto_ops->teardown(ds); 1784 rtnl_unlock(); 1785 1786 dsa_switch_for_each_available_port(dp, ds) 1787 ocelot_deinit_port(ocelot, dp->index); 1788 1789 ocelot_devlink_sb_unregister(ocelot); 1790 ocelot_deinit_timestamp(ocelot); 1791 ocelot_deinit(ocelot); 1792 1793 if (felix->info->mdio_bus_free) 1794 felix->info->mdio_bus_free(ocelot); 1795 } 1796 1797 static int felix_hwtstamp_get(struct dsa_switch *ds, int port, 1798 struct kernel_hwtstamp_config *config) 1799 { 1800 struct ocelot *ocelot = ds->priv; 1801 1802 ocelot_hwstamp_get(ocelot, port, config); 1803 1804 return 0; 1805 } 1806 1807 static int felix_hwtstamp_set(struct dsa_switch *ds, int port, 1808 struct kernel_hwtstamp_config *config, 1809 struct netlink_ext_ack *extack) 1810 { 1811 struct ocelot *ocelot = ds->priv; 1812 struct felix *felix = ocelot_to_felix(ocelot); 1813 bool using_tag_8021q; 1814 int err; 1815 1816 err = ocelot_hwstamp_set(ocelot, port, config, extack); 1817 if (err) 1818 return err; 1819 1820 using_tag_8021q = felix->tag_proto == DSA_TAG_PROTO_OCELOT_8021Q; 1821 1822 return felix_update_trapping_destinations(ds, using_tag_8021q); 1823 } 1824 1825 static bool felix_check_xtr_pkt(struct ocelot *ocelot) 1826 { 1827 struct felix *felix = ocelot_to_felix(ocelot); 1828 int err = 0, grp = 0; 1829 1830 if (felix->tag_proto != DSA_TAG_PROTO_OCELOT_8021Q) 1831 return false; 1832 1833 if (!felix->info->quirk_no_xtr_irq) 1834 return false; 1835 1836 ocelot_lock_xtr_grp(ocelot, grp); 1837 1838 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp)) { 1839 struct sk_buff *skb; 1840 unsigned int type; 1841 1842 err = ocelot_xtr_poll_frame(ocelot, grp, &skb); 1843 if (err) 1844 goto out; 1845 1846 /* We trap to the CPU port module all PTP frames, but 1847 * felix_rxtstamp() only gets called for event frames. 1848 * So we need to avoid sending duplicate general 1849 * message frames by running a second BPF classifier 1850 * here and dropping those. 1851 */ 1852 __skb_push(skb, ETH_HLEN); 1853 1854 type = ptp_classify_raw(skb); 1855 1856 __skb_pull(skb, ETH_HLEN); 1857 1858 if (type == PTP_CLASS_NONE) { 1859 kfree_skb(skb); 1860 continue; 1861 } 1862 1863 netif_rx(skb); 1864 } 1865 1866 out: 1867 if (err < 0) { 1868 dev_err_ratelimited(ocelot->dev, 1869 "Error during packet extraction: %pe\n", 1870 ERR_PTR(err)); 1871 ocelot_drain_cpu_queue(ocelot, 0); 1872 } 1873 1874 ocelot_unlock_xtr_grp(ocelot, grp); 1875 1876 return true; 1877 } 1878 1879 static bool felix_rxtstamp(struct dsa_switch *ds, int port, 1880 struct sk_buff *skb, unsigned int type) 1881 { 1882 u32 tstamp_lo = OCELOT_SKB_CB(skb)->tstamp_lo; 1883 struct skb_shared_hwtstamps *shhwtstamps; 1884 struct ocelot *ocelot = ds->priv; 1885 struct timespec64 ts; 1886 u32 tstamp_hi; 1887 u64 tstamp; 1888 1889 switch (type & PTP_CLASS_PMASK) { 1890 case PTP_CLASS_L2: 1891 if (!(ocelot->ports[port]->trap_proto & OCELOT_PROTO_PTP_L2)) 1892 return false; 1893 break; 1894 case PTP_CLASS_IPV4: 1895 case PTP_CLASS_IPV6: 1896 if (!(ocelot->ports[port]->trap_proto & OCELOT_PROTO_PTP_L4)) 1897 return false; 1898 break; 1899 } 1900 1901 /* If the "no XTR IRQ" workaround is in use, tell DSA to defer this skb 1902 * for RX timestamping. Then free it, and poll for its copy through 1903 * MMIO in the CPU port module, and inject that into the stack from 1904 * ocelot_xtr_poll(). 1905 */ 1906 if (felix_check_xtr_pkt(ocelot)) { 1907 kfree_skb(skb); 1908 return true; 1909 } 1910 1911 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts); 1912 tstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 1913 1914 tstamp_hi = tstamp >> 32; 1915 if ((tstamp & 0xffffffff) < tstamp_lo) 1916 tstamp_hi--; 1917 1918 tstamp = ((u64)tstamp_hi << 32) | tstamp_lo; 1919 1920 shhwtstamps = skb_hwtstamps(skb); 1921 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps)); 1922 shhwtstamps->hwtstamp = tstamp; 1923 return false; 1924 } 1925 1926 static void felix_txtstamp(struct dsa_switch *ds, int port, 1927 struct sk_buff *skb) 1928 { 1929 struct ocelot *ocelot = ds->priv; 1930 struct sk_buff *clone = NULL; 1931 1932 if (!ocelot->ptp) 1933 return; 1934 1935 if (ocelot_port_txtstamp_request(ocelot, port, skb, &clone)) { 1936 dev_err_ratelimited(ds->dev, 1937 "port %d delivering skb without TX timestamp\n", 1938 port); 1939 return; 1940 } 1941 1942 if (clone) 1943 OCELOT_SKB_CB(skb)->clone = clone; 1944 } 1945 1946 static int felix_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1947 { 1948 struct ocelot *ocelot = ds->priv; 1949 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1950 1951 ocelot_port_set_maxlen(ocelot, port, new_mtu); 1952 1953 mutex_lock(&ocelot->fwd_domain_lock); 1954 1955 if (ocelot_port->taprio && ocelot->ops->tas_guard_bands_update) 1956 ocelot->ops->tas_guard_bands_update(ocelot, port); 1957 1958 mutex_unlock(&ocelot->fwd_domain_lock); 1959 1960 return 0; 1961 } 1962 1963 static int felix_get_max_mtu(struct dsa_switch *ds, int port) 1964 { 1965 struct ocelot *ocelot = ds->priv; 1966 1967 return ocelot_get_max_mtu(ocelot, port); 1968 } 1969 1970 static int felix_cls_flower_add(struct dsa_switch *ds, int port, 1971 struct flow_cls_offload *cls, bool ingress) 1972 { 1973 struct ocelot *ocelot = ds->priv; 1974 struct felix *felix = ocelot_to_felix(ocelot); 1975 bool using_tag_8021q; 1976 int err; 1977 1978 err = ocelot_cls_flower_replace(ocelot, port, cls, ingress); 1979 if (err) 1980 return err; 1981 1982 using_tag_8021q = felix->tag_proto == DSA_TAG_PROTO_OCELOT_8021Q; 1983 1984 return felix_update_trapping_destinations(ds, using_tag_8021q); 1985 } 1986 1987 static int felix_cls_flower_del(struct dsa_switch *ds, int port, 1988 struct flow_cls_offload *cls, bool ingress) 1989 { 1990 struct ocelot *ocelot = ds->priv; 1991 1992 return ocelot_cls_flower_destroy(ocelot, port, cls, ingress); 1993 } 1994 1995 static int felix_cls_flower_stats(struct dsa_switch *ds, int port, 1996 struct flow_cls_offload *cls, bool ingress) 1997 { 1998 struct ocelot *ocelot = ds->priv; 1999 2000 return ocelot_cls_flower_stats(ocelot, port, cls, ingress); 2001 } 2002 2003 static int felix_port_policer_add(struct dsa_switch *ds, int port, 2004 const struct flow_action_police *policer) 2005 { 2006 struct ocelot *ocelot = ds->priv; 2007 struct ocelot_policer pol = { 2008 .rate = div_u64(policer->rate_bytes_ps, 1000) * 8, 2009 .burst = policer->burst, 2010 }; 2011 2012 return ocelot_port_policer_add(ocelot, port, &pol); 2013 } 2014 2015 static void felix_port_policer_del(struct dsa_switch *ds, int port) 2016 { 2017 struct ocelot *ocelot = ds->priv; 2018 2019 ocelot_port_policer_del(ocelot, port); 2020 } 2021 2022 static int felix_port_mirror_add(struct dsa_switch *ds, int port, 2023 struct dsa_mall_mirror_tc_entry *mirror, 2024 bool ingress, struct netlink_ext_ack *extack) 2025 { 2026 struct ocelot *ocelot = ds->priv; 2027 2028 return ocelot_port_mirror_add(ocelot, port, mirror->to_local_port, 2029 ingress, extack); 2030 } 2031 2032 static void felix_port_mirror_del(struct dsa_switch *ds, int port, 2033 struct dsa_mall_mirror_tc_entry *mirror) 2034 { 2035 struct ocelot *ocelot = ds->priv; 2036 2037 ocelot_port_mirror_del(ocelot, port, mirror->ingress); 2038 } 2039 2040 static int felix_port_setup_tc(struct dsa_switch *ds, int port, 2041 enum tc_setup_type type, 2042 void *type_data) 2043 { 2044 struct ocelot *ocelot = ds->priv; 2045 struct felix *felix = ocelot_to_felix(ocelot); 2046 2047 if (felix->info->port_setup_tc) 2048 return felix->info->port_setup_tc(ds, port, type, type_data); 2049 else 2050 return -EOPNOTSUPP; 2051 } 2052 2053 static int felix_sb_pool_get(struct dsa_switch *ds, unsigned int sb_index, 2054 u16 pool_index, 2055 struct devlink_sb_pool_info *pool_info) 2056 { 2057 struct ocelot *ocelot = ds->priv; 2058 2059 return ocelot_sb_pool_get(ocelot, sb_index, pool_index, pool_info); 2060 } 2061 2062 static int felix_sb_pool_set(struct dsa_switch *ds, unsigned int sb_index, 2063 u16 pool_index, u32 size, 2064 enum devlink_sb_threshold_type threshold_type, 2065 struct netlink_ext_ack *extack) 2066 { 2067 struct ocelot *ocelot = ds->priv; 2068 2069 return ocelot_sb_pool_set(ocelot, sb_index, pool_index, size, 2070 threshold_type, extack); 2071 } 2072 2073 static int felix_sb_port_pool_get(struct dsa_switch *ds, int port, 2074 unsigned int sb_index, u16 pool_index, 2075 u32 *p_threshold) 2076 { 2077 struct ocelot *ocelot = ds->priv; 2078 2079 return ocelot_sb_port_pool_get(ocelot, port, sb_index, pool_index, 2080 p_threshold); 2081 } 2082 2083 static int felix_sb_port_pool_set(struct dsa_switch *ds, int port, 2084 unsigned int sb_index, u16 pool_index, 2085 u32 threshold, struct netlink_ext_ack *extack) 2086 { 2087 struct ocelot *ocelot = ds->priv; 2088 2089 return ocelot_sb_port_pool_set(ocelot, port, sb_index, pool_index, 2090 threshold, extack); 2091 } 2092 2093 static int felix_sb_tc_pool_bind_get(struct dsa_switch *ds, int port, 2094 unsigned int sb_index, u16 tc_index, 2095 enum devlink_sb_pool_type pool_type, 2096 u16 *p_pool_index, u32 *p_threshold) 2097 { 2098 struct ocelot *ocelot = ds->priv; 2099 2100 return ocelot_sb_tc_pool_bind_get(ocelot, port, sb_index, tc_index, 2101 pool_type, p_pool_index, 2102 p_threshold); 2103 } 2104 2105 static int felix_sb_tc_pool_bind_set(struct dsa_switch *ds, int port, 2106 unsigned int sb_index, u16 tc_index, 2107 enum devlink_sb_pool_type pool_type, 2108 u16 pool_index, u32 threshold, 2109 struct netlink_ext_ack *extack) 2110 { 2111 struct ocelot *ocelot = ds->priv; 2112 2113 return ocelot_sb_tc_pool_bind_set(ocelot, port, sb_index, tc_index, 2114 pool_type, pool_index, threshold, 2115 extack); 2116 } 2117 2118 static int felix_sb_occ_snapshot(struct dsa_switch *ds, 2119 unsigned int sb_index) 2120 { 2121 struct ocelot *ocelot = ds->priv; 2122 2123 return ocelot_sb_occ_snapshot(ocelot, sb_index); 2124 } 2125 2126 static int felix_sb_occ_max_clear(struct dsa_switch *ds, 2127 unsigned int sb_index) 2128 { 2129 struct ocelot *ocelot = ds->priv; 2130 2131 return ocelot_sb_occ_max_clear(ocelot, sb_index); 2132 } 2133 2134 static int felix_sb_occ_port_pool_get(struct dsa_switch *ds, int port, 2135 unsigned int sb_index, u16 pool_index, 2136 u32 *p_cur, u32 *p_max) 2137 { 2138 struct ocelot *ocelot = ds->priv; 2139 2140 return ocelot_sb_occ_port_pool_get(ocelot, port, sb_index, pool_index, 2141 p_cur, p_max); 2142 } 2143 2144 static int felix_sb_occ_tc_port_bind_get(struct dsa_switch *ds, int port, 2145 unsigned int sb_index, u16 tc_index, 2146 enum devlink_sb_pool_type pool_type, 2147 u32 *p_cur, u32 *p_max) 2148 { 2149 struct ocelot *ocelot = ds->priv; 2150 2151 return ocelot_sb_occ_tc_port_bind_get(ocelot, port, sb_index, tc_index, 2152 pool_type, p_cur, p_max); 2153 } 2154 2155 static int felix_mrp_add(struct dsa_switch *ds, int port, 2156 const struct switchdev_obj_mrp *mrp) 2157 { 2158 struct ocelot *ocelot = ds->priv; 2159 2160 return ocelot_mrp_add(ocelot, port, mrp); 2161 } 2162 2163 static int felix_mrp_del(struct dsa_switch *ds, int port, 2164 const struct switchdev_obj_mrp *mrp) 2165 { 2166 struct ocelot *ocelot = ds->priv; 2167 2168 return ocelot_mrp_add(ocelot, port, mrp); 2169 } 2170 2171 static int 2172 felix_mrp_add_ring_role(struct dsa_switch *ds, int port, 2173 const struct switchdev_obj_ring_role_mrp *mrp) 2174 { 2175 struct ocelot *ocelot = ds->priv; 2176 2177 return ocelot_mrp_add_ring_role(ocelot, port, mrp); 2178 } 2179 2180 static int 2181 felix_mrp_del_ring_role(struct dsa_switch *ds, int port, 2182 const struct switchdev_obj_ring_role_mrp *mrp) 2183 { 2184 struct ocelot *ocelot = ds->priv; 2185 2186 return ocelot_mrp_del_ring_role(ocelot, port, mrp); 2187 } 2188 2189 static int felix_port_get_default_prio(struct dsa_switch *ds, int port) 2190 { 2191 struct ocelot *ocelot = ds->priv; 2192 2193 return ocelot_port_get_default_prio(ocelot, port); 2194 } 2195 2196 static int felix_port_set_default_prio(struct dsa_switch *ds, int port, 2197 u8 prio) 2198 { 2199 struct ocelot *ocelot = ds->priv; 2200 2201 return ocelot_port_set_default_prio(ocelot, port, prio); 2202 } 2203 2204 static int felix_port_get_dscp_prio(struct dsa_switch *ds, int port, u8 dscp) 2205 { 2206 struct ocelot *ocelot = ds->priv; 2207 2208 return ocelot_port_get_dscp_prio(ocelot, port, dscp); 2209 } 2210 2211 static int felix_port_add_dscp_prio(struct dsa_switch *ds, int port, u8 dscp, 2212 u8 prio) 2213 { 2214 struct ocelot *ocelot = ds->priv; 2215 2216 return ocelot_port_add_dscp_prio(ocelot, port, dscp, prio); 2217 } 2218 2219 static int felix_port_del_dscp_prio(struct dsa_switch *ds, int port, u8 dscp, 2220 u8 prio) 2221 { 2222 struct ocelot *ocelot = ds->priv; 2223 2224 return ocelot_port_del_dscp_prio(ocelot, port, dscp, prio); 2225 } 2226 2227 static int felix_get_mm(struct dsa_switch *ds, int port, 2228 struct ethtool_mm_state *state) 2229 { 2230 struct ocelot *ocelot = ds->priv; 2231 2232 return ocelot_port_get_mm(ocelot, port, state); 2233 } 2234 2235 static int felix_set_mm(struct dsa_switch *ds, int port, 2236 struct ethtool_mm_cfg *cfg, 2237 struct netlink_ext_ack *extack) 2238 { 2239 struct ocelot *ocelot = ds->priv; 2240 2241 return ocelot_port_set_mm(ocelot, port, cfg, extack); 2242 } 2243 2244 static void felix_get_mm_stats(struct dsa_switch *ds, int port, 2245 struct ethtool_mm_stats *stats) 2246 { 2247 struct ocelot *ocelot = ds->priv; 2248 2249 ocelot_port_get_mm_stats(ocelot, port, stats); 2250 } 2251 2252 /* Depending on port type, we may be able to support the offload later (with 2253 * the "ocelot"/"seville" tagging protocols), or never. 2254 * If we return 0, the dp->hsr_dev reference is kept for later; if we return 2255 * -EOPNOTSUPP, it is cleared (which helps to not bother 2256 * dsa_port_simple_hsr_leave() with an offload that didn't pass validation). 2257 */ 2258 static int felix_port_hsr_join(struct dsa_switch *ds, int port, 2259 struct net_device *hsr, 2260 struct netlink_ext_ack *extack) 2261 { 2262 struct ocelot *ocelot = ds->priv; 2263 struct felix *felix = ocelot_to_felix(ocelot); 2264 2265 if (felix->tag_proto == DSA_TAG_PROTO_OCELOT_8021Q) { 2266 int err; 2267 2268 err = dsa_port_simple_hsr_validate(ds, port, hsr, extack); 2269 if (err) 2270 return err; 2271 2272 NL_SET_ERR_MSG_MOD(extack, 2273 "Offloading not supported with \"ocelot-8021q\""); 2274 return 0; 2275 } 2276 2277 if (!(dsa_to_port(ds, port)->user->flags & IFF_UP)) 2278 return 0; 2279 2280 return dsa_port_simple_hsr_join(ds, port, hsr, extack); 2281 } 2282 2283 static int felix_port_hsr_leave(struct dsa_switch *ds, int port, 2284 struct net_device *hsr) 2285 { 2286 struct ocelot *ocelot = ds->priv; 2287 struct felix *felix = ocelot_to_felix(ocelot); 2288 2289 if (felix->tag_proto == DSA_TAG_PROTO_OCELOT_8021Q) 2290 return 0; 2291 2292 if (!(dsa_to_port(ds, port)->user->flags & IFF_UP)) 2293 return 0; 2294 2295 return dsa_port_simple_hsr_leave(ds, port, hsr); 2296 } 2297 2298 static const struct phylink_mac_ops felix_phylink_mac_ops = { 2299 .mac_select_pcs = felix_phylink_mac_select_pcs, 2300 .mac_config = felix_phylink_mac_config, 2301 .mac_link_down = felix_phylink_mac_link_down, 2302 .mac_link_up = felix_phylink_mac_link_up, 2303 }; 2304 2305 static const struct dsa_switch_ops felix_switch_ops = { 2306 .get_tag_protocol = felix_get_tag_protocol, 2307 .change_tag_protocol = felix_change_tag_protocol, 2308 .connect_tag_protocol = felix_connect_tag_protocol, 2309 .setup = felix_setup, 2310 .teardown = felix_teardown, 2311 .set_ageing_time = felix_set_ageing_time, 2312 .get_mm = felix_get_mm, 2313 .set_mm = felix_set_mm, 2314 .get_mm_stats = felix_get_mm_stats, 2315 .get_stats64 = felix_get_stats64, 2316 .get_pause_stats = felix_get_pause_stats, 2317 .get_rmon_stats = felix_get_rmon_stats, 2318 .get_ts_stats = felix_get_ts_stats, 2319 .get_eth_ctrl_stats = felix_get_eth_ctrl_stats, 2320 .get_eth_mac_stats = felix_get_eth_mac_stats, 2321 .get_eth_phy_stats = felix_get_eth_phy_stats, 2322 .get_strings = felix_get_strings, 2323 .get_ethtool_stats = felix_get_ethtool_stats, 2324 .get_sset_count = felix_get_sset_count, 2325 .get_ts_info = felix_get_ts_info, 2326 .phylink_get_caps = felix_phylink_get_caps, 2327 .port_enable = felix_port_enable, 2328 .port_disable = felix_port_disable, 2329 .port_fast_age = felix_port_fast_age, 2330 .port_fdb_dump = felix_fdb_dump, 2331 .port_fdb_add = felix_fdb_add, 2332 .port_fdb_del = felix_fdb_del, 2333 .lag_fdb_add = felix_lag_fdb_add, 2334 .lag_fdb_del = felix_lag_fdb_del, 2335 .port_mdb_add = felix_mdb_add, 2336 .port_mdb_del = felix_mdb_del, 2337 .port_pre_bridge_flags = felix_pre_bridge_flags, 2338 .port_bridge_flags = felix_bridge_flags, 2339 .port_bridge_join = felix_bridge_join, 2340 .port_bridge_leave = felix_bridge_leave, 2341 .port_lag_join = felix_lag_join, 2342 .port_lag_leave = felix_lag_leave, 2343 .port_lag_change = felix_lag_change, 2344 .port_stp_state_set = felix_bridge_stp_state_set, 2345 .port_vlan_filtering = felix_vlan_filtering, 2346 .port_vlan_add = felix_vlan_add, 2347 .port_vlan_del = felix_vlan_del, 2348 .port_hwtstamp_get = felix_hwtstamp_get, 2349 .port_hwtstamp_set = felix_hwtstamp_set, 2350 .port_rxtstamp = felix_rxtstamp, 2351 .port_txtstamp = felix_txtstamp, 2352 .port_change_mtu = felix_change_mtu, 2353 .port_max_mtu = felix_get_max_mtu, 2354 .port_policer_add = felix_port_policer_add, 2355 .port_policer_del = felix_port_policer_del, 2356 .port_mirror_add = felix_port_mirror_add, 2357 .port_mirror_del = felix_port_mirror_del, 2358 .cls_flower_add = felix_cls_flower_add, 2359 .cls_flower_del = felix_cls_flower_del, 2360 .cls_flower_stats = felix_cls_flower_stats, 2361 .port_setup_tc = felix_port_setup_tc, 2362 .devlink_sb_pool_get = felix_sb_pool_get, 2363 .devlink_sb_pool_set = felix_sb_pool_set, 2364 .devlink_sb_port_pool_get = felix_sb_port_pool_get, 2365 .devlink_sb_port_pool_set = felix_sb_port_pool_set, 2366 .devlink_sb_tc_pool_bind_get = felix_sb_tc_pool_bind_get, 2367 .devlink_sb_tc_pool_bind_set = felix_sb_tc_pool_bind_set, 2368 .devlink_sb_occ_snapshot = felix_sb_occ_snapshot, 2369 .devlink_sb_occ_max_clear = felix_sb_occ_max_clear, 2370 .devlink_sb_occ_port_pool_get = felix_sb_occ_port_pool_get, 2371 .devlink_sb_occ_tc_port_bind_get= felix_sb_occ_tc_port_bind_get, 2372 .port_mrp_add = felix_mrp_add, 2373 .port_mrp_del = felix_mrp_del, 2374 .port_mrp_add_ring_role = felix_mrp_add_ring_role, 2375 .port_mrp_del_ring_role = felix_mrp_del_ring_role, 2376 .tag_8021q_vlan_add = felix_tag_8021q_vlan_add, 2377 .tag_8021q_vlan_del = felix_tag_8021q_vlan_del, 2378 .port_get_default_prio = felix_port_get_default_prio, 2379 .port_set_default_prio = felix_port_set_default_prio, 2380 .port_get_dscp_prio = felix_port_get_dscp_prio, 2381 .port_add_dscp_prio = felix_port_add_dscp_prio, 2382 .port_del_dscp_prio = felix_port_del_dscp_prio, 2383 .port_set_host_flood = felix_port_set_host_flood, 2384 .port_change_conduit = felix_port_change_conduit, 2385 .port_hsr_join = felix_port_hsr_join, 2386 .port_hsr_leave = felix_port_hsr_leave, 2387 }; 2388 2389 int felix_register_switch(struct device *dev, resource_size_t switch_base, 2390 int num_flooding_pgids, bool ptp, 2391 bool mm_supported, 2392 enum dsa_tag_protocol init_tag_proto, 2393 const struct felix_info *info) 2394 { 2395 struct dsa_switch *ds; 2396 struct ocelot *ocelot; 2397 struct felix *felix; 2398 int err; 2399 2400 felix = devm_kzalloc(dev, sizeof(*felix), GFP_KERNEL); 2401 if (!felix) 2402 return -ENOMEM; 2403 2404 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 2405 if (!ds) 2406 return -ENOMEM; 2407 2408 dev_set_drvdata(dev, felix); 2409 2410 ocelot = &felix->ocelot; 2411 ocelot->dev = dev; 2412 ocelot->num_flooding_pgids = num_flooding_pgids; 2413 ocelot->ptp = ptp; 2414 ocelot->mm_supported = mm_supported; 2415 2416 felix->info = info; 2417 felix->switch_base = switch_base; 2418 felix->ds = ds; 2419 felix->tag_proto = init_tag_proto; 2420 2421 ds->dev = dev; 2422 ds->num_ports = info->num_ports; 2423 ds->num_tx_queues = OCELOT_NUM_TC; 2424 ds->ops = &felix_switch_ops; 2425 ds->phylink_mac_ops = &felix_phylink_mac_ops; 2426 ds->priv = ocelot; 2427 2428 err = dsa_register_switch(ds); 2429 if (err) 2430 dev_err_probe(dev, err, "Failed to register DSA switch\n"); 2431 2432 return err; 2433 } 2434 EXPORT_SYMBOL_GPL(felix_register_switch); 2435 2436 struct net_device *felix_port_to_netdev(struct ocelot *ocelot, int port) 2437 { 2438 struct felix *felix = ocelot_to_felix(ocelot); 2439 struct dsa_switch *ds = felix->ds; 2440 2441 if (!dsa_is_user_port(ds, port)) 2442 return NULL; 2443 2444 return dsa_to_port(ds, port)->user; 2445 } 2446 EXPORT_SYMBOL_GPL(felix_port_to_netdev); 2447 2448 int felix_netdev_to_port(struct net_device *dev) 2449 { 2450 struct dsa_port *dp; 2451 2452 dp = dsa_port_from_netdev(dev); 2453 if (IS_ERR(dp)) 2454 return -EINVAL; 2455 2456 return dp->index; 2457 } 2458 EXPORT_SYMBOL_GPL(felix_netdev_to_port); 2459 2460 MODULE_DESCRIPTION("Felix DSA library"); 2461 MODULE_LICENSE("GPL"); 2462