1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2 /* 3 * Copyright 2025-2026 NXP 4 */ 5 6 #ifndef _NETC_SWITCH_HW_H 7 #define _NETC_SWITCH_HW_H 8 9 #include <linux/bitops.h> 10 11 #define NETC_SWITCH_VENDOR_ID 0x1131 12 #define NETC_SWITCH_DEVICE_ID 0xeef2 13 14 /* Definition of Switch base registers */ 15 #define NETC_BPCAPR 0x0008 16 #define BPCAPR_NUM_BP GENMASK(7, 0) 17 18 #define NETC_PBPMCR0 0x0400 19 #define NETC_PBPMCR1 0x0404 20 21 #define NETC_CBDRMR(a) (0x0800 + (a) * 0x30) 22 #define NETC_CBDRBAR0(a) (0x0810 + (a) * 0x30) 23 #define NETC_CBDRBAR1(a) (0x0814 + (a) * 0x30) 24 #define NETC_CBDRPIR(a) (0x0818 + (a) * 0x30) 25 #define NETC_CBDRCIR(a) (0x081c + (a) * 0x30) 26 #define NETC_CBDRLENR(a) (0x0820 + (a) * 0x30) 27 28 #define NETC_SWCR 0x1018 29 #define SWCR_SWID GENMASK(2, 0) 30 31 #define NETC_DOSL2CR 0x1220 32 #define DOSL2CR_SAMEADDR BIT(0) 33 #define DOSL2CR_MSAMCC BIT(1) 34 35 #define NETC_DOSL3CR 0x1224 36 #define DOSL3CR_SAMEADDR BIT(0) 37 #define DOSL3CR_IPSAMCC BIT(1) 38 39 /* Hash table memory capability register, the memory is shared by 40 * the following tables: 41 * 42 * - Ingress Stream Identification table 43 * - Ingress Stream Filter table 44 * - VLAN Filter table 45 * - FDB table 46 * - L2 IPv4 Multicast Filter table 47 * 48 * Each hash table entry is one word in size. 49 */ 50 #define NETC_HTMCAPR 0x1900 51 #define HTMCAPR_NUM_WORDS GENMASK(15, 0) 52 53 #define NETC_VFHTDECR1 0x2014 54 #define NETC_VFHTDECR2 0x2018 55 #define VFHTDECR2_ET_PORT(a) BIT((a)) 56 #define VFHTDECR2_MLO GENMASK(26, 24) 57 #define VFHTDECR2_MFO GENMASK(28, 27) 58 59 /* Definition of Switch port registers */ 60 #define NETC_PCAPR 0x0000 61 #define PCAPR_LINK_TYPE BIT(4) 62 #define PCAPR_NUM_TC GENMASK(15, 12) 63 #define PCAPR_NUM_Q GENMASK(19, 16) 64 #define PCAPR_NUM_CG GENMASK(27, 24) 65 #define PCAPR_TGS BIT(28) 66 #define PCAPR_CBS BIT(29) 67 68 #define NETC_PMCAPR 0x0004 69 #define PMCAPR_HD BIT(8) 70 #define PMCAPR_FP GENMASK(10, 9) 71 #define FP_SUPPORT 2 72 73 #define NETC_PCR 0x0010 74 #define PCR_HDR_FMT BIT(0) 75 #define PCR_NS_TAG_PORT BIT(3) 76 #define PCR_L2DOSE BIT(4) 77 #define PCR_L3DOSE BIT(5) 78 #define PCR_TIMER_CS BIT(8) 79 #define PCR_PSPEED GENMASK(29, 16) 80 #define PSPEED_SET_VAL(s) FIELD_PREP(PCR_PSPEED, ((s) / 10 - 1)) 81 82 #define NETC_PQOSMR 0x0054 83 #define PQOSMR_VS BIT(0) 84 #define PQOSMR_VE BIT(1) 85 #define PQOSMR_DDR GENMASK(3, 2) 86 #define PQOSMR_DIPV GENMASK(6, 4) 87 #define PQOSMR_VQMP GENMASK(19, 16) 88 #define PQOSMR_QVMP GENMASK(23, 20) 89 90 #define NETC_PIPFCR 0x0084 91 #define PIPFCR_EN BIT(0) 92 93 #define NETC_POR 0x100 94 #define POR_TXDIS BIT(0) 95 #define POR_RXDIS BIT(1) 96 97 #define NETC_PSR 0x104 98 #define PSR_TX_BUSY BIT(0) 99 #define PSR_RX_BUSY BIT(1) 100 101 #define NETC_PTGSLACR 0x130 102 103 #define NETC_PRXDCR 0x1c0 104 #define NETC_PRXDCRRR 0x1c4 105 #define NETC_PRXDCRR0 0x1c8 106 #define NETC_PRXDCRR1 0x1cc 107 #define NETC_PTXDCR 0x1e0 108 109 #define NETC_PTCTMSDUR(a) (0x208 + (a) * 0x20) 110 #define PTCTMSDUR_MAXSDU GENMASK(15, 0) 111 #define PTCTMSDUR_SDU_TYPE GENMASK(17, 16) 112 #define SDU_TYPE_PPDU 0 113 #define SDU_TYPE_MPDU 1 114 #define SDU_TYPE_MSDU 2 115 116 #define NETC_PSDFTCR 0x4c4 117 #define NETC_PSDFDDCR 0x4c8 118 119 #define NETC_BPCR 0x500 120 #define BPCR_DYN_LIMIT GENMASK(15, 0) 121 #define BPCR_MLO GENMASK(22, 20) 122 #define BPCR_UUCASTE BIT(24) 123 #define BPCR_UMCASTE BIT(25) 124 #define BPCR_MCASTE BIT(26) 125 #define BPCR_BCASTE BIT(27) 126 #define BPCR_STAMVD BIT(28) 127 #define BPCR_SRCPRND BIT(29) 128 129 /* MAC learning options, see BPCR[MLO], VFHTDECR2[MLO] and 130 * VLAN Filter Table CFGE_DATA[MLO] 131 */ 132 enum netc_mlo { 133 MLO_NOT_OVERRIDE = 0, 134 MLO_DISABLE, 135 MLO_HW, 136 MLO_SW_SEC, 137 MLO_SW_UNSEC, 138 MLO_DISABLE_SMAC, 139 }; 140 141 /* MAC forwarding options, see VFHTDECR2[MFO] and VLAN 142 * Filter Table CFGE_DATA[MFO] 143 */ 144 enum netc_mfo { 145 MFO_NO_FDB_LOOKUP = 1, 146 MFO_NO_MATCH_FLOOD, 147 MFO_NO_MATCH_DISCARD, 148 }; 149 150 #define NETC_BPDVR 0x510 151 #define BPDVR_VID GENMASK(11, 0) 152 #define BPDVR_DEI BIT(12) 153 #define BPDVR_PCP GENMASK(15, 13) 154 #define BPDVR_TPID BIT(16) 155 #define BPDVR_RXTAGA GENMASK(23, 20) 156 #define BPDVR_RXVAM BIT(24) 157 #define BPDVR_TXTAGA GENMASK(26, 25) 158 159 #define NETC_BPSTGSR 0x520 160 161 enum netc_stg_stage { 162 NETC_STG_STATE_DISABLED = 0, 163 NETC_STG_STATE_LEARNING, 164 NETC_STG_STATE_FORWARDING, 165 }; 166 167 #define NETC_BPDCR 0x580 168 169 /* Definition of Switch ethernet MAC port registers */ 170 #define NETC_PMAC_OFFSET 0x400 171 #define NETC_PM_CMD_CFG(a) (0x1008 + (a) * 0x400) 172 #define PM_CMD_CFG_TX_EN BIT(0) 173 #define PM_CMD_CFG_RX_EN BIT(1) 174 #define PM_CMD_CFG_PAUSE_IGN BIT(8) 175 176 #define NETC_PM_MAXFRM(a) (0x1014 + (a) * 0x400) 177 #define PM_MAXFRAM GENMASK(15, 0) 178 179 #define NETC_PM_IEVENT(a) (0x1040 + (a) * 0x400) 180 #define PM_IEVENT_TX_EMPTY BIT(5) 181 #define PM_IEVENT_RX_EMPTY BIT(6) 182 183 #define NETC_PM_PAUSE_QUANTA(a) (0x1054 + (a) * 0x400) 184 #define NETC_PM_PAUSE_THRESH(a) (0x1064 + (a) * 0x400) 185 186 #define NETC_PM_IF_MODE(a) (0x1300 + (a) * 0x400) 187 #define PM_IF_MODE_IFMODE GENMASK(2, 0) 188 #define IFMODE_MII 1 189 #define IFMODE_RMII 3 190 #define IFMODE_RGMII 4 191 #define IFMODE_SGMII 5 192 #define PM_IF_MODE_REVMII BIT(3) 193 #define PM_IF_MODE_M10 BIT(4) 194 #define PM_IF_MODE_HD BIT(6) 195 #define PM_IF_MODE_SSP GENMASK(14, 13) 196 #define SSP_100M 0 197 #define SSP_10M 1 198 #define SSP_1G 2 199 200 /* Port MAC 0/1 Receive Ethernet Octets Counter */ 201 #define NETC_PM_REOCT(a) (0x1100 + (a) * 0x400) 202 203 /* Port MAC 0/1 Receive Octets Counter */ 204 #define NETC_PM_ROCT(a) (0x1108 + (a) * 0x400) 205 206 /* Port MAC 0/1 Receive Alignment Error Counter Register */ 207 #define NETC_PM_RALN(a) (0x1110 + (a) * 0x400) 208 209 /* Port MAC 0/1 Receive Valid Pause Frame Counter */ 210 #define NETC_PM_RXPF(a) (0x1118 + (a) * 0x400) 211 212 /* Port MAC 0/1 Receive Frame Counter */ 213 #define NETC_PM_RFRM(a) (0x1120 + (a) * 0x400) 214 215 /* Port MAC 0/1 Receive Frame Check Sequence Error Counter */ 216 #define NETC_PM_RFCS(a) (0x1128 + (a) * 0x400) 217 218 /* Port MAC 0/1 Receive VLAN Frame Counter */ 219 #define NETC_PM_RVLAN(a) (0x1130 + (a) * 0x400) 220 221 /* Port MAC 0/1 Receive Frame Error Counter */ 222 #define NETC_PM_RERR(a) (0x1138 + (a) * 0x400) 223 224 /* Port MAC 0/1 Receive Unicast Frame Counter */ 225 #define NETC_PM_RUCA(a) (0x1140 + (a) * 0x400) 226 227 /* Port MAC 0/1 Receive Multicast Frame Counter */ 228 #define NETC_PM_RMCA(a) (0x1148 + (a) * 0x400) 229 230 /* Port MAC 0/1 Receive Broadcast Frame Counter */ 231 #define NETC_PM_RBCA(a) (0x1150 + (a) * 0x400) 232 233 /* Port MAC 0/1 Receive Dropped Packets Counter */ 234 #define NETC_PM_RDRP(a) (0x1158 + (a) * 0x400) 235 236 /* Port MAC 0/1 Receive Packets Counter */ 237 #define NETC_PM_RPKT(a) (0x1160 + (a) * 0x400) 238 239 /* Port MAC 0/1 Receive Undersized Packet Counter */ 240 #define NETC_PM_RUND(a) (0x1168 + (a) * 0x400) 241 242 /* Port MAC 0/1 Receive 64-Octet Packet Counter */ 243 #define NETC_PM_R64(a) (0x1170 + (a) * 0x400) 244 245 /* Port MAC 0/1 Receive 65 to 127-Octet Packet Counter */ 246 #define NETC_PM_R127(a) (0x1178 + (a) * 0x400) 247 248 /* Port MAC 0/1 Receive 128 to 255-Octet Packet Counter */ 249 #define NETC_PM_R255(a) (0x1180 + (a) * 0x400) 250 251 /* Port MAC 0/1 Receive 256 to 511-Octet Packet Counter */ 252 #define NETC_PM_R511(a) (0x1188 + (a) * 0x400) 253 254 /* Port MAC 0/1 Receive 512 to 1023-Octet Packet Counter */ 255 #define NETC_PM_R1023(a) (0x1190 + (a) * 0x400) 256 257 /* Port MAC 0/1 Receive 1024 to 1522-Octet Packet Counter */ 258 #define NETC_PM_R1522(a) (0x1198 + (a) * 0x400) 259 260 /* Port MAC 0/1 Receive 1523 to Max-Octet Packet Counter */ 261 #define NETC_PM_R1523X(a) (0x11a0 + (a) * 0x400) 262 263 /* Port MAC 0/1 Receive Oversized Packet Counter */ 264 #define NETC_PM_ROVR(a) (0x11a8 + (a) * 0x400) 265 266 /* Port MAC 0/1 Receive Jabber Packet Counter */ 267 #define NETC_PM_RJBR(a) (0x11b0 + (a) * 0x400) 268 269 /* Port MAC 0/1 Receive Fragment Packet Counter */ 270 #define NETC_PM_RFRG(a) (0x11b8 + (a) * 0x400) 271 272 /* Port MAC 0/1 Receive Control Packet Counter */ 273 #define NETC_PM_RCNP(a) (0x11c0 + (a) * 0x400) 274 275 /* Port MAC 0/1 Receive Dropped Not Truncated Packets Counter */ 276 #define NETC_PM_RDRNTP(a) (0x11c8 + (a) * 0x400) 277 278 /* Port MAC 0/1 Transmit Ethernet Octets Counter */ 279 #define NETC_PM_TEOCT(a) (0x1200 + (a) * 0x400) 280 281 /* Port MAC 0/1 Transmit Octets Counter */ 282 #define NETC_PM_TOCT(a) (0x1208 + (a) * 0x400) 283 284 /* Port MAC 0/1 Transmit Excessive Deferral Packet Counter */ 285 #define NETC_PM_TEDFR(a) (0x1210 + (a) * 0x400) 286 287 /* Port MAC 0/1 Transmit Valid Pause Frame Counter */ 288 #define NETC_PM_TXPF(a) (0x1218 + (a) * 0x400) 289 290 /* Port MAC 0/1 Transmit Frame Counter */ 291 #define NETC_PM_TFRM(a) (0x1220 + (a) * 0x400) 292 293 /* Port MAC 0/1 Transmit Frame Check Sequence Error Counter */ 294 #define NETC_PM_TFCS(a) (0x1228 + (a) * 0x400) 295 296 /* Port MAC 0/1 Transmit VLAN Frame Counter */ 297 #define NETC_PM_TVLAN(a) (0x1230 + (a) * 0x400) 298 299 /* Port MAC 0/1 Transmit Frame Error Counter */ 300 #define NETC_PM_TERR(a) (0x1238 + (a) * 0x400) 301 302 /* Port MAC 0/1 Transmit Unicast Frame Counter */ 303 #define NETC_PM_TUCA(a) (0x1240 + (a) * 0x400) 304 305 /* Port MAC 0/1 Transmit Multicast Frame Counter */ 306 #define NETC_PM_TMCA(a) (0x1248 + (a) * 0x400) 307 308 /* Port MAC 0/1 Transmit Broadcast Frame Counter */ 309 #define NETC_PM_TBCA(a) (0x1250 + (a) * 0x400) 310 311 /* Port MAC 0/1 Transmit Packets Counter */ 312 #define NETC_PM_TPKT(a) (0x1260 + (a) * 0x400) 313 314 /* Port MAC 0/1 Transmit Undersized Packet Counter */ 315 #define NETC_PM_TUND(a) (0x1268 + (a) * 0x400) 316 317 /* Port MAC 0/1 Transmit 64-Octet Packet Counter */ 318 #define NETC_PM_T64(a) (0x1270 + (a) * 0x400) 319 320 /* Port MAC 0/1 Transmit 65 to 127-Octet Packet Counter */ 321 #define NETC_PM_T127(a) (0x1278 + (a) * 0x400) 322 323 /* Port MAC 0/1 Transmit 128 to 255-Octet Packet Counter */ 324 #define NETC_PM_T255(a) (0x1280 + (a) * 0x400) 325 326 /* Port MAC 0/1 Transmit 256 to 511-Octet Packet Counter */ 327 #define NETC_PM_T511(a) (0x1288 + (a) * 0x400) 328 329 /* Port MAC 0/1 Transmit 512 to 1023-Octet Packet Counter */ 330 #define NETC_PM_T1023(a) (0x1290 + (a) * 0x400) 331 332 /* Port MAC 0/1 Transmit 1024 to 1522-Octet Packet Counter */ 333 #define NETC_PM_T1522(a) (0x1298 + (a) * 0x400) 334 335 /* Port MAC 0/1 Transmit 1523 to TX_MTU-Octet Packet Counter */ 336 #define NETC_PM_T1523X(a) (0x12a0 + (a) * 0x400) 337 338 /* Port MAC 0/1 Transmit Control Packet Counter */ 339 #define NETC_PM_TCNP(a) (0x12c0 + (a) * 0x400) 340 341 /* Port MAC 0/1 Transmit Deferred Packet Counter */ 342 #define NETC_PM_TDFR(a) (0x12d0 + (a) * 0x400) 343 344 /* Port MAC 0/1 Transmit Multiple Collisions Counter */ 345 #define NETC_PM_TMCOL(a) (0x12d8 + (a) * 0x400) 346 347 /* Port MAC 0/1 Transmit Single Collision */ 348 #define NETC_PM_TSCOL(a) (0x12e0 + (a) * 0x400) 349 350 /* Port MAC 0/1 Transmit Late Collision Counter */ 351 #define NETC_PM_TLCOL(a) (0x12e8 + (a) * 0x400) 352 353 /* Port MAC 0/1 Transmit Excessive Collisions Counter */ 354 #define NETC_PM_TECOL(a) (0x12f0 + (a) * 0x400) 355 356 /* Port MAC 0/1 Transmit Invalid Octets Counter */ 357 #define NETC_PM_TIOCT(a) (0x12f8 + (a) * 0x400) 358 359 #define NETC_PEMDIOCR 0x1c00 360 #define NETC_EMDIO_BASE NETC_PEMDIOCR 361 362 /* Definition of global registers (read only) */ 363 #define NETC_IPBRR0 0x0bf8 364 #define IPBRR0_IP_REV GENMASK(15, 0) 365 366 #endif 367